TW201611261A - Self-aligned metal oxide transistors and methods of fabricating the same - Google Patents

Abstract

A self-aligned metal oxide transistor can be fabricated by contacting the source and drain regions of the metal oxide active layer with a reductive polymer, thereby doping the source and drain regions with valence electrons from the reductive polymer and reducing the electrical resistance in the source and drain regions. The reductive polymer can be an electrically insulating polymer that has, in its backbone and/or its pendant group(s), one or more nitrogen atoms with a lone pair of electrons. The reductive polymer can be deposited over the oxide semiconductor layer as the organic interlayer dielectric.

Description

Self-aligned metal oxide transistor and method of manufacturing same Cross-references to related applications

This is a Patent Cooperation Treaty (PCT) application which claims priority and rights to the filing date of US Provisional Patent Application Serial No. 62/009,144, filed on Jun. 6, 2014, the entire disclosure of which is incorporated by reference. Incorporated herein for all purposes.

The present invention relates to self-aligned metal oxide transistors and methods of making the same.

Background of the invention

Flat panel displays such as liquid crystal displays, organic light emitting displays, and electrophoretic displays have been adopted as current mainstream display technologies. These displays are much lighter and thinner than conventional cathode ray tube displays, thus allowing them to be used in applications such as laptops, mobile phones, digital cameras, and camcorders, not only in televisions and video displays. (Camcorders), and other smaller portable devices.

A flat panel display having a thin film transistor backplane is referred to as an active matrix flat panel display. The thin film electro-crystal system in the backplane is used to cut or drive pixels in the panel of the display, so each pixel can be individually Turned on and off. Therefore, these thin film transistors are one of the main factors for the performance of the display.

One of the development trends in flat panel displays is to achieve higher Resolution, which means a smaller pixel size, results in a smaller thin film transistor. Different methods have been proposed to reduce the size of thin film transistors.

In recent years, new thin film transistor technology based on semiconductor metal oxides has attracted great attention. These transistors are made using a semiconductor metal oxide (such as ZnO, In ₂ O ₃ , IGZO, etc.) as a channel layer. Metal oxide thin film transistors (or oxide TET) can provide a number of advantages including high mobility, uniformity, and operational stability; therefore, they have become a tradition based on amorphous or polymorphous germanium. Suitable for the competition of thin film transistor technology.

The most commonly used structure of an oxide TFT is one having one The bottom gate structure of the etch stop member or back channel etch (BCE) configuration. These two configurations have their respective advantages and disadvantages. For example, the etch stop configuration is typically more stable than the back channel etch type because the back channel is protected by the etch stop layer, while during the source and drain etch methods, a BCE, oxide The back channel of the TFT is damaged. However, due to the additional etch stop layer, the etch stop oxide TFT has a larger element size than the BCE oxide TFT.

In terms of component size, an important feature is the channel length of the TFT. Referring to Figure 1, there is illustrated an oxide TFT 10 having a BCE type structure defined by the spacing of the source drains 105, 106. Therefore, the minimum channel length is obtained between the source and the drain Determined by the minimum interval.

For comparison, an oxide having an etch stop type structure The TFT 20 system is illustrated in Figure 2. As shown in FIG. 2, there is an etch stop layer (or etch stop layer) 208 between the oxide semiconductor 204 and the source/drain electrodes 205, 206. Within this architecture, the channel length of the TFT is actually defined by the width of the etch stop layer. Therefore, the minimum channel length of an etch stop type TFT is determined not only by the minimum spacing between the source and the drain but also by the length of the channel overlapping the source and drain on each side. Determination. Therefore, the minimum channel length of the etch stop type structure is substantially greater than the minimum channel length of the back channel etch type structure, which means that the BCE transistor is more suitable for forming than the etch stop type TFT due to the smaller component size. High resolution display. However, as described above, when the BCE structure is fabricated, the back channel is typically damaged during source and drain etching, which can result in poor bias stress stability and other component performance controversies.

Recently, several studies in this reference have suggested an oxygen application. The new self-aligned upper gate (SA-TG) structure of the TFT. As shown in Figures 3-6, within a self-aligned oxide TFT 30, a metal oxide semiconductor (e.g., IGZO) island 304 is formed over the substrate 301, followed by a gate dielectric (or gate insulation). A layer, GI) 303 and a gate 302 are formed on top of the metal oxide semiconductor. The gate and gate dielectrics are etched through the same pattern to expose side regions 309, 310 of the metal oxide semiconductor layer. These exposed side regions are then disposed of such that they are less resistant than the untreated region (i.e., channel region 311) below the gate. Interlayer dielectric An (ILD) material 307 is deposited over the exposed side regions 309, 310 of the metal oxide island 304, the gate dielectric 303, and the gate 302. The ILD 307 is then patterned to turn on vias for depositing the source and drain electrodes 305, 306 (which are in contact with the source drain regions 309, 310 of the metal oxide semiconductor layer 304). The minimum channel length of this type of construction is defined by the minimum width available to the operator using the gate (in other words, the length of the channel is self-aligned with the width of the gate), which is used by the operator to use the BCE type structure. The minimum channel length obtained is similar because no additional etch stop layer is required. At the same time, self-aligned TFTs tend to provide more stable component performance since the sources and gates are not etched on top of the channel region. Thus, self-aligned TFTs have the potential to provide both of these BCE type TFTs and etch stop type TFTs, and can be a good choice for implementing future high resolution flat panel display applications.

However, one of the difficulties in obtaining a SA-TG oxide TFT is how to reduce the resistance of the source and the drain of the metal oxide layer. Three different methods have been described in this reference. The first method uses a plasma treatment method, and the preparation process thereof is shown in Fig. 4. Specifically, after the metal oxide island (for example, IGZO) 304 is formed, and the gate dielectric 303 and the gate 302 are sequentially deposited and then patterned together, as shown in FIG. 4(c). As shown, the operator can apply a plasma treatment 312 (such as Ar plasma or NH ₃ plasma) to the exposed metal oxide regions 309, 310. After this treatment, the voltage drop of the exposed metal oxide regions 309, 310 can be reduced because the plasma processing method can generate oxygen vacancies in the exposed metal oxide regions (eg, IGZO→n ⁺ IGZO). Therefore, the number of charge carriers therein can be increased and the exposed regions 309, 310 can be made more conductive than the channel region 311 of the metal oxide island 304 protected by the gate dielectric 303 and the gate 302. . However, the generated oxygen vacancies are not stable, and after the plasma treatment process, the resistance in the exposed metal oxide regions can be easily increased over a period of time. See, for example, Park et al, Applied Phys. Letts, 93: 053501 (2008); and Kim et al, IEEE Electron Device Letts., 30(4): 374-376 (2009).

The second method is called hydrogen diffusion, and its process flow diagram is illustrated in Figure 5. As shown in FIG. 5(c), the hydrogen diffusion method includes depositing a hydrogen-rich film 313 (generally SiN _x :H, which can also serve as the interlayer dielectric) on the gate 302 and the like. The top of the metal oxide regions 309, 310 are exposed. When hydrogen diffuses from the hydrogen-rich film 313 into the exposed metal oxide regions 309, 310, charge carriers are generated in these regions, thereby reducing the electrical resistance thereof. Unfortunately, as with the plasma processing method, since, in particular, once the thermal annealing is performed, part of the hydrogen can also diffuse into the channel region, which causes the channel region to be excessively conductive, so that the hydrogen diffusion method is low. The resistive metal oxide region is not stable. See, for example, Wu et al., J. Display Technology, 5(12): 515-519 (2009).

The third method is called the metal reaction method, and the process flow chart thereof is illustrated in Fig. 6. The method includes depositing a very thin reactive metal layer 314, such as an aluminum foil, on top of the gate 302 and the exposed metal oxide regions 309, 310 as shown in Figure 6(c). Then, an oxidation step (for example, by an annealing step) is performed to oxidize the aluminum foil to Al ₂ O ₃ . In the oxidation reaction of the metal film 314, a portion of the oxygen in the exposed metal oxide regions 309, 310 is used. It can generate oxygen vacancies and create a carrier within the exposed metal oxide regions, and which can reduce the electrical resistance within the regions 309, 310 as compared to the channel region 311. However, a problem associated with the present method is that the film thickness or oxidation method of the thin reactive metal is not easily controlled. See, for example, U.S. Patent Application Publication No. 2012/0001167.

Therefore, there is a research and development within this art to reduce one self-right The desire for a new method of resistance in the source/drain region of a Zener TFT.

Summary of invention

In accordance with the above, the teachings of the present invention provide a self-aligned oxide TFT in which the source/drain regions are contacted by a reducing polymer, thereby doping the sources with valence electrons from the reduced polymer. The source/drain regions of the oxide semiconductor layer are generated by reducing the resistance in the source/drain regions. The reduced polymer may be an electrically insulating polymer; its main chain and/or its side groups (groups) have one or more nitrogen atoms provided with a lone pair of electrons. The reduced polymer may be deposited on the oxide semiconductor layer as an organic interlayer dielectric. The self-aligned oxide TFT of the present invention is produced as follows. A metal oxide (e.g., IGZO) layer is first formed on a substrate, and then a gate dielectric (or gate insulating layer, GI) and a gate are formed on top of the metal oxide layer. The gate and gate dielectrics are etched through the same pattern to expose side portions of the metal oxide layer. Rather than requiring a separate method (whether by plasma treatment, hydrogen diffusion, or metal reaction) to reduce the source/drain region (ie, the source can be formed thereon) Prior art methods of electrical resistance in the exposed metal oxide regions of the drain, the method of the present invention uses a reduced polymer as the interlayer dielectric (ILD). After depositing the ILD on the source/drain regions of the metal oxide active layer, valence electrons from the reduced polymer diffuse into the source/drain regions (but not the gate) Within the channel region where the dielectric/gate is shielded, it increases the number of charge carriers in the source/drain regions and, therefore, reduces the resistance in the source/drain regions. The ILD is then patterned to open vias for depositing the source and drain.

The above and other features and advantages of the present teachings will be more fully understood from the following description, description, claims, and claims.

10‧‧‧ bottom gate back channel etch oxide film transistor

20‧‧‧Bottom gate etch stop oxide thin film transistor

30, 40‧‧‧ Self-aligned top gate oxide film transistor

50‧‧‧ Self-aligned bottom gate oxide film transistor; bottom gate structure

60‧‧‧Component structure

70‧‧‧Comparative component structure

101, 201, 301, 401, 501, 601, 701‧‧‧ substrates

102, 202, 302, 502, 402‧‧ ‧ gate

103, 203, 303, 403‧‧ ‧ gate insulation

104, 204, 304, 404, 604, 704‧‧‧ oxide semiconductor active layer

105, 205, 305, 405, 505‧‧ ‧ bungee

106, 206, 306, 406, 506‧‧‧ source

107, 207‧‧‧ Passivation layer

208, 508‧‧‧ etching stop layer

307, 407, 507, 607‧‧ ‧ interlayer dielectric

309, 409, 509‧‧ ‧ bungee area

310, 410‧‧‧ source area

311, 511‧‧‧ passage area

312‧‧‧ Plasma treatment

313‧‧‧ Film

314‧‧‧Metal film; reactive metal layer

411‧‧‧ channel

503‧‧‧gate dielectric

504‧‧‧Metal oxide semiconductor layer

507‧‧‧Reducing organic ILD

605, 606, 705, 706‧‧‧ patterned source/bungee

609, 709‧‧‧ passage area

It should be understood that the following figures are for illustration only. The illustrations are not necessarily to scale, and are generally intended to clarify the principles of the teachings of the invention. The drawings are not intended to limit the scope of the teachings in any way.

1 illustrates the structure of a bottom gate back channel etch (BCE) oxide thin film transistor 10 including a substrate 101, a gate 102, a gate insulating layer 103, an oxide semiconductor active layer 104, and source drains 105, 106. And a passivation layer 107.

2 illustrates the structure of a bottom gate etch stop oxide thin film transistor 20 including a substrate 201, a gate 202, a gate insulating layer 203, an oxide semiconductor active layer 204, source drains 205, 206, and a passivation layer 207. And etching the stop layer 208.

Figure 3 illustrates a self-aligned top gate (SA-TG) oxide thin The structure of the film transistor 30 includes a substrate 301, a gate 302, a gate insulating layer 303, an oxide semiconductor active layer 304, source drains 305, 306, and an interlayer dielectric 307. The oxide semiconductor layer 304 includes source drain regions 309, 310 which have a lower resistance than the channel region 311.

4 is a flow chart showing how to fabricate a SA-TG oxide thin film transistor, wherein the low resistance source/drain regions are formed by partially doping the oxide semiconductor layer by a prior art plasma processing method. .

Fig. 5 is a flow chart showing how to fabricate a SA-TG oxide thin film transistor in which the low resistance source/drain regions are formed by partially doping the oxide semiconductor layer by a hydrogen diffusion method of the prior art.

Figure 6 is a diagram showing a process for fabricating a SA-TG oxide thin film transistor in which the low resistance source/drain regions are formed by partially doping the oxide semiconductor layer using a metal reaction method of the prior art.

Figure 7 illustrates the structure of a self-aligned top gate (SA-TG) oxide thin film transistor 40 in accordance with the teachings of the present invention incorporating an organic interlayer dielectric (ILD) 407 comprised of a reduced polymer. The transistor 40 includes a substrate 401, a gate 402, a gate insulating layer 403, an oxide semiconductor active layer 404, source drains 405, 406, and an interlayer dielectric 407 composed of a reduced polymer. The oxide semiconductor layer 404 includes source drain regions 409, 410 which have a lower resistance than the channel 411.

8 is a diagram showing a process for fabricating a SA-TG oxide thin film transistor according to the teachings of the present invention, wherein the low resistance source/drain regions are formed by using an organic interlayer dielectric composed of a reduced polymer. The mass (ILD) is formed by contacting the source/drain regions.

9 is a diagram showing a process for fabricating a self-aligned bottom gate oxide film transistor 50 in accordance with the teachings of the present invention, wherein the low resistance source/drain regions are organically composed of a reduced polymer. An interlayer dielectric (ILD) 507 is formed in contact with the source/drain regions.

Figure 10 is a diagram showing the (a) element structure 60, and (b) of the present inventors for determining the doping effect of directly depositing the reduced ILD 607 deposited on one of the exposed surfaces of the metal oxide semiconductor layer 604 in accordance with the teachings of the present invention. The element structure 70 is compared wherein the metal oxide semiconductor layer 704 is untreated. The device structure 60 includes a substrate 601, a metal oxide semiconductor layer 604, patterned source drains 605, 606 that define the channel region 609, and is deposited on the channel region 609 and directly in contact with the source drains 605, 606. Restore ILD 607. The comparison element structure 70 includes a substrate 701, a metal oxide semiconductor layer 704, and patterned source drains 705, 706 that define an exposed channel region 709.

Figure 11 is a comparison of the sheet resistance of a metal oxide semiconductor layer (IGZO) measured in the channel region 709 in the comparison element structure 70 (without the organic ILD cap layer) and having a reduced organic ILD coverage in accordance with the teachings of the present invention. The sheet resistance of the IGZO measured in the channel region 609 in the element structure 60 of the layer. Specifically, poly(2-vinylpyridine), poly(4-vinylpyridine), branched polyethyleneimine, and polyvinylpyrrolidone are representative reduction organic ILDs.

Detailed description

In the present application from the beginning to the end, if the composition is described as having, Including or including a particular component, or if the method is described as having, including, or comprising a particular process step, it is contemplated that the compositions of the present teachings are also substantially comprised of the listed components, or Compositions, and methods of the present teachings, also consist essentially of, or consist of, the recited process steps.

In the present application, if an element or component is said to be included in and/or selected from the list of listed elements or components, it should be understood that the element or component may be in the listed elements or components. Either or the component or component may be selected from the group consisting of two or more of the listed elements or components. In addition, it will be appreciated that elements and/or features of the compositions, devices, or methods described herein may be combined in various ways, without departing from the spirit and scope of the invention.

The use of the terms "including" and "having" should be construed as being

The use of the singular includes the plural (and vice versa) unless otherwise specified. In addition, if the use of the term "about" is preceded by a value, the teachings of the present invention also include the numerical values themselves unless otherwise specifically indicated. As used herein, unless otherwise specified or inferred, the term "about" means ±10% of the nominal value.

It should be understood that as long as the teachings of the present invention remain practicable, the order of the steps or the order in which they are used to perform certain functions does not matter. Moreover, two or more steps or actions can be performed simultaneously.

From the beginning to the end of this patent specification, a chemical structure having a chemical name may or may not be provided. If the naming produces any problems, the structure works.

In order to address the limitations imposed by prior art methods for doping the source/drain regions of a self-aligned metal oxide thin film transistor, the present teachings provide for the creation of a blend in a metal oxide semiconductor layer. A new method of the hetero-source/drain region is to contact the regions of the stacked organic layer which change the conductivity of the metal oxide semiconductor layer upon direct contact. More specifically, the organic layer may comprise a reducing polymer which, when contacting the metal oxide semiconductor layer, may be doped with the valence electrons, thereby reducing the source/drain regions Thin film resistance inside. In some embodiments, the organic layer can be a layer that can be removed after the doping effect is achieved. In other embodiments, the organic layer can be an additional layer on which an interlayer dielectric (ILD) can be deposited to complete the element. However, in the preferred embodiment, in order to simplify the process and reduce the number of photoetching steps, the organic layer containing the reduced polymer is electrically insulating and thus may be combined as the ILD. The organic layer can also be modulated into a photo-patternable material, thus eliminating the need for a photoresist, which can be directly photopatterned (eg, allowing via openings).

A self-aligned top gate oxide semiconductor system in accordance with the teachings of the present invention is illustrated in FIG. Referring to FIG. 7, the self-aligned top gate metal oxide thin film transistor 40 includes a substrate 401, a metal oxide semiconductor layer 404, a gate dielectric 403, and a gate 402 in order from bottom to top, including the following The organic interlayer dielectric 407 of the reduced polymer, and the source drains 405, 406, are described in more detail. The gate dielectric 402 and the gate 403 on the metal oxide semiconductor layer 404 are etched in the same pattern, so the metal oxide semiconductor layer includes a masked region 411 (which is located in the gate dielectric) Below the gate) and two unmasked (exposed) side regions 409, 410. The masked region 411 can define a channel region within the metal oxide semiconductor layer 404 and is aligned with the gate 402. Therefore, the length of the channel is equivalent to the width of the gate. As shown in FIG. 7, the two unshielded side regions 409, 410 are in direct contact with the organic ILD 407, and the shielded channel region 411 is protected by the gate dielectric 403 and the gate 402. Since the valence electrons diffuse from the organic ILD into the unmasked side regions, the conductivity in the unshielded side region increases and is generated as compared with the masked channel region in the metal oxide semiconductor layer. Low resistance source/drain region. Source drains 405, 406 deposited on the organic ILD extend through vias in the organic ILD to make electrical contact with the low resistance source/drain regions 409, 410 within the metal oxide semiconductor layer.

Figure 8 is a diagram showing the process flow for how to fabricate a SA-TG oxide thin film transistor in accordance with the teachings of the present invention. The substrate 401 for the oxide TFT may be any of the substrate materials known in the art including, but not limited to, doped yttrium, indium tin oxide (ITO), ITO coated Covered glass, ITO coated polyimide or other plastic, copper, molybdenum, chromium, aluminum or other metal coated alone or on a polymer or other substrate. In a preferred embodiment, the substrate may be a transparent substrate such as glass or a high temperature plastic, examples of which include polycarbonate (PC), polyether enamel (PES), polyacrylate (PA), poly. drop Alkene (PNB), polyethylene terephthalate (PET), polyetheretherketone (PEEK), polyethylene naphthalate (PEN) or polyetherimine (PEI).

A metal oxide semiconductor island 404 can be deposited on the substrate using methods known in the art (Fig. 8(a)). Suitable metal oxide semiconductors include, but are not limited to, indium oxide (In ₂ O ₃ ), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), Indium gallium oxide (IGO), indium bismuth oxide (IYO), indium tin zinc oxide (ITZO), tin oxide (SnO ₂ ), zinc oxide (ZnO), zirconia indium zinc (ZrInZnO), and zirconia zinc tin (ZrZnSnO) ). In a preferred embodiment, the metal oxide semiconductor layer in the TFT comprises IGZO. In a conventional method, the metal oxide semiconductor layer is subjected to vapor phase processing (for example, DC sputtering by a target). However, liquid phase processes are described, for example, in U.S. Patent No. 8,017,458. An annealing step (between about 250-400 ° C, preferably about 300 ° C or less) can be performed to improve the semiconductor of the metal oxide layer. In order to pattern the metal oxide layer, a photoresist may be used, and then the metal oxide semiconductor is etched according to the development pattern of the photoresist. A wet etchant such as oxalic acid can be used, or a dry etching step can be performed.

Next, the gate dielectric 403 and the gate 402 can be deposited and patterned by a photolithography process. The gate dielectric 403 may be composed of an inorganic substance such as an oxide such as SiO _x , Al ₂ O ₃ , or HfO ₂ ; a nitride such as Si _x N _y ; and an oxynitride such as yttrium oxynitride SiO _x N _y ), organic matter (e.g., polymers such as polymethyl methacrylate, polyester, polystyrene, polyvinyl halide, and other organic dielectric polymers known in the art), or mixed organic/inorganic material. If an inorganic dielectric such as hafnium oxide or tantalum nitride is used, a vapor phase deposition method such as plasma enhanced chemical vapor deposition (PECVD) may be used. Liquid phase methods such as printing, spin coating, slot coating, or spray coating are commonly used for machine dielectrics. The gate 402 can be formed by a thin layer of sputtered metal (e.g., Mo or Ag) on top of the gate dielectric. The gate is then patterned by photolithography and etched through the pattern of the metal oxide semiconductor layer as described above. By using the patterned gate as a hard mask, the gate dielectric can be patterned by dry or wet etching to obtain the same pattern as the gate (Fig. 8(b)). As shown in FIG. 8(b) and FIG. 8(c), a central region 411 of the MOS layer 404 is shielded by the gate dielectric 403 and the gate 402, but the side regions 409, The 410 system was exposed (unmasked). The central shaded region 411 can define the channel region, and the unmasked regions 409, 410 on both sides of the central shielded region can be doped in the next step to make the conductivity higher than the A masked channel region containing an intrinsic metal oxide.

An organic interlayer dielectric 407 comprising a reduced polymer is then deposited over the portion of the stack, which directly contacts the unshielded side regions 409, 410 within the metal oxide semiconductor layer 404 (Fig. 8 (c )). The reduced polymer is typically an electrically insulating polymer having a backbone and/or pendant groups (groups) comprising one or more nitrogen atoms having a lone pair of electrons. For example, the reduced polymer may be an electrically insulating polymer, and its main chain and/or side groups (groups) include an amine molecular group, an imine molecular group, a guanamine group, and a quinone group. ,One A combination of a molecular group, an azole group, or the like. In certain embodiments, the backbone of the reduced polymer can include one of the following molecular groups:

Wherein L is a covalent bond or a divalent organic group; and each R is independently H or a C _1-20 alkyl group. In certain embodiments, the reduced polymer can include one of the following side groups: Wherein L is a covalent bond or a divalent organic group; and each R is independently H or a C _1-20 alkyl group. Representative reduced polymers that can serve as organic ILDs within the self-aligned oxide TFTs in accordance with the teachings of the present invention include: i) polyimines such as: Ii) an imine copolymer such as: Or C _1-20 alkyl, Iii) Polyallylamine, such as: It includes and And a polymer comprising a nitrogen-containing cyclic (eg, pyridine, pyrrole, pyrrolidone, imidazole, benzimidazole) molecular group, such as: Polymer with the following repeating unit Wherein R is a C _1-20 alkyl group.

The organic interlayer dielectric can be deposited from a composition containing the reduced polymer in a solvent via various liquid phase methods (e.g., printing, spin coating, slit coating, spray coating, etc.). The reduced polymer can be formulated using a crosslinking agent to improve the mechanical and thermal stability of the formed organic ILD. Various crosslinkers are known in the art, and examples thereof include various epoxides, acrylates, maleimide, dienes, and cinnamic acid esters. In a preferred embodiment, the reduced polymer composition is formulated into a photo-patternable composition, thus, without the use of a photoresist, the organic ILD can be photocrosslinked and patterned. Embodiments of this composition can include one or more photocrosslinkers and/or photosensitizers. Examples of useful photosensitizers include anthrone, anthracene, nitrone, and morpholine. In order to improve the adhesion between the organic ILD and the next layer, the reduced polymer composition may also include an adhesion promoter such as a decanoate, a decane, a phosphonate, or a carboxylic acid ester.

Experimental data confirms that the resistance of a metal oxide thin film semiconductor can be reduced by at least a factor of 10 (on the order of magnitude) upon direct contact with the reduced polymer in accordance with the teachings of the present invention. In some embodiments, the reduction in resistance is shown to be 2-3 orders of magnitude (i.e., >100-1000 times). Thus, the method of the present invention can be used to create a doped source/drain region within a self-aligned oxide TFT.

Referring to FIG. 8(d), the source ILD 407 can be patterned to create vias that expose the unmasked source/drain regions 409, 410 a part. Next, source/drain electrodes 405, 406 are formed by depositing, for example, a thinned and patterned metal (eg, Mo) film on top of the reduced ILD 407 and via the vias to neutralize the metal oxide semiconductor layer 404. The equal low resistance source/drain regions 409, 410 create electrical contact with Figure 8(e). A passivation layer (not shown) can be deposited on top of the stack to complete the component.

A self-aligned oxide TFT having a bottom gate structure 50 as shown in FIG. 9 can be fabricated. Specifically, an etch stop layer 508 is used in place of the gate dielectric 503/gate 502 to shield the metal oxide channel region 511. In general, the bottom gate structure 50 includes a substrate 501, a gate 502, a gate dielectric 503, a metal oxide semiconductor layer 504, an etch stop layer 508, and a reduction according to the teachings of the present invention, from bottom to top. Sexual organic ILD 507, and source bungee 505, 506. The channel region 511 is aligned with the gate 502 by patterning the etch stop layer 508 to be aligned with the gate 502. As described in greater detail below, the etch stop layer 508 can be exposed to illumination via the transparent substrate 501 (i.e., from the bottom of the component) by using the gate 502 as a reticle.

Referring to Figure 9(a), the gate can be formed by sputtering a thin metal film (e.g., Mo) under a transparent substrate, followed by photoetching patterning and etching as described with reference to the top gate structure. The gate dielectric can be formed by depositing an organic dielectric (e.g., by spin coating) or an inorganic dielectric (e.g., depositing SiOx by PECVD) on the gate. Then, as shown in FIG. 9b, IGZO may be sputtered, for example, and patterned to form a metal oxide semiconductor island on the gate dielectric. Then, an etch stop (ES) layer (such as SiO _x ) may be deposited on the metal oxide semiconductor layer and patterned by photoetching with backside exposure (Fig. 9c). An organic material, preferably a photo-patternable polymeric material, can also be used as the ES layer and, similarly, patterned by backside exposure. The ES layer can thus have the same pattern as the gate, and the masked region of the metal oxide semiconductor layer below the ES layer that can define the channel region can be aligned with the gate. The subsequent steps are the same as the top gate structure. That is, an organic interlayer dielectric comprising a reduced polymer according to the teachings of the present invention is deposited on the portion of the stack and directly contacts the unmasked side regions of the metal oxide semiconductor layer (FIG. 9). (d)). The organic ILD can be patterned to create vias that expose portions of the unmasked source/drain regions (Fig. 9(e)). Next, a source (drain) metal (eg, Mo) film is deposited on top of the organic ILD to form a source/drain, and through the dielectric holes to neutralize the low resistance in the metal oxide semiconductor layer The source/drain regions are electrically contacted and then patterned (Fig. 9(f)). A passivation layer can be deposited on top of the stack to complete the element.

The various embodiments of the transistors described herein can be arranged in a row and serve as switching elements or peripheral drivers in active matrix displays such as active matrix liquid crystal displays (AMLCDs), active matrix organic light emitting displays, and active matrix electrophoresis. a display; and as a pixel driver for an active matrix organic light emitting diode (AMOLED).

The following examples are provided to further illustrate and facilitate the understanding of the teachings of the present invention and are not intended to limit the invention in any way.

Example 1: Doping effect of reduced polymer

In order to confirm the doping effect of contacting a reduced polymer with a metal oxide thin film semiconductor, a test element having the structure shown in Fig. 10 was fabricated. The structure shown in Figure 10(b) is a control element that does not contain a reduced polymer coating. The methods for making these components are as follows. IGZO is used as the representative metal oxide, and a film of IGZO (30 nm) is sputtered on a glass using a sputtering system having a DC power of 300 watts, an Ar flow rate of 100 sccm, and an O ₂ flow rate of 10 sccm. On the substrate. The IGZO film was patterned by photolithography and wet etched in oxalic acid to form an IGZO island. Molybdenum is then patterned by photolithography and wet etched to form contact pads on both sides of each IGZO island. Each IGZO has a width of about 500 microns and the channel length (distance between the two molybdenum pads) is about 250 microns. For this control element, the average initial sheet resistance of IGZO between the two metal pads was determined to be about 2.95 x 10 ¹⁰ ohms.

For the test elements, one of four different formulations is spin coated onto the top of the metal pads and the exposed IGZO channel. The four formulations include poly(2-vinylpyridine) (P2VPy), poly(4-vinylpyridine) (P4VPy), branched polyethyleneimine (PEI) (polyethyleneimine, ethylenediamine branch). , from Sigma-Aldrich), and polyvinylpyrrolidone. After spin coating, the organic ILD was cured at 200 °C. The sheet resistance of the IGZO channel region in contact with the organic ILD was measured, and the results are shown in FIG.

Specifically, the poly(2-vinylpyridine) coated IGZO showed an average resistance of 2.08 x 10 ⁷ ohm; the poly(4-vinylpyridine) coated IGZO showed an average resistance of 7.99 x 10 ⁶ ohm, The branched PEI coated IGZO showed an average resistance of 1.31 x 10 ⁸ ohms, and the polyvinylpyrrolidone coated IGZO showed an average resistance of 2.50 x 10 ⁸ ohms. Therefore, each of the organic ILD-coated IGZO display resistors is reduced by at least 2 to 3 orders of magnitude from the inherent IGZO.

Therefore, the experimental data confirmed that the contact of the reduced polymer with a metal oxide thin film semiconductor can effectively reduce the resistance of the metal thin film semiconductor.

All publications, patent applications, patents, and other references mentioned herein are incorporated by reference. In case of conflicts, this manual (including definitions) is the main one.

The teachings of the present invention may be embodied in other specific forms without departing from the spirit or scope of the invention. The above-described embodiments are therefore considered as illustrative and not as a limitation of the invention. Therefore, the scope of the invention is to be construed as being limited by the scope of the claims

40‧‧‧ Self-aligned top gate oxide film transistor

401‧‧‧ substrates

402‧‧‧ gate

403‧‧‧ gate insulation

404‧‧‧Oxide semiconductor active layer

405‧‧‧汲polar

406‧‧‧ source

407‧‧‧Interlayer dielectric

409‧‧‧Bungee area

410‧‧‧ source area

411‧‧‧ channel

Claims (30)

A self-aligned metal oxide thin film transistor comprising a substrate, a metal oxide semiconductor layer, a gate dielectric, an organic interlayer dielectric, a gate, and a source and a drain, wherein The metal oxide semiconductor layer includes a shielded region and an unmasked region, the shielded region is aligned with a gate that is not in direct contact with the dielectric of the organic layer, and the unmasked region is directly interposed between the organic layer and the dielectric layer. Contact, and wherein the inter-organic dielectric comprises a polymeric material that increases the conductivity of the metal oxide semiconducting layer upon direct contact. The transistor of claim 1, wherein the polymeric material comprises a reduced polymer. The transistor of claim 2, wherein the reduced polymer is an electrically insulating polymer whose backbone and/or pendant groups (groups) comprise one or more nitrogen atoms having a lone pair of electrons. The transistor of claim 2, wherein the reduced polymer is a main chain and/or a side group (group) comprising an amine group, an imine group, a monoamine group, and an imine molecule. Group, one An electrically insulating polymer of a molecular group, an azole group, or a combination thereof. The transistor of claim 4, wherein the reduced polymer comprises one of the following side groups: Wherein L is a covalent bond or a divalent organic group; and each R is independently H or a C _1-20 alkyl group. The transistor of claim 4, wherein the backbone of the reduced polymer comprises one of the following molecular groups: Wherein L is a covalent bond or a divalent organic group; and each R is independently H or a C _1-20 alkyl group. The transistor of claim 4, wherein the reduced polymer is a polyimine. The transistor of claim 4, wherein the reduced polymer is a polyallylamine. The transistor of claim 4, wherein the main chain and/or the side group (group) of the reduced polymer comprises a pyridine molecule group, a pyrrole group, an imidazole group, a benzimidazole group, a pyrrole group. a ketone ketone molecular group, or a combination thereof. The transistor of claim 2, wherein the reduced polymer is selected from the group consisting of poly(vinylpyridine), poly(vinylpyrrolidone), and poly(ethyleneimine). The transistor of claim 2, wherein the polymeric material comprises the reduced poly One of the compounds is crosslinked to the matrix. The transistor of claim 1, wherein the metal oxide semiconductor layer comprises indium gallium zinc oxide (IGZO). The transistor of claim 1, wherein the gate dielectric comprises hafnium oxide, tantalum nitride, or hafnium oxynitride. The transistor of claim 1, wherein the gate dielectric comprises an organic material. The transistor of claim 1, wherein the substrate comprises a flexible plastic substrate. The transistor of claim 1, wherein the unmasked regions of the metal oxide semiconductor layer in direct contact with the organic interlayer dielectric have a metal oxide semiconductor that is in direct contact with the dielectric of the organic interlayer. The conductivity of the masked regions of the layer is more than 10 times higher than the conductivity. The transistor of claim 16, wherein the unmasked regions of the metal oxide semiconductor layer in direct contact with the organic interlayer dielectric have a metal oxide semiconductor that is in direct contact with the dielectric of the organic interlayer. The conductivity of the masked regions of the layer is greater than 100 times the conductivity. The transistor of claim 17, wherein the unmasked regions of the metal oxide semiconductor layer in direct contact with the organic interlayer dielectric have a metal oxide semiconductor that is in direct contact with the organic interlayer dielectric. The conductivity of the masked regions of the layer is greater than 1000 times the conductivity. The transistor of any one of claims 1 to 18, wherein the transistor has a top gate structure comprising, in order from bottom to top, the substrate, the metal oxide semiconductor layer, the gate dielectric The gate, the organic interlayer dielectric, and the source and the drain, wherein the masked region of the metal oxide semiconductor layer is aligned with the gate dielectric and the gate, and the organic layer is dielectrically The material includes vias through which the source and drain contacts the unmasked regions of the metal oxide semiconductor layer. The transistor of any one of claims 1 to 18, wherein the transistor has a bottom gate structure comprising, in order from bottom to top, the substrate, the gate, the gate dielectric, the metal An oxide semiconductor layer, an etch stop layer, the organic interlayer dielectric, and the source and drain electrodes, wherein the masked region of the metal oxide semiconductor layer is aligned with the gate and the etch stop layer, and the organic layer is interposed The dielectric material includes via holes through which the source and drain electrodes contact the unmasked regions of the metal oxide semiconductor layer. A method of fabricating a self-aligned metal oxide thin film transistor, the method comprising: forming a metal oxide semiconductor layer on a substrate; forming a gate dielectric on the metal oxide semiconductor layer; Forming a gate on the electrolyte, and patterning the gate and the gate dielectric together to provide a masked region of the metal oxide semiconductor layer and an unmasked region of the metal oxide semiconductor layer; Forming an organic interlayer dielectric by depositing a composition containing a reduced polymer on the gate of the metal oxide semiconductor layer and the unmasked regions; patterning the organic interlayer dielectric to provide a via hole extending through the organic interlayer dielectric and extending to the unmasked regions of the metal oxide semiconductor layer; and forming the same with the metal oxide semiconductor layer via the via holes The source and the drain of the shielded area. The method of claim 21, wherein the composition comprising the reduced polymer further comprises a crosslinking agent. The method of claim 22, wherein the crosslinking agent is selected from the group consisting of cinnamic acid esters, dienes, maleimide, acrylates, and epoxides. The method of claim 21, wherein the composition comprising the reduced polymer further comprises an adhesion promoter. The method of claim 24, wherein the adhesion promoter is selected from the group consisting of phthalates, decanes, phosphonates, and carboxylates. The method of claim 21, wherein the composition comprising the reduced polymer further comprises a photosensitizer. The method of claim 26, wherein the photosensitizer is selected from the group consisting of anthrone, anthracene, nitrone, and morpholine. The method of claim 21, further comprising forming a passivation layer between the organic interlayer dielectric and the source and drain electrodes. A method of manufacturing a self-aligned metal oxide thin film transistor, the method The method comprises: forming a gate on a substrate; forming a gate dielectric on the gate; forming a metal oxide semiconductor layer on the gate dielectric; forming a gate on the metal oxide semiconductor layer Etching a stop layer; patterning the etch stop layer to align with the gate and providing a masked region of the metal oxide semiconductor layer and an unmasked region of the metal oxide semiconductor layer; a composition deposited on the etch stop layer and the unmasked regions of the metal oxide semiconductor layer to form an organic interlayer dielectric; the organic interlayer dielectric is patterned to provide a via hole through which The organic interlayer dielectric extends to the unmasked regions of the metal oxide semiconductor layer; and a source that is in contact with the unmasked regions of the metal oxide semiconductor layer is formed through the vias and Bungee jumping. The method of claim 29, wherein the composition comprising the reduced polymer further comprises a crosslinking agent, an adhesion promoter, and/or a photosensitizer.