WO2017034203A1 - Transistor à oxyde et son procédé de fabrication - Google Patents

Transistor à oxyde et son procédé de fabrication Download PDF

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Publication number
WO2017034203A1
WO2017034203A1 PCT/KR2016/009000 KR2016009000W WO2017034203A1 WO 2017034203 A1 WO2017034203 A1 WO 2017034203A1 KR 2016009000 W KR2016009000 W KR 2016009000W WO 2017034203 A1 WO2017034203 A1 WO 2017034203A1
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WIPO (PCT)
Prior art keywords
oxide
thin film
substrate
active layer
mixed solution
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PCT/KR2016/009000
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English (en)
Korean (ko)
Inventor
김성진
김원유
엄주송
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충북대학교 산학협력단
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Publication of WO2017034203A1 publication Critical patent/WO2017034203A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to an oxide transistor manufacturing technology, and more particularly to an oxide transistor having a bottom gate structure and a method of manufacturing the same.
  • TFTs thin film transistors
  • the TFT thus manufactured may be applied to various flexible electronic devices implemented on a polymer substrate.
  • Photolithography is mainly used as a TFT process for forming electrodes or wirings according to the prior art.
  • the photolithography method after forming a conductive film by an existing film forming method, such as sputtering, plating, or CDD, by applying a photosensitive material on a substrate, and developing by irradiating with light, the conductive film is etched according to a resist pattern. The electrode or wiring pattern of the functional thin film is formed.
  • This photolithography method requires extensive equipment and complicated processes such as a vacuum device in forming, patterning, film forming, and etching the thin film.
  • a vacuum device in forming, patterning, film forming, and etching the thin film.
  • the material use efficiency is only a few percent, when the process is terminated, it cannot be reused and must be disposed of, resulting in high manufacturing costs and a large amount of unnecessary chemical waste.
  • the present invention has been made in the technical background as described above, and an object thereof is to provide an oxide transistor capable of lowering the process temperature and a method of manufacturing the same.
  • An oxide transistor includes a substrate used as a gate electrode; A gate insulating film formed on the substrate; In the process of spin coating a mixed solution of a semiconductor material having a band gap greater than or equal to a predetermined reference value on the silicon insulating film for a predetermined time to form an oxide active layer and then annealing Oxide thin film formed according to; And source and drain electrodes formed by depositing aluminum on the oxide thin film.
  • an oxide transistor wherein the oxide is irradiated with ultraviolet rays during a spin coating process of a mixed solution of a semiconductor material having a band gap (gap) on the substrate on which the silicon gate insulating film is formed.
  • Forming an active layer Forming an oxide thin film by annealing the substrate on which the oxide active layer is formed; And depositing aluminum on the oxide thin film to form source and drain electrodes.
  • the process temperature can be lowered and the transistor performance can be improved.
  • FIG 1 illustrates an oxide transistor according to an embodiment of the present invention.
  • FIG 2 illustrates an oxide transistor manufacturing process according to an embodiment of the present invention.
  • 3A and 3B are graphs showing an output curve (drain current) and a transfer curve of an oxide transistor manufactured by varying ultraviolet irradiation time during spin coating, respectively, according to an embodiment of the present invention.
  • FIG. 1 is a diagram illustrating an oxide transistor according to an embodiment of the present invention
  • FIG. 2 is a diagram illustrating an oxide transistor manufacturing process according to an embodiment of the present invention.
  • an oxide transistor having a top-contact bottom-gate structure has been described as an example.
  • an oxide transistor 10 includes a substrate 110, a gate insulating layer 120, an IZO thin film 130, and source and drain electrodes 141 and 142. .
  • the substrate 110 is manufactured using a 600um heavy doped n-type Si wafer, and is used as a gate electrode.
  • the gate insulating layer 120 is formed on the substrate 110 and is formed by growing silicon dioxide (SiO 2 ) to a thickness of 100 nm through a thermal oxidation process in a furnace.
  • the substrate 110 on which the gate insulating film 120 is formed may be used to form the IZO thin film 130 after standard cleaning by, for example, piranha cleaning.
  • the IZO thin film 130 is formed by annealing the oxide active layer formed by irradiating ultraviolet rays while spin-processing an indium-zinc solution onto the substrate 110 to evaporate the remaining solvent.
  • the indium zinc solution may be prepared through the following process. Specifically, 2-methoxyethanol is used as a solvent for preparing a 0.1 M indium and zinc solution. To the indium solution, acetylacetone is added as a stabilizer for dissolving reagents, NH 3 is added as a catalyst for rapid reaction, and zinc solution is added with only acetylacetone, which is stabilized at 60 ° C. for 1 hour. ). In this case, indium nitrate hydrate [In (NO 3 ) 32 O], zinc acetate dihydrate [Zn (CH 3 COO) 22 O] is used as the reagent. Thereafter, the In solution and the Zn solution were mixed at a ratio of 7: 3, and steering was performed at room temperature for 2 hours.
  • 2-methoxyethanol is used as a solvent for preparing a 0.1 M indium and zinc solution.
  • acetylacetone is added as a stabilizer for dissolving reagents
  • NH 3 is added as a catalyst for
  • the indium-zinc solution described above may be replaced with a mixed solution of other semiconductor materials having a band gap of more than a predetermined reference value.
  • the predetermined reference value may be 3.5, which is a band gap of the IZO semiconductor thin film.
  • the mixed solution of another semiconductor material may be an oxide-based semiconductor indium gallium zinc oxide (IYO), zinc tin oxide (IGZO), indium yttrium oxide (ZTO), or the like.
  • the oxide active layer rotates the substrate 110 at a predetermined speed, and coats an indium-zinc solution with a thickness of 20 to 30 nm, while applying predetermined ultraviolet rays to the upper portion of the gate insulating film 120. It may be formed by irradiation for a predetermined time.
  • the spin speed of the substrate 110 during the spin coating is 1500rpm
  • the predetermined ultraviolet light may have a wavelength of 300nm ⁇ 450nm.
  • the intensity of the ultraviolet ray is 1200mW / cm 2 It may be a time of 60 seconds or more while the irradiation time of the ultraviolet ray is 90 seconds or less.
  • the predetermined intensity and irradiation time of ultraviolet rays may be determined in consideration of the on / off ratio and mobility characteristics. For example, UV irradiation time during spin coating becomes shorter as the intensity of ultraviolet light increases, but as a result of the test, the on / off ratio and mobility of the oxide transistor 10 according to the embodiment of the present invention can be maintained above a predetermined value. It can be set to.
  • the constant values of the on / off ratio and mobility may be 10 4 and 3 cm 2 / Vs, respectively.
  • the overall process time can be shortened, and the temperature of the solution process can be lowered to fabricate a flexible device.
  • the IZO thin film 130 may be formed by annealing the substrate 110 coated with the oxide active layer at a temperature of 350 ° C. in a furnace for 4 hours.
  • annealing using the furnace may prevent performance unevenness for each device, and an annealing using the furnace after UV irradiation and spin may prevent the device from deteriorating characteristics due to the annealing. Can be.
  • the source and drain electrodes 141 and 142 may deposit an aluminum source having a thickness of 100 nm by using a metal evaporator at positions where the source and drain electrodes of the IZO thin film 130 will be formed. It is formed as.
  • the embodiment of the present invention can shorten the process step by using the solution process, and can shorten the process time by simultaneously proceeding the UV irradiation and the solution process, and lower the temperature of the solution process to provide a flexible device. I can make it.
  • the embodiment of the present invention can maintain the device-specific performance to some extent, and can prevent the deterioration of the characteristics of the device due to the annealing.
  • the embodiment of the present invention can be applied to a transparent electronic device by fabricating an indium-zinc oxide semiconductor transistor having a large band gap.
  • embodiments of the present invention may improve characteristics of various fields such as oxide transistors, display backplane devices, flexible electronic devices, and transparent electronic devices.
  • FIGS. 3A and 3B are graphs illustrating output curves (drain currents) and transfer curves of oxide transistors manufactured by varying ultraviolet irradiation time during spin coating, respectively, according to an embodiment of the present invention.
  • the source electrode of the oxide transistor was grounded, and a voltage was applied to the drain electrode and the gate electrode.
  • 3a and 3b (a) is not irradiated with ultraviolet light during spin coating, (b) is irradiated with ultraviolet light for 30 seconds during spin coating, (c) is 60 seconds irradiated with ultraviolet light during spin coating and (d) are graphs when 90 seconds of ultraviolet radiation was applied during spin coating.
  • the on / off ratio is 10 7
  • the mobility is 3 cm 2 / Vs or more.
  • the mobility is excellent in more than 5cm 2 / Vs, it can be seen that the on / off ratio is low as 10 4 .
  • the present invention it is possible to assist in manufacturing an oxide transistor capable of guaranteeing an on / off ratio and mobility to some extent as the UV irradiation time is adjusted during the spin coating process.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

La présente invention concerne un transistor à oxyde et son procédé de fabrication. Selon un aspect de la présente invention, le transistor à oxyde comprend : un substrat destiné à être utilisé en tant qu'électrode de grille ; un isolateur de grille formé sur le substrat ; un film mince d'oxyde formé par la formation d'une couche active d'oxyde en exposant à des rayons ultraviolets prédéfinis pendant une durée prédéfinie au cours d'une étape de revêtement par centrifugation la partie supérieure de l'isolateur au silicium, une solution de mélange d'un matériau semi-conducteur ayant une bande interdite supérieure ou égale à une valeur de référence prédéfinie, et en recuisant celui-ci ; et des électrodes de source et de drain formées par un dépôt d'aluminium sur la partie supérieure de la couche mince d'oxyde.
PCT/KR2016/009000 2015-08-21 2016-08-17 Transistor à oxyde et son procédé de fabrication WO2017034203A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2015-0118067 2015-08-21
KR1020150118067A KR101759495B1 (ko) 2015-08-21 2015-08-21 산화물 트랜지스터 및 그 제조 방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504323A (zh) * 2019-08-29 2019-11-26 电子科技大学 一种柔性薄膜晶体管及其制备方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102036972B1 (ko) 2017-11-23 2019-10-25 연세대학교 산학협력단 산화물 박막 트랜지스터 및 그 제조방법
KR102431923B1 (ko) * 2020-11-30 2022-08-11 김성진 Tft 제작 방법
KR102564866B1 (ko) * 2021-07-27 2023-08-07 충북대학교 산학협력단 산화물 이중 층 기반 ｉｇｚｏ 멤트랜지스터 및 이의 제조방법

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KR20120107665A (ko) * 2011-03-22 2012-10-04 삼성디스플레이 주식회사 산화물 반도체의 전구체 조성물 및 이를 이용한 박막 트랜지스터 표시판의 제조 방법
KR20130025703A (ko) * 2011-09-02 2013-03-12 연세대학교 산학협력단 산화물 박막 형성을 위한 조성물, 산화물 박막 제조방법 및 박막 트랜지스터 제조방법
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504323A (zh) * 2019-08-29 2019-11-26 电子科技大学 一种柔性薄膜晶体管及其制备方法
CN110504323B (zh) * 2019-08-29 2020-12-11 电子科技大学 一种柔性薄膜晶体管及其制备方法

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KR20170022722A (ko) 2017-03-02
KR101759495B1 (ko) 2017-07-19

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