WO2017032317A1 - 网络设备 - Google Patents

网络设备 Download PDF

Info

Publication number
WO2017032317A1
WO2017032317A1 PCT/CN2016/096633 CN2016096633W WO2017032317A1 WO 2017032317 A1 WO2017032317 A1 WO 2017032317A1 CN 2016096633 W CN2016096633 W CN 2016096633W WO 2017032317 A1 WO2017032317 A1 WO 2017032317A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus
board
pci
forwarding
network interface
Prior art date
Application number
PCT/CN2016/096633
Other languages
English (en)
French (fr)
Inventor
赵志宇
Original Assignee
杭州华三通信技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 杭州华三通信技术有限公司 filed Critical 杭州华三通信技术有限公司
Priority to JP2018528374A priority Critical patent/JP6550192B2/ja
Priority to EP16838575.5A priority patent/EP3343853B1/en
Priority to US15/753,471 priority patent/US10432557B2/en
Publication of WO2017032317A1 publication Critical patent/WO2017032317A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0803—Configuration setting
    • H04L41/0806—Configuration setting for initial configuration or provisioning, e.g. plug-and-play
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/38—Flow based routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring

Definitions

  • the network device includes a forwarding board and an interface board.
  • the forwarding board can be configured with active/standby redundancy.
  • the physical switching operation can be performed on the I/O bus between the forwarding board and the interface board. That is, the physical connection of the interface board to the I/O bus between the forwarding boards that are down to the standby state is broken, and the physical connection of the new I/O bus is established between the interface board and the forwarding board that is promoted to the active state. Moreover, the forwarding board that is promoted to the active state also needs to be initialized and configured for the newly established physical connection I/O bus.
  • FIG. 1 is a schematic diagram of a network device in an embodiment
  • FIG. 1 are schematic views showing the working state of the embodiment shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a network device based on a PCI-E bus in an embodiment
  • FIG. 3 are schematic diagrams showing the working state of the embodiment shown in FIG. 3;
  • FIG. 5 is a schematic diagram showing an extended structure of the network device shown in FIG. 3;
  • FIG. 6 is a schematic flowchart of a packet forwarding method used in a network device in an embodiment
  • FIG. 7 is a schematic diagram of an initialization process of a network device in an embodiment.
  • network device 10 includes:
  • the first forwarding board 11 The first forwarding board 11;
  • An interface board 13 having a control device (also referred to as a logic device) 131 and a network interface chip 132.
  • the control device 131 is connected to the first forwarding board 11 through the first I/O bus 21 and through the second I/O.
  • the bus 22 is connected to the second forwarding board 12, and is connected to the network interface chip 132 through the network interface bus 23;
  • the control device 131 forms the data packet 200a received by the network interface chip 132 from the outside of the network device 10 into the first uplink data packet stream 211 sent to the first forwarding board 11 through the first I/O bus 21, And a second uplink data packet 212 sent to the second forwarding board 12 through the second I/O bus 22;
  • control device processes the first downlink data packet stream 221 processed by the first forwarding board 11 received by the first I/O bus 21 according to the active/standby state of the first forwarding board 11 and the second forwarding board 12.
  • the second downlink data packet stream 222 processed by the second forwarding board 12 received through the second I/O bus 22 is selectively turned on by the network interface bus 23 through the network interface bus 23, so that the network interface chip 132 can be The data packet is sent in the outbound direction of the network device 10. 200b.
  • uplink for limiting the flow direction of the data packet can be understood as the direction from the outside of the network device 10 to the inside of the network device 10 (ie, the inbound direction), or can be understood as the first from the interface board 13 The direction in which the forwarding board 11 and the second forwarding board 12 transmit.
  • the “downlink” that defines the direction of the data packet flow can be understood as the direction from the inside of the network device 10 to the outside of the network device 10 (ie, the outgoing direction), or can also be understood as the first forwarding board 11 And the direction in which the second forwarding board 12 transmits to the interface board 13.
  • upstream and downstream are used to define the opposite two opposite directions, rather than the absolute direction.
  • control device 131 may utilize one copy of data message 200a as the first upstream data message stream 211 and another copy of data message 200a as the second upstream data message stream 212. That is, when receiving a data message, the control device 131 may add the data message to the first uplink data packet stream 211 and the second uplink data packet stream 212.
  • control device 131 or modules therein may be implemented by specialized hardware, for example, a specially designed permanent circuit or logic device (such as a dedicated processor such as an FPGA or ASIC) for performing a particular operation.
  • control device 131 or modules therein may be implemented by hardware executing machine readable instructions, for example, may include programmable logic devices or circuits temporarily configured by software (eg, including general purpose processors or other programmable processors). Used to perform specific operations.
  • FIGS. 2a and 2b The principles described in the above embodiments may include two states as shown in FIGS. 2a and 2b:
  • the control device 131 can receive the data packet 200a from the outside of the network device 10 through the network interface chip 132. Transmitted to the first turn through the first I/O bus 21
  • the first upstream data packet stream 211 of the dispatching board 11 and the second upstream data packet stream 212 sent to the second forwarding board 12 through the second I/O bus 22 are provided.
  • the first downlink data packet stream 221 received by the control device 131 from the first forwarding board 11 is connected to the network interface chip 132
  • the second downlink data packet stream 222 received by the control device 131 from the second forwarding board 12 is The network interface chip 132 is disconnected.
  • the data packet 200b sent by the network interface chip 132 to the outside of the network device 10 is from the first downlink data packet stream 221;
  • the control device 131 can receive the data message 200a from the outside of the network device 10 through the network interface chip 132. Forming a first uplink data packet stream 211 that is sent to the first forwarding board 11 through the first I/O bus 21 and a second uplink data packet stream 212 that is sent to the second forwarding board 12 through the second I/O bus 22 .
  • the first downlink data packet stream 221 received by the control device 131 from the first forwarding board 11 is disconnected from the network interface chip 132, and the second downlink data packet stream received by the control device 131 from the second forwarding board 12 is received.
  • 222 is electrically connected to the network interface chip 132.
  • the data message 200b sent by the network interface chip 132 to the outside of the network device 10 is from the second downlink data message stream 222.
  • the second forwarding board 12 in the standby state and the first forwarding board 11 in the standby state can be forwarded normally as an example. Therefore, there is a second downlink data packet stream 222 in FIG. 2a and a first downlink data packet stream 221 in FIG. 2b. If the second forwarding board 12 in FIG. 2a or the first forwarding board 11 in FIG. 2b is switched to the standby state due to its own failure, the second forwarding board 12 in FIG. 2a or the first in FIG. 2b The forwarding board 11 may not have the capability of forwarding in the outbound direction of the network device 10. Correspondingly, the second downlink data packet stream 222 in FIG. 2a or the first downlink data packet stream 221 in FIG. 2b may not exist. .
  • the interface board 13 is connected to the first forwarding board 11 and the second forwarding board 12 via the first I/O bus 21 and the second I/O bus 22 which are independent of each other.
  • the data message 200a received by the network interface chip 132 of the board 13 in the inbound direction may be formed as a first uplink data packet stream 211 sent to the first forwarding board 11 through the first I/O bus 21, and through the second The I/O bus 22 transmits a second upstream data message stream 212 to the second forwarding board 12.
  • both the first forwarding board 11 and the second forwarding board 12 in the active state and the standby state can be normally forwarded, they can exist independently through the first I/O bus 21 and the second I/O bus 22, respectively.
  • the first downlink data packet stream 221 and the second downlink data packet stream 222 are transmitted. Therefore, the downlink data packet stream can be forwarded by selectively connecting the first downlink data packet stream 221 and the second downlink data packet stream 222 to the network interface chip 132.
  • the forwarding board needs the active/standby switchover, the physical switching operation of the first I/O bus 21 and the second I/O bus 22 may not be performed. Therefore, the above embodiment can avoid the I/O.
  • first forwarding board 11 and the second forwarding board 12 in the foregoing embodiment may be a board body having at least a forwarding function.
  • first forwarding board 11 and/or the second forwarding board 12 can further integrate functions of control, calculation, storage, and the like. That is, the above embodiment refers to a board having a forwarding function as a forwarding board, and does not mean that the function of the forwarding board is limited to forwarding.
  • first I/O bus 21 and the second I/O bus 22 in the above embodiment are both PCI-E (Peripheral Component Interconnect Express) buses
  • PCI-E Peripheral Component Interconnect Express
  • one end of the PCI-E bus will The PCI-E RC (Root Complex) is formed on the forwarding board, and the PCI-E Endpoint (endpoint) is formed on the interface board at the other end. Physical switching operation is performed on the PCI-E bus, which causes the PCI-E of the interface board.
  • the Endpoint is hot-swapped and hot-inserted on the PCI-E RC of different forwarding boards.
  • the hot insertion process performed on the forwarding board in the promotion state may cause the traffic interruption to reach the order of 10 seconds, and the above example in the application can avoid the physical switching operation of the PCI-E bus. at least The flow interruption is reduced to the order of nanoseconds, and the shortening of the flow interruption time is very obvious.
  • the PCI-E bus is selected as an example for the first I/O bus and the second I/O bus.
  • network device 30 includes:
  • a first forwarding board 31 having a first PCI-E RC 411 connected to the first PCI-E bus 41 and a first CPU 310 driving the first PCI-E RC 411; wherein, in FIG. 3
  • the first PCI-E RC 411 is integrated in the first CPU 310 of the first forwarding board 31, but it can be understood that the first PCI-E RC 411 can also be independent of the first CPU 310 and independent of the first
  • the first PCI-E RC 411 of the CPU 310 can also be driven by the first CPU 310;
  • a second forwarding board 32 having a second PCI-E RC 421 connected to the second PCI-E bus 42 and a second CPU 320 driving the second PCI-E RC 421; wherein, in FIG.
  • the second PCI-E RC 421 is integrated in the second CPU 320 of the second forwarding board 32, but it can be understood that the second PCI-E RC 421 can also be independent of the second CPU 320 and independent of the second The second PCI-E RC 421 of the CPU 320 can also be driven by the second CPU 320;
  • the interface board 33 has a control device 331 and a network interface chip 332.
  • the control device 331 is connected to the first forwarding board 31 via the first PCI-E bus 41 and to the second forwarding via the second PCI-E bus 42.
  • the board 32, and the control device 331 includes:
  • the first transmit buffer queue 414 and the second transmit buffer queue 424 are selectively coupled to the select switch 450 of the network interface bus controller 430. Referring to FIG. 3 in conjunction with FIG. 4a, when the first forwarding board 31 is in the active state and the second forwarding board 32 is in the standby state:
  • the copy driver 440 in the control device 331 copies the data message 400a received by the network interface chip 332 from the outside of the network device 30, and stores it in the first receive buffer queue 413 and the second receive buffer queue 423;
  • the first PCI-E Endpoint 412 reads the first receive buffer queue 413 and sends the first uplink data packet stream 811 to the first forwarding board 31 through the first PCI-E bus 41 for processing by the first CPU 310.
  • the second PCI-E Endpoint 422 reads the second receive buffer queue 423 and sends the second uplink data packet stream 812 to the second forwarding board 32 through the second PCI-E bus 42 for processing by the second CPU 320;
  • the first PCI-E Endpoint 412 also receives the first downlink data packet stream 821 processed by the first CPU 310 from the first forwarding board 31 through the first PCI-E bus 41, and fills the first transmit buffer queue 414.
  • the second PCI-E Endpoint 412 also receives the second downlink data packet stream 822 processed by the second CPU 320 from the second forwarding board 32 through the second PCI-E bus 42 and fills in the second sending buffer queue 424. ;
  • the selection switch 450 connects the first transmit buffer queue 414 to the network interface bus controller 430 and disconnects the second transmit buffer queue 424 from the network interface bus controller 430 to be cached in the first transmit buffer queue 414.
  • the first downlink data message stream 821 can be read by the network interface bus controller 430 and sent to the network interface chip 332 through the network interface bus 43, so that the network interface chip 332 is sent in the outbound direction of the network device 40.
  • the outgoing data message 400b is from the first downstream data message stream 821.
  • the copy driver 440 in the control device 331 copies the data message 400a received by the network interface chip 332 from the outside of the network device 30, and stores it in the first receive buffer queue 413 and the second receive buffer queue 423;
  • the first PCI-E Endpoint 412 reads the first receive buffer queue 413 and sends the first uplink data packet stream 811 to the first forwarding board 31 through the first PCI-E bus 41 for processing by the first CPU 310.
  • the second PCI-E Endpoint 422 reads the second receive buffer queue 423 and sends the second uplink data packet stream 812 to the second forwarding board 32 through the second PCI-E bus 42 for processing by the second CPU 320;
  • the first PCI-E Endpoint 412 also receives the first downlink data packet stream 821 processed by the first CPU 310 from the first forwarding board 31 through the first PCI-E bus 41, and fills the first transmit buffer queue 414.
  • the second PCI-E Endpoint 412 also receives the second downlink data packet stream 822 processed by the second CPU 320 from the second forwarding board 32 through the second PCI-E bus 42 and fills in the second sending buffer queue 424. ;
  • the selection switch 450 disconnects the first transmit buffer queue 414 from the network interface bus controller 430 and connects the second transmit buffer queue 424 to the network interface bus controller 430 for caching in the second transmit buffer queue 424.
  • the second downlink data message stream 822 can be read by the network interface bus controller 430 and sent to the network interface chip 332 through the network interface bus 43, so that the network interface chip 332 sends data in the outbound direction of the network device 40.
  • Message 400b is from second data message stream 420.
  • the primary forwarding board When the network device 30 is powered on, the primary forwarding board performs board-level initialization configuration on the interface board 13 through the board-level initialization process, such as powering on the board, resetting, and identifying the board.
  • the first PCI-E bus 41 can be driven by the first CPU 310.
  • the first receive buffer queue 413 and the first transmit buffer queue 414 may be mapped within a predetermined space of the first PCI-E Endpoint 412, and the first PCI-E RC 411 is configured with the first PCI driven by the first CPU 310.
  • E Endpoint 412, the configuration of the first PCI-E Endpoint 412, and the first receive buffer queue 413 and the first transmit buffer queue 414 can be implemented;
  • the second PCI-E bus 42 may be driven by the second CPU 320.
  • the second PCI-E RC 421 configuration For example, the second receive buffer queue 423 and the second transmit buffer queue 424 may be mapped in a predetermined space of the second PCI-E Endpoint 422, and the second PCI-E RC 421 is configured to drive the second PCI under the driving of the second CPU 320.
  • E Endpoint 422, the configuration of the second PCI-E Endpoint 422, and the second receive buffer queue 423 and the second transmit buffer queue 424 can be implemented;
  • network interface configuration is performed on the network interface bus controller 430 and the network interface chip 332, which may include, for example, auto-negotiation settings, duplex or half-duplex configuration, 100 Mbps or Gigabit configuration. Equal link layer configuration.
  • the network interface bus controller 430 and the network interface chip 332 shared by the first PCI-E bus 41 and the second PCI-E bus 42 can be configured by the PCI-E RC of the forwarding board in the active state, that is, if When the forwarding board 31 is in the active state, the network interface bus controller 430 and the network interface chip 332 can be driven by the first CPU 310 to drive the first PCI-E RC. In the 411 configuration, if the second forwarding board 32 is in the active state, the network interface bus controller 430 and the network interface chip 332 may be configured by the second CPU 320 by driving the second PCI-E RC 421.
  • control device 331 may further include:
  • the state identification module 510 is connected to the control pin 511 of the first CPU 310 of the first forwarding board 31 and the control pin 512 of the second CPU 320 of the second forwarding board 32 for identifying by controlling the control pins 511 and 512. And recording the active and standby states of the first forwarding board 31 and the second forwarding board 32 for the selection switch 450 to identify;
  • the board level configuration module 520 is connected to the first CPU 310 of the first forwarding board 31 through the first management bus 521, and to the second CPU 320 of the second forwarding board 32 via the second management bus 522; and the board level configuration module 520 can The status of the first forwarding board 31 and the second forwarding board 32 are identified by the state identification module 510.
  • the board level configuration module 520 When the power-on of the network device is started, if the first forwarding board 31 is in the active state, the board level configuration module 520 The first CPU 310 of the first forwarding board 31 receives the board level initial configuration of the interface board 33 through the first management bus 521, and if the second forwarding board 32 is found to be in the active state, the board level configuration module 520 passes the second management.
  • the bus 522 receives the board-level initial configuration of the interface board 33 by the second CPU 320 of the second forwarding board 32;
  • the network interface configuration module 530 can identify the active and standby states of the first forwarding board 31 and the second forwarding board 32 through the state identification module 510. If the first forwarding board 31 is in the active state, the network interface configuration module 530 passes the A PCI-E Endpoint 412 receives an initial configuration of the first CPU 310 to the network interface bus controller 430 and the network interface chip 332 from the first PCI-E RC 411.
  • the interface configuration module 530 receives an initial configuration of the second CPU 320 to the network interface bus controller 430 and the network interface chip 332 from the second PCI-E RC 421 through the second PCI-E Endpoint 422; and the network interface configuration module 530 is completing Network interface bus controller After the initial configuration of 430, the drive network interface bus controller 430 configures the network interface chip 332 via the network interface bus 43.
  • the following embodiment further provides a packet forwarding method for use in a network device.
  • the network device applying the packet forwarding method may include an interface board having a network interface chip, a first forwarding board connected to the interface board through the first I/O bus, and a second forwarding connected to the interface board through the second I/O bus. board.
  • the packet forwarding method includes the following steps applied to the interface board.
  • the data packet received by the network interface chip from the outside of the network device is formed into a first uplink data packet stream sent to the first forwarding board by using the first I/O bus, and sent to the second I/O bus to the second I/O bus. a second uplink data packet stream exchanged by the second forwarding board;
  • the first downlink data packet processed by the first forwarding board received through the first I/O bus and the second I/O bus are used according to the active/standby state of the first forwarding board and the second forwarding board.
  • the second downlink data packet stream processed by the received second forwarding board is selectively connected to the network interface chip through the network interface bus.
  • the first I/O bus is the first PCI-E bus and the second I/O bus is the second PCI-E bus, then:
  • the first forwarding board may have a first PCI-E RC connected to the first PCI-E bus, and a first CPU driving the first PCI-E RC;
  • the second forwarding board may have a second PCI-E RC connected to the second PCI-E bus, and a second CPU driving the second PCI-E RC;
  • the interface board has a first PCI-E Endpoint connected to the first PCI-E bus and a second PCI-E Endpoint connected to the second PCI-E bus, a first receive buffer queue connected to the first PCI-E Endpoint, and a first send A cache queue, a second receive buffer queue and a second transmit buffer queue connected to the second PCI-E Endpoint, and a network interface bus controller connected to the network interface chip through the network interface bus.
  • the message forwarding method copies the data packets received by the network interface bus controller from the network interface chip, and respectively fills the first receiving buffer queue and the second receiving buffer queue to form a first receiving buffer queue.
  • the first uplink data packet stream is formed by using the second receiving buffer queue to form a second uplink data packet stream;
  • the packet forwarding method may further connect the first sending buffer queue and the second sending buffer queue to the network interface bus controller to enable the first downlink data packet flow and the second downlink data packet.
  • the flow is selectively turned on by the network interface bus and the network interface chip.
  • the packet forwarding method in the foregoing embodiment may further implement an initialization process of an interface board of the network device, including a board level initial configuration, a PCI-E initial configuration, and a network interface configuration.
  • the first forwarding board is in the active state during the initialization process after the network device is powered on, and the second forwarding board is in the standby state after the network device is powered on.
  • the process initiates an initialization process by the first forwarding board and includes the following steps.
  • the first forwarding board performs board level initial configuration on the interface board, and notifies the second forwarding board to start PCI-E initial configuration after the board level initial configuration is completed.
  • the first forwarding board performs PCI-E initial configuration on the first PCI-E Endpoint and the first receiving buffer queue and the first sending buffer queue in the interface board, and the second forwarding board is in the second PCI-E in the interface board.
  • the Endpoint and the second receive buffer queue and the second transmit buffer queue are configured for PCI-E initialization.
  • the first forwarding board performs network interface configuration on the network interface bus controller and the network interface chip of the interface board.
  • the operations performed by the first forwarding board and the second forwarding board in the above process may be understood to be implemented by the first CPU and the second CPU, respectively.
  • the interface board can identify the first forwarding board and the control pin of the first CPU of the first forwarding board and the control pin of the second CPU of the second forwarding board The active/standby status of the second forwarding board,
  • the message forwarding method may further receive the first CPU from the first or second PCI-E RC of the first or second forwarding board in the active state. Or the second CPU initializes the board level of the interface board.
  • the interface board may further connect the first CPU of the first forwarding board through the first management bus, and further connect the second CPU of the second forwarding board by using the second management bus.
  • the packet forwarding method further includes:
  • the first forwarding board If the first forwarding board is in the active state, receiving, by the first management bus, the first CPU of the first forwarding board to initialize the board level of the interface board;
  • the second CPU of the second forwarding board receives the board level initial configuration of the interface board through the second management bus.
  • PCI-E initialization configuration shown in Figure 7 it may include:
  • the first PCI-E Endpoint, the first receive buffer queue, and the first transmit buffer queue may be configured by the first CPU to drive the first PCI-E RC;
  • the second PCI-E Endpoint, the second receive buffer queue, and the second transmit buffer queue may be configured by the second CPU to drive the second PCI-E RC;
  • the interface configuration on the network interface may include: when the first forwarding board is the primary forwarding board, receiving, from the first PCI-E root complex, initial configuration of the network interface bus controller and the network interface chip by the first CPU; When the second forwarding board is the primary forwarding board, the second PCI-E root complex receives the initial configuration of the network interface bus controller and the network interface chip from the second CPU.

Abstract

一种网络设备包括第一转发板、第二转发板和具有网络接口芯片的接口板。将网络接口芯片从网络设备外部接收到的数据报文形成通过第一I/O总线发送至第一转发板的第一上行数据报文流、以及通过第二I/O总线发送至第二转发板的第二上行数据报文流。根据第一转发板和第二转发板的主备状态，将通过第一I/O总线接收的第一转发板处理后的第一下行数据报文流和通过第二I/O总线接收的第二转发板处理后的第二下行数据报文流通过网络接口总线与网络接口芯片择一地导通。

Description

网络设备
发明背景
网络设备包括转发板和接口板，并且，为了提高转发的可靠性，转发板可以采用主备冗余的配备方式。
当需要进行转发板的主备切换时，可以对转发板与接口板之间的I/O总线执行物理切换操作。即，接口板与降至备用状态的转发板之间的I/O总线的物理连接断开，接口板与晋升为主用状态的转发板之间建立新的I/O总线的物理连接。并且，晋升为主用状态的转发板还需要对新建立物理连接的I/O总线进行初始化配置。
附图简要说明
以下附图仅为本发明技术方案的一些例子，本发明并不局限于图中示出的特征。以下附图中，相似的标号表示相似的元素：
图1为一个实施例中的网络设备的原理性示意图；
图2a和图2b为如图1所示实施例的工作状态示意图；
图3为一个实施例中基于PCI-E总线的网络设备的结构示意图；
图4a和图4b为如图3所示实施例的工作状态示意图；
图5为如图3所示的网络设备的扩展结构示意图；
图6为一个实施例中用于网络设备中的报文转发方法的流程示意图；
图7为一个实施例中的网络设备的初始化流程示意图。
实施本发明的方式
为了描述上的简洁和直观，下文通过描述若干代表性的实施例来对 本发明的方案进行阐述。下文中描述了很多细节以使技术方案易于理解。但是，本申请技术方案的实现并不依赖于这些细节。为了避免不必要地模糊了本技术方案，一些例子中的方法和结构没有详细地描述。下文中，“一个”是为了以某一特定元素为例进行说明。下文中，“包括”是指“包括但不限于”，“根据......”是指“至少根据......，但不限于仅根据......”。说明书和权利要求书中的“包括”及其变形是指某种程度上至少包括，应当解释为除了包括之后提到的特征外，其它特征也可以存在。下文中没有特别指出一个成分的数量时，意味着该成分可以是一个也可以是多个，或可理解为至少一个。
如图1所示，在一个实施例中，网络设备10包括：
第一转发板11；
第二转发板12；
接口板13，该接口板13具有控制装置(也称为逻辑装置)131和网络接口芯片132，该控制装置131通过第一I/O总线21连接第一转发板11、通过第二I/O总线22连接第二转发板12、并通过网络接口总线23连接网络接口芯片132；
其中，该控制装置131将网络接口芯片132从网络设备10的外部接收到的数据报文200a形成通过第一I/O总线21发送至第一转发板11的第一上行数据报文流211、以及通过第二I/O总线22发送至第二转发板12的第二上行数据报文流212；
并且，该控制装置根据第一转发板11和第二转发板12的主备状态，将通过第一I/O总线21接收的第一转发板11处理后的第一下行数据报文流221和通过第二I/O总线22接收的第二转发板12处理后的第二下行数据报文流222通过网络接口总线23与网络接口芯片132择一地导通，使网络接口芯片132可以在网络设备10的出方向上发出数据报文 200b。
其中，上述限定数据报文流方向的“上行”可以理解为从网络设备10的外部进入到网络设备10内部的方向(即，入方向)，或者，也可以理解为从接口板13向第一转发板11和第二转发板12发送的方向。相应地，上述限定数据报文流方向的“下行”可以理解为从网络设备10的内部发出至网络设备10外部的方向(即，出方向)，或者，也可以理解为从第一转发板11和第二转发板12向接口板13发送的方向。并且，“上行”和“下行”是用来限定相反的两个相对方向，而非表示绝对方向。
一个例子中，控制装置131可以利用数据报文200a的一个拷贝作为第一上行数据报文流211，利用数据报文200a的另一个拷贝作为第二上行数据报文流212。也即，当接收到一个数据报文时，控制装置131可以将该数据报文加入第一上行数据报文流211和第二上行数据报文流212中。
一个例子中，控制装置131或其中的模块可以由专门的硬件实现，例如，可以为专门设计的永久性电路或逻辑器件(如专用处理器，如FPGA或ASIC)用于完成特定的操作。一些例子中，控制装置131或其中的模块可以由执行机器可读指令的硬件实现，例如，可以包括由软件临时配置的可编程逻辑器件或电路(如包括通用处理器或其它可编程处理器)用于执行特定操作。
上述的实施例所述的原理中，可以包括如图2a和图2b所示的两种状态：
如图2a所示，当第一转发板11处于主用状态、第二转发板12处于备用状态时，控制装置131可以通过网络接口芯片132从网络设备10的外部接收到数据报文200a，形成通过第一I/O总线21发送至第一转 发板11的第一上行数据报文流211和通过第二I/O总线22发送至第二转发板12的第二上行数据报文流212。控制装置131从第一转发板11接收到的第一下行数据报文流221与网络接口芯片132导通，控制装置131从第二转发板12接收到的第二下行数据报文流222与网络接口芯片132断开。从而，网络接口芯片132向网络设备10的外部发出的数据报文200b为来自第一下行数据报文流221；
如图2b所示，当第一转发板11处于备用状态、第二转发板12处于主用状态时，控制装置131可以通过网络接口芯片132从网络设备10的外部接收到的数据报文200a，形成通过第一I/O总线21发送至第一转发板11的第一上行数据报文流211和通过第二I/O总线22发送至第二转发板12的第二上行数据报文流212。并且，控制装置131从第一转发板11接收到的第一下行数据报文流221与网络接口芯片132断开，控制装置131从第二转发板12接收到的第二下行数据报文流222与网络接口芯片132导通。从而，网络接口芯片132向网络设备10的外部发出的数据报文200b为来自第二下行数据报文流222。
上述的图2a和图2b中，分别以备用状态的第二转发板12和备用状态的第一转发板11可以正常转发为例。因此，图2a中存在第二下行数据报文流222、图2b中存在第一下行数据报文流221。若图2a中的第二转发板12或图2b中的第一转发板11是由于自身的故障而切换成为备用状态的时，则图2a中的第二转发板12或图2b中的第一转发板11可能不具备在网络设备10的出方向上转发的能力，相应地，可能不存在图2a中的第二下行数据报文流222或图2b中的第一下行数据报文流221。
在上述的实施例中，接口板13通过相互独立的第一I/O总线21和第二I/O总线22分别连接第一转发板11和第二转发板12。并且，接口 板13的网络接口芯片132在入方向上接收到的数据报文200a可以形成为通过第一I/O总线21发送至第一转发板11的第一上行数据报文流211、以及通过第二I/O总线22发送至第二转发板12的第二上行数据报文流212。
从而，当分别处于主用状态和备用状态的第一转发板11和第二转发板12均能够正常转发时，可以同时存在分别通过第一I/O总线21和第二I/O总线22独立传输的第一下行数据报文流221和第二下行数据报文流222。从而，通过将第一下行数据报文流221和第二下行数据报文流222与网络接口芯片132择一地导通，即可进行下行数据报文流的转发。
可见，当转发板需要主备切换时，可以不需要对第一I/O总线21和第二I/O总线22中的任意一个执行物理切换操作，因此，上述实施例可以避免对I/O总线的物理切换操作及物理切换完成后的初始化过程，从而，上述实施例可以缩短主备切换导致的流量中断的时间。
另外，上述实施例中的第一转发板11和第二转发板12可以是至少具有转发功能的板体。并且，第一转发板11和/或第二转发板12还可以进一步集成控制、计算、存储等功能。即，上述的实施例将具有转发功能的板体称作转发板，并不意味着转发板的功能仅限于转发。
当上述实施例中的第一I/O总线21和第二I/O总线22均为PCI-E(Peripheral Component Interconnect Express，高速外设部件互连标准)总线时，PCI-E总线的一端会在转发板形成PCI-E RC(Root Complex，根复合体)、另一端会在接口板形成PCI-E Endpoint(端点)，对PCI-E总线执行物理切换操作，会导致接口板的PCI-E Endpoint分别在不同转发板的PCI-E RC发生热拔出和热插入。并且，在晋升为主用状态的转发板执行的热插入过程，会导致流量中断达到10秒的量级，而采用本申请中上面的例子，可以避免对PCI-E总线的物理切换操作，可以至少 将流量中断降低至纳秒的量级，流量中断时间的缩短程度非常明显。
下面以第一I/O总线和第二I/O总线均选用PCI-E总线为例进行说明。
如图3所示，在一个实施例中，网络设备30包括：
第一转发板31，该第一转发板31具有连接第一PCI-E总线41的第一PCI-E RC 411、以及驱动第一PCI-E RC 411的第一CPU 310；其中，在图3中，第一PCI-E RC 411集成于第一转发板31的第一CPU 310，但可以理解的是，第一PCI-E RC 411也可以独立于第一CPU 310，并且，独立于第一CPU 310的第一PCI-E RC 411同样能够被第一CPU 310驱动；
第二转发板32，该第二转发板32具有连接第二PCI-E总线42的第二PCI-E RC 421、以及驱动第二PCI-E RC 421的第二CPU 320；其中，在图3中，第二PCI-E RC 421集成于第二转发板32的第二CPU 320，但可以理解的是，第二PCI-E RC 421也可以独立于第二CPU 320，并且，独立于第二CPU 320的第二PCI-E RC 421同样能够被第二CPU 320驱动；
接口板33，该接口板33具有控制装置331和网络接口芯片332，该控制装置331通过第一PCI-E总线41连接第一转发板31、并通过第二PCI-E总线42连接第二转发板32，并且，该控制装置331包括：
连接第一PCI-E总线41的第一PCI-E Endpoint 412；
连接第二PCI-E总线42的第二PCI-E Endpoint 422；
连接第一PCI-E Endpoint 412的第一接收缓存队列413和第一发送缓存队列414；
连接第二PCI-E Endpoint 422的第二接收缓存队列423和第二发送缓存队列424；
通过网络接口总线43连接网络接口芯片332的网络接口总线控制器430；
将网络接口总线控制器430分别连接第一接收缓存队列413和第二接收缓存队列423的复制驱动器440；
将第一发送缓存队列414和第二发送缓存队424列择一地连接至网络接口总线控制器430的选择切换器450。请在参见图3的同时结合图4a，当第一转发板31处于主用状态、第二转发板32处于备用状态时：
控制装置331中的复制驱动器440将网络接口芯片332从网络设备30的外部接收到的数据报文400a复制、并存储至第一接收缓存队列413和第二接收缓存队列423中；
第一PCI-E Endpoint 412读取第一接收缓存队列413、并通过第一PCI-E总线41向第一转发板31发送第一上行数据报文流811、以供第一CPU 310处理，第二PCI-E Endpoint 422读取第二接收缓存队列423、并通过第二PCI-E总线42向第二转发板32发送第二上行数据报文流812、以供第二CPU 320处理；
第一PCI-E Endpoint 412还通过第一PCI-E总线41从第一转发板31接收经第一CPU 310处理后的第一下行数据报文流821、并填入第一发送缓存队列414，第二PCI-E Endpoint 412还通过第二PCI-E总线42从第二转发板32接收经第二CPU 320处理后的第二下行数据报文流822、并填入第二发送缓存队列424；
并且，选择切换器450将第一发送缓存队列414连接至网络接口总线控制器430、并将第二发送缓存队424与网络接口总线控制器430断开，使缓存在第一发送缓存队列414中的第一下行数据报文流821可以被网络接口总线控制器430读取、并通过网络接口总线43向网络接口芯片332发送，从而，网络接口芯片332在网络设备40的出方向上发 出的数据报文400b来自第一下行数据报文流821。
请在参见图3的同时结合图4b，当第一转发板31处于备用状态、第二转发板32处于主用状态时：
控制装置331中的复制驱动器440将网络接口芯片332从网络设备30的外部接收到的数据报文400a复制、并存储至第一接收缓存队列413和第二接收缓存队列423中；
第一PCI-E Endpoint 412读取第一接收缓存队列413、并通过第一PCI-E总线41向第一转发板31发送第一上行数据报文流811、以供第一CPU 310处理，第二PCI-E Endpoint 422读取第二接收缓存队列423、并通过第二PCI-E总线42向第二转发板32发送第二上行数据报文流812、以供第二CPU 320处理；
第一PCI-E Endpoint 412还通过第一PCI-E总线41从第一转发板31接收经第一CPU 310处理后的第一下行数据报文流821、并填入第一发送缓存队列414，第二PCI-E Endpoint 412还通过第二PCI-E总线42从第二转发板32接收经第二CPU 320处理后的第二下行数据报文流822、并填入第二发送缓存队列424；
并且，选择切换器450将第一发送缓存队列414与网络接口总线控制器430断开、并将第二发送缓存队424连接至网络接口总线控制器430，使缓存在第二发送缓存队列424中的第二下行数据报文流822可以被网络接口总线控制器430读取、并通过网络接口总线43向网络接口芯片332发送，从而，网络接口芯片332在网络设备40的出方向上发出的数据报文400b来自第二数据报文流420。
在网络设备30上电启动时，主用转发板对接口板13通过板级初始化过程进行板级的初始化配置，例如板卡上电、解复位、板卡识别等。
在板级初始化过程之后，进行PCI-E配置，包括第一PCI-E Endpoint 412、第二PCI-E Endpoint 422、第一接收缓存队列413和第一发送缓存队列414、第二接收缓存队列423和第二发送缓存队列424将被配置，可以是PCI-E协议的Endpoint Function(端点功能)配置，Endpoint Function配置可以通过板级初始化过程之后的PCI-E初始化过程实现。
对于被第一PCI-E总线41独占的第一PCI-E Endpoint 412、以及第一接收缓存队列413和第一发送缓存队列414，可以由第一CPU 310通过驱动第一PCI-E总线41对端的第一PCI-E RC 411配置。例如，第一接收缓存队列413和第一发送缓存队列414可以映射在第一PCI-E Endpoint 412的预定空间内，第一PCI-E RC 411在第一CPU 310的驱动下配置第一PCI-E Endpoint 412，即可实现对第一PCI-E Endpoint 412、以及第一接收缓存队列413和第一发送缓存队列414的配置；
对于被第二PCI-E总线42独占的第二PCI-E Endpoint 422、以及第二接收缓存队列423和第二发送缓存队列424，可以由第二CPU 320通过驱动第二PCI-E总线42对端的第二PCI-E RC 421配置。例如，第二接收缓存队列423和第二发送缓存队列424可以映射在第二PCI-E Endpoint 422的预定空间内，第二PCI-E RC 421在第二CPU 320的驱动下配置第二PCI-E Endpoint 422，即可实现对第二PCI-E Endpoint 422、以及第二接收缓存队列423和第二发送缓存队列424的配置；
在PCI-E初始化配置过程之后，对网络接口总线控制器430和网络接口芯片332进行网络接口配置，网络接口配置可以包括例如自协商设置、双工或半双工配置、百兆或千兆配置等链路层配置。
对于被第一PCI-E总线41和第二PCI-E总线42共用的网络接口总线控制器430和网络接口芯片332，可以由主用状态的转发板的PCI-E RC配置，即，若第一转发板31处于主用状态，则网络接口总线控制器430和网络接口芯片332可以由第一CPU 310通过驱动第一PCI-E RC 411配置，若第二转发板32处于主用状态，则网络接口总线控制器430和网络接口芯片332可以由第二CPU 320通过驱动第二PCI-E RC 421配置。
另外，控制装置331可以进一步包括：
状态识别模块510，连接第一转发板31的第一CPU 310的控制管脚511以及第二转发板32的第二CPU 320的控制管脚512，用于通过检测控制管脚511和512，识别并记录第一转发板31和第二转发板32的主备状态，以供选择切换器450识别；
板级配置模块520，通过第一管理总线521连接第一转发板31的第一CPU 310、通过第二管理总线522连接第二转发板32的第二CPU 320；并且，板级配置模块520可以通过状态识别模块510识别第一转发板31和第二转发板32的主备状态；在网络设备的上电启动时，若识别出第一转发板31处于主用状态，则板级配置模块520通过第一管理总线521接收第一转发板31的第一CPU 310对接口板33的板级初始化配置，若识别出第二转发板32处于主用状态，则板级配置模块520通过第二管理总线522接收第二转发板32的第二CPU 320对接口板33的板级初始化配置；
网络接口配置模块530，可以通过状态识别模块510识别第一转发板31和第二转发板32的主备状态；若识别出第一转发板31处于主用状态，则网络接口配置模块530通过第一PCI-E Endpoint 412从第一PCI-E RC 411接收第一CPU 310对网络接口总线控制器430和网络接口芯片332的初始化配置，若识别出第二转发板32处于主用状态，则网络接口配置模块530通过第二PCI-E Endpoint 422从第二PCI-E RC 421接收第二CPU 320对网络接口总线控制器430和网络接口芯片332的初始化配置；以及，网络接口配置模块530在完成对网络接口总线控制器 430的初始化配置后，驱动网络接口总线控制器430通过网络接口总线43配置网络接口芯片332。
除了上述实施例中的网络设备，后续实施例还提供了一种用于网络设备中的报文转发方法。应用该报文转发方法的网络设备可以包括具有网络接口芯片的接口板、通过第一I/O总线连接接口板的第一转发板、以及通过第二I/O总线连接接口板的第二转发板。
并且，如图6所示，该报文转发方法包括应用在接口板的如下步骤。
S61，将网络接口芯片从网络设备的外部接收到的数据报文形成通过第一I/O总线发送至第一转发板的第一上行数据报文流、以及通过第二I/O总线发送至第二转发板交互的第二上行数据报文流；
S62，根据第一转发板和第二转发板的主备状态，将通过第一I/O总线接收的第一转发板处理后的第一下行数据报文流和通过第二I/O总线接收的第二转发板处理后的第二下行数据报文流通过网络接口总线与网络接口芯片择一地导通。
在应用该报文转发方法的网络设备中，若第一I/O总线为第一PCI-E总线、第二I/O总线为第二PCI-E总线，则：
第一转发板可以具有连接第一PCI-E总线的第一PCI-E RC、以及驱动第一PCI-E RC的第一CPU；
第二转发板可以具有连接第二PCI-E总线的第二PCI-E RC、以及驱动第二PCI-E RC的第二CPU；
接口板具有连接第一PCI-E总线的第一PCI-E Endpoint和连接第二PCI-E总线的第二PCI-E Endpoint、连接第一PCI-E Endpoint的第一接收缓存队列和第一发送缓存队列、连接第二PCI-E Endpoint的第二接收缓存队列和第二发送缓存队列、以及通过网络接口总线连接网络接口芯片的网络接口总线控制器。
相应地，该报文转发方法将网络接口总线控制器从网络接口芯片接收到的数据报文复制、并分别填充至第一接收缓存队列和第二接收缓存队列，以利用第一接收缓存队列形成第一上行数据报文流、利用第二接收缓存队列形成第二上行数据报文流；
并且，该报文转发方法还可以将第一发送缓存队列和第二发送缓存队列择一地与网络接口总线控制器导通，以使第一下行数据报文流和第二下行数据报文流通过网络接口总线与网络接口芯片择一地导通。
另外，上述实施例中的报文转发方法还可以实现网络设备的接口板的初始化过程，包括板级初始化配置、PCI-E初始化配置以及网络接口配置。
如图7所示，以第一转发板在网络设备上电启动后的初始化过程中处于主用状态、第二转发板在网络设备上电起动后的初始化过程中处于备用状态为例，该初始化过程由第一转发板发起初始化流程、并包括以下步骤。
S711，第一转发板对接口板进行板级初始化配置、并在板级初始化配置完成后通知第二转发板开始PCI-E初始化配置。
S712，第一转发板对接口板中的第一PCI-E Endpoint以及第一接收缓存队列和第一发送缓存队列进行PCI-E初始化配置，第二转发板对接口板中的第二PCI-E Endpoint以及第二接收缓存队列和第二发送缓存队列进行PCI-E初始化配置。
S713，第一转发板对接口板的网络接口总线控制器和网络接口芯片进行网络接口配置。
上述流程中由第一转发板和第二转发板执行的操作，可以理解为分别由第一CPU和第二CPU实现。接口板可以通过第一转发板的第一CPU的控制管脚和第二转发板的第二CPU的控制管脚识别第一转发板和第 二转发板的主备状态，
为实现如图7所示的初始化过程中的板级初始化配置，该报文转发方法可以进一步从主用状态的第一或第二转发板的第一或第二PCI-E RC接收第一CPU或第二CPU对接口板的板级初始化配置。
其中，接口板可以进一步通过第一管理总线连接第一转发板的第一CPU、进一步通过第二管理总线连接第二转发板的第二CPU。该报文转发方法进一步包括：
若第一转发板处于主用状态，则通过第一管理总线接收第一转发板的第一CPU对接口板的板级初始化配置；
若第二转发板处于主用状态，则通过第二管理总线接收第二转发板的第二CPU对接口板的板级初始化配置。
对于如图7所示的PCI-E初始化配置可以包括：
第一PCI-E Endpoint、第一接收缓存队列以及第一发送缓存队列可以由第一CPU通过驱动第一PCI-E RC配置；
第二PCI-E Endpoint、第二接收缓存队列以及第二发送缓存队列可以由第二CPU通过驱动第二PCI-E RC配置；
对于网络接口进行接口配置可以包括：当第一转发板为主用转发板时，从第一PCI-E根复合体接收第一CPU对网络接口总线控制器和网络接口芯片的初始化配置；当第二转发板为主用转发板时，从第二PCI-E根复合体接收第二CPU对网络接口总线控制器和网络接口芯片的初始化配置。
需要说明的是，上述各流程和各结构图中不是所有的步骤和模块都是必须的，可以根据实际的需要忽略某些步骤或模块。各步骤的执行顺序不是固定的，可以根据需要进行调整。各模块的划分仅仅是为了便于描述采用的功能上的划分，实际实现时，一个模块可以分由多个模块实 现，多个模块的功能也可以由同一个模块实现，这些模块可以位于同一个设备中，也可以位于不同的设备中。另外，上面描述中采用“第一”、“第二”仅仅为了方便区分具有同一含义的两个对象，并不表示其有实质的区别。
综上所述，权利要求的范围不应局限于以上描述的例子中的实施方式，而应当将说明书作为一个整体并给予最宽泛的解释。

Claims (12)

  1. 一种网络设备，其特征在于，包括：
    第一转发板；
    第二转发板；
    接口板，该接口板具有控制装置和网络接口芯片，该控制装置通过第一I/O总线连接第一转发板、通过第二I/O总线连接第二转发板、以及通过网络接口总线连接网络接口芯片；
    其中，该控制装置将网络接口芯片从网络设备的外部接收到的数据报文形成通过第一I/O总线发送至第一转发板的第一上行数据报文流、以及通过第二I/O总线发送至第二转发板的第二上行数据报文流；
    并且，该控制装置根据第一转发板和第二转发板的主备状态，将通过第一I/O总线接收的第一转发板处理后的第一下行数据报文流和通过第二I/O总线接收的第二转发板处理后的第二下行数据报文流通过网络接口总线与网络接口芯片择一地导通。
  2. 根据权利要求1所述的网络设备，其特征在于，第一I/O总线为第一PCI-E总线，第二I/O总线为第二PCI-E总线，第一转发板具有连接第一PCI-E总线的第一PCI-E根复合体和驱动第一PCI-E根复合体的第一CPU，第二转发板具有连接第二PCI-E总线的第二PCI-E根复合体和驱动第二PCI-E根复合体的第二CPU，并且，控制装置包括：
    连接第一PCI-E总线的第一PCI-E端点；
    连接第二PCI-E总线的第二PCI-E端点；
    连接第一PCI-E端点的第一接收缓存队列和第一发送缓存队列；
    连接第二PCI-E端点的第二接收缓存队列和第二发送缓存队列；
    通过网络接口总线连接网络接口芯片的网络接口总线控制器；
    将网络接口总线控制器分别连接第一接收缓存队列和第二接收缓存 队列的复制驱动器，用于利用第一接收缓存队列形成第一上行数据报文流、利用第二接收缓存队列形成第二上行数据报文流；
    以及，将第一发送缓存队列和第二发送缓存队列择一地连接至网络接口总线控制器的选择切换器，用于使第一下行数据报文流和第二下行数据报文流通过网络接口总线与网络接口芯片择一地导通。
  3. 根据权利要求2所述的网络设备，其特征在于，
    所述第一PCI-E端点、所述第一接收缓存队列以及所述第一发送缓存队列，在网络设备上电启动时的PCI-E初始化过程中，由第一CPU通过驱动第一PCI-E根复合体配置；
    所述第二PCI-E端点、所述第二接收缓存队列以及所述第二发送缓存队列，在网络设备上电启动时的PCI-E初始化过程中，由第二CPU通过驱动第二PCI-E根复合体配置。
  4. 根据权利要求2所述的网络设备，其特征在于，该控制装置进一步包括：
    状态识别模块，用于通过第一CPU的控制管脚和第二CPU的控制管脚记录第一转发板和第二转发板的主备状态；
    选择切换开关，用于根据状态识别模块记录的主备状态，当第一转发板为主用转发板时，将通过第一I/O总线接收的第一转发板处理后的第一下行数据报文流通过网络接口总线与网络接口芯片导通，当第二转发板为主用转发板时，将通过第二I/O总线接收的第二转发板处理后的第二下行数据报文流通过网络接口总线与网络接口芯片导通。
  5. 根据权利要求4所述的网络设备，其特征在于，该控制装置进一步包括：
    网络接口配置模块，用于在网络接口配置过程中，根据状态识别模块记录的主备状态，当第一转发板为主用转发板时，从第一PCI-E根复 合体接收第一CPU对网络接口总线控制器和网络接口芯片的初始化配置；当第二转发板为主用转发板时，从第二PCI-E根复合体接收第二CPU对网络接口总线控制器和网络接口芯片的初始化配置。
  6. 根据权利要求4所述的网络设备，其特征在于，该控制装置进一步包括：
    板级配置模块，通过第一管理总线连接第一CPU、并通过第二管理总线连接第二CPU，用于在网络设备启动时，根据状态识别模块记录的主备状态，当第一转发板为主用转发板时，通过第一管理总线接收第一CPU对接口板的初始化配置，当第二转发板为主用转发板时，通过第二管理总线接收第二CPU对接口板的初始化配置。
  7. 一种用于网络设备中的报文转发方法，其特征在于，该网络设备包括具有网络接口芯片的接口板、通过第一I/O总线连接接口板的第一转发板、以及通过第二I/O总线连接接口板的第二转发板，并且，该报文转发方法包括应用在接口板的如下步骤：
    将网络接口芯片从网络设备的外部接收到的数据报文形成通过第一I/O总线发送至第一转发板的第一上行数据报文流、以及通过第二I/O总线发送至第二转发板的第二上行数据报文流；
    根据第一转发板和第二转发板的主备状态，将通过第一I/O总线接收的第一转发板处理后的第一下行数据报文流和通过第二I/O总线接收的第二转发板处理后的第二下行数据报文流通过网络接口总线与网络接口芯片择一地导通。
  8. 根据权利要求7所述的报文转发方法，其特征在于，第一I/O总线为第一PCI-E总线，第二I/O总线为第二PCI-E总线，第一转发板具有连接第一PCI-E总线的第一PCI-E根复合体和驱动第一PCI-E根复合体的第一CPU，第二转发板具有连接第二PCI-E总线的第二PCI-E根复 合体和驱动第二PCI-E根复合体的第二CPU，接口板具有连接第一PCI-E总线的第一PCI-E端点、连接第二PCI-E总线的第二PCI-E端点、连接第一PCI-E端点的第一接收缓存队列和第一发送缓存队列、连接第二PCI-E端点的第二接收缓存队列和第二发送缓存队列、以及通过网络接口总线连接网络接口芯片的网络接口总线控制器；
    该报文转发方法将网络接口总线控制器从网络接口芯片接收到的数据报文复制、并分别填充至第一接收缓存队列和第二接收缓存队列，以利用第一接收缓存队列形成第一上行数据报文流、利用第二接收缓存队列形成第二上行数据报文流；
    并且，该报文转发方法还包括：将第一发送缓存队列和第二发送缓存队列择一地与网络接口总线控制器导通，以使第一下行数据报文流和第二下行数据报文流通过网络接口总线与网络接口芯片择一地导通。
  9. 根据权利要求8所述的报文转发方法，其特征在于，在网络设备上电启动后的PCI-E初始化过程中，该报文转发方法进一步包括：
    第一PCI-E端点、第一接收缓存队列以及第一发送缓存队列由第一CPU通过驱动第一PCI-E根复合体配置；
    第二PCI-E端点、第二接收缓存队列以及第二发送缓存队列由第二CPU通过驱动第二PCI-E根复合体配置。
  10. 根据权利要求8所述的报文转发方法，其特征在于，该报文转发方法进一步包括：
    通过第一CPU的控制管脚和第二CPU的控制管脚识别第一转发板和第二转发板的主备状态，当第一转发板为主用转发板时，将通过第一I/O总线接收的第一转发板处理后的第一下行数据报文流通过网络接口总线与网络接口芯片导通，当第二转发板为主用转发板时，将通过第二I/O总线接收的第二转发板处理后的第二下行数据报文流通过网络接口 总线与网络接口芯片导通。
  11. 根据权利要求10所述的报文转发方法，其特征在于，在网络接口配置过程中，该报文转发方法进一步包括：
    当第一转发板为主用转发板时，从第一PCI-E根复合体接收第一CPU对网络接口总线控制器和网络接口芯片的初始化配置；当第二转发板为主用转发板时，从第二PCI-E根复合体接收第二CPU对网络接口总线控制器和网络接口芯片的初始化配置。
  12. 根据权利要求10所述的报文转发方法，其特征在于，在网络设备启动时，该报文转发方法进一步包括：
    当第一转发板为主用转发板时，通过第一管理总线接收第一CPU对接口板的初始化配置，当第二转发板为主用转发板时，通过第二管理总线接收第二CPU对接口板的初始化配置。
PCT/CN2016/096633 2015-08-25 2016-08-25 网络设备 WO2017032317A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2018528374A JP6550192B2 (ja) 2015-08-25 2016-08-25 ネットワーク機器
EP16838575.5A EP3343853B1 (en) 2015-08-25 2016-08-25 Network device
US15/753,471 US10432557B2 (en) 2015-08-25 2016-08-25 Network device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510524605.5 2015-08-25
CN201510524605.5A CN106487721B (zh) 2015-08-25 2015-08-25 网络设备和用于网络设备中的报文转发方法

Publications (1)

Publication Number Publication Date
WO2017032317A1 true WO2017032317A1 (zh) 2017-03-02

Family

ID=58099575

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/096633 WO2017032317A1 (zh) 2015-08-25 2016-08-25 网络设备

Country Status (5)

Country Link
US (1) US10432557B2 (zh)
EP (1) EP3343853B1 (zh)
JP (1) JP6550192B2 (zh)
CN (1) CN106487721B (zh)
WO (1) WO2017032317A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109947579A (zh) * 2019-03-22 2019-06-28 中车青岛四方车辆研究所有限公司 轨道车辆通用网络控制器平台及控制方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10761939B1 (en) * 2018-12-13 2020-09-01 Amazon Technologies, Inc. Powering-down or rebooting a device in a system fabric
CN109995681B (zh) * 2019-03-07 2021-03-23 盛科网络（苏州）有限公司 一种单芯片实现双主控主备切换的装置及方法
DE102020117632B4 (de) * 2020-07-03 2022-03-03 Krohne Messtechnik Gmbh Bussystem für eine Prozessanlage
US11829315B2 (en) 2020-12-16 2023-11-28 Samsung Electronics Co., Ltd. Electronic device including a structure in which an insertable device is insertable and method for operating the same
US11892550B2 (en) 2020-12-22 2024-02-06 Samsung Electronics Co., Ltd. Three-dimensional angle of arrival capability in electronic devices
CN113839816B (zh) * 2021-09-23 2024-01-19 新华三信息安全技术有限公司 一种配线装置及其故障切换方法
CN114709205B (zh) * 2022-06-02 2022-09-09 西安紫光国芯半导体有限公司 一种三维堆叠芯片及其数据处理方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1540933A (zh) * 2003-04-23 2004-10-27 华为技术有限公司 业务板接口及与双千兆以太网交换平面互连的方法
US7382724B1 (en) * 2001-11-21 2008-06-03 Juniper Networks, Inc. Automatic switchover mechanism in a network device
CN104283718A (zh) * 2014-10-27 2015-01-14 杭州华三通信技术有限公司 网络设备及用于网络设备的硬件故障诊断方法
CN104410502A (zh) * 2014-10-28 2015-03-11 杭州华三通信技术有限公司 网络设备及用于网络设备的接口板上电初始化方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3608534B2 (ja) 2001-07-18 2005-01-12 日本電気株式会社 パケット交換装置
JP2003087832A (ja) * 2001-09-07 2003-03-20 Matsushita Electric Ind Co Ltd デジタル構内交換機とデジタル専用電話機及びデジタル構内交換システム
ATE290285T1 (de) 2001-10-30 2005-03-15 Cit Alcatel Weiterleitung von ip-paketen für leitweglenkungsprotokole
US6791554B1 (en) * 2001-12-27 2004-09-14 Advanced Micro Devices, Inc. I/O node for a computer system including an integrated graphics engine
US7376760B1 (en) * 2003-02-28 2008-05-20 United Electronic Industries Methods and apparatus to support acquisition of data
CN1996993B (zh) * 2006-01-05 2010-08-04 华为技术有限公司 一种提高背板业务总线利用率的方法和系统
CN1909559B (zh) * 2006-08-30 2010-04-14 杭州华三通信技术有限公司 基于快速外围组件互连的接口板及其切换主控板的方法
CN101977139B (zh) * 2010-07-28 2012-09-05 北京星网锐捷网络技术有限公司 路由转发实现装置、方法及交换设备
US8527666B2 (en) * 2011-02-21 2013-09-03 International Business Machines Corporation Accessing a configuration space of a virtual function
JP6007849B2 (ja) 2013-03-28 2016-10-12 日立金属株式会社 ネットワーク中継装置
JP6155500B2 (ja) * 2014-02-12 2017-07-05 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 中継装置
MY173962A (en) * 2014-03-19 2020-02-28 Intel Corp Method, apparatus and system for single-ended communication of transaction layer packets
CN104301145B (zh) * 2014-10-20 2018-03-23 新华三技术有限公司 网络设备及用于网络设备的控制串口配置方法
CN104601490B (zh) * 2015-02-16 2018-10-09 新华三技术有限公司 网络设备的流控方法和流控装置以及网络设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7382724B1 (en) * 2001-11-21 2008-06-03 Juniper Networks, Inc. Automatic switchover mechanism in a network device
CN1540933A (zh) * 2003-04-23 2004-10-27 华为技术有限公司 业务板接口及与双千兆以太网交换平面互连的方法
CN104283718A (zh) * 2014-10-27 2015-01-14 杭州华三通信技术有限公司 网络设备及用于网络设备的硬件故障诊断方法
CN104410502A (zh) * 2014-10-28 2015-03-11 杭州华三通信技术有限公司 网络设备及用于网络设备的接口板上电初始化方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3343853A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109947579A (zh) * 2019-03-22 2019-06-28 中车青岛四方车辆研究所有限公司 轨道车辆通用网络控制器平台及控制方法
CN109947579B (zh) * 2019-03-22 2021-04-09 中车青岛四方车辆研究所有限公司 轨道车辆通用网络控制器平台及控制方法

Also Published As

Publication number Publication date
JP2018523957A (ja) 2018-08-23
EP3343853B1 (en) 2020-12-16
EP3343853A4 (en) 2018-12-26
US10432557B2 (en) 2019-10-01
EP3343853A1 (en) 2018-07-04
US20180241698A1 (en) 2018-08-23
JP6550192B2 (ja) 2019-07-24
CN106487721A (zh) 2017-03-08
CN106487721B (zh) 2019-10-08

Similar Documents

Publication Publication Date Title
WO2017032317A1 (zh) 网络设备
KR102304678B1 (ko) 베이스보드 관리 컨트롤러(BMC)를 사용하여 NVMe-oF 디바이스를 구성하는 시스템 및 방법
US20190379586A1 (en) Method for Unified Communication of Server, Baseboard Management Controller, and Server
US10747688B2 (en) Low latency retimer
US8843689B2 (en) Concurrent repair of the PCIe switch units in a tightly-coupled, multi-switch, multi-adapter, multi-host distributed system
US10284499B2 (en) Dedicated control path architecture for systems of devices
US9860189B2 (en) Systems and methods to enable network communications for management controllers
US9331922B2 (en) Automatic recover after loss of signal event in a network device
JP5207198B2 (ja) パケットを送受信する装置、プログラムおよびその方法
JP2016076257A5 (zh)
US7502369B2 (en) High speed interface systems and methods
US9606950B2 (en) Verifying runtime switch-over between multiple I/O protocols on shared I/O connection
EP3899740A1 (en) Alternative protocol selection
CN105897623B (zh) 一种数据的传输方法和装置
TW201447595A (zh) 透過 ｅｔｈｅｒｎｅｔ 連接傳送ｐｃｉ ｅｘｐｒｅｓｓ資料的系統和方法
WO2016135919A1 (ja) ストレージ装置
JP5699756B2 (ja) 情報処理装置及び情報処理装置制御方法
CN104536853B (zh) 一种保障双控制器存储设备资源连续可用性的装置
US11061462B2 (en) Remote terminal apparatus enabled to reset a plug-and-play compatible device even fixedly connected without removing the device from the apparatus, control method thereof, computer system, and non-transitory recording medium
TW201506605A (zh) 至少部分接收及／或至少部分發布至少一封包以請求功率消耗狀態之改變的技術
US20150067221A1 (en) Data transfer apparatus and method
WO2015131722A1 (zh) 一种接口卡及控制方法
WO2016197798A1 (zh) 一种实现配置同步的方法、虚拟机及备机
US11960367B2 (en) Peripheral component interconnect express device and operating method thereof
US11757799B2 (en) Line monitor device and network switch

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16838575

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2018528374

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 15753471

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2016838575

Country of ref document: EP