WO2017022122A1 - Récepteur - Google Patents

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Publication number
WO2017022122A1
WO2017022122A1 PCT/JP2015/072364 JP2015072364W WO2017022122A1 WO 2017022122 A1 WO2017022122 A1 WO 2017022122A1 JP 2015072364 W JP2015072364 W JP 2015072364W WO 2017022122 A1 WO2017022122 A1 WO 2017022122A1
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Prior art keywords
detector
signal
amplifier
variable gain
output
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PCT/JP2015/072364
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English (en)
Japanese (ja)
Inventor
圭佑 中村
暁人 平井
正信 平峰
田島　賢一
檜枝　護重
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2017532338A priority Critical patent/JP6260746B2/ja
Priority to PCT/JP2015/072364 priority patent/WO2017022122A1/fr
Publication of WO2017022122A1 publication Critical patent/WO2017022122A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits

Definitions

  • the present invention relates to a receiver that receives a modulated signal.
  • an RSSI (Received Signal Strength Indication) detector is widely used as a receiver circuit of an ASK modulated signal receiver.
  • an envelope of the ASK modulation signal is obtained as an output of the RSSI detector, and the output is used as a baseband signal and demodulated by a demodulator at the subsequent stage.
  • the RSSI detector described in Non-Patent Document 1 As the RSSI detector, the RSSI detector described in Non-Patent Document 1 is disclosed.
  • a combination of an amplifier and a detector connected to the amplifier is connected in five stages, and five detectors are connected to a current adder. .
  • a current-voltage converter is connected after the current adder.
  • the RF signal input to the conventional RSSI detector is amplified by each amplifier having a fixed gain Gv.
  • the detector loaded after the first stage amplifier detects the RF signal output from the first stage amplifier and outputs a direct current according to the signal amplitude output from the amplifier.
  • the second-stage amplifier further amplifies the RF signal.
  • the detector loaded after the second-stage amplifier detects the RF signal output from the second-stage amplifier and outputs a direct current, in the same manner as the first-stage amplifier detector.
  • the subsequent amplifier and detector perform the same operation, and the current adder adds the output currents of the respective detectors, and outputs the sum of the output currents of the detectors to the current converter.
  • the current-voltage converter converts the sum of the output currents of the detector into a voltage and outputs it from the RSSI detector.
  • the detection characteristic of the RSSI detector shows a linear characteristic with respect to the input RF signal, and the detection of the conventional RSSI detector is performed.
  • the range is determined by the sum of the gains of the amplifiers. In the above example, since five amplifiers are connected, the detection range is 5 Gv.
  • An object of the present invention is made in view of such a situation, and is to obtain a receiver capable of detecting a received signal even when an RSSI detector having a saturation region within the detection range is used.
  • the receiver of the present invention switches a gain by a control signal, a variable gain amplifier that amplifies the modulated reception signal, and a dynamic gain that is smaller than the gain of the variable gain amplifier and detects the reception signal amplified by the variable gain amplifier.
  • the saturation region of the first detector is the linear region
  • a controller for outputting a control signal for switching the gain of the variable gain amplifier discontinuously.
  • FIG. 1 is a block diagram showing a configuration example of a receiver according to Embodiment 1 of the present invention.
  • the receiver includes an antenna 1, an RSSI detector 2, a controller 3 (an example of a controller), and a demodulation circuit 4.
  • Antenna 1 is an antenna that receives an ASK modulated signal.
  • a dipole antenna, an aperture antenna, a phased array antenna, or the like is used as the antenna 1.
  • the RSSI detector 2 is a detector that amplifies and detects the ASK modulation signal input from the antenna 1 and outputs the detection signal to the controller 3.
  • the RSSI detector 2 includes a variable gain amplifier 20 (an example of a variable gain amplifier), an amplifier 21 (an example of an amplifier), amplifiers 22 to 24 (an example of a first detector), and detectors 25 to 27 (a second detector). 1), a voltage adder 28 (an example of a voltage adder), and an LPF 29 (an example of a Low Pass Filter low pass filter).
  • the variable gain amplifier 20 is located in the first stage of the RSSI detector 2 and is a variable gain amplifier that switches the gain according to the gain control signal from the controller 3 and amplifies the received signal received by the antenna 1.
  • the input terminal of the variable gain amplifier 20 is connected to the antenna 1, and the output terminal of the variable gain amplifier 20 is connected to the input terminal of the amplifier 21 and the input terminal of the detector 24.
  • the control terminal of the variable gain amplifier 20 is connected to the output terminal of the determination circuit 33 in the controller 3.
  • FIG. 2 is a configuration diagram showing a configuration example of the variable gain amplifier 20 according to the first embodiment of the present invention.
  • the variable gain amplifier 20 includes a differential amplifier 201, a resistor 202, a resistor 203, a capacitor 204, a switch 205, a switch 206, a capacitor 207, a switch 208, a switch 209, and an inverter 210.
  • the differential output terminal pair of the differential amplifier 201 is connected to the input terminals of the resistor 202 and the resistor 203.
  • the output terminals of the resistor 202 and the resistor 203 are a differential output terminal pair of the variable gain amplifier 20.
  • the output terminal of the resistor 202 is connected to one end of the switch 205, the other end of the switch 205 is connected to one end of the capacitor 204, one end of the switch 206 is connected to the other end of the capacitor 204, and the other end of the switch 206. Is connected to the output terminal of the resistor 203.
  • the switch 208, the capacitor 207, and the switch 209 are connected to the differential output terminal pair of the variable gain amplifier 20 in the same connection relationship as the switch 205, the capacitor 204, and the switch 206.
  • the switches 205 and 206 are switches that receive a gain control signal from the control terminal and change the state of the switch.
  • the gain control signal is “H”
  • the switch 205 and the switch 206 are short-circuited
  • the gain control signal is “L”
  • the switch 205 and the switch 206 are open.
  • “H” is a logic signal whose voltage indicates a high level
  • “L” is a logic signal whose voltage indicates a low level.
  • the switch 208 and the switch 209 receive the gain control signal via the inverter 210 and change the state of the switch. Since the inverter 210 is used, when the gain control signal is “H”, the switch 208 and the switch 209 are opened, and when the gain control signal is “L”, they are short-circuited.
  • variable gain amplifier 20 is configured as described above, and the gain is switched by switching the cut-off frequency of the RC circuit composed of the resistors 202 and 203 and the capacitor 204 or the capacitor 207.
  • FIG. 3 is a gain frequency characteristic diagram of the variable gain amplifier 20 according to the first embodiment of the present invention.
  • the vertical axis is gain, and the horizontal axis is frequency.
  • fc1 is a cutoff frequency before gain control (when the gain control signal is “L”)
  • fc2 is a cutoff frequency after gain control (when the gain control signal is “H”).
  • f 0 is the center frequency of the input ASK modulation signal.
  • the gain control signal changes from “L” to “H”
  • the capacitor of the RC circuit is switched from the capacitor 207 to the capacitor 204, and the cutoff frequency of the variable gain amplifier 20 is switched from fc1 to fc2.
  • the gain of the variable gain amplifier 20 is switched from Gv to Gv / 2.
  • the amplifier 21 is an amplifier that further amplifies the signal output from the variable gain amplifier 20.
  • the input terminal of the amplifier 21 is connected to the output terminal of the variable gain amplifier 20, and the output terminal of the amplifier 21 is connected to the input terminal of the amplifier 22 and the input terminal of the detector 25.
  • the reception signal input from the output terminal of the amplifier 20 is amplified by a gain Gv and output to the input terminal of the amplifier 22 and the input terminal of the detector 25.
  • the amplifier 21 is a differential amplifier mounted on an IC using a process such as CMOS (Complementary Metal Oxide Semiconductor).
  • the amplifier 22, the amplifier 23, and the amplifier 24 are amplifiers having the same configuration as the amplifier 21 and further amplifying the signal amplified by the amplifier 21.
  • the detector 24 is a detector that detects the signal output from the variable gain amplifier 20.
  • the input terminal of the detector 24 is connected to the output terminal of the variable gain amplifier 20, and the output terminal of the detector 24 is connected to the input terminal of the voltage adder 28.
  • the detector 24 detects the received signal amplified by the variable gain amplifier 20 and outputs an output voltage corresponding to the logarithm value of the input power to the input terminal of the voltage adder 28.
  • the detector 24 holds a threshold value with respect to the input power, and has a characteristic of being saturated at a predetermined voltage when power exceeding the threshold value is input.
  • FIG. 4 is a detection characteristic diagram of the detector 24 according to the first embodiment of the present invention.
  • the vertical axis is the detection voltage (Vdet), and the horizontal axis is the input voltage (Vin).
  • Vin_min is the minimum input voltage that can be detected by the detector 24, and Vin_max is the maximum input voltage at which the detector 24 is not saturated.
  • Vlim is a detection voltage at Vin_max. Between Vin_min and Vin_max, the linear area
  • the linear region refers to a region where the output voltage is linearly proportional to the input power, that is, a region where the first-order differential coefficient of the detection characteristic is larger than other higher-order differential coefficients.
  • the difference between Vin_max and Vin_min corresponds to the dynamic range of the detector 24.
  • the slope of the detection characteristic is determined by the mutual conductance (gm) of the transistors constituting the detector 24.
  • the detector 24 may be a detector or a diode detector configured with a transistor and a resistor mounted on an IC (Integrated Circuit) using a process such as CMOS.
  • the detectors 25 to 27 have the same configuration as the detector 24 and are connected to the output terminals of the amplifiers 21 to 23, respectively.
  • the voltage adder 28 is a voltage adder that adds the detection voltages output from the detector 24, the detector 25, the detector 26, and the detector 27, respectively.
  • the input terminal of the voltage adder 28 is connected to the output terminals of the detector 24, the detector 25, the detector 26, and the detector 27, and the output terminal of the voltage adder 28 is connected to the input terminal of the LPF 29.
  • the voltage adder 28 adds the voltages input from the detectors and outputs the added voltage to the LPF 29.
  • the voltage adder 28 is an operational amplifier mounted on an IC using a process such as CMOS.
  • the LPF 29 is a low-pass filter that blocks unnecessary signals and allows a desired received signal to pass by passing a signal having a frequency equal to or lower than its own cutoff frequency from the detection voltage added by the voltage adder 28.
  • the input terminal of the LPF 29 is connected to the output terminal of the voltage adder 28, and the output terminal of the LPF 29 is connected to the input terminal of the comparator 34 built in the controller 3 and the input terminal of the smoothing circuit 37.
  • the LPF 29 has a cut-off frequency and cuts a frequency component higher than its own cut-off frequency to limit the band of the input signal.
  • the LPF 29 is mounted with a resistor, a capacitor, or the like mounted on an IC using a process such as CMOS.
  • the RSSI detector 2 amplifies the reception signal received by the antenna 1 with the variable gain amplifier 20, the amplifier 21, the amplifier 22, and the amplifier 23, and also includes the detector 24, the detector 25, the detector 26, The detector 27 detects the output signal of each amplifier.
  • the RSSI detector 2 outputs the amplified reception signal to the detector 31 in the controller 3 and outputs the detection signal to the comparator 34 and the smoothing circuit 37.
  • the RSSI detector 2 changes the gain of the variable gain amplifier 20 according to the gain control signal from the controller 3.
  • FIG. 5 is a detection characteristic diagram of the RSSI detector 2 according to the first embodiment of the present invention.
  • the vertical axis is the detection voltage
  • the horizontal axis is the input power.
  • DR is a dynamic range of the detector 24, the detector 25, the detector 26, and the detector 27, and is a linear region.
  • Gv is the gain of the variable gain amplifier 20, the amplifier 21, the amplifier 22, and the amplifier 23.
  • Det1, det2, det3, and det4 are detection ranges of the detector 24, the detector 25, the detector 26, and the detector 27, respectively.
  • the controller 3 determines whether or not at least one of the detectors 24 to 27 is saturated from the detection signal output from the RSSI detector 2, and when at least one of the detectors 24 to 27 is saturated
  • the controller outputs a gain control signal for switching the gain of the variable gain amplifier 20 to the variable gain amplifier 20.
  • the controller 3 includes a detector 31, a comparator 32, a determination circuit 33, a comparator 34 (an example of a comparator), a preamble detector 35, a reference voltage source 36, and a smoothing circuit 37 (an example of a smoothing circuit).
  • the detector 31 is a detector that detects the signal output from the amplifier 23.
  • the input terminal of the detector 31 is connected to the output terminal of the amplifier 23, and the output terminal of the detector 31 is connected to the input terminal of the comparator 32.
  • the detector 31 detects the reception signal amplified by the amplifier 23 and outputs an output voltage corresponding to the logarithmic value of the input power to the input terminal of the comparator 32.
  • the detector 31 may be a detector composed of a transistor and a resistor mounted on an IC using a process such as CMOS, a diode detector, or the like.
  • the comparator 32 is a comparator that compares the detection signal output from the detector 31 with a reference voltage in order to determine whether the received signal input to the RSSI detector 2 is greater than the minimum input power that can be detected. is there.
  • the first input terminal of the comparator 32 is connected to the output terminal of the detector 31, and the second input terminal is connected to the output terminal of the reference voltage source 36.
  • the output terminal of the comparator 32 is connected to the input terminal of the determination circuit 33.
  • the comparator 32 compares the detection voltage of the received signal output from the detector 31 with the reference voltage output from the reference voltage source 36. When the detection voltage is larger than the reference voltage source, the comparator 32 is the lowest that the RSSI detector 2 can detect.
  • the comparator 32 is an operational amplifier mounted on an IC using a process such as CMOS.
  • the determination circuit 33 determines whether the detector in the RSSI detector 2 is saturated within the detection range of the RSSI detector 2 based on the preamble detection signal output from the preamble detector 35 and the detection signal output from the comparator 32. Is a determination circuit that outputs a gain control signal for switching the gain of the variable gain amplifier 20 to the control terminal of the RSSI detector 2.
  • the first input terminal of the determination circuit 33 is connected to the output terminal of the comparator 32, the second input terminal of the determination circuit 33 is connected to the output terminal of the preamble detector 35, and the output terminal of the determination circuit 33 is
  • the RSSI detector 2 is connected to the control terminal of the variable gain amplifier 20 incorporated therein.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • FIG. 6 is a configuration diagram showing a configuration example of the determination circuit 33 according to the first embodiment of the present invention.
  • the determination circuit 33 includes a control circuit 331 and a memory 332.
  • the control circuit 331 is a control circuit that controls a gain control signal output to the RSSI detector 2.
  • the first input terminal of the control circuit 331 is the first input terminal of the determination circuit 33, and the second input terminal of the control circuit 331 is the second input terminal of the determination circuit 33.
  • a memory terminal of the control circuit 331 is connected to the memory 332.
  • the control circuit 331 is a logic circuit mounted on an ASIC or FPGA.
  • the memory 332 is a memory that stores the initial state of the variable gain amplifier 20.
  • the memory 332 stores a gain control signal indicating whether each switch in the variable gain amplifier 20 is open or short before the gain control of the variable gain amplifier 20 is performed.
  • the memory 332 stores that the initial state of the switch 205 and the switch 206 is open, the initial state of the switch 208 and the switch 209 is a short circuit state, and the state is “L” as the gain control signal.
  • the memory 332 is connected to the control circuit 331 and outputs an initial value to the control circuit 331.
  • the memory 332 is a non-volatile memory mounted on an ASIC or FPGA.
  • FIG. 7 is a flowchart of the determination circuit 33 according to the first embodiment of the present invention.
  • the control circuit 331 determines whether or not the RSSI detector 2 can detect the reception signal from the detection signal output from the comparator 31.
  • the detection signal output from the comparator 31 is “H”
  • the control circuit 331 determines that a received signal having a minimum input power that can be detected is input to the RSSI detector 2, and proceeds to step S103.
  • the detection signal output from the comparator 31 is “L”
  • the control circuit 331 receives a received signal less than the minimum input power that can be detected by the RSSI detector 2, and the RSSI detector 2 receives the received signal. It is determined that detection has not been performed, and the process proceeds to step S102.
  • step S102 the control circuit 331 outputs a control signal indicating the initial state of the variable gain amplifier 20 stored in the memory 332 to the variable gain amplifier 20, and returns the gain of the variable gain amplifier 20 to the initial state.
  • step S103 the control circuit 331 determines whether or not a preamble signal has been detected from the preamble detection signal output by the preamble detector 35. If the preamble detection signal is “H”, it is determined that the preamble signal has been detected, and the process proceeds to step S104. On the other hand, when the preamble detection signal is “L”, it is determined that the preamble signal has been detected, and the process proceeds to step S105.
  • step S104 the control circuit 331 holds the content of the gain control signal output to the variable gain amplifier 20, and outputs the same gain control signal as before the gain control. For example, when “L” is output as the gain control signal, the control circuit 331 outputs the gain control signal “L” to the variable gain amplifier 20.
  • step 105 the control circuit 331 changes the content of the gain control signal output to the variable gain amplifier 20 and outputs it to the variable gain amplifier 20. For example, when “L” is output as a gain control signal to the variable gain amplifier 20, the control circuit 331 outputs a gain control signal of “H” to the variable gain amplifier 20.
  • the comparator 34 is a comparator that compares the instantaneous value of the detection voltage of the RSSI detector 2 with the time average value of the detection voltage of the RSSI detector 2 output from the smoothing circuit 37 and outputs a comparison result.
  • the first input terminal of the comparator 34 is connected to the LPF 29 built in the RSSI detector 2, and the second input terminal is connected to the output terminal of the smoothing circuit 37.
  • the output terminal of the comparator 34 is connected to the input terminal of the preamble detector 35 and the input terminal of the demodulation circuit 4.
  • the comparator 34 compares the instantaneous value of the detection signal output from the LPF 29 with the time average voltage of the detection signal output from the smoothing circuit 37.
  • the comparator 34 compares "H". If it is smaller than the voltage, “L” is output as a baseband signal to the input terminal of the preamble detector 35 and the input terminal of the demodulation circuit 4.
  • the comparator 34 is an operational amplifier mounted on an IC using a process such as CMOS.
  • the baseband signal is a signal obtained by digitizing the detection signal output from the RSSI detector 2.
  • the preamble detector 35 is a detector that detects a preamble signal included in the baseband signal output from the comparator 34.
  • the input terminal of the preamble detector 35 is connected to the output terminal of the comparator 34, and the output terminal of the preamble detector 35 is connected to the input terminal of the determination circuit 33 and the input terminal of the demodulation circuit 4.
  • the preamble detector 35 extracts a preamble signal from the baseband signal output from the comparator 34 using an internal clock extraction circuit, and the extracted preamble signal matches the data pattern of the preamble signal stored therein.
  • “H” is output to the determination circuit 33 and the demodulation circuit 4 as a preamble detection signal.
  • “L” is output to the determination circuit 33 and the demodulation circuit 4 as the preamble detection signal.
  • the preamble detector 35 is configured by ASIC or FPGA.
  • FIG. 8 is a configuration diagram showing a configuration example of the preamble detector 35 according to the first embodiment of the present invention.
  • the preamble detector 35 includes a clock extraction circuit 351, a shift register 352, a memory 353, and a comparator 354.
  • the clock extraction circuit 351 is a clock extraction circuit that extracts a baseband signal clock based on the edge of the baseband signal output from the comparator 34.
  • the input terminal of the clock extraction circuit 351 is connected to the input terminal of the preamble detector 35, and the output terminal of the clock extraction circuit 351 is connected to the clock terminal of the shift register 352.
  • the clock extraction circuit 351 is configured by a logic circuit on an ASIC or FPGA.
  • the shift register 352 uses the clock signal output from the clock extraction circuit 351 to sample and hold the baseband signal output from the comparator 34 bit by bit, and outputs the sampled and held result in parallel to the comparator 354 bit by bit. Shift register.
  • the input terminal of the shift register 352 is connected to the input terminal of the preamble detector 35, and the clock terminal of the shift register 352 is connected to the output terminal of the clock extraction circuit 351.
  • the shift register 352 includes an N-bit output terminal, and the N-bit output terminal is connected to the input terminal of the comparator 354.
  • the memory 353 is a memory in which preamble data included in the received signal is stored in advance.
  • the memory 353 has N-bit output terminals, and these output terminals are connected to the comparator 354 input terminal.
  • the memory 353 stores binary preamble data, and outputs the preamble data to the comparator 354 in parallel in 1-bit units.
  • the comparator 354 is a comparator that compares the preamble data stored in the memory 353 and the sample hold result of the baseband signal output from the shift register 352.
  • the comparator 354 has a 2 ⁇ N (N is a natural number) bit input terminal, one N-bit input terminal is connected to the memory 353, and the other N-bit input terminal is a shift register 352. Is connected to the output terminal.
  • the comparator 354 performs exclusive OR operation on the N-bit preamble data output from the memory 353 and the sample-and-hold result of the N-bit baseband signal output from the shift register 351 one bit at a time. Judge whether or not. When N bits match, “H” is output to the determination circuit 33, and when they do not match, “L” is output to the determination circuit 33.
  • the reference voltage source 36 is a reference voltage source that outputs a reference voltage to the comparator 32.
  • the output terminal of the reference voltage source 36 is connected to the input terminal of the comparator 32.
  • the reference voltage source 36 is set in advance so as to output a voltage equal to the detection voltage output by the detector 31 when the RSSI detector 2 receives the signal of the lowest input power, and the voltage is compared with the comparator. 32.
  • the reference voltage source 36 is configured using a fixed current source and a resistor mounted on an IC using a process such as CMOS.
  • the smoothing circuit 37 is a smoothing circuit that averages the detection signal of the RSSI detector 2 output from the LPF 29 with a predetermined time constant for smoothing.
  • the input terminal of the smoothing circuit 37 is connected to the LPF 29 built in the RSSI detector 2, and the output terminal of the smoothing circuit 37 is connected to the input terminal of the comparator 34.
  • the smoothing circuit 37 time averages the detection signal with a predetermined time constant by passing a signal in a frequency band lower in frequency than the ASK modulation signal component in the detection signal among the signals output from the LPF 29.
  • the detection signal is output to the comparator 34.
  • the time constant of the smoothing circuit 37 corresponds to the reciprocal of the cutoff frequency of the smoothing circuit 37.
  • the smoothing circuit 37 is configured by a low-pass filter using a resistor and a capacitor.
  • the ASK modulation signal input to this receiver is composed of a preamble signal and a communication data signal.
  • the preamble signal is a signal that is ASK-modulated with predetermined N-bit pattern data.
  • the communication data signal is a signal obtained by ASK modulation of data to be communicated, and is transmitted after the preamble signal.
  • the antenna 1 receives the ASK modulated signal and outputs the received ASK modulated signal to the RSSI detector 2.
  • the RSSI detector 2 outputs the ASK modulation signal amplified by the variable gain amplifier 20, the amplifier 21, the amplifier 22, and the amplifier 23 to the detector 31.
  • the detector 31 detects the ASK modulation signal and outputs a detection voltage to the comparator 32.
  • the comparator 32 compares the detection voltage output from the detector 31 with the reference voltage output from the reference voltage source 36.
  • the reference voltage output from the reference voltage source 36 is the lowest received voltage of the RSSI detector 2.
  • the comparator 32 outputs “H” to the determination circuit 33 when the detection voltage is higher than the minimum reception voltage, and “L” when the detection voltage is lower than the minimum reception voltage.
  • the RSSI detector 2 outputs a detection signal to the comparator 34 and the smoothing circuit 34 of the controller 3.
  • the variable gain amplifier 20 in the RSSI detector 2 amplifies the ASK modulation signal output from the antenna 1 and outputs the amplified ASK modulation signal to the amplifier 21.
  • the logic of the control terminal of the variable gain amplifier 20 is “L”
  • the switches 205 and 206 built in the amplifier 20 are open, and the switches 208 and 209 are short-circuited.
  • the RC circuit composed of the resistors 202 and 203 and the capacitor 207 determines the frequency characteristics of the amplifier 20, and the cut-off frequency is set so that the gain in the frequency band of the ASK modulation signal becomes Gv.
  • the ASK modulation signal amplified by the variable gain amplifier 20 is further amplified by the amplifier 21, the amplifier 22 and the amplifier 23 to be amplified to the power at which the detector 27 reacts.
  • the power of the received signal input to the RSSI detector 2 is the lowest input power of the RSSI detector 2, the detector 24, the detector 25, and the detector 26 do not react because the input power is small, and each detector The output of the device is 0V. Therefore, the output voltage of the detector 27 is input to the voltage adder 28, and the voltage adder 28 outputs the output voltage to the LPF 29 as it is.
  • the LPF 29 blocks unnecessary components from the voltage signal output from the voltage adder 28 and allows the signal components to pass therethrough.
  • the LPF 29 outputs the band-limited signal to the comparator 34 and the smoothing circuit 37.
  • the smoothing circuit 37 cuts off a signal having a frequency higher than the cut-off frequency of the smoothing circuit 37 and passes a signal having a frequency lower than the cut-off frequency, thereby averaging and smoothing the signal output from the LPF 29.
  • the smoothing circuit 37 outputs the smoothed signal to the comparator 34.
  • the comparator 34 compares the instantaneous voltage of the detection signal output from the LPF 29 with the time average voltage of the detection signal output from the smoothing circuit 37, and if it is higher than the average voltage, "H” is used, and if it is lower, "L” is used as the baseband.
  • the signal is output to the preamble detector 35 and the demodulation circuit 4 as a signal.
  • the preamble detector 35 extracts a clock from the baseband signal output from the comparator 34, and samples and holds the baseband signal using the clock.
  • the preamble detector 35 compares the result of the sample and hold with the pattern data of the preamble signal read from the built-in memory, and determines whether or not the preamble signal is included in the baseband signal. When there is no interference wave, the result of the sample hold matches the pattern data of the preamble signal read from the memory, so the preamble detector 35 outputs “H” as the preamble detection signal to the demodulation circuit 4 and the determination circuit 33. To do.
  • the demodulation circuit 4 starts when the preamble detection signal is input, and then demodulates the baseband signal input at a predetermined time.
  • the determination circuit 33 receives the signal “H” output from the comparator 32 and the signal “H” output from the preamble detector 35. Based on the two signals, the determination circuit 33 determines whether or not a signal equal to or higher than the lowest received signal is input to the RSSI detector 2 and whether or not a preamble signal can be detected, and determines the gain control signal as a variable gain. Output to the amplifier 20. Since the signal output from the comparator 32 is “H” and the signal output from the preamble detector 35 is “H”, the determination circuit 33 receives a signal equal to or higher than the lowest received signal in the RSSI detector 2. Therefore, the preamble detector 35 determines that the preamble signal can be detected without the influence of the interference wave, and holds the content of the gain control signal. Therefore, the determination circuit 33 outputs a gain control signal “L” that does not change the gain to the variable gain amplifier 20. It is assumed that the variable gain amplifier 20 has a configuration corresponding to the gain control signal “L” in the initial state.
  • the antenna 1 receives the interference wave together with the ASK modulation signal, and outputs the received signal to the RSSI detector 2.
  • FIG. 9 is a diagram showing detection characteristics and operating points of the RSSI detector 2 according to Embodiment 1 of the present invention.
  • the vertical axis is the detection voltage, and the horizontal axis is the input power.
  • the dotted line is the detection characteristic before gain control, and the solid line is the detection characteristic after gain control.
  • a portion surrounded by a dotted line is a saturation region before gain control, and a hatched portion is a saturation region after gain control.
  • DR is the dynamic range of the detector 24, the detector 25, the detector 26, and the detector 27, and Gv is the gain of the variable gain amplifier 20, the amplifier 21, the amplifier 22, and the amplifier 23.
  • DET4, DET3, DET2, and DET1 correspond to the detector 24, the detector 25, the detector 26, and the detector 27, respectively.
  • Point A indicates the operating point of the RSSI detector 2. Note that the power of the received signal at point A is the sum of the power of the ASK modulated signal and the power of the interference wave.
  • the detector 27 When the RSSI detector 2 is operating at the point A on the dotted line in FIG. 9, the detector 27 is saturated. This occurs because the dynamic range of the detector 27 is smaller than the gain of the variable gain amplifier 20. When the detector 27 in the RSSI detector 2 operates in the saturation region, detection is performed in a region where the nonlinearity of the detector 27 is strong, so that the detection signal includes intermodulation distortion. A detection signal including distortion is output to the voltage adder 28.
  • the voltage adder 28 adds the detection signals of the detector 24, the detector 25, the detector 26, and the detector 27, but only the detector 27 detects the received power at the point A in FIG.
  • the adder 28 outputs the detection signal of the detector 27 to the LPF 29 as it is.
  • the LPF 29 blocks a component having a frequency higher than its own cutoff frequency, but intermodulation distortion having a frequency lower than the cutoff frequency passes through the LPF 29 and is output to the comparator 34 and the smoothing circuit 37.
  • the output signal of the LPF 29 includes an interference wave and a detection signal of the ASK modulation signal.
  • the smoothing circuit 37 averages and smoothes the detection signal that has passed through the LPF 29.
  • the smoothing circuit 37 outputs the time averaged detection signal to the comparator 34. Since the smoothing circuit 37 passes a frequency lower than its own cutoff frequency, if the frequency of the interference wave detection signal is lower than the cutoff frequency, the interference wave detection signal is output to the comparator 34.
  • the cutoff frequency of the smoothing circuit 37 is lower than the frequency of the detection signal of the ASK modulation signal and higher than the frequency of the detection signal of the interference wave. Therefore, the output signal of the smoothing circuit 37 does not include the detection signal of the ASK modulation signal, but includes the detection signal of the interference wave.
  • the comparator 34 compares the instantaneous voltage of the detection signal output from the LPF 29 with the time average voltage of the detection signal output from the smoothing circuit 37. If the instantaneous voltage is higher than the time average voltage, the comparator 34 compares "H". "Is output to the preamble detector 35 and the demodulation circuit 4 as a baseband signal. The comparator 34 compares the ASK modulation signal and the interference wave detection signal output from the LPF 29 with the interference wave detection signal output from the smoothing circuit 37. Therefore, the output signal of the comparator 34 includes an interference wave component. Not included. That is, if the interference wave is CW (Continus Wave) or a modulation signal narrower than the modulation band of the ASK modulation signal, the interference wave component is not output to the comparator 34 and thereafter.
  • CW Continuous Wave
  • the baseband signal output from the comparator 34 includes not only an ASK modulation signal component but also an intermodulation distortion component. Therefore, chattering due to intermodulation distortion is observed in the time waveform of the input baseband signal in the preamble detector 35. Due to this chattering, the preamble detector 35 samples and holds erroneous data when the baseband signal is sampled and held. The preamble detector 35 compares the preamble signal obtained as a result of the sample and hold with the pattern data of the preamble signal stored in the memory. Here, since an interference wave exists and the RSSI detector 2 operates in the saturation region and the two do not match, the preamble detector 35 outputs the preamble detection signal “L” to the determination circuit 33 and the demodulation circuit 4. To do.
  • the RSSI detector 2 outputs the amplified ASK modulation signal to the detector 27 and outputs the amplified ASK modulation signal to the detector 31.
  • the detector 31 detects the ASK modulation signal and outputs a detection voltage to the comparator 32.
  • the comparator 32 compares the detection voltage output from the detector 31 with the reference voltage output from the reference voltage source 36. Since the point A in FIG. 9 is higher than the minimum reception voltage of the RSSI detector 2, the comparator 32 outputs “H” to the determination circuit 33.
  • the determination circuit 33 receives “H” from the comparator 32 and “L” from the preamble detector 35. According to the flow of FIG. 7, the determination circuit 33 determines that the input power of the RSSI detector 2 has been detected in step S101, and proceeds to step S103. In step S103, the determination circuit 33 determines that the preamble signal has not been detected because the output signal of the preamble detector 35 is "L", and proceeds to step S105. In step S ⁇ b> 105, the determination circuit 33 changes the content of the gain control signal from “L” to “H” and outputs it to the variable gain amplifier 20.
  • the variable gain amplifier 20 changes the switch state according to the gain control signal and changes the gain. Since the gain control signal is changed from “L” to “H”, the switch 205 and the switch 206 incorporated in the variable gain amplifier 20 change from the open state to the short-circuit state. Similarly, the switch 208 and the switch 209 change from the short-circuit end state to the open state. As a result, the output circuit of the differential amplifier 201 is changed from the RC circuit configured by the resistor 202, the resistor 203, and the capacitor 207 to the RC circuit configured by the resistor 202, the resistor 203, and the capacitor 204. The gain of the variable gain amplifier 20 changes. Here, the capacitor 207 and the capacitor 204 have different capacities.
  • the gain of the variable gain amplifier 20 changes from Gv to Gv / 2 at the frequency of the ASK modulation signal.
  • the detection characteristic of the RSSI detector 2 changes as shown in FIG.
  • the RSSI detector 2 shifts the saturation region of the RSSI detector 2 to be a linear region by changing the gain of the variable gain amplifier 20 that is the first stage amplifier of the RSSI detector 2.
  • the point A in FIG. 9 is the saturation region before the gain control, but changes to the linear region after the gain control.
  • the RSSI detector 2 can detect the received signal without being saturated at the point A, and no intermodulation distortion occurs in the detected signal.
  • the detector 27 of the RSSI detector 2 outputs a detection signal to the voltage adder 28.
  • the subsequent operation is the same as the operation when there is no interference wave. Since chattering observed in the time waveform of the baseband signal is alleviated, the preamble detector 35 can detect the preamble signal, and the demodulation circuit 4 can demodulate the baseband signal.
  • the determination circuit 33 determines whether the RSSI detector 2 is saturated from the detection signal output by the preamble detector 35, and determines that it is saturated. In this case, since the gain of the variable gain amplifier 20 in the RSSI detector 2 is changed, even if the RSSI detector 2 is saturated within the detection range due to the interference wave, the RSSI detector 2 shifts the saturation region and receives the received signal. Can receive. For this reason, the receiver of Embodiment 1 can be used as a detector of a receiver even with an RSSI detector having a dynamic range of the detector smaller than the gain of the amplifier. Therefore, it is not necessary to use a detector with large power consumption in order to widen the dynamic range of the detector, and the power consumption of the RSSI detector 2 and the receiver can be reduced.
  • the gain change amount of the variable gain amplifier 20 is set to Gv / 2. However, if the gain change amount is greater than or equal to Gv-DR and less than or equal to Gv, the received signal can be received by shifting the saturation region. If the gain change amount is Gv-DR, the detection characteristic is shifted by the saturation region, so the portion that was the saturation region before gain control is replaced with the linear region after gain control, and the received signal is detected in the linear region. Can do.
  • the gain of the variable gain amplifier 20 in the frequency band of the ASK modulation signal is controlled, but the gain of the variable gain amplifier 20 in the frequency band of the interference wave may be controlled.
  • the controller 3 When the frequency of the interference wave that affects the system is specified and the power of the interference wave is larger than the ASK modulation signal, it is effective for the controller 3 to control the gain at the frequency of the interference wave. Thereby, even if the operating point of the detector 27 is determined not by the power of the ASK modulation signal but by the power of the interference wave, the detector 27 can detect by shifting the saturation region.
  • the gain control in the frequency band of the interference wave is effective when the power of the interference wave is large when the gain in the frequency band of the ASK modulation signal of the variable gain amplifier 20 is different from the gain in the frequency band of the interference wave.
  • FIG. 10 is a diagram showing an example of gain control during intermittent operation according to Embodiment 1 of the present invention.
  • the solid line is the gain characteristic of the receiver of the present invention, and the broken line is the gain characteristic of the receiver using an AGC (Automatic Gain Control) circuit.
  • AGC Automatic Gain Control
  • the polling signal is a signal having periodicity generated based on a highly accurate clock signal, and is used for the purpose of reducing power consumption.
  • An accurate clock signal is generated by, for example, a crystal oscillator.
  • the gain of the variable gain amplifier 20 is changed to a gain that can detect the preamble signal while continuously changing the gain.
  • the AGC circuit since the AGC circuit has a time constant in the built-in feedback circuit, it takes time to converge the gain control amount. Therefore, if a data signal is transmitted while the gain control amount is converged, the data signal cannot be received with a gain that does not saturate the detector in the receiver, and the data signal cannot be demodulated. That is, in a system that performs intermittent operation, the AGC circuit cannot cope with intermittent operation, and it takes time to receive a data signal.
  • the receiver inverts the logic of the gain control signal, and does not require a convergence operation by feedback control, and switches the gain of the variable gain amplifier 20 discontinuously.
  • the detection region of the detector is switched from the saturation region to the linear region.
  • the receiver does not need to wait for a convergence response and can receive a signal within a predetermined period.
  • switching the gain discontinuously means switching the gain to a predetermined value when a certain condition is satisfied.
  • This receiver does not continuously switch the gain corresponding to the magnitude of a certain observation signal (for example, a signal indicating the power level of the interference wave) like an AGC circuit, but a threshold value with a magnitude of the observation signal.
  • the gain of the variable gain amplifier 20 is switched to a predetermined value.
  • the variable amplifier 20 is an amplifier whose gain can be controlled by a digital signal
  • the control signal output from the controller 3 indicates the gain of the variable amplifier 20
  • the controller 3 determines that the variable amplifier 20 has been determined in advance.
  • a control signal indicating the gain may be output.
  • Embodiment 2 In the receiver according to the first embodiment of the present invention, by comparing the preamble pattern of the preamble signal included in the detection signal of the RSSI detector 2 with the pattern stored in advance, the detector in the RSSI detector 2 is It was determined whether or not it was in the saturation region. In the receiver according to the second embodiment of the present invention, it is determined whether or not the detector in the RSSI detector 2 is in the saturation region by detecting the intermodulation distortion included in the detection signal of the RSSI detector 2. Thereby, it is not necessary to detect a preamble pattern, and it can be determined whether the detector is in a saturated state at high speed.
  • FIG. 11 is a block diagram showing a configuration example of a receiver according to Embodiment 2 of the present invention. 11, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.
  • the comparator 34 outputs the output signal not only to the preamble detector 35 but also to the interference wave detector 38.
  • the interference wave detector 38 outputs an output signal to the determination circuit 33, and the determination circuit 33 outputs a gain control signal based on the output signal of the interference wave detector 38.
  • the variable gain amplifier 40 is loaded instead of the variable gain amplifier 20, and the detector 30 is connected to the input stage of the variable gain amplifier 40.
  • the interference wave detector 38 is a detector that detects intermodulation distortion of the detector from the baseband signal output from the comparator 34.
  • the input terminal of the interference wave detector 38 is connected to the output terminal of the comparator 34, and the output terminal of the interference wave detector is connected to the input terminal of the determination circuit 33.
  • FIG. 12 is a configuration diagram showing a configuration example of the interference wave detector 38 according to Embodiment 2 of the present invention.
  • the interference wave detector 38 includes an HPF (High Pass Filter) 381, a detector 382, a reference voltage source 383, and a comparator 384.
  • the input terminal of the HPF 381 is an input terminal of the interference wave detector, and the output terminal of the HPF 381 is connected to the input terminal of the detector 382.
  • the output terminal of the detector 382 is connected to the first input terminal of the comparator 384.
  • the second input terminal of the comparator 384 is connected to the output terminal of the reference voltage source 383.
  • the output terminal of the comparator 384 is connected to the output terminal of the interference wave detector 38.
  • the HPF 381 blocks the signal component of the baseband signal output from the comparator 34, passes the intermodulation distortion component, and outputs the signal to the detector 382.
  • the detector 382 detects intermodulation distortion from the signal output from the HPF 381 and outputs the detected signal to the comparator 384 at the subsequent stage.
  • the reference voltage source 383 outputs to the comparator 384 a voltage indicating the level of intermodulation distortion that does not affect the demodulation. That is, the reference voltage source 383 outputs a voltage indicating a reference that can be demodulated even if intermodulation distortion exists if the voltage is equal to or lower than this voltage.
  • the comparator 384 compares the intermodulation distortion detection signal output from the detector 382 with the reference voltage output from the reference voltage source 383. If the detection signal is higher than the reference voltage, the comparator 384 indicates “H”, and the detection signal indicates the reference voltage. If it is lower, “L” is output to the determination circuit 33.
  • the comparator 384 uses an operational amplifier mounted on an IC using a process such as CMOS.
  • the variable gain amplifier 40 is a variable gain amplifier that switches the gain according to the gain control signal from the determination circuit 33.
  • FIG. 13 is a configuration diagram showing a configuration example of the variable gain amplifier 40 according to the second embodiment of the present invention.
  • the variable gain amplifier 40 includes a differential amplifier 401, an attenuator 402, a switch 403, a switch 404, a switch 405, a switch 406, and an inverter 407.
  • the input terminal pair of the differential amplifier 401 is connected to the output terminal pair of the switch 404.
  • An output terminal pair of the differential amplifier 401 is an output terminal of the variable gain amplifier 40.
  • the input terminal pair of the switch 404 is connected to the output terminal pair of the attenuator 402, and the control terminal of the switch 404 is connected to the control terminal of the variable gain amplifier 40.
  • the input terminal pair of the attenuator 402 is connected to the switch 403 output terminal pair, and the output terminal pair of the attenuator 402 is connected to the input terminal pair of the switch 404.
  • the attenuator 402 attenuates the input signal and outputs it to the differential amplifier 401.
  • the attenuation amount of the attenuator 402 is 1/3 ⁇ Gv.
  • the switch 403 output terminal pair is connected to the input terminal pair of the attenuator 402.
  • the switch 403 input terminal pair is an input terminal of the variable amplifier 40.
  • the control terminal of the switch 403 is connected to the control terminal of the variable gain amplifier 40.
  • the switch 405 and the switch 406 are connected in series.
  • the input terminal pair and the output terminal pair of the switches 405 and 406 connected in series are connected to the input terminal pair of the switch 402 and the differential amplifier 401 so as to bypass the switch 403, the attenuator 402, and the switch 404, respectively. Connected to the input terminal pair.
  • the input terminal of the inverter 407 is connected to the control terminal of the variable gain amplifier 40, and the output terminal of the inverter 407 is connected to the control terminals of the switch 405 and the switch 406.
  • the switch 405 and the switch 406 are short-circuited because the inverter 407 inverts the logic, and the switch 403 and the switch 404 are opened. Therefore, the signal input to the variable gain amplifier 40 is input to the differential amplifier 401 without passing through the attenuator 402, amplified by the differential amplifier 401, and the amplified signal is output.
  • the switch 405 and the switch 406 are opened, and the switch 403 and the switch 404 are short-circuited. Therefore, the signal input to the variable gain amplifier 40 passes through the attenuator 402, is input to the differential amplifier 401, is amplified by the differential amplifier 401, and the amplified signal is output. Since the signal passes through the attenuator 402, the gain of the variable gain amplifier 40 becomes lower than when the gain control signal is “L”.
  • FIG. 14 is a gain frequency characteristic diagram of the variable gain amplifier 20 according to the second embodiment of the present invention.
  • the vertical axis is gain, and the horizontal axis is frequency.
  • the dotted line indicates the gain before gain control, and the solid line indicates the gain after gain control.
  • the variable gain amplifier 40 switches the gain from Gv to 2/3 ⁇ Gv by switching the signal path according to the gain control signal input to the control terminal.
  • Embodiment 2 The operation of the receiver according to Embodiment 2 will be described. A description of the same parts as those in the first embodiment will be omitted, and a description will be made mainly on parts having different operations.
  • FIG. 15 is a detection characteristic diagram of the RSSI detector 2 according to Embodiment 2 of the present invention.
  • the vertical axis is the detection voltage, and the horizontal axis is the input power.
  • the detector 30 is added to the input terminal of the variable gain amplifier 40, so that in FIG. 15, the detection range of the RSSI detector 2 is larger by the area of DET 0 than in FIG. 2.
  • DET 0 corresponds to the dynamic range of the detector 30.
  • the antenna 1 outputs the input ASK modulation signal and interference wave to the variable gain amplifier 40 of the RSSI detector 2.
  • the logic of the control input terminal of the amplifier 40 is “L”, and the gain is Gv.
  • a signal of power indicated by a point A in FIG. 15 is input from the antenna 1 to the RSSI detector 2.
  • the ASK modulation signal amplified by the variable gain amplifier 40 is amplified by the amplifier 21, the amplifier 22, and the amplifier 23 in the subsequent stage.
  • the final stage amplifier 23 outputs the amplified signal to the detector 27 and the detector 31. Since the operation of the detector 31, the reference voltage source 36, and the comparator 32 is the same as that of the first embodiment, the description thereof is omitted.
  • the detector 27 detects the signal output from the amplifier 23 and outputs the detection signal to the voltage adder 28. Since only the detector 27 (DET4) reacts at the point A in FIG. 15, nothing is added by the voltage adder 28, and the detection signal of the detector 27 is output to the LPF 29 as it is.
  • the LPF 29 blocks a signal having a frequency higher than its cut-off frequency from the detection signal, and outputs the band-limited detection signal to the comparator 34 and the smoothing circuit 37.
  • the smoothing circuit 37 time averages the output signal of the LPF 29 and outputs the time averaged signal to the comparator 34.
  • the comparator 34 compares the output signal of the LPF 29 and the output signal of the smoothing circuit 37. If the output signal of the LPF 29 is higher than the output signal of the smoothing circuit 37, the comparator 34 outputs “H”. If it is lower than the signal, “L” is output as a baseband signal to the interference wave detector 38, the preamble detector 35 and the demodulation circuit 4.
  • the baseband signal output from the comparator 34 includes the intermodulation distortion of the detector 27.
  • the interference wave detector 38 detects the intermodulation distortion from the output signal of the comparator 34, and determines whether or not the level affects the demodulation. When the detected level of intermodulation distortion is higher than the output voltage of the reference voltage source 383, the interference wave detector 38 outputs “H” to the determination circuit 33.
  • the determination circuit 33 determines the gain control signal output to the variable gain amplifier 40 based on the signal output from the comparator 32 and the output signal from the interference wave detector 38. Basically, the determination circuit 33 determines the gain control signal according to the flowchart shown in FIG. 7, but in the second embodiment, in step 103 of FIG. 7, “detect the preamble signal” to “detect the intermodulation distortion”. To read and execute. Since the signal output from the comparator 32 is “H” and the output signal from the interference wave detector 38 is “H”, the gain control signal “H” is output to the variable gain amplifier 40.
  • the variable gain amplifier 40 switches the path through which the signal passes in accordance with the gain control signal “H”, and lowers the gain.
  • the gain control signal changes from “L” to “H”
  • the input signal passes through the attenuator 402, so that the gain of the variable gain amplifier 40 changes from Gv to 2/3 ⁇ Gv.
  • the RSSI detector 2 detects the received signal in the linear region with the saturation region shifted as shown in FIG. Thereby, since the RSSI detector 2 detects a signal in a linear region, the generation amount of intermodulation distortion can be reduced.
  • the subsequent operation is the same as that of the first embodiment, the description thereof is omitted. Since the RSSI detector 2 can detect the received signal while suppressing the intermodulation distortion caused by the interference wave, the receiver can demodulate the detected signal while suppressing the adverse effect due to the intermodulation distortion.
  • the interference wave detector 38 detects the intermodulation distortion included in the detection signal, and the determination circuit 33 determines the saturation state of the RSSI detector 2 from the detection signal, and is saturated. In this state, the gain of the variable gain amplifier 40 is switched, and the saturation region of the detection characteristic in the RSSI detector 2 is shifted to the linear region. Therefore, even if an interference wave is included in the received signal, the gain region has a good detection characteristic. The received signal can be detected. As a result, the receiver of the second embodiment can be used as a detector for a receiver even if it is an RSSI detector whose dynamic range is lower than the gain of the amplifier. Further, the receiver of the second embodiment can determine the saturation state of the detector even if the received signal does not include a preamble signal.
  • variable gain amplifier 40 switches the gain depending on whether or not the attenuator 402 is bypassed, the gain can be changed while the frequency characteristic of the gain is flat. That is, the variable gain amplifier 40 does not change the difference between the gain for the frequency of the ASK modulated signal and the gain for the frequency of the interference wave before and after gain control.
  • the gain with respect to the frequency of the interference wave is controlled. After the gain control, the gain with respect to the frequency of the ASK modulation signal increases, Even if the operating point of the detector is determined by the electric power and the gain is controlled, there is a problem that it enters the saturation region.
  • variable gain amplifier 40 does not change the frequency characteristic of the gain before and after gain control, the problem can be avoided. Further, since the variable gain amplifier 40 can switch the gain while the frequency characteristic is flat, the operating point of the detector is appropriately moved even for an interference wave whose frequency does not change and the frequency changes with time. be able to.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

L'invention vise à résoudre le problème lié au fait que des récepteurs utilisant des détecteurs d'ondes RSSI ne permettent pas d'élargir la plage de détection d'onde tout en réduisant la consommation d'énergie. Un récepteur selon la présente invention comprend : un amplificateur à gain variable qui modifie un gain d'après un signal de commande, et amplifie un signal de réception modulé ; un premier détecteur d'onde dont la plage dynamique est inférieure au gain de l'amplificateur à gain variable et qui détecte le signal de réception amplifié par l'amplificateur à gain variable ; et un contrôleur qui détermine un état de saturation du premier détecteur d'onde à partir du signal d'onde détecté provenant du premier détecteur d'onde, et qui, si le premier détecteur d'onde est dans un état de saturation, délivre en sortie le signal de commande de sorte à commander la modification discrète du gain de l'amplificateur à gain variable de telle sorte qu'une région de saturation du premier détecteur d'onde soit remplacée par une région linéaire.
PCT/JP2015/072364 2015-08-06 2015-08-06 Récepteur WO2017022122A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107222228A (zh) * 2017-07-18 2017-09-29 上海东软载波微电子有限公司 自动增益控制电路及其控制方法、接收机
CN114221668A (zh) * 2021-12-20 2022-03-22 湖南迈克森伟电子科技有限公司 一种自适应功率的增益控制方法及接收机

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621980A (ja) * 1992-07-03 1994-01-28 Fujitsu Ltd 光信号復調方式
JP2001211125A (ja) * 2000-01-26 2001-08-03 Matsushita Electric Ind Co Ltd 検波回路
WO2003084059A1 (fr) * 2002-03-28 2003-10-09 Thine Electronics, Inc. Circuit integre a semi-conducteur

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621980A (ja) * 1992-07-03 1994-01-28 Fujitsu Ltd 光信号復調方式
JP2001211125A (ja) * 2000-01-26 2001-08-03 Matsushita Electric Ind Co Ltd 検波回路
WO2003084059A1 (fr) * 2002-03-28 2003-10-09 Thine Electronics, Inc. Circuit integre a semi-conducteur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HUNG-WEN LIN ET AL.: "A Low- IF AGC Amplifier for DSRC Receiver", SOC DESIGN CONFERENCE(ISOCC), 2014 INTERNATIONAL, November 2014 (2014-11-01), pages 5 - 6, XP032764439 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107222228A (zh) * 2017-07-18 2017-09-29 上海东软载波微电子有限公司 自动增益控制电路及其控制方法、接收机
CN114221668A (zh) * 2021-12-20 2022-03-22 湖南迈克森伟电子科技有限公司 一种自适应功率的增益控制方法及接收机

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