WO2017008293A1 - 应用于iii-v族衬底的复合栅介质层及其制作方法 - Google Patents

应用于iii-v族衬底的复合栅介质层及其制作方法 Download PDF

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WO2017008293A1
WO2017008293A1 PCT/CN2015/084198 CN2015084198W WO2017008293A1 WO 2017008293 A1 WO2017008293 A1 WO 2017008293A1 CN 2015084198 W CN2015084198 W CN 2015084198W WO 2017008293 A1 WO2017008293 A1 WO 2017008293A1
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layer
passivation layer
substrate
iii
interface
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王盛凯
刘洪刚
孙兵
常虎东
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Institute of Microelectronics of CAS
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Definitions

  • the invention relates to a composite gate dielectric structure applied to a III-V substrate, in particular to a composite gate dielectric layer applied to a III-V substrate and a fabrication method thereof.
  • III-V compound semiconductors represented by InGaAs, InP, InAs, GaAs, GaSb, etc., because they have better electron mobility or hole mobility than silicon, are considered as An important candidate for the fabrication of metal-oxide-semiconductor (MOS) field effect transistors in the Moore Technology era to replace silicon channels.
  • MOS metal-oxide-semiconductor
  • III-V substrate and gate dielectric structures face many challenges in terms of device reliability and device power consumption. Most of the gate dielectric structures so far have the disadvantages of large gate dielectric leakage and poor reliability. How to prepare high reliability, low defect interface state density and ultra-low equivalent oxide thickness gate dielectric structure on the surface of III-V substrate becomes the key technology to realize the application of III-V substrate in logic device of post-molar technology era .
  • the main object of the present invention is to provide a composite gate dielectric layer applied to a III-V substrate and a fabrication method thereof to reduce the interface state density and the boundary trap density, and to increase the III-V MOS channel. Mobility, reducing gate leakage current, and further improving the resistance of the dielectric layer The pressure capability improves the quality of the III-V substrate MOS and enhances its reliability.
  • the present invention provides a composite gate dielectric layer applied to a III-V substrate, comprising: an Al x Y 2-x O 3 interface passivation layer formed over a III-V substrate. And a high dielectric insulating layer formed over the Al x Y 2-x O 3 interface passivation layer; wherein 1.2 ⁇ x ⁇ 1.9.
  • the III-V group substrate comprises a GaAs substrate, an InP substrate, a GaSb substrate, an InAs substrate or an InGaAs substrate and an epitaxial wafer thereof, and the doping concentration thereof is 1 ⁇ 10 15 cm -3 or more. And less than or equal to 5 ⁇ 10 17 cm -3 .
  • the Al x Y 2-x O 3 interface passivation layer has a thickness of 0.4 nm or more and 4 nm or less.
  • the high dielectric insulating layer comprises HfO 2 , ZrO 2 , La 2 O 3 or Y 2 O 3 , and a ternary or multi-component compound obtained by mixing the above four materials, the high dielectric insulation
  • the layer thickness is greater than or equal to 0 nm and less than or equal to 4 nm.
  • the present invention also provides a method for fabricating a composite gate dielectric layer applied to a III-V substrate, comprising:
  • Step 1 cleaning the III-V substrate, and growing an Al 2 O m passivation layer over the III-V substrate, wherein 2.5 ⁇ m ⁇ 3;
  • Step 2 growing a Y 2 O n strengthening layer over the Al 2 O m passivation layer, wherein 2.5 ⁇ n ⁇ 3;
  • Step 3 heat-treated in situ Al 2 O m passivation layer and the reinforcing layer Y 2 O n, m passivation layer and mixing Y 2 O n reinforcing layer of Al 2 O realized to obtain Al x Y 2-x O 3 Interface passivation layer, wherein 1.2 ⁇ x ⁇ 1.9;
  • Step 4 A high dielectric insulating layer is grown on the Al x Y 2-x O 3 interface passivation layer.
  • the Al 2 O m passivation layer is grown on the III-V substrate as described in the step 1, including: using the atomic layer deposition method at the range of 200 ° C to 400 ° C in the III-V group.
  • An Al 2 O m passivation layer having a thickness of d 1 nm is grown over the substrate, wherein 0.2 nm ⁇ d 1 ⁇ 3.8 nm.
  • the flexibility of the O tetrahedral mesh structure increases the rotatable nature of the Al-O tetrahedron in the Al 2 O m passivation layer, thereby achieving passivation of surface defects of the III-V substrate; Al 2 O m passivation layer
  • the higher oxygen content can reduce the leakage of the composite gate dielectric layer and improve reliability.
  • the growing of the Y 2 O n strengthening layer on the Al 2 O m passivation layer in the step 2 includes: using an atomic layer deposition method at 200 ° C to 400 ° C in the Al 2 O m A Y 2 O n strengthening layer having a thickness of d 2 nm is grown over the passivation layer, wherein 0.4 nm ⁇ d 1 + d 2 ⁇ 4 nm.
  • the in-situ annealing treatment was carried out in an atomic layer deposition apparatus at °C.
  • the method realizes mixing of the Al 2 O m passivation layer and the Y 2 O n strengthening layer according to a certain ratio by adjusting the temperature of the in-situ heat treatment, and the mixing ratio is from the Al 2 O m passivation layer thickness d 1 and Y.
  • the method passes through the Al 2 O m passivation layer and the Y 2 O n enhancement layer
  • the Al x Y 2-x O 3 interface passivation layer is mixed to realize the regulation of the average coordination number of the Al x Y 2-x O 3 interface passivation layer of 2.8 to 4.2, thereby satisfying the interface defect density and reliability of various devices.
  • the high dielectric insulating layer is grown on the Al x Y 2-x O 3 interface passivation layer in the step 4, and is formed by atomic layer deposition at 200 ° C - 400 ° C in Al x
  • a high dielectric insulating layer having a thickness of 0 nm or more and 4 nm or less is deposited on the Y 2-x O 3 interface passivation layer.
  • the composite gate dielectric layer for a III-V substrate provided by the present invention and a method for fabricating the same, using an Al x Y 2-x O 3 interface passivation layer, by adjusting the oxygen concentration in the Al 2 O m and Incorporating Y 2 O n , softening the Al 2 O m grid structure, so that there is more twisting freedom between Al-O tetrahedrons, Al x Y 2-x O 3 is easier to be combined with III-V lining
  • the bottom surface defect is bonded to achieve passivation of the interface defect.
  • the interface layer has lower Gibbs system free energy, and ion breakage is not easy to occur under the action of large electrical stress, thereby reducing gate leakage current and improving reliability.
  • FIG. 1 is a schematic structural view of a composite gate dielectric layer applied to a III-V substrate provided by the present invention
  • FIG. 2 is a process flow diagram of the composite gate dielectric layer shown in FIG. 1 provided by the present invention
  • FIG. 3 is a flow chart of a method of fabricating the composite gate dielectric layer of FIG. 1 provided by the present invention.
  • FIG. 1 is a schematic structural view of a composite gate dielectric layer applied to a III-V substrate provided by the present invention, the composite gate dielectric layer comprising: Al formed on the III-V substrate 1 a Y Y 2-x O 3 interface passivation layer 23; and a high dielectric insulating layer 24 formed over the Al x Y 2-x O 3 interface passivation layer 23; wherein 1.2 ⁇ x ⁇ 1.9, Al x Y
  • the 2-x O 3 interface passivation layer 23 and the HfO 2 high dielectric insulating layer 24 constitute a composite gate dielectric layer 2.
  • the III-V substrate 1 may be a GaAs substrate, an InP substrate, a GaSb substrate, an InAs substrate or an InGaAs substrate and an epitaxial wafer thereof, and the doping concentration thereof is 1 ⁇ 10 15 cm or more. -3 and less than or equal to 5 ⁇ 10 17 cm -3 .
  • the thickness of the Al x Y 2-x O 3 interface passivation layer 23 is 0.4 nm or more and 4 nm or less.
  • the high dielectric insulating layer 24 may be HfO 2 , ZrO 2 , La 2 O 3 or Y 2 O 3 , and a ternary or multi-component compound obtained by mixing the above four materials, the thickness of the high dielectric insulating layer 24. It is greater than or equal to 0 nm and less than or equal to 4 nm.
  • FIG. 2 is a process flow diagram of the composite gate dielectric layer shown in FIG. 1 provided by the present invention.
  • the Al x Y 2-x O 3 interface passivation formed on the III-V substrate 1 is known.
  • the layer 23 is obtained by in-situ heat treatment, that is, in-situ annealing treatment, by interdiffusion of the Al 2 O m passivation layer 21 and the Y 2 O n enhancement layer 22.
  • a gate dielectric layer composed of an Al x Y 2-x O 3 interface passivation layer 23 and a HfO 2 high dielectric insulating layer 24 is a composite gate dielectric layer to reduce interface state density and boundary trap density, and increase MOS channel migration. Rate, reduce gate leakage current, and further improve the withstand voltage capability of the dielectric layer, improve the quality and reliability of MOS.
  • FIG. 3 is a flow chart of a method for fabricating the composite gate dielectric layer of FIG. 1 provided by the present invention, the method comprising the following steps:
  • Step 1 cleaning the III-V substrate, and growing an Al 2 O m passivation layer over the III-V substrate, wherein 2.5 ⁇ m ⁇ 3;
  • the Al 2 O m passivation layer is grown on the III-V substrate, including: using an atomic layer deposition method, on the III-V substrate at 200 ° C to 400 ° C.
  • An Al 2 O m passivation layer having a thickness of d 1 nm is grown, wherein 0.2 nm ⁇ d 1 ⁇ 3.8 nm.
  • the flexibility of the lattice structure increases the rotatable nature of the Al-O tetrahedron in the passivation layer of Al 2 O m , thereby achieving passivation of surface defects of the III-V substrate; higher in the Al 2 O m passivation layer
  • the oxygen content can reduce leakage of the composite gate dielectric layer and improve reliability.
  • Step 2 growing a Y 2 O n strengthening layer over the Al 2 O m passivation layer, wherein 2.5 ⁇ n ⁇ 3;
  • the Y 2 O n strengthening layer is grown on the Al 2 O m passivation layer, including: using an atomic layer deposition method, in the Al 2 O m passivation layer at 200 ° C to 400 ° C.
  • a Y 2 O n strengthening layer having a thickness of d 2 nm is grown thereon, wherein 0.4 nm ⁇ d 1 + d 2 ⁇ 4 nm.
  • Step 3 heat-treated in situ Al 2 O m passivation layer and the reinforcing layer Y 2 O n, m passivation layer and mixing Y 2 O n reinforcing layer of Al 2 O realized to obtain Al x Y 2-x O 3 Interface passivation layer, wherein 1.2 ⁇ x ⁇ 1.9;
  • the in-situ heat treatment of the Al 2 O m passivation layer and the Y 2 O n enhancement layer is performed by using an Al 2 O m passivation layer and a Y 2 O n enhancement layer at 200 ° C to 400 ° C in the atom.
  • the in-situ annealing treatment is performed in the layer deposition apparatus.
  • the method realizes mixing of the Al 2 O m passivation layer and the Y 2 O n strengthening layer according to a certain ratio by adjusting the temperature of the in-situ heat treatment, and the mixing ratio is strengthened by the Al 2 O m passivation layer thickness d 1 and Y 2 O n .
  • the ratio d 1 :d 2 of the layer thickness d 2 is determined, wherein 19: 1 ⁇ d 1 :d 2 ⁇ 1:19; the method obtains Al x by mixing the Al 2 O m passivation layer and the Y 2 O n strengthening layer.
  • the Y 2-x O 3 interface passivation layer realizes the regulation of the average coordination number of the Al x Y 2-x O 3 interface passivation layer from 2.8 to 4.2, thereby satisfying the requirements of various devices for interface defect density and reliability.
  • 1.2 ⁇ x ⁇ 1.9 in the Al x Y 2-x O 3 interface passivation layer is a superior result as an interface passivation layer.
  • Step 4 A high dielectric insulating layer is grown on the Al x Y 2-x O 3 interface passivation layer.
  • a high dielectric insulating layer is grown on the Al x Y 2-x O 3 interface passivation layer by means of atomic layer deposition at 200 ° C - 400 ° C in Al x Y 2-x
  • a high dielectric insulating layer having a thickness of 0 nm or more and 4 nm or less is deposited on the O 3 interface passivation layer.
  • a method of fabricating a composite gate dielectric layer for a III-V substrate in accordance with Embodiment 1 of the present invention includes the following steps:
  • Step 101 cleaning the InP substrate having a thickness of 400 ⁇ m and an N-type doping concentration of 5 ⁇ 10 15 cm ⁇ 3 , and then growing the thickness to 0.5 nm at 200° C. by atomic layer deposition. Al 2 O 2.5 layer; the step 101 specifically includes:
  • Step 101.1 completely immersing the surface of the InP substrate into the absolute ethanol, and ultrasonically cleaning for 3 minutes to remove the partially polarized organic matter on the surface;
  • Step 101.2 taking the InP substrate after the step 101.1 in the deionized water for 15 seconds, and then taking out;
  • Step 101.3 completely immersing the surface of the InP substrate passing through the step 101.2 into the acetone, and ultrasonically cleaning for 3 minutes to remove the non-polarized organic matter on the surface;
  • Step 101.4 The InP substrate after the step 101.3 is wetted in deionized water for 15 seconds and then taken out;
  • Step 101.5 Take concentrated hydrochloric acid (mass fraction 37%) and deionized water, and mix in a volume ratio of 1:9; keep the surface of the InP substrate which is subjected to step 101.4 upwards and completely immersed in the diluted hydrochloric acid solution obtained after mixing. minute;
  • Step 101.6 The InP substrate after the step 101.5 is immersed in deionized water for 15 seconds and then taken out;
  • Step 101.7 completely immersing the surface of the InP substrate passing through step 101.6 upward into a 22% by mass ammonia sulfide (NH 4 ) 2 S solution for 15 minutes;
  • Step 101.8 The InP substrate subjected to the step 101.7 is immersed in deionized water for 15 seconds, and then taken out, and quickly dried with nitrogen;
  • Step 101.9 Put the InP substrate subjected to the step 101.8 into an atomic layer deposition apparatus, and use a method of atomic layer deposition to use trimethylaluminum and water as a reaction precursor (first pass through the trimethylaluminum and then into the water) In order), an Al 2 O 2.5 layer having a thickness of 0.5 nm was grown at 200 ° C.
  • Step 102 using a method of atomic layer deposition, using tris(butylcyclopentadiene) ruthenium and water as a reaction precursor (the order of passing water after first introducing tris(butylcyclopentadiene) ruthenium) at 300 ° C A layer of Y 2 O 3 having a thickness of 0.3 nm was grown underneath.
  • Step 103 In-situ heat treatment of the grown Al 2 O 2.5 layer and the Y 2 O 3 layer in an atomic layer deposition apparatus at 300 ° C to obtain an Al 1.25 Y 0.75 O 3 interface passivation having a thickness of 0.8 nm.
  • the step 103 specifically includes:
  • Step 103.1 After the completion of step 102, a nitrogen gas having a purity of 99.999% is introduced into the atomic layer deposition chamber, and the gas pressure is maintained at 50 Pascals, and the timing is started after the gas pressure is stabilized.
  • Step 103.2 In-situ annealing treatment at a temperature of 300 ° C for 30 minutes to diffuse Al and Y atoms to form an Al 1.25 Y 0.75 O 3 interface passivation layer having a thickness of 0.8 nm and an average coordination number of 3.25. .
  • Step 104 using an atomic layer deposition method, using bis(ethylcyclopentanediyl)phosphonium dichloride and water as the reaction precursor on the annealed Al 1.25 Y 0.75 O 3 interface passivation layer (first pass)
  • the order of introduction of bis(ethylcyclopentayl)phosphonium chloride followed by water was carried out to grow a layer of HfO 2 having a thickness of 3 nm at 300 °C.
  • a method of fabricating a composite gate dielectric layer for a III-V substrate in accordance with Embodiment 2 of the present invention includes the following steps:
  • Step 201 cleaning the In 0.53 Ga 0.47 As substrate on the silicon-based insulator having an epitaxial layer thickness of 20 nm and an N-type doping concentration of 1 ⁇ 10 18 cm ⁇ 3 , the silicon substrate is intrinsic silicon, and the insulating layer The thickness is 50 nm; then, an Al 2 O 2.5 layer having a thickness of 0.3 nm is grown at 200 ° C by atomic layer deposition; the step 201 specifically includes:
  • Step 201.1 completely immersing the surface of the In 0.53 Ga 0.47 As substrate on the silicon-based insulator into the absolute ethanol, and ultrasonically cleaning for 3 minutes to remove the partially polarized organic matter on the surface;
  • Step 201.2 The In 0.53 Ga 0.47 As substrate on the silicon-based insulator after the step 201.1 is wetted in deionized water for 15 seconds, and then taken out;
  • Step 201.3 completely immersing the surface of the In 0.53 Ga 0.47 As substrate on the silicon-based insulator in step 201.2 into the acetone, and ultrasonically cleaning for 3 minutes to remove the non-polarized organic matter on the surface;
  • Step 201.4 The In 0.53 Ga 0.47 As substrate on the silicon-based insulator after the step 201.3 is wetted in deionized water for 15 seconds, and then taken out;
  • Step 201.5 Concentrated hydrochloric acid (mass fraction 37%) and deionized water are mixed at a volume ratio of 1:4; the surface of the In 0.53 Ga 0.47 As substrate on the silicon-based insulator subjected to step 201.4 is completely immersed into the mixture. The obtained dilute hydrochloric acid solution was kept for 1 minute;
  • Step 201.6 The In 0.53 Ga 0.47 As substrate on the silicon-based insulator after the step 201.5 is wetted in deionized water for 15 seconds, and then taken out;
  • Step 201.7 completely immersing the surface of the In 0.53 Ga 0.47 As substrate on the silicon-based insulator subjected to the step 201.6 into a 22% by mass ammonia sulfide (NH 4 ) 2 S solution for 15 minutes;
  • Step 201.8 The In 0.53 Ga 0.47 As substrate on the silicon-based insulator subjected to the step 201.7 is wetted in deionized water for 15 seconds, and then taken out, and quickly dried with nitrogen;
  • Step 201.9 Put the In 0.53 Ga 0.47 As substrate on the silicon-based insulator through step 201.8 into an atomic layer deposition apparatus, using a solution of atomic layer deposition, using trimethylaluminum and water as reaction precursors (first access) After the addition of trimethylaluminum to the water, a layer of Al 2 O 2.5 having a thickness of 0.3 nm was grown at 200 ° C.
  • Step 202 using a method of atomic layer deposition, using tris(butylcyclopentadiene) ruthenium and water as a reaction precursor (in the order of passing into the water after the introduction of tris(butylcyclopentadiene) ruthenium) at 300 ° C
  • a layer of Y 2 O 3 having a thickness of 0.3 nm was grown underneath.
  • Step 203 performing in-situ heat treatment of the grown Al 2 O 2.5 layer and the Y 2 O 3 layer in an atomic layer deposition apparatus at 300 ° C to obtain an AlYO 3 interface passivation layer having a thickness of 0.6 nm; 203 specifically includes:
  • Step 203.1 After completing step 202, a nitrogen gas having a purity of 99.999% is introduced into the atomic layer deposition chamber, and the gas pressure is maintained at 50 Pascals. The gas phase pressure is stabilized and the timing is started.
  • Step 203.2 In-situ annealing treatment was carried out at a temperature of 300 ° C for 30 minutes to diffuse Al and Y atoms to form an AlYO 3 interface passivation layer having a thickness of 0.6 nm and an average coordination number of 3.4.
  • Step 204 The Hf 0.9 Y 0.13 O 2 layer having a thickness of 3 nm is grown on the AlYO 3 interface passivation layer after the annealing treatment by using an atomic layer deposition method; the step 204 specifically includes:
  • Step 204.1 using the method of atomic layer deposition, after step 203.2, using bis(ethylcyclopentayl)phosphonium dichloride and water as the reaction precursor at 300 ° C (first pass into the double (ethyl cyclopentane) The order of the dibasic ruthenium dichloride and the water is introduced into the HfO 2 layer having a thickness of 1.35 nm;
  • Step 204.2 using the atomic layer deposition method, after step 204.1, using tris(butylcyclopentadiene) ruthenium and water as the reaction precursor at 300 ° C (first pass into the tris(butylcyclopentadiene) ruthenium The order of passing water) is to grow a layer of Y 2 O 3 having a thickness of 0.3 nm at 300 ° C;
  • Step 204.3 using a method of atomic layer deposition, after step 204.2, using bis(ethylcyclopentayl)phosphonium dichloride and water as a reaction precursor at 300 ° C (first pass into the double (ethyl cyclopentane) The order of the dibasic ruthenium dichloride and the water is introduced into the HfO 2 layer having a thickness of 1.35 nm;
  • Step 204.4 After the completion of step 204.3, a nitrogen gas having a purity of 99.999% is introduced into the atomic layer deposition chamber, and the gas pressure is maintained at 50 Pascals, and the timing is started after the gas pressure is stabilized.
  • Step 204.5 In-situ annealing treatment is carried out at a temperature of 300 ° C for 30 minutes to diffuse Hf and Y atoms to form a Hf 0.9 Y 0.13 O 2 high dielectric insulating layer having a thickness of 3 nm.
  • a method of fabricating a composite gate dielectric layer for a III-V substrate in accordance with Embodiment 3 of the present invention includes the following steps:
  • Step 301 cleaning a GaAs substrate having a thickness of 400 ⁇ m and an N-type doping concentration of 1 ⁇ 10 17 cm ⁇ 3 , and then growing the thickness to 2 nm at 250° C. by atomic layer deposition.
  • Al 2 O 2.7 layer; the step 301 specifically includes:
  • Step 301.1 completely immersing the surface of the GaAs substrate into the absolute ethanol, and ultrasonically cleaning for 3 minutes to remove the partially polarized organic matter on the surface;
  • Step 301.2 The GaAs substrate subjected to the step 301.1 is immersed in deionized water for 15 seconds and then taken out;
  • Step 301.3 completely immersing the surface of the GaAs substrate subjected to the step 301.2 upward into the acetone, ultrasonically cleaning for 3 minutes, and removing the non-polarized organic matter on the surface;
  • Step 301.4 The GaAs substrate subjected to the step 301.3 is immersed in deionized water for 15 seconds and then taken out;
  • Step 301.5 Take concentrated hydrochloric acid (mass fraction 37%) and deionized water, and mix in a volume ratio of 1:4; keep the surface of the InP substrate which is subjected to step 101.4 upwards and completely immersed in the diluted hydrochloric acid solution obtained after mixing. minute;
  • Step 301.6 Wetting the GaAs substrate passing through step 301.5 in deionized water 15 Take out after two seconds;
  • Step 301.7 completely immersing the surface of the GaAs substrate subjected to step 301.6 upward into a 22% by mass ammonia sulfide (NH 4 ) 2 S solution for 15 minutes;
  • Step 301.8 After immersing the GaAs substrate subjected to the step 301.7 in deionized water for 15 seconds, taking it out, and rapidly drying it with nitrogen gas;
  • Step 301.9 Put the GaAs substrate subjected to the step 301.8 into an atomic layer deposition apparatus, and use a method of atomic layer deposition to use trimethylaluminum and water as a reaction precursor (first pass through the trimethylaluminum and then into the water) In order), a layer of Al 2 O 2.7 having a thickness of 2 nm was grown at 250 °C.
  • Step 302 using a method of atomic layer deposition, using tris(butylcyclopentadiene) ruthenium and water as a reaction precursor (the order of introducing water after first introducing tris(butylcyclopentadiene) ruthenium) at 300 ° C conditions A layer of Y 2 O 3 having a thickness of 0.3 nm was grown underneath.
  • Step 303 In-situ heat treatment of the grown Al 2 O 2.7 layer and the Y 2 O 3 layer in an atomic layer deposition apparatus at 300 ° C to obtain an Al 1.74 Y 0.26 O 3 interface passivation having a thickness of 2.3 nm. Floor;
  • Step 303.1 After completing step 302, nitrogen gas having a purity of 99.999% is introduced into the atomic layer deposition chamber, and the gas pressure is maintained at 50 Pascals, and the gas phase is started to be stabilized after the gas pressure is stabilized.
  • Step 303.2 In-situ annealing treatment is carried out at a temperature of 300 ° C for 30 minutes to diffuse Al and Y atoms to form an Al 1.74 Y 0.26 O 3 interface passivation layer having a thickness of 2.3 nm and an average coordination number of 2.96. .
  • Step 304 using an atomic layer deposition method, using bis(ethylcyclopentayl)phosphonium dichloride and water as the reaction precursor on the annealed Al 1.74 Y 0.26 O 3 interface passivation layer (first pass)
  • the order of introduction of bis(ethylcyclopentanediyl)phosphonium chloride into water was carried out by growing a 2 nm-thick HfO 2 layer at 300 °C.

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Abstract

一种应用于III-V族衬底的复合栅介质层（2）及其制作方法，该复合栅介质层（2）包括：形成于III-V族衬底（1）之上的Al xY 2-xO 3界面钝化层（23），以及形成于该Al xY 2-xO 3界面钝化层（23）之上的高介电绝缘层（24），其中1.2≤x≤1.9。该复合栅介质层（2）通过调整Al xY 2-xO 3界面钝化层（23）的Al/Y比例，改变了Al xY 2-xO 3界面钝化层（23）中的平均原子配位数，降低了III-V族衬底（1）界面态密度和边界陷阱密度，增加了MOS沟道迁移率；通过Al xY 2-xO 3界面钝化层（23）与高介电绝缘层（24）的配合，减小了栅漏电流，并提升了介质层的耐压能力，提高了III-V族衬底（1）MOS电容的质量和增强了其可靠性。

Description

应用于III-V族衬底的复合栅介质层及其制作方法 技术领域
本发明涉及应用于III-V族衬底的复合栅介质结构，尤其是一种应用于III-V族衬底的复合栅介质层及其制作方法。
背景技术
随着微电子技术的不断发展，以InGaAs、InP、InAs、GaAs、GaSb等为代表的III-V族化合物半导体因其具有优于硅的电子迁移率或空穴迁移率，被认为是作为后摩尔技术时代替代硅沟道制作金属－氧化物－半导体(MOS)场效应晶体管的重要备选材料。
III-V族衬底与栅介质界面普遍存在着大量的界面缺陷密度，通常比SiO2/Si的界面陷阱密度高1-2个数量级，高的界面陷阱密度会大大降低载流子的迁移率，导致导通电阻增大，功耗增加。目前，业界科研学者通过采用基于原子层沉积技术的表面Al2O3钝化，界面硫化以及表面氮化等方法，栅介质/III-V族衬底的界面质量及整体特性有了一定的提升，不过与SiO2/Si界面质量相比仍有不小的差距。
另外，从器件可靠性及器件功耗方面，III-V族衬底与栅介质结构也面临着诸多挑战。目前为止的大部分栅介质结构普遍存在着栅介质漏电大，可靠性差的缺点。如何在III-V族衬底表面制备高可靠性，低缺陷界面态密度以及超低等价氧化物厚度的栅介质结构成为实现III-V族衬底在后摩尔技术时代逻辑器件应用的关键技术。
发明内容
有鉴于此，本发明的主要目的在于提供了一种应用于III-V族衬底的复合栅介质层及其制作方法，以降低界面态密度和边界陷阱密度，增加III-V族MOS沟道迁移率，减小栅漏电流，并进一步提高介质层的耐 压能力，提高III-V族衬底MOS的质量和增强其可靠性。
为达到上述目的，本发明提供了一种应用于III-V族衬底的复合栅介质层，包括：形成于III-V族衬底之上的AlxY2-xO3界面钝化层；以及形成于该AlxY2-xO3界面钝化层之上的高介电绝缘层；其中1.2≤x≤1.9。
上述方案中，所述III-V族衬底包括GaAs衬底、InP衬底、GaSb衬底、InAs衬底或InGaAs衬底及其外延片，其掺杂浓度大于等于1×1015cm-3且小于等于5×1017cm-3。
上述方案中，所述AlxY2-xO3界面钝化层的厚度大于等于0.4nm且小于等于4nm。
上述方案中，所述高介电绝缘层包括HfO2、ZrO2、La2O3或Y2O3，以及通过上述四种材料进行混合而得到的三元或多元化合物，该高介电绝缘层厚度大于等于0nm且小于等于4nm。
为达到上述目的，本发明还提供了一种应用于III-V族衬底的复合栅介质层的制作方法，包括：
步骤1：清洗III-V族衬底，在该III-V族衬底之上生长Al2Om钝化层，其中2.5≤m≤3；
步骤2：在该Al2Om钝化层之上生长Y2On强化层，其中2.5≤n≤3；
步骤3：对Al2Om钝化层和Y2On强化层进行原位热处理，实现Al2Om钝化层和Y2On强化层的混合，获得AlxY2-xO3界面钝化层，其中1.2≤x≤1.9；
步骤4：在该AlxY2-xO3界面钝化层上生长高介电绝缘层。
上述方案中，步骤1中所述在III-V族衬底之上生长Al2Om钝化层，包括：利用原子层淀积的方法，在200℃-400℃条件下在III-V族衬底之上生长厚度为d1纳米的Al2Om钝化层，其中0.2nm≤d1≤3.8nm。
上述方案中，该方法通过调节200℃-400℃原子层沉积温度来调节Al2Om钝化层中氧的含量，其中200℃倾向于形成低氧含量的Al2Om钝化层，m＝2.5；400℃倾向于形成高氧含量的Al2Om钝化层，m＝3；Al2Om钝化层中较低的氧含量，能够提高Al2Om钝化层中Al-O四面体网格结构的柔性，增加Al2Om钝化层中Al-O四面体可旋转的特性，从而实现对于 III-V族衬底表面缺陷的钝化；Al2Om钝化层中较高的氧含量，能够降低复合栅介质层的漏电并提升可靠性。
上述方案中，步骤2中所述在Al2Om钝化层之上生长Y2On强化层，包括：利用原子层淀积的方法，在200℃-400℃条件下在Al2Om钝化层之上生长厚度为d2纳米的Y2On强化层，其中0.4nm≤d1+d2≤4nm。
上述方案中，该方法通过调节200℃-400℃原子层沉积温度来调节Y2On强化层中氧的含量，其中200℃倾向于形成低氧含量的Y2On强化层，n＝2.5；400℃倾向于形成高氧含量的Y2On强化层，n＝3。
上述方案中，步骤3中所述对Al2Om钝化层和Y2On强化层进行原位热处理，是将Al2Om钝化层和Y2On强化层在200℃-400℃条件下在原子层淀积设备中进行原位退火处理。
上述方案中，该方法通过调节原位热处理的温度来实现Al2Om钝化层和Y2On强化层按照一定比例的混合，混合比由Al2Om钝化层厚度d1与Y2On强化层厚度d2的比d1:d2决定，其中19:1≤d1:d2≤1:19；该方法通过Al2Om钝化层和Y2On强化层的混合得到AlxY2-xO3界面钝化层，实现AlxY2-xO3界面钝化层的平均配位数2.8到4.2的调控，进而满足各种器件对界面缺陷密度以及可靠性的需求，其中，平均配位数2.8是在d1:d2等于19:1、m＝3及n＝3的条件下获得的；平均配位数4.2是在d1:d2等于1:19、m＝2.5及n＝2.5的条件下获得的。
上述方案中，所述AlxY2-xO3界面钝化层中1.2≤x≤1.9是作为界面钝化层的较优结果，该AlxY2-xO3界面钝化层的平均配位数介于3.28至2.86，其中x＝1.2时平均配位数为3.28，x＝1.9时平均配位数为2.86。
上述方案中，步骤4中所述在AlxY2-xO3界面钝化层上生长高介电绝缘层，是利用原子层淀积的方法，在200℃-400℃条件下在AlxY2-xO3界面钝化层上淀积厚度大于等于0nm且小于等于4nm的高介电绝缘层。
从上述技术方案可以看出，本发明具有以下有益效果：
1、本发明提供的应用于III-V族衬底的复合栅介质层及其制作方法，采用AlxY2-xO3界面钝化层，通过调整Al2Om中的氧浓度并向其中掺入Y2On,软化了Al2Om网格结构，使Al-O四面体之间具有更多的扭动自由度， AlxY2-xO3更易与III-V族衬底表面缺陷成键，实现界面缺陷的钝化。
2、本发明提供的应用于III-V族衬底的复合栅介质层及其制作方法，采用AlxY2-xO3界面钝化层，通过调整Al2Om中的氧浓度并向其中掺入Y2On,提高了AlxY2-xO3的平均配位数，使其中Al-O四面体尽管可以扭动但是仍然在七配位的Y3+离子作用下被吸引在Y3+附近从而变得更加致密，该界面层具有更低的Gibbs体系自由能，在较大电应力作用下也不容易发生离子断键，从而减小栅漏电流，提升了可靠性。
3、本发明提供的应用于III-V族衬底的复合栅介质层及其制作方法，采用AlxY2-xO3界面钝化层，与单一Al2O3界面钝化层相比(介电常数k大约为8)，本发明采用的AlxY2-xO3界面钝化层介电常数更高(介电常数k大约为12)，同时配合具备高介电常数的HfO2,ZrO2,La2O3,Y2O3,以及通过上述四种材料进行混合而得到的三元或多元化和物，有助于实现更小的等价氧化物厚度。
附图说明
为了更进一步说明本发明的内容，以下结合附图对本发明做详细描述，其中：
图1是本发明提供的应用于III-V族衬底的复合栅介质层的结构示意图；
图2是本发明提供的制作图1所示的复合栅介质层的工艺流程图；
图3是本发明提供的制作图1所示的复合栅介质层的方法流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
如图1所示，图1是本发明提供的应用于III-V族衬底的复合栅介质层的结构示意图，该复合栅介质层包括：形成于III-V族衬底1之上 的AlxY2-xO3界面钝化层23；以及形成于该AlxY2-xO3界面钝化层23之上的高介电绝缘层24；其中1.2≤x≤1.9，AlxY2-xO3界面钝化层23与HfO2高介电绝缘层24构成复合栅介质层2。
图1中，所述III-V族衬底1可以为GaAs衬底、InP衬底、GaSb衬底、InAs衬底或InGaAs衬底及其外延片，其掺杂浓度大于等于1×1015cm-3且小于等于5×1017cm-3。AlxY2-xO3界面钝化层23的厚度大于等于0.4nm且小于等于4nm。高介电绝缘层24可以为HfO2、ZrO2、La2O3或Y2O3，以及通过上述四种材料进行混合而得到的三元或多元化合物，该高介电绝缘层24的厚度大于等于0nm且小于等于4nm。
图2是本发明提供的制作图1所示的复合栅介质层的工艺流程图，根据图2可知，形成于III-V族衬底1之上的AlxY2-xO3界面钝化层23是通过原位热处理，即原位退火处理，使Al2Om钝化层21和Y2On强化层22互扩散得到的。
由AlxY2-xO3界面钝化层23与HfO2高介电绝缘层24组成的栅介质层是一个复合栅介质层，以降低界面态密度和边界陷阱密度，增加MOS沟道迁移率，减小栅漏电流，并进一步提高介质层的耐压能力，提高MOS的质量和可靠性。
图3是本发明提供的制作图1所示的复合栅介质层的方法流程图，该方法包括以下步骤：
步骤1：清洗III-V族衬底，在该III-V族衬底之上生长Al2Om钝化层，其中2.5≤m≤3；
在本步骤中，在III-V族衬底之上生长Al2Om钝化层，包括：利用原子层淀积的方法，在200℃-400℃条件下在III-V族衬底之上生长厚度为d1纳米的Al2Om钝化层，其中0.2nm≤d1≤3.8nm。该方法通过调节200℃-400℃原子层沉积温度来调节Al2Om钝化层中氧的含量，其中200℃倾向于形成低氧含量的Al2Om钝化层，m＝2.5；400℃倾向于形成高氧含量的Al2Om钝化层，m＝3；Al2Om钝化层中较低的氧含量，能够提高Al2Om钝化层中Al-O四面体网格结构的柔性，增加Al2Om钝化层中Al-O四面体可旋转的特性，从而实现对于III-V族衬底表面缺陷的钝化；Al2Om钝化层中较高 的氧含量，能够降低复合栅介质层的漏电并提升可靠性。
步骤2：在该Al2Om钝化层之上生长Y2On强化层，其中2.5≤n≤3；
在本步骤中，在Al2Om钝化层之上生长Y2On强化层，包括：利用原子层淀积的方法，在200℃-400℃条件下在Al2Om钝化层之上生长厚度为d2纳米的Y2On强化层，其中0.4nm≤d1+d2≤4nm。该方法通过调节200℃-400℃原子层沉积温度来调节Y2On强化层中氧的含量，其中200℃倾向于形成低氧含量的Y2On强化层，n＝2.5；400℃倾向于形成高氧含量的Y2On强化层，n＝3。
步骤3：对Al2Om钝化层和Y2On强化层进行原位热处理，实现Al2Om钝化层和Y2On强化层的混合，获得AlxY2-xO3界面钝化层，其中1.2≤x≤1.9；
本步骤中，对Al2Om钝化层和Y2On强化层进行原位热处理，是将Al2Om钝化层和Y2On强化层在200℃-400℃条件下在原子层淀积设备中进行原位退火处理。该方法通过调节原位热处理的温度来实现Al2Om钝化层和Y2On强化层按照一定比例的混合，混合比由Al2Om钝化层厚度d1与Y2On强化层厚度d2的比d1:d2决定，其中19:1≤d1:d2≤1:19；该方法通过Al2Om钝化层和Y2On强化层的混合得到AlxY2-xO3界面钝化层，实现AlxY2-xO3界面钝化层的平均配位数2.8到4.2的调控，进而满足各种器件对界面缺陷密度以及可靠性的需求，其中，平均配位数2.8是在d1:d2介于19:1、m＝3及n＝3的条件下获得的；平均配位数4.2是在d1:d2介于1:19、m＝2.5及n＝2.5的条件下获得的。AlxY2-xO3界面钝化层中1.2≤x≤1.9是作为界面钝化层的较优结果，该AlxY2-xO3界面钝化层的平均配位数介于3.28至2.86，其中x＝1.2时平均配位数为3.28，x＝1.9时平均配位数为2.86。
步骤4：在该AlxY2-xO3界面钝化层上生长高介电绝缘层。
在本步骤中，在AlxY2-xO3界面钝化层上生长高介电绝缘层，是利用原子层淀积的方法，在200℃-400℃条件下在AlxY2-xO3界面钝化层上淀积厚度大于等于0nm且小于等于4nm的高介电绝缘层。
实施例1
依照本发明实施例1制作应用于III-V族衬底的复合栅介质层的方法， 包括以下步骤：
步骤101：将厚度为400微米、N型掺杂浓度为5×1015cm-3的InP衬底进行清洗处理,然后利用原子层淀积的方法，在200℃条件下生长厚度为0.5纳米的Al2O2.5层；该步骤101具体包括：
步骤101.1：将InP衬底表面朝上完全浸没入无水乙醇中，超声清洗3分钟，去除表面有部分极化的有机物；
步骤101.2：将经过步骤101.1的InP衬底在去离子水中浸润15秒后取出；
步骤101.3：将经过步骤101.2的InP衬底表面朝上完全浸没入丙酮中，超声清洗3分钟，去除表面无极化的有机物；
步骤101.4：将经过步骤101.3的InP衬底在去离子水中浸润15秒后取出；
步骤101.5：取浓盐酸(质量分数37％)和去离子水，以1：9的体积比混合；将经过步骤101.4的InP衬底表面朝上完全浸没入混合后得到的稀盐酸溶液中保持1分钟；
步骤101.6：将经过步骤101.5的InP衬底在去离子水中浸润15秒后取出；
步骤101.7：将经过步骤101.6的InP衬底表面朝上完全浸没入质量分数为22％硫化氨(NH4)2S溶液中，保持15分钟；
步骤101.8：将经过步骤101.7的InP衬底在去离子水中浸润15秒后取出，迅速用氮气吹干；
步骤101.9：将经过步骤101.8的InP衬底放入原子层沉积设备中，利用原子层淀积的方法，以三甲基铝和水作为反应前驱体(先通入三甲基铝后通入水的顺序)，在200℃条件下生长厚度为0.5纳米的Al2O2.5层。
步骤102：利用原子层淀积的方法，以三(丁基环戊二烯)化钇和水作为反应前驱体(先通入三(丁基环戊二烯)化钇后通入水的顺序)在300℃条件下生长厚度为0.3纳米的Y2O3层。
步骤103：将所生长的Al2O2.5层和Y2O3层在300℃条件下在原子层淀积设备中进行原位热处理，获得厚度为0.8纳米的Al1.25Y0.75O3界面钝化层； 该步骤103具体包括：
步骤103.1：在完成步骤102之后，向原子层沉积室内通入纯度99.999％的氮气，保持气压为50帕斯卡，待气体压强稳定以后开始计时。
步骤103.2：在温度300℃条件下进行原位退火处理，保温30分钟，使Al和Y原子发生扩散，形成厚度为0.8纳米的平均配位数为3.25的Al1.25Y0.75O3界面钝化层。
步骤104：利用原子层淀积的方法，在退火处理后的Al1.25Y0.75O3界面钝化层上以双(乙基环戊二基)二氯化铪和水作为反应前驱体(先通入双(乙基环戊二基)二氯化铪后通入水的顺序)在300℃条件下生长厚度为3纳米的HfO2层。
实施例2
依照本发明实施例2制作应用于III-V族衬底的复合栅介质层的方法，包括以下步骤：
步骤201：将外延层厚度为20纳米、N型掺杂浓度为1×1018cm-3的硅基绝缘体上In0.53Ga0.47As衬底进行清洗处理，硅衬底为本征硅,绝缘层厚度为50纳米；然后利用原子层淀积的方法，在200℃条件下生长厚度为0.3纳米的Al2O2.5层；该步骤201具体包括：
步骤201.1：将硅基绝缘体上In0.53Ga0.47As衬底表面朝上完全浸没入无水乙醇中，超声清洗3分钟，去除表面有部分极化的有机物；
步骤201.2：将经过步骤201.1的硅基绝缘体上In0.53Ga0.47As衬底在去离子水中浸润15秒后取出；
步骤201.3：将经过步骤201.2的硅基绝缘体上In0.53Ga0.47As衬底表面朝上完全浸没入丙酮中，超声清洗3分钟，去除表面无极化的有机物；
步骤201.4：将经过步骤201.3的硅基绝缘体上In0.53Ga0.47As衬底在去离子水中浸润15秒后取出；
步骤201.5：取浓盐酸(质量分数37％)和去离子水，以1：4的体积比混合；将经过步骤201.4的硅基绝缘体上In0.53Ga0.47As衬底表面朝上完全浸没入混合后得到的稀盐酸溶液中保持1分钟；
步骤201.6：将经过步骤201.5的硅基绝缘体上In0.53Ga0.47As衬底在去离子水中浸润15秒后取出；
步骤201.7：将经过步骤201.6的硅基绝缘体上In0.53Ga0.47As衬底表面朝上完全浸没入质量分数为22％硫化氨(NH4)2S溶液中，保持15分钟；
步骤201.8：将经过步骤201.7的硅基绝缘体上In0.53Ga0.47As衬底在去离子水中浸润15秒后取出，迅速用氮气吹干；
步骤201.9：将经过步骤201.8的硅基绝缘体上In0.53Ga0.47As衬底放入原子层沉积设备中，利用原子层淀积的方法，以三甲基铝和水作为反应前驱体(先通入三甲基铝后通入水的顺序)，在200℃条件下生长厚度为0.3纳米的Al2O2.5层。
步骤202：利用原子层淀积的方法，以三(丁基环戊二烯)化钇和水作为反应前驱体(先通入三(丁基环戊二烯)化钇后通入水的顺序)在300℃条件下生长厚度为0.3纳米的Y2O3层。
步骤203：将所生长的Al2O2.5层和Y2O3层在300℃条件下在原子层淀积设备中进行原位热处理，获得厚度为0.6纳米的AlYO3界面钝化层；该步骤203具体包括：
步骤203.1：在完成步骤202之后，向原子层沉积室内通入纯度99.999％的氮气，保持气压为50帕斯卡，待气体压强稳定以后开始计时。
步骤203.2：在温度300℃条件下进行原位退火处理，保温30分钟，使Al和Y原子发生扩散，形成厚度为0.6纳米的平均配位数为3.4的AlYO3界面钝化层。
步骤204：利用原子层淀积的方法，在退火处理后的AlYO3界面钝化层上在300℃条件下生长厚度为3纳米的Hf0.9Y0.13O2层；该步骤204具体包括：
步骤204.1：利用原子层淀积的方法，步骤203.2后，在300℃条件下以双(乙基环戊二基)二氯化铪和水作为反应前驱体(先通入双(乙基环戊二基)二氯化铪后通入水的顺序)生长厚度为1.35纳米的HfO2层；
步骤204.2：利用原子层淀积的方法，步骤204.1后，在300℃条件下以三(丁基环戊二烯)化钇和水作为反应前驱体(先通入三(丁基环戊 二烯)化钇后通入水的顺序)在300℃条件下生长厚度为0.3纳米的Y2O3层；
步骤204.3：利用原子层淀积的方法，步骤204.2后，在300℃条件下以双(乙基环戊二基)二氯化铪和水作为反应前驱体(先通入双(乙基环戊二基)二氯化铪后通入水的顺序)生长厚度为1.35纳米的HfO2层；
步骤204.4：在完成步骤204.3之后，向原子层沉积室内通入纯度99.999％的氮气，保持气压为50帕斯卡，待气体压强稳定以后开始计时。
步骤204.5：在温度300℃条件下进行原位退火处理，保温30分钟，使Hf和Y原子发生扩散，形成厚度为3纳米的Hf0.9Y0.13O2高介电绝缘层。
实施例3
依照本发明实施例3制作应用于III-V族衬底的复合栅介质层的方法，包括以下步骤：
步骤301：将厚度为400微米、N型掺杂浓度为1×1017cm-3的GaAs衬底进行清洗处理,然后利用原子层淀积的方法，在250℃条件下生长厚度为2纳米的Al2O2.7层；该步骤301具体包括：
步骤301.1：将GaAs衬底表面朝上完全浸没入无水乙醇中，超声清洗3分钟，去除表面有部分极化的有机物；
步骤301.2：将经过步骤301.1的GaAs衬底在去离子水中浸润15秒后取出；
步骤301.3：将经过步骤301.2的GaAs衬底表面朝上完全浸没入丙酮中，超声清洗3分钟，去除表面无极化的有机物；
步骤301.4：将经过步骤301.3的GaAs衬底在去离子水中浸润15秒后取出；
步骤301.5：取浓盐酸(质量分数37％)和去离子水，以1：4的体积比混合；将经过步骤101.4的InP衬底表面朝上完全浸没入混合后得到的稀盐酸溶液中保持1分钟；
步骤301.6：将经过步骤301.5的GaAs衬底在去离子水中浸润15 秒后取出；
步骤301.7：将经过步骤301.6的GaAs衬底表面朝上完全浸没入质量分数为22％硫化氨(NH4)2S溶液中，保持15分钟；
步骤301.8：将经过步骤301.7的GaAs衬底在去离子水中浸润15秒后取出，迅速用氮气吹干；
步骤301.9：将经过步骤301.8的GaAs衬底放入原子层沉积设备中，利用原子层淀积的方法，以三甲基铝和水作为反应前驱体(先通入三甲基铝后通入水的顺序)，在250℃条件下生长厚度为2纳米的Al2O2.7层。
步骤302：利用原子层淀积的方法，以三(丁基环戊二烯)化钇和水作为反应前驱体(先通入三(丁基环戊二烯)化钇后通入水的顺序)在300℃条件下生长厚度为0.3纳米的Y2O3层。
步骤303：将所生长的Al2O2.7层和Y2O3层在300℃条件下在原子层淀积设备中进行原位热处理，获得厚度为2.3纳米的Al1.74Y0.26O3界面钝化层；
步骤303.1：在完成步骤302之后，向原子层沉积室内通入纯度99.999％的氮气，保持气压为50帕斯卡，待气体压强稳定以后开始计时。
步骤303.2：在温度300℃条件下进行原位退火处理，保温30分钟，使Al和Y原子发生扩散，形成厚度为2.3纳米的平均配位数为2.96的Al1.74Y0.26O3界面钝化层。
步骤304，利用原子层淀积的方法，在退火处理后的Al1.74Y0.26O3界面钝化层上以双(乙基环戊二基)二氯化铪和水作为反应前驱体(先通入双(乙基环戊二基)二氯化铪后通入水的顺序)在300℃条件下生长厚度为2纳米的HfO2层。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种应用于III-V族衬底的复合栅介质层，其特征在于，包括：
    形成于III-V族衬底之上的AlxY2-xO3界面钝化层；以及
    形成于该AlxY2-xO3界面钝化层之上的高介电绝缘层；
    其中，1.2≤x≤1.9。
  2. 根据权利要求1所述的应用于III-V族衬底的复合栅介质层，其特征在于，所述III-V族衬底包括GaAs衬底、InP衬底、GaSb衬底、InAs衬底或InGaAs衬底及其外延片，其掺杂浓度大于等于1×1015cm-3且小于等于5×1017cm-3。
  3. 根据权利要求1所述的应用于III-V族衬底的复合栅介质层，其特征在于，所述AlxY2-xO3界面钝化层的厚度大于等于0.4nm且小于等于4nm。
  4. 根据权利要求1所述的应用于III-V族衬底的复合栅介质层，其特征在于，所述高介电绝缘层包括HfO2、ZrO2、La2O3或Y2O3，以及通过上述四种材料进行混合而得到的三元或多元化合物，该高介电绝缘层厚度大于等于0nm且小于等于4nm。
  5. 一种应用于III-V族衬底的复合栅介质层的制作方法，其特征在于，包括：
    步骤1：清洗III-V族衬底，在该III-V族衬底之上生长Al2Om钝化层，其中2.5≤m≤3；
    步骤2：在该Al2Om钝化层之上生长Y2On强化层，其中2.5≤n≤3；
    步骤3：对Al2Om钝化层和Y2On强化层进行原位热处理，实现Al2Om钝化层和Y2On强化层的混合，获得AlxY2-xO3界面钝化层，其中1.2≤x≤1.9；
    步骤4：在该AlxY2-xO3界面钝化层上生长高介电绝缘层。
  6. 根据权利要求5所述的制作方法，其特征在于，步骤1中所述在III-V族衬底之上生长Al2Om钝化层，包括：
    利用原子层淀积的方法，在200℃-400℃条件下在III-V族衬底之上生长厚度为d1纳米的Al2Om钝化层，其中0.2nm≤d1≤3.8nm。
  7. 根据权利要求6所述的制作方法，其特征在于，该方法通过调节200℃-400℃原子层沉积温度来调节Al2Om钝化层中氧的含量，其中200℃倾向于形成低氧含量的Al2Om钝化层，m＝2.5；400℃倾向于形成高氧含量的Al2Om钝化层，m＝3；Al2Om钝化层中较低的氧含量，能够提高Al2Om钝化层中Al-O四面体网格结构的柔性，增加Al2Om钝化层中Al-O四面体可旋转的特性，从而实现对于III-V族衬底表面缺陷的钝化；Al2Om钝化层中较高的氧含量，能够降低复合栅介质层的漏电并提升可靠性。
  8. 根据权利要求6所述的制作方法，其特征在于，步骤2中所述在Al2Om钝化层之上生长Y2On强化层，包括：
    利用原子层淀积的方法，在200℃-400℃条件下在Al2Om钝化层之上生长厚度为d2纳米的Y2On强化层，其中0.4nm≤d1+d2≤4nm。
  9. 根据权利要求8所述的制作方法，其特征在于，该方法通过调节200℃-400℃原子层沉积温度来调节Y2On强化层中氧的含量，其中200℃倾向于形成低氧含量的Y2On强化层，n＝2.5；400℃倾向于形成高氧含量的Y2On强化层，n＝3。
  10. 根据权利要求5所述的制作方法，其特征在于，步骤3中所述对Al2Om钝化层和Y2On强化层进行原位热处理，是将Al2Om钝化层和Y2On强化层在200℃-400℃条件下在原子层淀积设备中进行原位退火处理。
  11. 根据权利要求10所述的制作方法，其特征在于，
    该方法通过调节原位热处理的温度来实现Al2Om钝化层和Y2On强化层按照一定比例的混合，混合比由Al2Om钝化层厚度d1与Y2On强化层厚度d2的比d1:d2决定，其中19:1≤d1:d2≤1:19；
    该方法通过Al2Om钝化层和Y2On强化层的混合得到AlxY2-xO3界面钝化层，实现AlxY2-xO3界面钝化层的平均配位数2.8到4.2的调控，进而满足各种器件对界面缺陷密度以及可靠性的需求，其中，平均配位数2.8是在d1:d2等于19:1、m＝3及n＝3的条件下获得的；平均配位数4.2是在d1:d2等于1:19、m＝2.5及n＝2.5的条件下获得的。
  12. 根据权利要求11所述的制作方法，其特征在于，所述AlxY2-xO3界面钝化层中1.2≤x≤1.9是作为界面钝化层的较优结果，该AlxY2-xO3界 面钝化层的平均配位数介于3.28至2.86，其中x＝1.2时平均配位数为3.28，x＝1.9时平均配位数为2.86。
  13. 根据权利要求5所述的制作方法，其特征在于，步骤4中所述在AlxY2-xO3界面钝化层上生长高介电绝缘层，是利用原子层淀积的方法，在200℃-400℃条件下在AlxY2-xO3界面钝化层上淀积厚度大于等于0nm且小于等于4nm的高介电绝缘层。
PCT/CN2015/084198 2015-07-16 2015-07-16 应用于iii-v族衬底的复合栅介质层及其制作方法 Ceased WO2017008293A1 (zh)

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