Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
  • H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
  • H03M1/0626—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by filtering
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/34—Analogue value compared with reference values
  • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
  • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type

Definitions

• Filter circuit for filtering an input signal of an analog-to-digital converter
• the invention relates to a filter circuit for filtering an input signal of an analog-to-digital converter, an analog-to-digital converter and an associated method for filtering an input signal of an analog-to-digital converter.
• An analog-to-digital converter should decide at a certain, repetitive time whether the input signal was above or below a certain threshold. By a plurality of thresholds so creates a digital representation of the signal to one each
• Input signal to be filtered before conversion (antialiasing filter).
• the input signal can be disturbed by noise or nonlinearities.
• An active filter consumes additional energy. In order to avoid a fluctuation of the sampling time, it is also endeavored in the
• Input signal is compared. Generate these fluctuations
• Filter circuit in particular for filtering an input signal of an analog-to-digital converter to provide.
• a filter circuit for filtering an input signal, in particular an analog
• the filter circuit comprises at least a first filter strand.
• the first filter strand comprises a first
• Input circuit Input circuit, a first integration circuit and a first
• the first input circuit is arranged to convert an analog input signal into at least two distinguishable first first-level output signals depending on the value of the input signal, and to forward the first-level output signals to the first integration circuit for a predetermined period of time.
• the first integration circuit is also set up, the first first-stage output signals of the first
• the first output circuit is set up, the first integration signal with a first
• the integration avoids that changes in the input signal, in particular high-frequency interference of the input signal, which are shorter than the predetermined period, have no or only a minor influence on the integration result.
• the first first-stage output signals may be of a discrete nature or a continuous image of the input signal referenced by the reference signal.
• An example of discrete first-order output signals would be the defined voltages at the output of a comparator, which compares whether the input signal is above or below a defined reference voltage.
• the first first-stage output signals can be output continuously or time-discretely.
• the first filter strand preferably has a first one
• the first input reference value can be fixed or freely programmable.
• the input signal is in one preferred embodiment with the first input reference value
• Input reference value may have a discrete value or a complex but known waveform.
• the first input circuit preferably comprises at least one input comparator and the first output circuit preferably comprises at least one output comparator.
• the first integration circuit preferably has at least a first capacitor and first switches.
• the first capacitor and the first switches are arranged in this embodiment, electrical
• Charges associated with the first first-level output signals accumulate over the predetermined time period.
• the first switches are switched so that charges flow to the first capacitor during the predetermined period of time due to the first first-stage output signals.
• the first switches are switched at the end of the specified time period to accumulate during the specified time period
• Charge can be forwarded on the first capacitor as an integration signal or the output circuit can be made available. Once the integration signal has been passed to the output circuit, the first switches are switched so that the first capacitor is discharged. In a subsequent predetermined period of time, the first capacitor be reloaded to provide an integration signal again.
• the predetermined period is preferably predetermined by a first regular time signal.
• the first regular time signal may, for example, be a periodic clock signal within one
• This clock signal can be for example a
• the first filter string preferably has a first time-discriminating circuit.
• the first circuit for time discrediting is configured to process the first two-stage output signal and convert it into a time-discrete output signal. Examples of time discriminating circuits are clocked flip-flops or latches.
• the first time discriminating circuit is preferably set up, the first two-stage
• the filter circuit preferably comprises at least a second one
• Assigned to the input signal and the second filter strand is associated with a second region of the input signal, wherein the first region of the input signal from the second region of the input signal is different.
• the first and second areas may partially overlap.
• the second filter train comprises a second input circuit, a second one
• Input circuit generates a second first-stage output signal.
• the integration circuit generates a second integration signal.
• Output circuit generates a second two-stage output signal.
• the first filter train is thus arranged to filter the first range of the input signal in the manner previously described.
• the second filter strand is thus configured to filter the second region of the input signal in the manner previously described.
• the filter circuit preferably comprises at least a third filter strand, wherein the third filter strand, a third region of the
• the third filter train comprises a third input circuit, a third one
• Input circuit generates a third first-level output signal.
• Integration circuit generates a third integration signal.
• Output circuit generates a third two-stage output signal.
• the third filter string is thus arranged to filter the third region of the input signal in the manner described above.
• the filter circuit may have further filter strands (4, 5, 6 or more), so that the
• Input signal by means of the filter strands a variety of two-stage
• Output signals or discrete-time output signals can be assigned.
• the first area, the second area, the third area and further areas of the input signal are preferably the same size.
• Input signal can thus be divided into a plurality of equally sized areas, for which the second-stage output signals or time-discrete output signals are determined by means of the individual filter strands of the filter circuit.
• the first filter strand preferably has a first one
• the second filter train a second
• the first area is by means of the first Assigned to input reference value.
• the second area is assigned by means of the second input reference value.
• the third area is assigned by means of the third input reference value.
• Thermometer code generated is preferably a time-discrete thermometer code.
• the analog-to-digital converter preferably comprises a filter circuit which generates a time-discrete thermometer code in the manner described above.
• the analog-to-digital converter further includes a
• Translation unit wherein the translation unit is adapted to convert the time-discrete thermometer code into a discrete-time binary output signal. It is a further object of the present invention to provide an improved
• the method comprises the steps:
• Claim 14 have similar and / or identical embodiment, as described in particular in the dependent claims.
• Fig. 1 shows a schematic diagram of a first filter circuit
• FIG. 2 shows a schematic diagram of a first analog-digital converter
• FIG. 3 shows a schematic diagram of a second analog-digital converter
• FIG. 4 shows a schematic diagram of a line of a third analog-to-digital converter.
• Fig. 5 shows a schematic diagram of an integrator of a
• FIG. 6 shows a schematic diagram of a method for filtering signals Detailed description of the embodiments
• the filter circuit 200 comprises a filter string 210 having an input circuit 10, an integration circuit 20 and an output circuit 30.
• An analog input signal 5 is converted by the input circuit 10 into first first-stage output signals which represent the input signal 5 into a defined reference to, for example, a defined input reference value 1 1, 12, 13, 14.
• the purpose of this referencing of the input signal 5 is the first first-order output signals by the reference to the
• the first first-stage output signals may be of a discrete nature or a continuous one by means of the input reference value 1 1, 12, 13 and 14 or
• first-order output signals would be the defined voltages at the output of a comparator, which compares whether the input signal 5 is above or below a defined reference voltage.
• the first first-stage output signals can be output continuously or time-discretely. In a discrete-time edition of the first first-stage
• Output signals are generated within the predetermined period.
• the integration circuit 20 receives the first first-stage output signals and integrates them over the predetermined period.
• the integration can be digital or analog.
• the number of time-discrete first-level output signals at a higher voltage and at a lower voltage (for example, at the output of a comparator) during the given period of time could be determined and subtracted from one another.
• a voltage resulting from a charge shift on one or more capacitors produced by the one-level output signals could be determined.
• the analog integration could have the advantage that it is less sensitive to short-term disturbances of the input signal 5.
• digital integration would require high clocking of the first first-order output signals to provide reliable integration within the system
• the integration circuit 20 generates a first integration signal 25 based on the integration of the first first-stage output signals and forwards the first integration signal 25 to the output circuit 30.
• the output circuit 30 compares the first integration signal 25 with a first output reference value and generates a first two-stage output signal 35.
• Such a filter circuit 200 could find application in particular in analog-to-digital converters.
• the analog signal would not be converted to a digital signal at a single time, this time being predetermined, for example, by the edge of a clock signal. Rather, the analog signal would be integrated over a predetermined period of time, which could correspond, for example, to a half cycle of the clock signal. The integration signal would then be used to generate the digital signal. This would have the advantage that short-term fluctuations or
• Clocksignals are to have a significantly reduced impact on the result of digitization.
• the short-term fluctuations or disturbance of the input signal 5 are preferably shorter than one half, one third, one fifth or for example one tenth of the predetermined period (in this Case a half-pode of the clock signal).
• Fig. 2 shows a schematic diagram of the first analog-to-digital converter.
• the analog-to-digital converter is a 1-bit analog-to-digital converter which comprises a filter circuit 200 with a filter string 210.
• the filter string 210 comprises an input circuit 10, which is designed as a rectifier, wherein the rectifier comprises an amplifier which is not counter-coupled.
• the rectifier depending on the input signal 5 and a first reference signal, forwards two different first-stage output signals to an integration circuit 20 of the filter string 210.
• the integration circuit 20 comprises in a simple embodiment 3 switches and a capacitor. Two switches are turned off such that the first first-stage output signal of the rectifier is forwarded to the capacitor within a first half-period of the clock signal.
• the output circuit 30 is implemented as a comparator, which compares the integration signal 25, which is output from the integration circuit 20, with a second reference signal and outputs a first two-stage output signal 35.
• Output 35 is passed to a time discriminating circuit 40 of the filter string 210.
• the time-discriminating circuit 40 is implemented as a clocked flip-flop or latch in this example.
• the clocked flip-flop outputs a time-discrete in response to the first two-stage output signal 35 and the predetermined by the clock signal timing clock
• the time-discrete output signal 45 can in given example either the value 0 or 1, wherein the 1 a first predetermined range of the amplitude of the input signal 5 (for example, positive half-wave) and the 0 a second specific range of the amplitude of the input signal 5 (for example, negative half-wave) is assigned.
• the input signal 5 is thus converted by means of the one filter strand 210 of the filter circuit 200 into a 1-bit binary signal.
• Fig. 3 shows a schematic diagram of a second analog-to-digital converter.
• the analog-to-digital converter has a filter circuit 200 with four
• Filter strands 210 on. Each of these filter strands 210 are
• Output signal to the respective integration circuit 20 pass.
• the integration circuits 20 now forward the respective integration signal 25 to the respective filter strand 210 associated output circuit 30 on.
• the output circuits 30 generate first, second, third and fourth second stage output signals which are forwarded to the time discriminating circuit 40 associated with each filter string.
• Each of the time discriminating circuits 40 outputs a time discrete output signal 45. Depending on the amplitude of the input signal 5 during the
• thermometer code 0000, 0001, 001 1, 01 1 1, 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
• the translation unit 50 could assign the respective thermometer code to a binary number using a simple assignment table (0000 -> 000, 0001 -> 001, 001 1 -> 010, 01 1 1 1 -> 01 1, 1 1 1 1 -> 100).
• Fig. 4 shows a schematic diagram of a second strand of a third analog-to-digital converter.
• the second string represents a possible concrete implementation of the second string of the analog-to-digital converter shown in FIG. 3.
• the input circuit 10 is concretely embodied as an input comparator 410 which compares the input signal 5 with the input reference value 12.
• the first first-level output signal of the input comparator 410 is forwarded to a differential stage 420a which, like the integrator 420b, is part of the integration circuit 20.
• the difference stage 420a converts this
• Integrator 420b has two branches, each branch comprising two capacitors.
• a branch is loaded in the half-period of the clock signal, in which the clock signal is high 425.
• the other branch is loaded in the half-period in which the clock signal is low 426. This is done by means of the arrangement of self-blocking transistors 422 and 42 shown in FIG.
• normally-on transistors 423 which either charge or discharge the capacitors of the first or second branch depending on the clock signal (high or low).
• the charge on the capacitors is by means of two
• Output comparators 430 included in the output circuit 30 are determined.
• An output comparator 430 is assigned to the first branch and another to the second branch of the integrator 420b.
• the outputs of the two output comparators 430 are again set to one
• the output of the first branch of the integrator 420 b associated output comparator 430 (lower part in Fig. 4 and right-hand part in Fig. 5) is thus at an input of a first clocked flip-flop passed.
• the first clocked flip flop is clocked by the clock signal low 426.
• the output of the output comparator 430 (upper part in FIG. 4 or left part in FIG. 5) assigned to the second branch of the integrator 420b is passed on to an input of a second clocked flip-flop.
• the second clocked flip flop is clocked by the clock signal high 426.
• the two branches of the integrator 420b in combination with the two output comparators 430 of the output circuit 30 and the respective associated clocked flip-flops of the time discriminating circuit 440, allow the input signal 5 to be second (second filter train) during both half cycles of the clock signal
• Input reference values 12 to convert time discrete output signals 45.
• a multiplexer 445 is then used around the discrete-time ones
• the translation unit 450 converts the
• Thermometer code as previously discussed, in a discrete-time binary
• the multiplexer 445 may in an alternative
• Embodiment also be mounted behind the translation unit 450, so that the discrete-time output signals of the two branches of the respective strand (or filter strand 210) are first digitized by means of the translation unit 450 and only then by the multiplexer 445 to a
• time discrete binary output signal 305 are composed.
• the number of filter strings 210 or strings of the analog-to-digital converter is selected as a function of which resolution is the time-discrete binary
• FIG. 6 shows a schematic diagram of a method for filtering
• an analogue input signal 5 is converted into at least two distinguishable first first-order output signals depending on the value of the input signal 5.
• this will be or integrated the first-stage output signals over a predetermined period.
• a first integration signal 25 is generated based on the result of the integration.
• a comparison of the first occurs
• step 550 based on the result of the comparison in step 540, a first two-stage output signal 35 is generated.
• Output signal 45 can in turn be converted into a discrete-time binary output signal 305.
• An influence of high-frequency fluctuations or disturbances on, for example, the digitization of analog input signals 5 compared to the given time period could thus be reduced since the digitization of the input signal no longer depends on a momentary value of the input signal 5.
• a suitably adapted filter circuit can be used, for example, in an analog-to-digital converter (ADC).
• ADC analog-to-digital converter
• the output signal of the amplifier corresponds to the
• thermometer code Periodic integration: Each bit of the thermometer code is integrated on its own for a half-period of a clock signal.
• the output of the integrator circuit is the sign whether the particular bit of the thermometer code was -1 or +1 more during the half period.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Analogue/Digital Conversion (AREA)
• Filters That Use Time-Delay Elements (AREA)

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• 2015
  • 2015-07-09 DE DE102015212848.2A patent/DE102015212848A1/de not_active Withdrawn
• 2016
  • 2016-07-05 CN CN201680040634.7A patent/CN108028660B/zh not_active Expired - Fee Related
  • 2016-07-05 WO PCT/EP2016/065856 patent/WO2017005745A1/de not_active Ceased
  • 2016-07-05 JP JP2018500574A patent/JP2018526868A/ja not_active Ceased
  • 2016-07-05 US US15/743,123 patent/US10284214B2/en active Active
  • 2016-07-05 EP EP16742192.4A patent/EP3320618B1/de active Active

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