WO2016208101A1 - 定寸装置、研磨装置、及び研磨方法 - Google Patents
定寸装置、研磨装置、及び研磨方法 Download PDFInfo
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- WO2016208101A1 WO2016208101A1 PCT/JP2016/001528 JP2016001528W WO2016208101A1 WO 2016208101 A1 WO2016208101 A1 WO 2016208101A1 JP 2016001528 W JP2016001528 W JP 2016001528W WO 2016208101 A1 WO2016208101 A1 WO 2016208101A1
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- 238000004513 sizing Methods 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims description 28
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- 229910052710 silicon Inorganic materials 0.000 description 10
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
- B24B37/013—Devices or means for detecting lapping completion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/11—Lapping tools
- B24B37/20—Lapping pads for working plane surfaces
- B24B37/205—Lapping pads for working plane surfaces provided with a window for inspecting the surface of the work being lapped
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
- B24B49/12—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Definitions
- the present invention relates to a sizing device, a polishing device, and a polishing method.
- polishing techniques such as DSP (Double Side Polishing) have become indispensable technologies that are indispensable for the manufacturing process of semiconductor devices.
- an eddy current sizing device In order to control the finishing thickness, an eddy current sizing device, a sizing device by measuring the distance from the upper surface of the carrier, a sizing device using laser light interference, and the like are used.
- the sizing accuracy of about ⁇ 0.1 ⁇ m required by the sizing device by measuring the distance from the upper surface of the carrier is not guaranteed. Further, when the eddy current sizing device and the laser beam interference sizing device are compared, the latter laser beam interference sizing device is superior in terms of restriction of the installation environment and measurement accuracy.
- the laser beam interference sizing device is an indispensable technique for increasing the uniformity of the finished thickness after polishing such as a DSP.
- the resistivity is approximately 10 ⁇ ⁇ cm or more for the P ⁇ substrate, greater than 0.01 ⁇ ⁇ cm for the P + substrate and less than 10 ⁇ ⁇ cm. In particular, in the description herein, the resistivity is 0.01 ⁇ ⁇ cm or less for the P ++ substrate. is there.
- Laser light interference sizing device injects a laser for light interference into a hole formed so as to penetrate the surface plate of the double-side polishing device.
- the substrate is rotated and revolved by rotation of the gear meshed with the carrier, and the hole is formed at a position through which the orbit of the substrate revolves. Therefore, the laser beam interference sizing device can irradiate the substrate being polished with the laser beam by entering the hole, and captures the reflected light from the front and back surfaces of the substrate at the light receiving portion almost simultaneously. .
- the signal is taken in as a digital signal and recognized as substrate thickness information using Fourier transform.
- P - or P + signal of the reflected light of the back surface of the substrate capture sufficiently in the substrate, but the reflected light becomes weak at P ++ substrate.
- FIG. 6 shows the relationship between the resistivity of the substrate (thickness: 775 ⁇ m) and the transmittance of the laser beam.
- the wavelength of laser light used in a general sizing apparatus is about 1300 nm, and the transmittance at this wavelength is about 50% for a P ⁇ substrate, but only about 1% for a P ++ substrate.
- the output of the laser beam is increased to about twice that of the measurement of the thickness of the P ⁇ substrate, and an optimum region is set as the frequency. ++ makes it possible to measure the thickness of the substrate.
- high-precision sizing is possible by changing the laser wavelength and intensity with the laser beam interference sizing device.
- the thickness data can be obtained not only on the P ⁇ substrate and the P + substrate but also on the lower resistivity P ++ substrate by optimizing the output of the laser beam and the signal used for the Fourier transform. .
- the deviation from the target thickness is deviated from the initial finished thickness of the substrate polished in the first polishing batch of that lot.
- a method of adjusting the target thickness by calculating and taking into account the deviation from the target thickness when processing the next polishing batch has come to be adopted.
- this method has a problem in that the yield is deteriorated and the production cost is increased due to the trial processing for obtaining the deviation from the target thickness at the time of changing the lot.
- the required sizing accuracy may not be maintained, and the deviation from the target thickness caused by a decrease in sizing accuracy may be suppressed.
- the yield is deteriorated by performing trial processing every time a lot is changed.
- the present invention has been made in view of the above-described problems. In continuous polishing, even when there is a lot change of a substrate to be polished, a decrease in sizing accuracy is prevented and high sizing accuracy can be obtained. It is an object to provide a size device.
- Another object is to provide a polishing method.
- the present invention is arranged in a polishing apparatus that polishes the surface of the wafer by sliding the wafer against a polishing cloth affixed to a surface plate.
- a sizing device for measuring the thickness of a wafer being polished comprising: a light source for irradiating the wafer being polished with laser light; and a wafer from the wafer being polished irradiated with the laser light from the light source
- a light receiving unit that receives the reflected light, and a calculation unit that calculates a measured value of the thickness of the wafer being polished that has been irradiated with the laser light, from the reflected light received by the light receiving unit.
- the portion is determined based on the correlation between the wafer resistivity and the wafer thickness measurement error value obtained in advance, and the wafer thickness measurement error is determined from the wafer resistivity being polished.
- the value of Providing a measuring device characterized in that the measurement error by correcting those that can be calculated thickness of the wafer in the polishing.
- the measurement error of the wafer thickness by the sizing device is calculated from the correlation between the resistivity of the wafer and the measurement error value of the wafer thickness and the resistivity of the wafer being polished. Is possible. Therefore, even if the lot of wafers to be polished changes during continuous polishing and the resistivity of the wafer to be polished changes, the measurement error can be corrected according to the resistivity, so the actual wafer of the wafer being polished can be accurately corrected. Thickness can be measured.
- the calculation unit calculates an offset value for canceling the measurement error in the measurement value based on the correlation between the resistivity of the wafer and the measurement error value of the wafer thickness. It is preferable that the measurement error of the thickness of the wafer being polished can be corrected by obtaining from the resistivity and adjusting the offset value to the measured value.
- the actual thickness of the wafer being polished is accurately measured by correcting the measurement error of the thickness of the wafer being polished by offsetting the measurement error using the offset value. can do.
- the resistivity of the wafer being polished may be obtained from the resistivity at both ends of the ingot from which the wafer being polished is cut and the portion of the ingot from which the wafer being polished is cut. it can.
- the resistivity of the wafer being polished can be easily obtained on a substrate basis.
- the correlation between the resistivity of the wafer and the measurement error value of the wafer thickness is obtained for each polishing apparatus.
- the sizing accuracy can be further improved by using the above correlation for each polishing apparatus. It will be a thing.
- the resistivity of the wafer is preferably 0.01 ⁇ ⁇ cm or less.
- the sizing apparatus of the present invention can be particularly suitably used when measuring the thickness of a low-resistance wafer having a resistivity of 0.01 ⁇ ⁇ cm or less.
- the present invention provides a polishing apparatus in which any one of the above sizing devices is provided.
- the thickness of the wafer being polished can be accurately calculated, so that a wafer with little deviation from the target thickness can be obtained. Moreover, since it is not always necessary to carry out trial processing for calculating the deviation from the target thickness, the yield can be improved.
- the present invention provides a polishing process for polishing a surface of a wafer by sliding the wafer against a polishing cloth affixed to a surface plate. Polishing is performed while measuring the thickness of the wafer being polished by a sizing device that measures the thickness, and polishing is performed when the measured value of the thickness of the wafer being polished by the sizing device reaches a predetermined value.
- a correlation deriving step of obtaining a correlation between the wafer resistivity and the value of the measurement error of the wafer thickness in advance before performing the polishing step Based on the correlation between the resistivity of the wafer and the measurement error value of the wafer thickness in the polishing process, the measurement error value of the thickness of the wafer being polished is calculated from the resistivity of the wafer being polished. And The measurement error is corrected to provide a polishing method characterized by polishing the wafer while calculating the thickness of the wafer in the polishing.
- the wafer thickness measurement error by the sizing device is calculated from the correlation between the wafer resistivity and the wafer thickness measurement error value, and the wafer resistivity during polishing. Can be calculated. Therefore, even when the lot of wafers to be polished changes during continuous polishing, and the resistivity of the wafer to be polished changes, the measurement error can be corrected according to the resistivity, so the wafer with less deviation from the target thickness Can be obtained. In addition, since it is not always necessary to perform trial processing for calculating a deviation from the target thickness every time a lot of the wafer is changed, the yield can be improved.
- the polishing method of the present invention is based on the correlation between the resistivity of the wafer and the value of the measurement error of the wafer thickness, in the measurement value of the thickness of the wafer being polished by the sizing device.
- the offset value for canceling the measurement error is calculated from the resistivity of the wafer to be polished, and the offset value is added to or subtracted from the measured value of the thickness of the wafer that is being polished. It is preferable to correct the measurement error.
- the measurement error of the thickness of the wafer being polished can be corrected by offsetting the measurement error by the offset value.
- the polishing method of the present invention measures a plurality of test wafers having different resistivities in advance with the sizing device before the correlation deriving step.
- the correlation between the wafer resistivity and the measurement error value of the wafer thickness is obtained from the thickness of the test wafer after the test polishing. It is preferable to determine the relationship.
- the correlation between the resistivity of the wafer and the value of the measurement error of the wafer thickness can be obtained in this way.
- the resistivity of the wafer to be polished can be obtained from the resistivity at both ends of the ingot from which the wafer to be polished is cut out and the portion of the ingot from which the wafer has been cut out.
- the resistivity of the wafer to be polished can be easily obtained for each substrate.
- the correlation between the resistivity of the wafer and the value of the measurement error of the wafer thickness is obtained for each polishing apparatus.
- the sizing accuracy can be further improved by using the above correlation for each polishing apparatus.
- the wafer to be polished has a resistivity of 0.01 ⁇ ⁇ cm or less.
- the polishing method of the present invention can be used particularly suitably when polishing is performed while measuring the thickness of a low-resistance wafer having a resistivity of 0.01 ⁇ ⁇ cm or less.
- the present invention it is possible to prevent a decrease in sizing accuracy due to a lot change of a substrate to be polished and to obtain a high sizing accuracy. Therefore, it is possible to obtain a substrate with a small deviation from a target thickness and to test a substrate Since it is not always necessary to perform processing, the yield can be improved.
- the present inventors have conducted intensive studies to solve such problems, and have found that the resistivity of the wafer has a correlation with the value of the measurement error of the wafer thickness. Then, the present inventors completed the present invention by conceiving that the thickness of the wafer can be calculated more accurately by correcting the measurement error from the correlation and the resistivity of the wafer to be polished.
- FIG. 1 shows an example in which the sizing device of the present invention is disposed in a double-side polishing apparatus. As shown in FIG. 1, the sizing apparatus 1 of the present invention can be disposed in a double-side polishing apparatus 10.
- the double-side polishing apparatus 10 includes an upper surface plate 11 and a lower surface plate 12 provided so as to face each other vertically, and a polishing cloth 13 is attached to each surface plate 11, 12. It is attached.
- a sun gear 14 is provided at the center between the upper surface plate 11 and the lower surface plate 12, and an annular internal gear 15 is provided at the periphery.
- the wafer W is held in the holding hole of the carrier 16 and is sandwiched between the upper surface plate 11 and the lower surface plate 12.
- the sizing apparatus 1 of the present invention measures the thickness of a wafer being polished by a polishing apparatus by laser light interference.
- This sizing apparatus 1 includes a light source 2 for irradiating a laser beam onto a wafer W being polished by the double-side polishing apparatus 10 as described above, a light receiving unit 3 for receiving reflected light from the wafer W being polished, and reflected light.
- the calculation unit 4 for calculating the measured value of the thickness of the wafer W being polished is provided. Further, as shown in FIG. 1, the incident light on the wafer W and the reflected light from the wafer W pass through a hole 17 provided in the upper surface plate 11.
- the calculation unit 4 calculates the resistance of the wafer W during polishing based on the correlation between the wafer resistivity and the measurement error value of the wafer thickness that has been obtained in advance.
- the value of the measurement error of the thickness of the wafer being polished can be calculated from the rate, and the thickness of the wafer W being polished can be calculated by correcting the measurement error.
- the calculation unit 4 calculates the offset value for offsetting the measurement error in the measurement value based on the correlation between the resistivity of the wafer and the measurement error value of the wafer thickness. It is possible to correct the measurement error of the thickness of the wafer being polished by calculating from the resistivity and adjusting the offset value to the measurement value.
- a terminal such as a personal computer (PC) as the calculation unit 4.
- PC personal computer
- the polishing method of the present invention includes a correlation deriving step of obtaining a correlation between the resistivity of the wafer and the value of the measurement error of the wafer thickness in advance before performing the polishing step of the wafer W.
- the above correlation can be obtained as follows. First, prior to the correlation derivation step, a test polishing step is performed in which a plurality of test wafers having different resistivities are subjected to test polishing while measuring the thickness of the test wafer using a sizing device. In the test polishing, the polishing is stopped when the measured value of the thickness of the test wafer by the sizing device reaches the target thickness value.
- the sizing device 1 of the present invention may be used as a sizing device. However, since the above correlation is not obtained at this time, the measurement error in the measurement value of the thickness of the test wafer is not corrected.
- a correlation derivation process is performed.
- the correlation between the wafer resistivity and the wafer thickness measurement error value can be obtained.
- [measurement error] obtained by calculating ([actual thickness of test wafer]-[target thickness]) from polishing data of wafers of various resistivity recorded in the test polishing process, The relationship with the resistance value of the test wafer] is plotted, and the relational expression of the measurement error due to the resistivity can be obtained by the least square method.
- FIGS. 2 and 3 show the relationship between resistivity and measurement error obtained in the examples described later.
- an approximate straight line having a high correlation is obtained between [measurement error] and [resistance value of test wafer].
- the correlation between the resistivity of the wafer and the value of the measurement error of the wafer thickness can be obtained.
- the correlation between the wafer resistivity and the value of the measurement error of the wafer thickness for each polishing apparatus.
- the slope and intercept may differ slightly for each polishing device equipped with a sizing device, so the measurement error is calculated with high accuracy.
- the sizing accuracy is further improved if the relational expression is constantly updated and used.
- polishing is performed while measuring the thickness of the wafer being polished by a sizing device that measures the thickness of the wafer being polished by laser light interference. Then, the polishing is stopped when the measured value of the thickness of the wafer being polished by the sizing device reaches a predetermined value.
- the wafer thickness being polished is determined from the resistivity of the wafer being polished. The value of the measurement error is calculated. Then, the wafer is polished while correcting the measurement error and calculating the thickness of the wafer being polished.
- the measurement error can be corrected as follows. First, based on the correlation between the resistivity of the wafer and the measurement error value of the wafer thickness as shown in FIG. 3, the measurement error in the measurement value of the wafer thickness being polished by the sizing device is calculated. An offset value for canceling is calculated from the resistivity of the wafer to be polished.
- the resistivity of the wafer to be polished can be determined from, for example, the resistivity at both ends of the ingot from which the wafer to be polished is cut out and the portion where the wafer of the ingot is cut out. Since the resistivity of the ingot is always measured before cutting (slicing) the wafer, the resistivity at both ends of the ingot can be easily obtained. Moreover, since the segregation phenomenon occurs when the ingot manufactured by the CZ pulling method is pulled, if the distance from the end of the ingot is used, the resistivity of the portion can be easily obtained. Therefore, it is possible to easily obtain the resistivity of the wafer to be polished in the unit of the substrate arranged and distinguished in the cut-out order.
- the calculation unit 4 cancels the measurement error by adding or subtracting the offset value to the measured value of the thickness of the wafer being polished. Thereby, the actual thickness of the wafer can be accurately calculated.
- the present invention calculates the value of the measurement error generated in the main polishing from the correlation between the wafer resistivity and the measurement error value of the wafer thickness and the resistivity of the wafer to be polished. It is possible to accurately calculate the actual thickness of the wafer being polished by measuring the thickness of the wafer being polished while correcting the measurement error. Therefore, trial processing is not necessarily required, and polishing with less deviation between the target thickness and the finished thickness is possible.
- the deviation of the finished thickness from the target thickness is about ⁇ 0.1 ⁇ m, or It is possible to suppress it smaller than this.
- Example 2 Using a double-side polishing apparatus 10 with a sizing apparatus 1 as shown in FIG. 1, a plurality of silicon wafers having a diameter of 300 mm were continuously polished by the polishing method of the present invention.
- caustic potash was added to colloidal silica having an average particle size of 35 to 70 nm, and diluted with pure water so that the pH became 10.5.
- a commercially available nonwoven fabric type was used for the polishing cloth.
- a double-side polishing apparatus 10 as shown in FIG. 1, a plurality of test P ++ silicon wafers (resistivity: 7.2 to 9.3 m ⁇ ⁇ cm) having different resistivities were continuously subjected to test polishing. .
- a PC was used as the calculation unit 4, and the PC was connected to the double-side polishing apparatus 10 to manage the input records of the actual wafer finish thickness, target thickness, offset value, and resistivity.
- the laser beam of the sizing apparatus was an infrared wavelength tunable laser, the wavelength was 1300 nm, and the output was 10 mW or more.
- Fig. 2 shows the relationship between the change in the resistivity of the test wafer and the measurement error (deviation from the target thickness of the finished thickness) during the test polishing. As can be seen from FIG. 2, there is a high correlation between the resistivity of the wafer and the measurement error.
- FIG. 3 shows the relationship between [measurement error] and [test wafer resistance] obtained here. As can be seen from FIG. 3, an approximate straight line with high correlation was obtained.
- the measurement error can be offset by subtracting the offset value ⁇ 0.2035 ⁇ m from the measurement value (adding 0.2035 ⁇ m). It can be seen that the finished thickness can be obtained.
- the resistivity of the wafer to be polished was measured before cutting out the substrate, and recorded in a PC (calculation unit 4) database together with lot information.
- the calculation unit 4 is loaded with a program that automatically calls the lot information and resistivity data before polishing and automatically calculates the offset amount from the difference between the resistivity of the wafer to be polished and the resistivity of the wafer in the previous lot. I kept it.
- polishing was performed while changing the offset value from the resistivity of the wafer to be polished when changing the lot. If such a program is introduced into the calculation unit 4, it is possible to sufficiently cope with changing the target thickness.
- FIG. 4 shows the distribution of the deviation from the target thickness of the finished thickness of the wafer continuously polished as described above.
- the deviation from the target thickness was suppressed to be small compared to the comparative example described later.
- the ratio of wafers whose deviation from the target thickness was within ⁇ 0.1 ⁇ m was higher than that of the comparative example described later. This is because highly accurate sizing can be performed by appropriately correcting the thickness measurement error in accordance with the change in the resistivity of the wafer when the lot is changed.
- a silicon wafer having a diameter of 300 mm was polished under the same conditions as in the example except that the sizing apparatus was a general sizing apparatus that performed polishing without correcting measurement errors.
- Fig. 5 shows the distribution of the deviation of the finished thickness of the polished wafer from the target thickness. As shown in FIG. 5, the variation in the finished thickness increased, and the deviation from the target thickness also increased. In particular, the percentage of wafers whose deviation from the target thickness was ⁇ 0.1 ⁇ m or more has increased significantly compared to the examples.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
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Abstract
Description
図1に示すような定寸装置1付きの両面研磨装置10を使用し、本発明の研磨方法で複数の直径300mmのシリコンウェーハを連続的に研磨した。研磨剤は、平均粒径35~70nmのコロイダルシリカに、苛性カリを添加し、pHが10.5となるように純水で希釈した。研磨布には、市販の不織布タイプを使用した。
定寸装置を、従来の測定誤差を補正しないで研磨を行う一般的な定寸装置としたこと以外、実施例と同様な条件で直径300mmのシリコンウェーハの研磨を実施した。
Claims (12)
- 定盤に貼り付けられた研磨布にウェーハを摺接することで前記ウェーハの表面を研磨する研磨装置に配設され、レーザー光干渉により前記研磨装置で研磨中のウェーハの厚さを測定する定寸装置であって、
前記研磨中のウェーハにレーザー光を照射するための光源と、
該光源から前記レーザー光を照射された前記研磨中のウェーハからの反射光を受光する受光部と、
該受光部で受光した前記反射光から、前記レーザー光を照射された前記研磨中のウェーハの厚さの測定値を算出する算出部とを有し、
該算出部は、予め求めておいた、ウェーハの抵抗率とウェーハの厚さの測定誤差の値との相関関係に基づき、前記研磨中のウェーハの抵抗率から前記研磨中のウェーハの厚さの測定誤差の値を算出し、該測定誤差を補正して前記研磨中のウェーハの厚さを算出できるものであることを特徴とする定寸装置。 - 前記算出部は、ウェーハの抵抗率とウェーハの厚さの測定誤差の値との相関関係に基づいて、前記測定値における測定誤差を相殺するためのオフセット値を前記研磨中のウェーハの抵抗率から求め、前記測定値に前記オフセット値を加減することで、前記研磨中のウェーハの厚さの測定誤差を補正することができるものであることを特徴とする請求項1に記載の定寸装置。
- 前記研磨中のウェーハの抵抗率は、前記研磨中のウェーハを切り出したインゴットの両端の抵抗率、及び前記インゴットの前記研磨中のウェーハを切り出した部位から求めたものであることを特徴とする請求項1又は請求項2に記載の定寸装置。
- 前記ウェーハの抵抗率とウェーハの厚さの測定誤差の値との相関関係は、前記研磨装置毎に求めたものであることを特徴とする請求項1から請求項3のいずれか1項に記載の定寸装置。
- 前記ウェーハの抵抗率が0.01Ω・cm以下であることを特徴とする請求項1から請求項4のいずれか1項に記載の定寸装置。
- 請求項1から請求項5のいずれか1項に記載の定寸装置が配設されたものであることを特徴とする研磨装置。
- 定盤に貼り付けられた研磨布にウェーハを摺接することで前記ウェーハの表面を研磨する研磨工程において、レーザー光干渉により研磨中のウェーハの厚さを測定する定寸装置によって、前記研磨中のウェーハの厚さを測定しながら研磨を行い、前記定寸装置による研磨中のウェーハの厚さの測定値が所定値となった時点で研磨を停止する研磨方法であって、
前記研磨工程を行う前に、予め、ウェーハの抵抗率とウェーハの厚さの測定誤差の値との相関関係を求めておく相関関係導出工程を有し、
前記研磨工程において、前記ウェーハの抵抗率とウェーハの厚さの測定誤差の値との相関関係に基づき、前記研磨中のウェーハの抵抗率から前記研磨中のウェーハの厚さの測定誤差の値を算出し、該測定誤差を補正して前記研磨中のウェーハの厚さを算出しながら前記ウェーハを研磨することを特徴とする研磨方法。 - 前記ウェーハの抵抗率とウェーハの厚さの測定誤差の値との相関関係に基づいて、前記定寸装置による前記研磨中のウェーハの厚さの測定値における測定誤差を相殺するためのオフセット値を、研磨するウェーハの抵抗率から算出し、前記研磨中のウェーハの厚さの測定値に前記オフセット値を加減することで、前記研磨中のウェーハの厚さの測定誤差を補正することを特徴とする請求項7に記載の研磨方法。
- 前記相関関係導出工程の前に、予め、抵抗率が互いに異なる複数の試験用ウェーハを、前記定寸装置により、前記試験用ウェーハの厚さを測定しながら試験研磨する試験研磨工程を有し、前記相関関係導出工程において、前記試験研磨後の前記試験用ウェーハの厚さから、前記ウェーハの抵抗率とウェーハの厚さの測定誤差の値との相関関係を求めることを特徴とする請求項7又は請求項8に記載の研磨方法。
- 前記研磨するウェーハの抵抗率を、前記研磨するウェーハを切り出すインゴットの両端の抵抗率及び前記インゴットの前記ウェーハを切り出した部位から求めることを特徴とする請求項7から請求項9のいずれか1項に記載の研磨方法。
- 前記ウェーハの抵抗率とウェーハの厚さの測定誤差の値との相関関係は、前記研磨装置毎に求めることを特徴とする請求項7から請求項10のいずれか1項に記載の研磨方法。
- 前記研磨するウェーハを、抵抗率が0.01Ω・cm以下のものとすることを特徴とする請求項7から請求項11のいずれか1項に記載の研磨方法。
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