WO2016201609A1 - Transistor à couches minces d'oxyde métallique et panneau d'affichage, ainsi que procédés de préparation de ceux-ci - Google Patents

Transistor à couches minces d'oxyde métallique et panneau d'affichage, ainsi que procédés de préparation de ceux-ci Download PDF

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Publication number
WO2016201609A1
WO2016201609A1 PCT/CN2015/081485 CN2015081485W WO2016201609A1 WO 2016201609 A1 WO2016201609 A1 WO 2016201609A1 CN 2015081485 W CN2015081485 W CN 2015081485W WO 2016201609 A1 WO2016201609 A1 WO 2016201609A1
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metal oxide
layer
source
electrode
active layer
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PCT/CN2015/081485
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English (en)
Chinese (zh)
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张盛东
邓伟
肖祥
贺鑫
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北京大学深圳研究生院
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Priority to PCT/CN2015/081485 priority Critical patent/WO2016201609A1/fr
Publication of WO2016201609A1 publication Critical patent/WO2016201609A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to the field of semiconductor device manufacturing, and in particular, to a thin film transistor, a display panel, and a method of fabricating the same.
  • TFT LCD Thin Film Crystal Liquid Crystal Display
  • amorphous oxide thin film transistors typified by a-IGZO (amorphous indium gallium zinc oxide) have been widely concerned.
  • the mobility of the metal oxide semiconductor TFT is generally 10 cm 2 /Vs, which is ten times that of the amorphous silicon TFT (0.5 to 1 cm 2 /Vs), and therefore, the on-state current of the metal oxide semiconductor TFT is large.
  • the driving ability is strong, which can meet the requirements of modern flat panel display for high frame rate, high resolution and narrow border.
  • IGZO thin films are easily formed into an amorphous state at normal temperature. Since amorphous structures do not have grain boundaries, they can maintain good uniformity over a large area and are suitable for large-size display applications.
  • a back channel etch (BCE) structure BCE
  • ESL etch stop
  • the metal oxide semiconductor film Since there is no etch barrier layer on the metal oxide semiconductor in the BCE structure, the metal oxide semiconductor film is generally sensitive to the acid and alkali environment, and is easily corroded during the source-drain patterning process, so the BCE structure is relatively Hard to achieve.
  • the realization of the BCE type metal oxide semiconductor TFT is of great significance in reducing production cost and improving display performance.
  • the technical problem to be solved by the present invention is that a thin film transistor for preparing a BCE structure is difficult, complicated, and costly for the prior art, and a thin film transistor and a method for fabricating the same are provided.
  • the method of the present invention provides a source-drain electrode using transparent conductive
  • the material can replace the ITO as a pixel electrode while forming the source/drain pattern, which can simplify the fabrication process of the device, save manufacturing cost, and easily realize metal wiring technology with high conductance and difficult etching, such as Cu, and can further improve display performance. And reduce costs.
  • a metal oxide thin film transistor including a gate electrode is provided;
  • the source and the drain are separated from each other, and the source and the drain are electrically contacted with the active layer, respectively, and the source and drain electrodes are metal oxide conductive materials.
  • the transistor wherein the source and drain electrodes are metal oxide transparent conductive materials.
  • a display panel comprising:
  • the thin film transistor being arranged corresponding to a pixel, the thin film transistor including a gate electrode, an active layer, and mutually separated source and drain, the active layer being isolated from the gate electrode by the gate dielectric layer,
  • the source layer is made of a metal oxide semiconductor material, the source and the drain are respectively electrically contacted with the active layer, and the source and drain electrodes are metal oxide transparent conductive materials;
  • a pixel electrode disposed corresponding to the pixel, wherein one of the source and drain electrodes in the thin film transistor is integrally formed with the pixel electrode;
  • a data electrode electrically connected to the other of the source and drain electrodes through an interconnection.
  • the display panel further includes a passivation layer covering the gate dielectric layer, the active layer, the source/drain electrode region and the pixel electrode region, the passivation layer is a transparent passivation layer, and the data electrode is a metal An electrode that widens the width of the segment line passing through the thin film transistor so as to cover the passivation layer of the thin film transistor region.
  • a method for fabricating a metal oxide thin film transistor comprising:
  • the transparent conductive layer is patterned using an etching solution to form a source/drain electrode.
  • the method for preparing a thin film transistor wherein the metal oxide conductive layer is a metal oxide transparent conductive material.
  • the active layer is photolithographically and etched to form an active region before the metal oxide conductive layer is formed.
  • the method for fabricating a thin film transistor wherein the gate dielectric layer, the active layer, and the metal oxide conductive layer are continuously grown, and after forming the source/drain electrode region, photolithography and etching of the active layer are formed. Active area.
  • a method for preparing a display panel including:
  • the metal oxide transparent conductive layer uses a material having a corrosion rate higher than that of the active layer;
  • a metal conductive wiring layer is formed on the surface of the passivation layer, and is formed by photolithography and etching to form a data electrode and an interconnection.
  • the data electrode is electrically connected to the other of the source and drain electrodes through the interconnection.
  • the method for fabricating a display panel is characterized in that the data electrode is widened in a width of a segment line passing through the thin film transistor so as to cover the passivation layer of the thin film transistor region.
  • the invention discloses a metal oxide thin film transistor, a display panel and a preparation method thereof, wherein a source-drain electrode is prepared by using a metal oxide transparent conductive layer, and an ITO pixel electrode is replaced by a drain to reduce the use of the rare element In. Reducing the production cost; utilizing the difference in etching selectivity between the metal oxide transparent conductive layer and the active layer to avoid damage to the channel region, improving product quality; using the gate electrode as a mask to form a source-drain electrode region pattern, which reduces The use of the mask enables precise alignment of the gate electrode and the channel region, reduces parasitic effects, improves device performance uniformity and operating speed, simplifies the process, reduces production costs, and performs passivation outside the passivation layer. Wiring, reducing the difficulty of the wiring process, using common high-conductivity metal wiring such as copper or aluminum, and wiring outside the passivation layer, while shielding the TFT tube, without the need for separate matrix blocks, further reducing the production cost.
  • FIG. 1 is a cross-sectional structural view of a preferred embodiment of a thin film transistor of the present invention
  • FIG. 2 is a flow chart showing a preferred embodiment of a method for fabricating a metal oxide thin film transistor of the present invention
  • (a) is a schematic view of a process step for forming a gate electrode
  • FIG. 4 is a flow chart showing a second embodiment of a method for fabricating a metal oxide thin film transistor of the present invention.
  • (b) is a schematic diagram of a process step of photolithographically coating a metal oxide conductive layer with a gate electrode as a mask;
  • Figure 6 (a) is a perspective structural view of a display panel of the present invention.
  • Figure 6 (b) is a cross-sectional view of the display panel of the present invention.
  • Figure 6 (c) is a cross-sectional view showing another embodiment of the display panel of the present invention.
  • FIG. 7 is a flow chart of an embodiment of a method of fabricating a display panel of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • a thin film transistor includes a gate electrode 110 formed on a substrate 100, a gate dielectric layer 120 formed on the substrate 100 and covering the gate electrode 110, and a gate dielectric layer 120 formed on the gate electrode 110.
  • a gate electrode 110 formed on a substrate 100
  • a gate dielectric layer 120 formed on the substrate 100 and covering the gate electrode 110
  • a gate dielectric layer 120 formed on the gate electrode 110.
  • an active layer 130 separated from the gate electrode 110 by the gate dielectric layer 120, and a source/drain electrode over the active layer 130.
  • the portion of the active layer 130 that is aligned with the gate electrode 110 forms a channel region 131.
  • the source electrode 151 and the drain electrode 152 are separated from each other on both sides of the channel region 131 and are in electrical contact with the active layer 130.
  • the source/drain electrodes are made of a metal oxide transparent material, and the metal oxide used for the source and drain electrodes has a higher etching selectivity than the active layer 130, so that the channel region can be avoided when etching the source drain electrode. 131 was damaged.
  • the surface of the gate dielectric layer 120 also functions as a passivation layer 160.
  • the passivation layer 160 covers the gate dielectric layer 120 and the active layer 130.
  • the surface of the passivation layer 160 is provided with a contact hole for connecting the data electrodes. 171.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the present invention also provides a method for fabricating the above metal oxide thin film transistor, as shown in FIG. 2, comprising the following steps:
  • a high-conductivity film of 100 to 300 nm thick is formed on the substrate 100 by thermal evaporation, electron beam evaporation or magnetron sputtering, and then processed to form a gate.
  • the electrode 110 can be formed into a gate electrode 110 by photolithography and etching.
  • the gate electrode 110 is a metal conductive material such as chromium, molybdenum, titanium or aluminum, and a high-conductivity metal oxide such as ITO, AZO, BZO, ZnO, etc. may be used, by magnetron sputtering or reactive sputtering.
  • a highly conductive film is formed, and the gate electrode 110 is formed after being processed.
  • the substrate 100 is a high temperature resistant material, such as a glass substrate, or a non-high temperature resistant material such as a transparent plastic substrate.
  • the gate dielectric layer and the active layer are continuously formed by covering the gate electrode on the substrate.
  • a 100-400 nm thick insulating film is formed on the substrate 100, and the insulating film is made of an insulating material such as silicon nitride or silicon oxide and covers the entire substrate 100 and the gate electrode 110.
  • the method for generating the theater film may be a plasma enhanced chemical vapor deposition method, a magnetron sputtering method, a reverse sputtering method, or the like.
  • a metal oxide semiconductor thin film is formed on the gate dielectric layer 120 by magnetron sputtering or reactive sputtering to form an active layer 130 having a thickness of 20 to 200 nm.
  • the active layer 130 is made of an amorphous or polycrystalline metal oxide semiconductor material such as a zinc oxide-based or indium oxide-based film.
  • amorphous or polycrystalline metal oxide semiconductor material such as a zinc oxide-based or indium oxide-based film.
  • the target used is composed of a mixed material of gallium oxide, indium oxide, and zinc oxide.
  • the target used is an indium oxide ceramic target or an indium metal target having a purity equal to or better than 99.99%.
  • the active layer 130 is formed by a magnetron sputtering method or a reactive sputtering method, and the sputtering gas pressure is between 0.1 and 2.5 Pa, and the gas is a mixed gas of argon gas and oxygen gas.
  • a positive photoresist is coated on the surface of the active layer 130, and an active region pattern is formed by photolithography and etching, wherein the active region is aligned with the gate electrode 110.
  • Channel region 131 As shown in FIG. 3(c), a positive photoresist is coated on the surface of the active layer 130, and an active region pattern is formed by photolithography and etching, wherein the active region is aligned with the gate electrode 110. Channel region 131.
  • a metal oxide conductive layer covering the active layer is formed on the gate dielectric layer and processed to form a source-drain electrode.
  • a metal oxide conductive film 150 having a thickness of 50 to 400 nm is formed on the gate dielectric layer 120 as a metal oxide conductive layer, and the metal oxide conductive film 150 is non- A crystalline or polycrystalline transparent metal oxide conductive material such as AZO or BZO.
  • a positive photoresist is coated on the surface of the metal oxide conductive film 150, and after exposure and development, a portion corresponding to the channel region 131 is exposed, and then the conductive film 150 is wet-etched to etch away the channel.
  • a portion corresponding to the region 131 forms a source/drain electrode pattern, and forms a source 151 and a drain 152 which are separated from each other.
  • the source 151 and the drain 152 are separated from each other on both sides of the channel region 131.
  • the conductive film 150 can be formed by continuous deposition using a magnetron sputtering method or a reactive sputtering method, wherein the sputtering gas pressure is between 0.1 and 2.5 Pa, and the gas is a mixed gas of argon gas and oxygen gas. Pure argon.
  • the conductive film 150 is selected from a metal oxide having a higher etching rate in the acid-base etching solution than the active layer 130.
  • the step of wet etching selects an etching solution having a difference in metal oxide selectivity ratio between the metal oxide semiconductor material of the active layer 130 and the conductive film 150.
  • the difference in the etching rate of the metal oxide conductive film 150 and the active layer 130 in the weakly acidic or weakly alkaline solution is utilized to avoid the formation of the channel region 131 during the etching process. Into the damage.
  • a passivation layer 160 covering the gate dielectric layer 120, the source/drain electrodes, and the channel region 131 is formed.
  • a 100-300 nm thick silicon nitride layer or a silicon oxide or aluminum oxide material is deposited as a passivation layer 160 by plasma enhanced chemical vapor deposition (PECVD) or magnetron sputtering.
  • the passivation layer 160 can also be prepared by using other transparent insulating materials, which can protect the internal components and can pass the light without damage.
  • This embodiment is an improvement of the preparation method of the metal oxide thin film transistor based on the second embodiment.
  • the difference between this embodiment and the previous embodiment is that, in the embodiment, the gate electrode 110 is used as a mask, and a negative photoresist is coated on the surface of the transparent conductive film 150, and is exposed upward from the bottom of the substrate 100, and is photolithographically and engraved. The etch forms a source/drain electrode region 151 and a pixel electrode region 152.
  • the method for preparing a thin film transistor in this embodiment includes the steps of:
  • the difference from the first embodiment is that the material used for the gate electrode 110 in this embodiment selects an opaque metal conductive material. High conductance opaque metal oxide materials can be used.
  • the substrate 100 is a high temperature resistant transparent material, such as a glass substrate, or a non-high temperature transparent material such as a transparent plastic substrate.
  • a gate dielectric layer, an active layer, and a metal oxide conductive layer are continuously formed on the substrate by covering the gate electrode.
  • an insulating film, a metal oxide semiconductor film, and a metal oxide conductive film 150 are sequentially deposited on the substrate over the gate electrode, respectively as the gate dielectric layer 120, the active layer 130, and the pre-layer.
  • a metal oxide conductive layer of the source and drain electrodes is prepared.
  • the gate dielectric layer 120 is made of a transparent insulating material
  • the active layer 130 is made of an amorphous or polycrystalline metal oxide semiconductor transparent material
  • the metal oxide conductive layer is made of a transparent metal oxide conductive material.
  • the metal oxide conductive layer selects a material having an etching ratio higher than that of the active layer 130, that is, the etching rate of the conductive film 150 pre-prepared from the source/drain electrode in the acid-base etching solution is higher than that of the active layer 130 semiconductors.
  • the deposition method and thickness of each layer in this embodiment are the same as those of the previous embodiment, and are not described herein again.
  • S131 exposing upward from the bottom of the substrate, and etching the metal oxide transparent conductive layer to form a source drain pattern.
  • a negative photoresist 154 is coated on the surface of the transparent conductive film 150, and is exposed upward from the bottom of the substrate 100, and the negative photoresist 154 opposite to the gate electrode 110 is not received by light. Dissolved, a portion of the conductive film 150 corresponding to the gate electrode 110 is exposed, and the negative photoresist 154 located on both sides of the portion is cured by exposure. Then exposed bare conductive thin The film 150 is etched to form a source 151 and a drain 152 which are separated from each other, and a source-drain electrode pattern as shown in Fig. 5(c) appears. The remaining negative photoresist 154 is then removed. A preliminary pattern of source and drain electrodes formed by this step.
  • the conductive film 150 and the active layer 130 are photolithographically etched and etched using a positive photoresist to form a source/drain electrode and an active region pattern as shown in FIG. 5(d).
  • the conductive film 150 and the active layer 130 are preferably etched by etching, and an etching solution capable of simultaneously etching the metal oxide conductive film 150 and the metal oxide semiconductor active layer 130 is selected.
  • the conductive film 150 is etched a second time to form a complete source/drain electrode pattern.
  • the gate electrode 110 is used as a mask, and the source and drain electrodes are prepared by negative photoresist lithography and etching the metal oxide conductive layer, compared with the previous implementation.
  • the mask required for the photolithographic metal oxide conductive layer is omitted, further reducing the production cost.
  • the gate electrode 110 is used as a mask to be exposed upward from the bottom of the substrate 100, which can achieve self-alignment of the channel region 131 and the gate electrode, reduce parasitic effects, and improve device performance uniformity and working speed. And reduce the difficulty of production and shorten the process.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • FIG. 6 (a) is a schematic structural diagram of a single pixel unit in the display panel according to the embodiment.
  • the display panel provided in this embodiment includes a plurality of pixel units, and data electrodes 172 between the pixel units, and each of the pixels is arranged with a metal oxide thin film transistor 10 and a pixel electrode 153, and the source and the drain in the thin film transistor 10
  • One pole of the pole is integrally formed with the pixel electrode 153; the data electrode 172 is electrically connected to the other of the source and drain electrodes through an interconnection.
  • the thin film transistor 10 includes a gate electrode 110 on the substrate 100, an active layer 130, and a source 151 and a drain 152 which are separated from each other, and the active layer 130 passes through the gate dielectric layer.
  • the 120 is isolated from the gate electrode 110, and the source 151 and the drain 152 are in electrical contact with the active layer 130, respectively.
  • the active layer 130 is made of a metal oxide semiconductor material, and the source and drain electrodes are made of a metal oxide transparent conductive material.
  • the pixel electrode 153 and the drain electrode 152 are integrally formed.
  • the active layer 130 is disposed as a channel region 131 corresponding to the gate electrode 110, and the source electrode 151 is separated from the drain electrode 152 at both sides of the channel region 131.
  • the drain 152 extends away from the end of the source 151 and widens to serve as the pixel electrode 153. Therefore, in the present embodiment, the drain 152 and the pixel electrode 153 have a unitary structure.
  • the ITO pixel electrode is replaced by the drain 152, so that the ITO pixel electrode is not separately prepared, the use of the rare element In is reduced, and the process of separately preparing the pixel electrode is omitted, thereby reducing the difficulty of production and processing, and greatly Reduce production costs.
  • the gate electrode of the thin film transistor 10 is electrically connected to the scan line 111 , the source is electrically connected to the data electrode 170 through the contact hole 171 , and the drain is connected to the pixel electrode 153 .
  • the voltage applied to the gate is controlled by the scan line 111 to achieve conduction and turn-off between the source and the drain.
  • the IC signal input of the source is controlled by the data electrode 170, thereby controlling the luminance of the pixel electrode.
  • the conductive metal film of the metal wiring layer of the embodiment is prepared by using one of Mo, Cr, Al, Cu, or the like.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • the data electrode 170 is made of an opaque metal material, and the surface of the thin film transistor 10 is covered with a transparent passivation layer, and the passivation layer is made of a transparent insulating material. Preparation, such as a silicon nitride layer or silicon dioxide, and covering the gate dielectric layer, the active layer, the source and drain electrode regions, and the pixel electrode region.
  • the data electrode 170 is widened by the width of the thin film transistor 10 and covers the passivation layer corresponding to the entire thin film transistor.
  • the data electrode 170 is an opaque metal electrode, the data electrode 170 functions as a shadow block of the matrix block in the prior art in this section, and it is no longer necessary to separately prepare the light shielding matrix block.
  • the present embodiment employs copper as a wiring layer.
  • This embodiment provides a method for preparing the above display panel.
  • the process of the method is as shown in FIG. 7 and includes the following steps:
  • This step is similar to step S110 of the second embodiment. For details, refer to FIG. 3(a) and corresponding description.
  • step S220 sequentially covering the gate electrode on the substrate to sequentially generate a gate dielectric layer and a metal oxide semiconductor active layer.
  • This step is similar to step S120 of the second embodiment, and the same part can be seen in FIG. 3(b) and its corresponding text description.
  • This step is similar to step S130 of the second embodiment. For details, refer to FIG. 3(c) and the corresponding description.
  • a metal oxide conductive layer is formed on the gate dielectric layer.
  • This step is similar to step S140 in the second embodiment, and can be seen in FIG. 3(d).
  • a metal oxide conductive layer covering the active layer 130 and the pre-prepared pixel electrode region is formed, and photolithography and etching are performed to form a source/drain electrode.
  • the embodiment is different from the second embodiment in that the conductive film 150 for preparing the source and drain electrodes is made of a transparent metal oxide conductive material, and the material used in the conductive film 150 is etched in an acid-base etching solution.
  • a layer of the conductive film 150 made of a transparent metal oxide covers the active layer 130 and also covers a region where the pixel electrode is pre-prepared, that is, a pixel electrode region.
  • the patterned transparent conductive layer forms a source/drain electrode and a pixel electrode.
  • the source and drain electrodes and the pixel electrode are formed by patterning the metal oxide conductive layer with an etching solution, and one of the source and drain electrodes is connected to the pixel electrode.
  • a positive photoresist is coated on the surface of the metal oxide conductive film 150, and after exposure and development, a portion corresponding to the channel region 131 is exposed, and then the transparent conductive film 150 is wet-etched.
  • the portion corresponding to the channel region 131 is etched away, and the source electrode 151, the drain electrode 152, and the pixel electrode 153 are formed.
  • the source 151 and the drain 152 are separated from each other, and are respectively located on both sides of the channel region 131, and the drain 152 is electrically connected to the pixel electrode 153.
  • the drain 152 is integrally formed with the pixel electrode 153, that is, the drain 152 is extended and covered to cover the reserved pixel electrode region. Since the conductive film for preparing the source and drain electrodes is a transparent metal oxide conductive material, The extension portion can be widened to function as the pixel electrode 153. Of course, in other embodiments of the present invention, the pixel electrode 153 separated from the drain electrode 152 may be formed by etching, and then the drain electrode 152 is electrically connected to the pixel electrode 153.
  • the transparent drain 152 is simultaneously used as the pixel electrode 153, and the ITO pixel electrode is not separately required, thereby reducing the use of the rare element In, thereby simplifying the production process and reducing the use of the rare material. Reduced production costs.
  • the metal oxide conductive layer 150 is selected to have a higher etching rate in the acid-base etching solution than the active layer 130. Preparation of metal oxides.
  • the step of wet etching selects the etching solution for the metal oxide semiconductor material of the active layer 130 and the metal oxide conductive film 150 to select a difference.
  • the difference in the etching rate of the metal oxide conductive film 150 and the active layer 130 in the weakly acidic or weakly alkaline solution is utilized to avoid damage to the channel region 131 during the etching.
  • a transparent passivation layer covering the source and drain electrodes, the active layer, and the pixel electrode is formed on the substrate, and a source contact hole is formed. This step is the same as in the second embodiment, and will not be described again.
  • a metal conductive wiring layer is formed on the surface of the passivation layer, and is lithographically and etched to form a data electrode and an interconnection.
  • the data electrode is electrically connected to the other of the source and drain electrodes through the interconnection.
  • the data electrode and the interconnection line are etched by the metal conductive wiring layer, and the interconnection line is in electrical contact with the source through the source contact hole.
  • a 300-300 nm thick metal conductive film is deposited as a wiring layer by magnetron sputtering or evaporation on the surface of the passivation layer 160, and photolithography is performed.
  • the data electrode 170 is formed by etching, and the data electrode 170 is in electrical contact with the source through the contact hole 171.
  • the conductive metal film of the wiring layer is prepared by using one of Mo, Cr, Al, Cu, or the like.
  • the common high-conductivity metal has low cost, but the etching is difficult, and it is inevitable to damage other components during the etching process, such as damage to the channel region. Therefore, it cannot be used as a wiring layer. For other rare metals with higher conductivity, the cost is much higher than common conductive metals such as copper.
  • the data electrode 170 is formed after the passivation layer 160 is formed, the presence of the passivation layer 160 can avoid components such as source and drain electrodes from being damaged during the etching process, and a better electrical effect.
  • the method of preparing the thin film transistor in the third embodiment may be used to continuously generate the gate dielectric layer 120, the active layer 130, and the metal oxide transparent conductive film 150, wherein the metal oxide transparent conductive film 150 As a transparent conductive layer, the source and drain electrodes are prepared by photolithography and etching of the transparent conductive layer using the gate electrode 110 as a mask.
  • the main steps have been described in the third embodiment, and will not be described again here.
  • the metal conductive wiring layer of the data electrode 170 is prepared as a light-shielding high-conductivity metal film, and the data electrode 170
  • the line width of the section through the thin film transistor 10 is widened so as to cover the passivation layer 160 of the thin film transistor region, and is electrically connected to the source 151 through the contact hole 171. Since the data electrode 170 is an opaque metal electrode, the data electrode 170 functions as both an interconnecting line and a matrix block after the section is widened, so that it is no longer necessary to separately prepare the shading matrix block.
  • the metal oxide thin film transistor, the display panel and the preparation method of the same according to the present invention adopt a transparent conductive layer to prepare a source/drain electrode, and the drain serves as a pixel electrode instead of the ITO pixel electrode, thereby reducing the use of the rare element In and reducing Production cost; using the etching selectivity ratio difference between the transparent conductive layer and the active layer to avoid damage to the channel region, improving product quality; using the gate electrode as a mask to form a source-drain electrode region pattern, which reduces the mask version
  • the use of the gate electrode and the channel region is precisely aligned, the parasitic effect is reduced, the uniformity of the device performance and the working speed are improved, the process process is simplified, the production cost is reduced, the wiring is performed outside the passivation layer, and the wiring is reduced.
  • the difficulty of the process enables the realization of common high-conductivity metal wiring such as copper or aluminum, further reducing the production cost.

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Abstract

La présente invention concerne un transistor à couches minces d'oxyde métallique et un panneau d'affichage, ainsi que des procédés de préparation de ceux-ci. Le procédé de préparation du transistor à couches minces comprend les étapes consistant à : préparer une électrode de grille (110) sur un substrat (100) ; produire à la suite une couche diélectrique de grille (120) et une couche active à semi-conducteurs d'oxyde métallique (130) sur le substrat (100) couvrant l'électrode de grille (110) ; produire une couche conductrice d'oxyde métallique (150) recouvrant la couche active (130), la couche conductrice d'oxyde métallique (150) utilisant un matériau ayant un taux de gravure plus élevé que le taux de gravure de la couche active (130) ; et utiliser une solution de gravure pour former un motif de couche conductrice d'oxyde métallique (150) afin de former une électrode source et une électrode de drain (151, 152). L'utilisation d'une électrode de drain (152) en remplacement d'une électrode de pixel IPO réduit l'utilisation de l'élément rare In ; l'utilisation de la différence de sélectivité de gravure de la couche conductrice transparente (150) et de la couche active (130) empêche la dégradation de la région de canal (131) ; et l'électrode de grille (110) étant utilisée en guise de masque pour former le motif de région d'électrode source et drain réduit l'utilisation de plaque de masque et permet également un alignement précis de l'électrode de grille (110) et de la région de canal (131), ce qui réduit l'effet parasite et simplifie le processus de fabrication.
PCT/CN2015/081485 2015-06-15 2015-06-15 Transistor à couches minces d'oxyde métallique et panneau d'affichage, ainsi que procédés de préparation de ceux-ci WO2016201609A1 (fr)

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CN113571586B (zh) * 2021-07-12 2023-09-19 沈阳工业大学 双掺杂源漏单晶体管同或门及制造方法
CN113571586A (zh) * 2021-07-12 2021-10-29 沈阳工业大学 双掺杂源漏单晶体管同或门及制造方法
DE112022003428T5 (de) 2021-09-03 2024-05-08 Nvidia Corporation 5g-nr-softwareschnittstelle
DE112023000334T5 (de) 2022-02-15 2024-08-22 Nvidia Corporation Dynamische objektdetektion mit lidar-daten für autonome maschinensysteme und anwendungen

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