WO2016201609A1 - 金属氧化物薄膜晶体管、显示面板及两者的制备方法 - Google Patents

金属氧化物薄膜晶体管、显示面板及两者的制备方法 Download PDF

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WO2016201609A1
WO2016201609A1 PCT/CN2015/081485 CN2015081485W WO2016201609A1 WO 2016201609 A1 WO2016201609 A1 WO 2016201609A1 CN 2015081485 W CN2015081485 W CN 2015081485W WO 2016201609 A1 WO2016201609 A1 WO 2016201609A1
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metal oxide
layer
source
electrode
active layer
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English (en)
French (fr)
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张盛东
邓伟
肖祥
贺鑫
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the present invention relates to the field of semiconductor device manufacturing, and in particular, to a thin film transistor, a display panel, and a method of fabricating the same.
  • TFT LCD Thin Film Crystal Liquid Crystal Display
  • amorphous oxide thin film transistors typified by a-IGZO (amorphous indium gallium zinc oxide) have been widely concerned.
  • the mobility of the metal oxide semiconductor TFT is generally 10 cm 2 /Vs, which is ten times that of the amorphous silicon TFT (0.5 to 1 cm 2 /Vs), and therefore, the on-state current of the metal oxide semiconductor TFT is large.
  • the driving ability is strong, which can meet the requirements of modern flat panel display for high frame rate, high resolution and narrow border.
  • IGZO thin films are easily formed into an amorphous state at normal temperature. Since amorphous structures do not have grain boundaries, they can maintain good uniformity over a large area and are suitable for large-size display applications.
  • a back channel etch (BCE) structure BCE
  • ESL etch stop
  • the metal oxide semiconductor film Since there is no etch barrier layer on the metal oxide semiconductor in the BCE structure, the metal oxide semiconductor film is generally sensitive to the acid and alkali environment, and is easily corroded during the source-drain patterning process, so the BCE structure is relatively Hard to achieve.
  • the realization of the BCE type metal oxide semiconductor TFT is of great significance in reducing production cost and improving display performance.
  • the technical problem to be solved by the present invention is that a thin film transistor for preparing a BCE structure is difficult, complicated, and costly for the prior art, and a thin film transistor and a method for fabricating the same are provided.
  • the method of the present invention provides a source-drain electrode using transparent conductive
  • the material can replace the ITO as a pixel electrode while forming the source/drain pattern, which can simplify the fabrication process of the device, save manufacturing cost, and easily realize metal wiring technology with high conductance and difficult etching, such as Cu, and can further improve display performance. And reduce costs.
  • a metal oxide thin film transistor including a gate electrode is provided;
  • the source and the drain are separated from each other, and the source and the drain are electrically contacted with the active layer, respectively, and the source and drain electrodes are metal oxide conductive materials.
  • the transistor wherein the source and drain electrodes are metal oxide transparent conductive materials.
  • a display panel comprising:
  • the thin film transistor being arranged corresponding to a pixel, the thin film transistor including a gate electrode, an active layer, and mutually separated source and drain, the active layer being isolated from the gate electrode by the gate dielectric layer,
  • the source layer is made of a metal oxide semiconductor material, the source and the drain are respectively electrically contacted with the active layer, and the source and drain electrodes are metal oxide transparent conductive materials;
  • a pixel electrode disposed corresponding to the pixel, wherein one of the source and drain electrodes in the thin film transistor is integrally formed with the pixel electrode;
  • a data electrode electrically connected to the other of the source and drain electrodes through an interconnection.
  • the display panel further includes a passivation layer covering the gate dielectric layer, the active layer, the source/drain electrode region and the pixel electrode region, the passivation layer is a transparent passivation layer, and the data electrode is a metal An electrode that widens the width of the segment line passing through the thin film transistor so as to cover the passivation layer of the thin film transistor region.
  • a method for fabricating a metal oxide thin film transistor comprising:
  • the transparent conductive layer is patterned using an etching solution to form a source/drain electrode.
  • the method for preparing a thin film transistor wherein the metal oxide conductive layer is a metal oxide transparent conductive material.
  • the active layer is photolithographically and etched to form an active region before the metal oxide conductive layer is formed.
  • the method for fabricating a thin film transistor wherein the gate dielectric layer, the active layer, and the metal oxide conductive layer are continuously grown, and after forming the source/drain electrode region, photolithography and etching of the active layer are formed. Active area.
  • a method for preparing a display panel including:
  • the metal oxide transparent conductive layer uses a material having a corrosion rate higher than that of the active layer;
  • a metal conductive wiring layer is formed on the surface of the passivation layer, and is formed by photolithography and etching to form a data electrode and an interconnection.
  • the data electrode is electrically connected to the other of the source and drain electrodes through the interconnection.
  • the method for fabricating a display panel is characterized in that the data electrode is widened in a width of a segment line passing through the thin film transistor so as to cover the passivation layer of the thin film transistor region.
  • the invention discloses a metal oxide thin film transistor, a display panel and a preparation method thereof, wherein a source-drain electrode is prepared by using a metal oxide transparent conductive layer, and an ITO pixel electrode is replaced by a drain to reduce the use of the rare element In. Reducing the production cost; utilizing the difference in etching selectivity between the metal oxide transparent conductive layer and the active layer to avoid damage to the channel region, improving product quality; using the gate electrode as a mask to form a source-drain electrode region pattern, which reduces The use of the mask enables precise alignment of the gate electrode and the channel region, reduces parasitic effects, improves device performance uniformity and operating speed, simplifies the process, reduces production costs, and performs passivation outside the passivation layer. Wiring, reducing the difficulty of the wiring process, using common high-conductivity metal wiring such as copper or aluminum, and wiring outside the passivation layer, while shielding the TFT tube, without the need for separate matrix blocks, further reducing the production cost.
  • FIG. 1 is a cross-sectional structural view of a preferred embodiment of a thin film transistor of the present invention
  • FIG. 2 is a flow chart showing a preferred embodiment of a method for fabricating a metal oxide thin film transistor of the present invention
  • (a) is a schematic view of a process step for forming a gate electrode
  • FIG. 4 is a flow chart showing a second embodiment of a method for fabricating a metal oxide thin film transistor of the present invention.
  • (b) is a schematic diagram of a process step of photolithographically coating a metal oxide conductive layer with a gate electrode as a mask;
  • Figure 6 (a) is a perspective structural view of a display panel of the present invention.
  • Figure 6 (b) is a cross-sectional view of the display panel of the present invention.
  • Figure 6 (c) is a cross-sectional view showing another embodiment of the display panel of the present invention.
  • FIG. 7 is a flow chart of an embodiment of a method of fabricating a display panel of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • a thin film transistor includes a gate electrode 110 formed on a substrate 100, a gate dielectric layer 120 formed on the substrate 100 and covering the gate electrode 110, and a gate dielectric layer 120 formed on the gate electrode 110.
  • a gate electrode 110 formed on a substrate 100
  • a gate dielectric layer 120 formed on the substrate 100 and covering the gate electrode 110
  • a gate dielectric layer 120 formed on the gate electrode 110.
  • an active layer 130 separated from the gate electrode 110 by the gate dielectric layer 120, and a source/drain electrode over the active layer 130.
  • the portion of the active layer 130 that is aligned with the gate electrode 110 forms a channel region 131.
  • the source electrode 151 and the drain electrode 152 are separated from each other on both sides of the channel region 131 and are in electrical contact with the active layer 130.
  • the source/drain electrodes are made of a metal oxide transparent material, and the metal oxide used for the source and drain electrodes has a higher etching selectivity than the active layer 130, so that the channel region can be avoided when etching the source drain electrode. 131 was damaged.
  • the surface of the gate dielectric layer 120 also functions as a passivation layer 160.
  • the passivation layer 160 covers the gate dielectric layer 120 and the active layer 130.
  • the surface of the passivation layer 160 is provided with a contact hole for connecting the data electrodes. 171.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the present invention also provides a method for fabricating the above metal oxide thin film transistor, as shown in FIG. 2, comprising the following steps:
  • a high-conductivity film of 100 to 300 nm thick is formed on the substrate 100 by thermal evaporation, electron beam evaporation or magnetron sputtering, and then processed to form a gate.
  • the electrode 110 can be formed into a gate electrode 110 by photolithography and etching.
  • the gate electrode 110 is a metal conductive material such as chromium, molybdenum, titanium or aluminum, and a high-conductivity metal oxide such as ITO, AZO, BZO, ZnO, etc. may be used, by magnetron sputtering or reactive sputtering.
  • a highly conductive film is formed, and the gate electrode 110 is formed after being processed.
  • the substrate 100 is a high temperature resistant material, such as a glass substrate, or a non-high temperature resistant material such as a transparent plastic substrate.
  • the gate dielectric layer and the active layer are continuously formed by covering the gate electrode on the substrate.
  • a 100-400 nm thick insulating film is formed on the substrate 100, and the insulating film is made of an insulating material such as silicon nitride or silicon oxide and covers the entire substrate 100 and the gate electrode 110.
  • the method for generating the theater film may be a plasma enhanced chemical vapor deposition method, a magnetron sputtering method, a reverse sputtering method, or the like.
  • a metal oxide semiconductor thin film is formed on the gate dielectric layer 120 by magnetron sputtering or reactive sputtering to form an active layer 130 having a thickness of 20 to 200 nm.
  • the active layer 130 is made of an amorphous or polycrystalline metal oxide semiconductor material such as a zinc oxide-based or indium oxide-based film.
  • amorphous or polycrystalline metal oxide semiconductor material such as a zinc oxide-based or indium oxide-based film.
  • the target used is composed of a mixed material of gallium oxide, indium oxide, and zinc oxide.
  • the target used is an indium oxide ceramic target or an indium metal target having a purity equal to or better than 99.99%.
  • the active layer 130 is formed by a magnetron sputtering method or a reactive sputtering method, and the sputtering gas pressure is between 0.1 and 2.5 Pa, and the gas is a mixed gas of argon gas and oxygen gas.
  • a positive photoresist is coated on the surface of the active layer 130, and an active region pattern is formed by photolithography and etching, wherein the active region is aligned with the gate electrode 110.
  • Channel region 131 As shown in FIG. 3(c), a positive photoresist is coated on the surface of the active layer 130, and an active region pattern is formed by photolithography and etching, wherein the active region is aligned with the gate electrode 110. Channel region 131.
  • a metal oxide conductive layer covering the active layer is formed on the gate dielectric layer and processed to form a source-drain electrode.
  • a metal oxide conductive film 150 having a thickness of 50 to 400 nm is formed on the gate dielectric layer 120 as a metal oxide conductive layer, and the metal oxide conductive film 150 is non- A crystalline or polycrystalline transparent metal oxide conductive material such as AZO or BZO.
  • a positive photoresist is coated on the surface of the metal oxide conductive film 150, and after exposure and development, a portion corresponding to the channel region 131 is exposed, and then the conductive film 150 is wet-etched to etch away the channel.
  • a portion corresponding to the region 131 forms a source/drain electrode pattern, and forms a source 151 and a drain 152 which are separated from each other.
  • the source 151 and the drain 152 are separated from each other on both sides of the channel region 131.
  • the conductive film 150 can be formed by continuous deposition using a magnetron sputtering method or a reactive sputtering method, wherein the sputtering gas pressure is between 0.1 and 2.5 Pa, and the gas is a mixed gas of argon gas and oxygen gas. Pure argon.
  • the conductive film 150 is selected from a metal oxide having a higher etching rate in the acid-base etching solution than the active layer 130.
  • the step of wet etching selects an etching solution having a difference in metal oxide selectivity ratio between the metal oxide semiconductor material of the active layer 130 and the conductive film 150.
  • the difference in the etching rate of the metal oxide conductive film 150 and the active layer 130 in the weakly acidic or weakly alkaline solution is utilized to avoid the formation of the channel region 131 during the etching process. Into the damage.
  • a passivation layer 160 covering the gate dielectric layer 120, the source/drain electrodes, and the channel region 131 is formed.
  • a 100-300 nm thick silicon nitride layer or a silicon oxide or aluminum oxide material is deposited as a passivation layer 160 by plasma enhanced chemical vapor deposition (PECVD) or magnetron sputtering.
  • the passivation layer 160 can also be prepared by using other transparent insulating materials, which can protect the internal components and can pass the light without damage.
  • This embodiment is an improvement of the preparation method of the metal oxide thin film transistor based on the second embodiment.
  • the difference between this embodiment and the previous embodiment is that, in the embodiment, the gate electrode 110 is used as a mask, and a negative photoresist is coated on the surface of the transparent conductive film 150, and is exposed upward from the bottom of the substrate 100, and is photolithographically and engraved. The etch forms a source/drain electrode region 151 and a pixel electrode region 152.
  • the method for preparing a thin film transistor in this embodiment includes the steps of:
  • the difference from the first embodiment is that the material used for the gate electrode 110 in this embodiment selects an opaque metal conductive material. High conductance opaque metal oxide materials can be used.
  • the substrate 100 is a high temperature resistant transparent material, such as a glass substrate, or a non-high temperature transparent material such as a transparent plastic substrate.
  • a gate dielectric layer, an active layer, and a metal oxide conductive layer are continuously formed on the substrate by covering the gate electrode.
  • an insulating film, a metal oxide semiconductor film, and a metal oxide conductive film 150 are sequentially deposited on the substrate over the gate electrode, respectively as the gate dielectric layer 120, the active layer 130, and the pre-layer.
  • a metal oxide conductive layer of the source and drain electrodes is prepared.
  • the gate dielectric layer 120 is made of a transparent insulating material
  • the active layer 130 is made of an amorphous or polycrystalline metal oxide semiconductor transparent material
  • the metal oxide conductive layer is made of a transparent metal oxide conductive material.
  • the metal oxide conductive layer selects a material having an etching ratio higher than that of the active layer 130, that is, the etching rate of the conductive film 150 pre-prepared from the source/drain electrode in the acid-base etching solution is higher than that of the active layer 130 semiconductors.
  • the deposition method and thickness of each layer in this embodiment are the same as those of the previous embodiment, and are not described herein again.
  • S131 exposing upward from the bottom of the substrate, and etching the metal oxide transparent conductive layer to form a source drain pattern.
  • a negative photoresist 154 is coated on the surface of the transparent conductive film 150, and is exposed upward from the bottom of the substrate 100, and the negative photoresist 154 opposite to the gate electrode 110 is not received by light. Dissolved, a portion of the conductive film 150 corresponding to the gate electrode 110 is exposed, and the negative photoresist 154 located on both sides of the portion is cured by exposure. Then exposed bare conductive thin The film 150 is etched to form a source 151 and a drain 152 which are separated from each other, and a source-drain electrode pattern as shown in Fig. 5(c) appears. The remaining negative photoresist 154 is then removed. A preliminary pattern of source and drain electrodes formed by this step.
  • the conductive film 150 and the active layer 130 are photolithographically etched and etched using a positive photoresist to form a source/drain electrode and an active region pattern as shown in FIG. 5(d).
  • the conductive film 150 and the active layer 130 are preferably etched by etching, and an etching solution capable of simultaneously etching the metal oxide conductive film 150 and the metal oxide semiconductor active layer 130 is selected.
  • the conductive film 150 is etched a second time to form a complete source/drain electrode pattern.
  • the gate electrode 110 is used as a mask, and the source and drain electrodes are prepared by negative photoresist lithography and etching the metal oxide conductive layer, compared with the previous implementation.
  • the mask required for the photolithographic metal oxide conductive layer is omitted, further reducing the production cost.
  • the gate electrode 110 is used as a mask to be exposed upward from the bottom of the substrate 100, which can achieve self-alignment of the channel region 131 and the gate electrode, reduce parasitic effects, and improve device performance uniformity and working speed. And reduce the difficulty of production and shorten the process.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • FIG. 6 (a) is a schematic structural diagram of a single pixel unit in the display panel according to the embodiment.
  • the display panel provided in this embodiment includes a plurality of pixel units, and data electrodes 172 between the pixel units, and each of the pixels is arranged with a metal oxide thin film transistor 10 and a pixel electrode 153, and the source and the drain in the thin film transistor 10
  • One pole of the pole is integrally formed with the pixel electrode 153; the data electrode 172 is electrically connected to the other of the source and drain electrodes through an interconnection.
  • the thin film transistor 10 includes a gate electrode 110 on the substrate 100, an active layer 130, and a source 151 and a drain 152 which are separated from each other, and the active layer 130 passes through the gate dielectric layer.
  • the 120 is isolated from the gate electrode 110, and the source 151 and the drain 152 are in electrical contact with the active layer 130, respectively.
  • the active layer 130 is made of a metal oxide semiconductor material, and the source and drain electrodes are made of a metal oxide transparent conductive material.
  • the pixel electrode 153 and the drain electrode 152 are integrally formed.
  • the active layer 130 is disposed as a channel region 131 corresponding to the gate electrode 110, and the source electrode 151 is separated from the drain electrode 152 at both sides of the channel region 131.
  • the drain 152 extends away from the end of the source 151 and widens to serve as the pixel electrode 153. Therefore, in the present embodiment, the drain 152 and the pixel electrode 153 have a unitary structure.
  • the ITO pixel electrode is replaced by the drain 152, so that the ITO pixel electrode is not separately prepared, the use of the rare element In is reduced, and the process of separately preparing the pixel electrode is omitted, thereby reducing the difficulty of production and processing, and greatly Reduce production costs.
  • the gate electrode of the thin film transistor 10 is electrically connected to the scan line 111 , the source is electrically connected to the data electrode 170 through the contact hole 171 , and the drain is connected to the pixel electrode 153 .
  • the voltage applied to the gate is controlled by the scan line 111 to achieve conduction and turn-off between the source and the drain.
  • the IC signal input of the source is controlled by the data electrode 170, thereby controlling the luminance of the pixel electrode.
  • the conductive metal film of the metal wiring layer of the embodiment is prepared by using one of Mo, Cr, Al, Cu, or the like.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • the data electrode 170 is made of an opaque metal material, and the surface of the thin film transistor 10 is covered with a transparent passivation layer, and the passivation layer is made of a transparent insulating material. Preparation, such as a silicon nitride layer or silicon dioxide, and covering the gate dielectric layer, the active layer, the source and drain electrode regions, and the pixel electrode region.
  • the data electrode 170 is widened by the width of the thin film transistor 10 and covers the passivation layer corresponding to the entire thin film transistor.
  • the data electrode 170 is an opaque metal electrode, the data electrode 170 functions as a shadow block of the matrix block in the prior art in this section, and it is no longer necessary to separately prepare the light shielding matrix block.
  • the present embodiment employs copper as a wiring layer.
  • This embodiment provides a method for preparing the above display panel.
  • the process of the method is as shown in FIG. 7 and includes the following steps:
  • This step is similar to step S110 of the second embodiment. For details, refer to FIG. 3(a) and corresponding description.
  • step S220 sequentially covering the gate electrode on the substrate to sequentially generate a gate dielectric layer and a metal oxide semiconductor active layer.
  • This step is similar to step S120 of the second embodiment, and the same part can be seen in FIG. 3(b) and its corresponding text description.
  • This step is similar to step S130 of the second embodiment. For details, refer to FIG. 3(c) and the corresponding description.
  • a metal oxide conductive layer is formed on the gate dielectric layer.
  • This step is similar to step S140 in the second embodiment, and can be seen in FIG. 3(d).
  • a metal oxide conductive layer covering the active layer 130 and the pre-prepared pixel electrode region is formed, and photolithography and etching are performed to form a source/drain electrode.
  • the embodiment is different from the second embodiment in that the conductive film 150 for preparing the source and drain electrodes is made of a transparent metal oxide conductive material, and the material used in the conductive film 150 is etched in an acid-base etching solution.
  • a layer of the conductive film 150 made of a transparent metal oxide covers the active layer 130 and also covers a region where the pixel electrode is pre-prepared, that is, a pixel electrode region.
  • the patterned transparent conductive layer forms a source/drain electrode and a pixel electrode.
  • the source and drain electrodes and the pixel electrode are formed by patterning the metal oxide conductive layer with an etching solution, and one of the source and drain electrodes is connected to the pixel electrode.
  • a positive photoresist is coated on the surface of the metal oxide conductive film 150, and after exposure and development, a portion corresponding to the channel region 131 is exposed, and then the transparent conductive film 150 is wet-etched.
  • the portion corresponding to the channel region 131 is etched away, and the source electrode 151, the drain electrode 152, and the pixel electrode 153 are formed.
  • the source 151 and the drain 152 are separated from each other, and are respectively located on both sides of the channel region 131, and the drain 152 is electrically connected to the pixel electrode 153.
  • the drain 152 is integrally formed with the pixel electrode 153, that is, the drain 152 is extended and covered to cover the reserved pixel electrode region. Since the conductive film for preparing the source and drain electrodes is a transparent metal oxide conductive material, The extension portion can be widened to function as the pixel electrode 153. Of course, in other embodiments of the present invention, the pixel electrode 153 separated from the drain electrode 152 may be formed by etching, and then the drain electrode 152 is electrically connected to the pixel electrode 153.
  • the transparent drain 152 is simultaneously used as the pixel electrode 153, and the ITO pixel electrode is not separately required, thereby reducing the use of the rare element In, thereby simplifying the production process and reducing the use of the rare material. Reduced production costs.
  • the metal oxide conductive layer 150 is selected to have a higher etching rate in the acid-base etching solution than the active layer 130. Preparation of metal oxides.
  • the step of wet etching selects the etching solution for the metal oxide semiconductor material of the active layer 130 and the metal oxide conductive film 150 to select a difference.
  • the difference in the etching rate of the metal oxide conductive film 150 and the active layer 130 in the weakly acidic or weakly alkaline solution is utilized to avoid damage to the channel region 131 during the etching.
  • a transparent passivation layer covering the source and drain electrodes, the active layer, and the pixel electrode is formed on the substrate, and a source contact hole is formed. This step is the same as in the second embodiment, and will not be described again.
  • a metal conductive wiring layer is formed on the surface of the passivation layer, and is lithographically and etched to form a data electrode and an interconnection.
  • the data electrode is electrically connected to the other of the source and drain electrodes through the interconnection.
  • the data electrode and the interconnection line are etched by the metal conductive wiring layer, and the interconnection line is in electrical contact with the source through the source contact hole.
  • a 300-300 nm thick metal conductive film is deposited as a wiring layer by magnetron sputtering or evaporation on the surface of the passivation layer 160, and photolithography is performed.
  • the data electrode 170 is formed by etching, and the data electrode 170 is in electrical contact with the source through the contact hole 171.
  • the conductive metal film of the wiring layer is prepared by using one of Mo, Cr, Al, Cu, or the like.
  • the common high-conductivity metal has low cost, but the etching is difficult, and it is inevitable to damage other components during the etching process, such as damage to the channel region. Therefore, it cannot be used as a wiring layer. For other rare metals with higher conductivity, the cost is much higher than common conductive metals such as copper.
  • the data electrode 170 is formed after the passivation layer 160 is formed, the presence of the passivation layer 160 can avoid components such as source and drain electrodes from being damaged during the etching process, and a better electrical effect.
  • the method of preparing the thin film transistor in the third embodiment may be used to continuously generate the gate dielectric layer 120, the active layer 130, and the metal oxide transparent conductive film 150, wherein the metal oxide transparent conductive film 150 As a transparent conductive layer, the source and drain electrodes are prepared by photolithography and etching of the transparent conductive layer using the gate electrode 110 as a mask.
  • the main steps have been described in the third embodiment, and will not be described again here.
  • the metal conductive wiring layer of the data electrode 170 is prepared as a light-shielding high-conductivity metal film, and the data electrode 170
  • the line width of the section through the thin film transistor 10 is widened so as to cover the passivation layer 160 of the thin film transistor region, and is electrically connected to the source 151 through the contact hole 171. Since the data electrode 170 is an opaque metal electrode, the data electrode 170 functions as both an interconnecting line and a matrix block after the section is widened, so that it is no longer necessary to separately prepare the shading matrix block.
  • the metal oxide thin film transistor, the display panel and the preparation method of the same according to the present invention adopt a transparent conductive layer to prepare a source/drain electrode, and the drain serves as a pixel electrode instead of the ITO pixel electrode, thereby reducing the use of the rare element In and reducing Production cost; using the etching selectivity ratio difference between the transparent conductive layer and the active layer to avoid damage to the channel region, improving product quality; using the gate electrode as a mask to form a source-drain electrode region pattern, which reduces the mask version
  • the use of the gate electrode and the channel region is precisely aligned, the parasitic effect is reduced, the uniformity of the device performance and the working speed are improved, the process process is simplified, the production cost is reduced, the wiring is performed outside the passivation layer, and the wiring is reduced.
  • the difficulty of the process enables the realization of common high-conductivity metal wiring such as copper or aluminum, further reducing the production cost.

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Abstract

一种金属氧化物薄膜晶体管、显示面板及两者的制备方法，其中薄膜晶体管的制备方法包括步骤：在衬底(100)上制备栅电极(110)；在所述衬底(100)上覆盖所述栅电极(110)依次生成栅介质层(120)及金属氧化物半导体有源层(130)；生成覆盖所述有源层(130)的金属氧化物导电层(150)，所述金属氧化物导电层(150)采用腐蚀速率高于所述有源层(130)的腐蚀速率的材料；采用腐蚀液图形化所述金属氧化物导电层(150)形成源漏电极(151,152)。采用漏极(152)替代ITO像素电极，减少稀有元素In的使用；利用透明导电层(150)与有源层(130)之间的刻蚀选择比差异避免损伤沟道区(131)；以栅电极(110)为掩膜形成源漏电极区图形，既减少了掩膜版的使用，又能实现栅电极(110)与沟道区(131)精确对准，减小了寄生效应，简化了流程工艺。

Description

金属氧化物薄膜晶体管、显示面板及两者的制备方法 技术领域
本发明涉及半导体器件制造领域，尤其涉及一种薄膜晶体管、显示面板及两者的制备方法。
背景技术
TFT LCD(薄膜晶体液晶显示屏)是现代平板显示领域的主流技术。随着高帧频、高分辨和大尺寸显示的发展，以a-IGZO(非晶铟镓锌氧化物)为代表的非晶氧化物薄膜晶体管得到广泛关注。金属氧化物半导体TFT(氧化物薄膜晶体管)的迁移率一般在10cm2/Vs，是非晶硅TFT(0.5～1cm2/Vs)的十几倍，因此，金属氧化物半导体TFT的开态电流大、驱动能力强，能够满足现代平板显示对高帧频、高分辨、窄边框的要求。不同于多晶硅，IGZO薄膜在常温下很容易形成非晶态，由于非晶结构不存在晶界，因此能够在较大面积内保持良好的均匀性，适合大尺寸显示的应用。
在大规模生产中，金属氧化物半导体TFT的结构一般有两种：背沟道刻蚀(BCE)结构和刻蚀阻挡(ESL)结构。由于刻蚀阻挡层的存在，ESL结构在工艺中很容易实现，得到的器件在应力作用下的稳定性相对较高，但ESL结构需要额外的掩模板，因此生产成本较高；由于套刻容差和刻蚀容差的存在，ESL结构一般scaling down比较困难、寄生效应较大，这使得金属氧化物半导体TFT的一些优势在应用(如高分辨显示)中体现的并不明显。由于BCE结构中金属氧化物半导体上没有刻蚀阻挡层，而金属氧化物半导体薄膜一般都对酸、碱环境比较敏感，在源漏图形化过程中极易被腐蚀掉，因此BCE结构又是相对较难实现的。
因此实现BCE型的金属氧化物半导体TFT在降低生产成本和提高显示性能上具有重要的意义。
发明内容
本发明要解决的技术问题在于，针对现有技术在制备BCE结构的薄膜晶体管难度大、工艺复杂且成本高，提供一种薄膜晶体管及其制备方法；本发明提供的方法源漏电极采用透明导电材料，在形成源漏区图形的同时还可以替代ITO作为像素电极，可以简化器件的制作工艺、节省制造成本，容易实现Cu等具有高电导又不易刻蚀的金属布线技术，能够进一步提高显示性能和降低成本。
本发明解决技术问题所采用的技术方案如下：根据本发明的第一方面，提供一种金属氧化物薄膜晶体管，包括栅电极；
通过栅介质层与栅电极隔离的有源层，有源层采用金属氧化物半导 体材料，所述有源层与栅电极对准的部分形成沟道区；
相互分离的源极和漏极，所述源极和漏极分别与有源层电性接触，源漏电极为金属氧化物导电材料。
所述的晶体管，其中，源漏电极为金属氧化物透明导电材料。
根据本发明第二方面，提供一种显示面板，包括：
金属氧化物薄膜晶体管，所述薄膜晶体管与像素对应排布，所述薄膜晶体管包括栅电极、有源层和相互分离的源极和漏极，有源层通过栅介质层与栅电极隔离，有源层采用金属氧化物半导体材料，所述源极和漏极分别与有源层电性接触，源漏电极为金属氧化物透明导电材料；
像素电极，与像素对应排布，所述薄膜晶体管中的源漏电极中的一极与像素电极一体成型；
数据电极，所述数据电极通过互连线与源漏电极中的另一极电性连接。
所述的显示面板，还包括一覆盖所述栅介质层、有源层、源漏电极区和像素电极区的钝化层，所述钝化层为透明钝化层，所述数据电极为金属电极，所述数据电极在经过薄膜晶体管的路段线路宽度拓宽以使其覆盖在薄膜晶体管区域的钝化层上。
根据本发明的第三方面，提供一种金属氧化物薄膜晶体管的制备方法，其特征在于，包括：
在衬底上制备栅电极；
在所述衬底上覆盖所述栅电极依次生成栅介质层及金属氧化物半导体有源层；
生成覆盖所述有源层的金属氧化物导电层，所述金属氧化物导电层采用腐蚀速率高于所述有源层的腐蚀速率的材料；
采用腐蚀液图形化所述透明导电层形成源漏电极。
所述的薄膜晶体管的制备方法，其中金属氧化物导电层为金属氧化物透明导电材料。
所述的薄膜晶体管的制备方法，其中，在生成金属氧化物导电层之前，光刻及刻蚀所述有源层形成有源区。
所述的薄膜晶体管的制备方法，其中，所述栅介质层、有源层、金属氧化物导电层连续生长，在形成所述源漏电极区后，光刻及刻蚀所述有源层形成有源区。
根据本发明第四方面，提供一种显示面板的制备方法，包括：
在衬底上制备栅电极；
在所述衬底上覆盖所述栅电极依次生成栅介质层及金属氧化物半导体有源层；
生成覆盖所述有源层和像素电极区的金属氧化物透明导电层，所述 金属氧化物透明导电层采用腐蚀速率高于所述有源层的腐蚀速率的材料；
采用腐蚀液图形化所述透明导电层形成源漏电极和像素电极，且源漏电极中的一极与像素电极相连；
在所述衬底上生成覆盖所述源漏电极、有源层和像素电极的透明钝化层，并形成源极接触孔；
在所述钝化层表面生成一金属导电布线层，并光刻及刻蚀形成数据电极和互连线，数据电极通过互连线与源漏电极中的另一极电性连接。
所述的显示面板的制备方法，其特征在于，所述数据电极在经过薄膜晶体管的路段线路宽度拓宽以使其覆盖在薄膜晶体管区域的钝化层上。
本实发明提出的一种金属氧化物薄膜晶体管、显示面板及二者的制备方法，采用金属氧化物透明导电层制备源漏电极，并由漏极替代ITO像素电极，减少稀有元素In的使用，降低生产成本；利用金属氧化物透明导电层与有源层之间的刻蚀选择比差异避免损伤沟道区，提高了产品质量；采用栅电极为掩膜形成源漏电极区图形，既减少了掩膜版的使用，又实现栅电极与沟道区精确对准，减小了寄生效应，提高了器件性能的均匀性和工作速度，简化了流程工艺，降低了生产成本，钝化层外进行布线，降低布线工艺难度，采用铜或铝等常见高电导的金属布线，且在钝化层外布线，同时遮蔽TFT管，无需另制矩阵块，进一步降低了生产成本。
附图说明
图1是本发明薄膜晶体管较佳实施例的剖面结构图；
图2是本发明金属氧化物薄膜晶体管制备方法较佳实施例的流程图；
图3(a)～(e)依次示出了本发明金属氧化物薄膜晶体管制备方法较佳实施例的主要工艺步骤，其中：
(a)为形成栅电极的工艺步骤示意图；
(b)为形成栅介质层及有源层的工艺步骤示意图；
(c)为形成有源区图案的工艺步骤示意图；
(d)为形成源漏电极区的工艺步骤示意图；
(e)为形成钝化层的工艺步骤示意图；
图4是本发明金属氧化物薄膜晶体管制备方法第二实施例的流程图；
图5(a)～(d)示出了本发明薄膜晶体管制备方法第二实施例的主要工艺步骤，其中，
(a)为连续淀积栅介质层、有源层、金属氧化物导电层及的工艺步 骤示意图；
(b)为以栅电极为掩膜光刻金属氧化物导电层的工艺步骤示意图；
(c)为制备源漏电极的工艺步骤示意图；
(d)为形成源漏电极区及有源区图形；
图6(a)是本发明一种显示面板的立体结构图；
图6(b)是本发明显示面板的剖面图；
图6(c)是本发明显示面板另一实施例的剖面图；
图7是本发明显示面板制作方法实施例的流程图。
具体实施方式
为使本发明的目的、技术方案及优点更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一：
请参见图1，本实施例给出的薄膜晶体管，包括生成于衬底100上的栅电极110；生成于衬底100上并覆盖所述栅电极110的栅介质层120；生成于所述栅介质层120上、通过栅介质层120与栅电极110相互隔离的有源层130，在所述有源层130之上的源漏电极。其中，有源层130与栅电极110相对准的部分形成沟道区131，源极151与漏极152相互分离的位于沟道区131两侧，并与有源层130电性接触。
进一步地，源漏电极为金属氧化物透明材料制备，且源漏电极所用的金属氧化物相对于有源层130具有较高的刻蚀选择比，这样在刻蚀源漏电极时可以避免沟道区131受到损伤。
进一步，栅介质层120表面还起保护作用的钝化层160，钝化层160覆盖栅介质层120、有源层130，钝化层160表面对应源极处设有用于连接数据电极的接触孔171。
实施例二：
基于上述实施例的描述，本发明还给出了上述金属氧化物薄膜晶体管的制备方法，如图2所示，包括以下步骤：
S110、在衬底上制备栅电极。
首先，如图3(a)所示，采用热蒸发、电子束蒸发或磁控溅射法衬底100上生成一层100～300纳米厚的高导电薄膜，然后将其进行相应的处理形成栅电极110，如可将其通过光刻和刻蚀形成栅电极110。本实施例中栅电极110为铬、钼、钛或铝等金属导电材料，也可采用高电导的金属氧化物，如ITO、AZO、BZO、ZnO等，通过磁控溅射或反应溅射法形成高导电薄膜，在经过处理形成栅电极110。衬底100为耐高温材质，如玻璃衬底，也可为非耐高温材质，如透明的塑料衬底。
S120、在衬底上覆盖栅电极连续生成栅介质层及有源层。
如图3(b)所示，在衬底100上生成一层100～400纳米厚的绝缘薄膜，该绝缘薄采用氮化硅、氧化硅等绝缘材并覆盖整个衬底100及栅电极110。其中，生成该剧院薄膜的方法可以采用等离子增强化学汽相淀积法或磁控溅射、反溅射法等。
接下来，采用磁控溅射法或反应溅射法淀积在栅介质层120上生成一层金属氧化物半导体薄膜作为有源层130，其厚度可为20～200纳米。
进一步地，有源层130采用非晶或多晶的金属氧化物半导体材料，如氧化锌基或氧化铟基薄膜。当选用氧化铟镓锌(IGZO)作为材料时，使用的靶由氧化镓、氧化铟和氧化锌的混合材料构成。当为选用氧化铟作为材料时，所用的靶材为纯度等于或优于99.99％的氧化铟陶瓷靶或铟金属靶。
较佳的，形成有源层130采用磁控溅射法或反应溅射法，溅射气压在0.1～2.5Pa之间，气体为氩气和氧气的混合气体。
S130、光刻及刻蚀有源层形成有源区。
如图3(c)所示，在有源层130表面涂布正性光刻胶，通过光刻及刻蚀形成有形成有源区图形，其中，有源区与栅电极110相对准处为沟道区131。
S140、制备源漏电极。
在栅介质层上生成覆盖所述有源层的金属氧化物导电层，并经过处理形成源漏电极。
具体地，如图3(d)所示，在栅介质层120上生成一层厚度为50～400纳米的金属氧化物导电薄膜150作为金属氧化物导电层，该金属氧化物导电薄膜150采用非晶或多晶的透明金属氧化物导电材料，如AZO或BZO等制备而成。然后，在金属氧化物导电薄膜150表面涂布正性光刻胶，经曝光显影后，露出与沟道区131相对应的部分，然后通过湿法刻蚀该导电薄膜150，腐蚀掉与沟道区131对应的部分，形成源漏电极图案，形成相互分离的源极151及漏极152。其中，源极151与漏极152相互分离的位于沟道区131两侧。
较佳的，可采用磁控溅射法或反应溅射法连续淀积生成该导电薄膜150，其中溅射气压在0.1～2.5Pa之间，气体为氩气和氧气的混合气体，也可以为纯氩气。
进一步地，为了在刻蚀导电薄膜150形成源漏电极过程中，避免腐蚀液损伤沟道区131，导电薄膜150选用在酸碱腐蚀液中腐蚀速率高于有源层130的金属氧化物制备。同时，该步骤湿法刻蚀选用对有源层130的金属氧化物半导体材料和导电薄膜150的金属氧化物选择比存在差异的腐蚀液。这样，利用金属氧化物导电薄膜150和有源层130在弱酸性或弱碱性溶液中的腐蚀速率的差异，来避免刻蚀过程中对沟道区131造 成损伤。
S150、制备表面钝化层。
如图3(e)所示，生成覆盖栅介质层120、源漏电极、沟道区131的钝化层160。具体地，用等离子增强化学汽相淀积(PECVD)或磁控溅射方法淀积一层100～300纳米厚的氮化硅层或二氧化硅或氧化铝材料作为钝化层160。
较佳的是，该钝化层160也可采用其他透明绝缘材质制备，其既能起到保护内部元器件的作用，又能使光线无损伤的穿过即可。
实施例三、
本实施例为基于实施例二给出的金属氧化物薄膜晶体管的制备方法的一种改进。本实施例与前一实施例的区别在于，本实施例以栅电极110为掩膜，在透明导电薄膜150表面涂布负性光刻胶，从衬底100底部向上曝光，通过光刻及刻蚀形成源漏电极区151及像素电极区152。
本实施例制备薄膜晶体管的方法，如图4所示，包括步骤：
S111、在衬底上生成栅电极。
此步骤与前一实施例相似，请参见图3(a)及对应的说明内容，其区别于实施例一之处是，本实施例中的栅电极110所用材料选择不透明的金属导电材料，也可采用高电导的不透明金属氧化物材料。衬底100为耐高温透明材质，如玻璃衬底，也可为非耐高温透明材质，如透明的塑料衬底。
S121、在衬底上覆盖栅电极连续生成栅介质层、有源层及金属氧化物导电层。
如图5(a)所示，在衬底上覆盖栅电极依次淀积一层绝缘薄膜、金属氧化物半导体薄膜及金属氧化物导电薄膜150，分别作为栅介质层120、有源层130及预制备源漏电极的金属氧化物导电层。
进一步地，栅介质层120采用透明绝缘材料，有源层130采用非晶或多晶的金属氧化物半导体透明材料，金属氧化物导电层采用透明金属氧化物导电材料。其中，金属氧化物导电层选用刻蚀比高于有源层130的材料，即，预制备源漏电极的导电薄膜150在酸碱腐蚀液中的腐蚀速率高于有源层130的金属氧化物半导体材料。本实施例中涉及各层的淀积方法及厚度与前一实施例相同，此处不再赘述。
S131、由衬底底部向上曝光，并刻蚀金属氧化物透明导电层，初步形成源漏极图形。
如图5(b)所示，在透明的导电薄膜150表面涂布负性光刻胶154，并从衬底100底部向上曝光，与栅电极110相对部分的负性光刻胶154未受光而溶解，露出与栅电极110相对应的部分导电薄膜150，而位于该部分两侧的负性光刻胶154经曝光后固化。然后对裸露出来的导电薄 膜150进行刻蚀，形成彼此分离的源极151和漏极152，显现如图5(c)源漏电极图形。然后清除剩余的负性光刻胶154。此步骤形成的源漏电极的初步图形。
S141、形成有源区图形。
采用正性光刻胶通过光刻及刻蚀导电薄膜150和有源层130，形成如图5(d)所示的源漏电极及有源区图形。此步骤刻蚀导电薄膜150及有源层130优选湿法刻蚀，并选择能够同时腐蚀金属氧化物导电薄膜150及金属氧化物半导体有源层130的腐蚀液。此步骤形成有源区图形时，对导电薄膜150进行了第二次刻蚀，形成完整的源漏电极图形。
S151、制备表面钝化层。
比步骤与前一实施例相同，这里不再赘述。
本实施例给出的金属氧化物薄膜晶体管的制备方法，以栅电极110为掩膜，通过负性光刻胶光刻及刻蚀金属氧化物导电层，制备源漏电极，相比前一实施例，省去了光刻金属氧化物导电层所需的掩膜版，进一步降低了生产成本。此外，以栅电极110为掩膜，从衬底100底部向上曝光，这样能够实现沟道区131与栅电极的自对准，减小了寄生效应，提高了器件性能的均匀性和工作速度，并且降低了生产难度，缩短工艺流程。
实施例四：
基于以上实施例的描述，本实施例提供了一种显示面板，参照图6(a)～(b)，图6(a)为本实施例给出的显示面板中单个像素单元的结构示意图，本实施例提供的显示面板包括若干个像素单元，以及像素单元之间的数据电极172，每个像素上对应排布有金属氧化物薄膜晶体管10及像素电极153，并且薄膜晶体管10中的源漏电极中的一极与像素电极153一体成型；数据电极172通过互连线与源漏电极中的另一极电性连接。
进一步地，如图6(b)所示，薄膜晶体管10包括位于衬底100上的栅电极110、有源层130和相互分离的源极151和漏极152，有源层130通过栅介质层120与栅电极110隔离，源极151和漏极152分别与有源层130电性接触。其中，有源层130采用金属氧化物半导体材料，源漏电极为金属氧化物透明导电材料制备。
进一步地，在本实施例中，如图6(a)～(b)所示，像素电极153与漏极152一体成型。有源层130与栅电极110相对应处设置为沟道区131，源极151与漏极152相分离的位于沟道区131两侧。其中，漏极152背离源极151一端延伸并拓宽，充当像素电极153。因此，在本实施例中，漏极152与像素电极153为一整体结构。由漏极152取代了ITO像素电极，这样就不需要单独制备ITO像素电极，减少了稀有元素In的使用，又省去了单独制备像素电极的工艺流程，降低了生产加工难度，极大地 减小了生产成本。
进一步地，如图6(a)所示，薄膜晶体管10的栅电极与扫描线111电性相连，源极通过接触孔171与数据电极170电性相连，漏极与像素电极153相连。通过扫描线111控制施加给栅极的电压，实现源极与漏极之间的导通与截止。通过数据电极170控制源极的IC信号输入，从而控制像素电极的发光亮度。
较佳的，为降低生产成本，又能提高产品的性能，本实施例金属布线层的导电金属薄膜采用Mo、Cr、Al、Cu等其中一种来制备。
实施例五：
本实施例作为前一实施例的一种改进，如图6(c)所示，数据电极170采用不透明的金属材料，薄膜晶体管10表面覆盖有透明钝化层，该钝化层采用透明绝缘材料制备，如氮化硅层或二氧化硅等，并覆盖栅介质层、有源层、源漏电极区及像素电极区。数据电极170经过薄膜晶体管10的路段宽度拓宽，并覆盖在整个薄膜晶体管对应的钝化层上。
由于数据电极170为不透明的金属电极，这样数据电极170在该路段又起到了现有技术中矩阵块遮光的作用，无需再单独制备遮光矩阵块。
进一步地，为降低制作成本且提高金属布线层的导电性能，本实施例采用铜为布线层。
实施例六：
本实施例提供了一种制备上述显示面板的方法，其方法的流程如图7所示，包括步骤：
S210、在衬底上制备栅电极。
此步骤与实施例二的步骤S110相近，具体可参见图3(a)及对应说明。
S220、在衬底上覆盖栅电极依次生成栅介质层及金属氧化物半导体有源层。此步骤与实施例二的步骤S120相近，其相同部分可参见图3(b)及其对应文字说明。
S230、光刻及刻蚀有源层形成有源区。
此步骤与实施例二的步骤S130相近，具体可参见图3(c)及对应说明。
S240、在栅介质层上生成金属氧化物导电层。
本步骤与实施例二中步骤S140相近，可参见图3(d)。生成覆盖所述有源层130和预制备像素电极区域的金属氧化物导电层，并光刻及刻蚀形成源漏电极。本实施例区别于实施例二的是，金属氧化物导电层用于制备源漏电极的导电薄膜150采用透明金属氧化物导电材质，并且该导电薄膜150采用的材料在酸碱腐蚀液中腐蚀速率高于有源层130的金属氧化物半导体材料。
进一步地，透明金属氧化物材质的导电薄膜150层覆盖了有源层130，还同时覆盖了预制备像素电极的区域，即像素电极区。
S250、图形化透明导电层形成源漏电极和像素电极。
采用腐蚀液图形化金属氧化物导电层形成源漏电极和像素电极，且源漏电极中的一极与像素电极相连。参见图3(d),在金属氧化物导电薄膜150表面涂布正性光刻胶，经曝光显影后，露出与沟道区131相对应的部分，然后通过湿法刻蚀该透明导电薄膜150，腐蚀掉与沟道区131对应的部分，形成源极151、漏极152及像素电极153。其中，源极151与漏极152彼此分离，分别位于沟道区131两侧上方，漏极152与像素电极153电性相连。
进一步地，本实施例中，漏极152与像素电极153一体成型，即漏极152经拓宽延长并覆盖预留像素电极区域，由于制备源漏电极的导电薄膜为透明金属氧化物导电材料，该拓宽延伸部分就可以充当像素电极153。当然，在本发明其他实施例中，还可以通过刻蚀形成与漏极152相分离的像素电极153，然后使漏极152与像素电极153电性相连。
现有的像素电极大多采用ITO等材料制备，因此需要使用稀有元素In，这样导致制造成本很高。而采用本实施例的方法，使透明的漏极152同时作为像素电极153，不需要另外制作ITO像素电极，减少稀有元素In的使用，从而简化了生产工艺，减小稀有材料的使用，极大的降低了生产成本。
进一步地，为了在刻蚀金属氧化物导电层150形成源漏电极过程中，避免腐蚀液损伤沟道区131，金属氧化物导电层150选用在酸碱腐蚀液中腐蚀速率高于有源层130的金属氧化物制备。同时，该步骤湿法刻蚀选用对有源层130的金属氧化物半导体材料和金属氧化物导电薄膜150选择比存在差异的腐蚀液。这样，利用金属氧化物导电薄膜150和有源层130在弱酸性或弱碱性溶液中的腐蚀速率的差异，避免刻蚀过程中对沟道区131造成损伤。
S260、表面钝化并制作源极接触孔。
在衬底上生成覆盖源漏电极、有源层和像素电极的透明钝化层，并形成源极接触孔。此步骤与实施例二中相同，再此不再赘述。
S270、在钝化层表面生成数据电极和互联线。
在钝化层表面生成一金属导电布线层，并光刻及刻蚀形成数据电极和互连线，数据电极通过互连线与源漏电极中的另一极电性连接。在本实施例中，数据电极与互联线由金属导电布线层刻蚀而成的整体结构，互联线通过源极接触孔与源极电性接触。
具体地，参见图6(a)～(b)，在钝化层160表面用磁控溅射或蒸发方法淀积一层300～300纳米厚的金属导电薄膜作为布线层，并光刻及 刻蚀形成数据电极170，数据电极170通过接触孔171与源极电性接触。
进一步的，为降低生产成本，又能提高产品的性能，该布线层的导电金属薄膜采用Mo、Cr、Al、Cu等其中一种来制备。
源漏电极区采用导电性能越好的材料产品性能越高，而常见的高电导的金属虽然成本低，但其刻蚀难度大，刻蚀过程中难免损伤其他元器件，例如损伤沟道区，因而无法无法作为布线层。而对于其他电导率较高的稀有金属来讲，其成本远远高于铜等常见导电金属。而本发明由于数据电极170是在钝化层160生成之后形成，这样由于钝化层160的存在，就能避免刻蚀过程损伤源漏电极等元器件，并且更佳的电性效果。
本实施例步骤S210～S260也可采用实施例三中制备薄膜晶体管的方法步骤，连续生成栅介质层120、有源层130及金属氧化物透明导电薄膜150，其中，金属氧化物透明导电薄膜150作为透明导电层，然后以栅电极110为掩膜，采用负性光刻胶光刻及刻蚀该透明导电层，制备源漏电极。其主要步骤已在实施例三中描述，这里不再赘述。
实施例七：
进一步地，作为前一实施例的另一种改进，可参见图6(a)及图6(c)，制备数据电极170的金属导电布线层为不透光的高电导金属薄膜，数据电极170在经过薄膜晶体管10的路段线路宽度拓宽以使其覆盖在薄膜晶体管区域的钝化层160上，并通过接触孔171与源极151电性相连。由于数据电极170为不透明的金属电极，这样数据电极170在该路段拓宽后既作为互联线又可作为矩阵块起到遮光的作用，因而无需再单独制备遮光矩阵块。
本实发明提出的金属氧化物薄膜晶体管、显示面板及两者的制备方法，采用透明导电层制备源漏电极，并由漏极充当像素电极，替代ITO像素电极，减少稀有元素In的使用，降低生产成本；利用透明导电层与有源层之间的刻蚀选择比差异避免损伤沟道区，提高了产品质量；采用栅电极为掩膜形成源漏电极区图形，既减少了掩膜版的使用，又实现栅电极与沟道区精确对准，减小了寄生效应，提高了器件性能的均匀性和工作速度，简化了流程工艺，降低了生产成本，钝化层外进行布线，降低布线工艺难度，能够实现铜或铝等常见高电导的金属布线，进一步降低了生产成本。
应当理解的是，本发明的应用不限于上述的举例，以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本领域的一般技术人员，依据本发明的思想，可以对上述具体实施方式进行变化。

Claims (10)

  1. 一种金属氧化物薄膜晶体管，其特征在于包括：
    栅电极；
    通过栅介质层与栅电极隔离的有源层，有源层采用金属氧化物半导体材料，所述有源层与栅电极对准的部分形成沟道区；
    相互分离的源极和漏极，所述源极和漏极分别与有源层电性接触，源漏电极为金属氧化物导电材料。
  2. 根据权利要求1所述的晶体管，其特征在于，源漏电极为金属氧化物透明导电材料。
  3. 一种显示面板，其特征在于包括：
    金属氧化物薄膜晶体管，所述薄膜晶体管与像素对应排布，所述薄膜晶体管包括栅电极、有源层和相互分离的源极和漏极，有源层通过栅介质层与栅电极隔离，有源层采用金属氧化物半导体材料，所述源极和漏极分别与有源层电性接触，源漏电极为金属氧化物透明导电材料；
    像素电极，与像素对应排布，所述薄膜晶体管中的源漏电极中的一极与像素电极一体成型；
    数据电极，所述数据电极通过互连线与源漏电极中的另一极电性连接。
  4. 根据权利要求3所述的显示面板，还包括一覆盖所述栅介质层、有源层、源漏电极区和像素电极区的钝化层，所述钝化层为透明钝化层，所述数据电极为金属电极，所述数据电极在经过薄膜晶体管的路段线路宽度拓宽以使其覆盖在薄膜晶体管区域的钝化层上。
  5. 一种金属氧化物薄膜晶体管的制备方法，其特征在于，包括：
    在衬底上制备栅电极；
    在所述衬底上覆盖所述栅电极依次生成栅介质层及金属氧化物半导体有源层；
    生成覆盖所述有源层的金属氧化物导电层，所述金属氧化物导电层采用腐蚀速率高于所述有源层的腐蚀速率的材料；
    采用腐蚀液图形化所述金属氧化物导电层形成源漏电极。
  6. 根据权利要求5所述的薄膜晶体管的制备方法，其特征在于，所述金属氧化物导电层为金属氧化物透明导电材料。
  7. 根据权利要求5所述的薄膜晶体管的制备方法，其特征在于，在生成金属氧化物导电层之前，光刻及刻蚀所述有源层形成有源区。
  8. 根据权利要求5所述的薄膜晶体管的制备方法，其特征在于，所述栅介质层、有源层、金属氧化物导电层连续生长，在形成所述源漏电极区后，光刻及刻蚀所述有源层形成有源区。
  9. 一种显示面板的制备方法，其特征在于包括：
    在衬底上制备栅电极；
    在所述衬底上覆盖所述栅电极依次生成栅介质层及金属氧化物半导体有源层；
    生成覆盖所述有源层和像素电极区的金属氧化物透明导电层，所述金属氧化物透明导电层采用腐蚀速率高于所述有源层的腐蚀速率的材料；
    采用腐蚀液图形化所述透明导电层形成源漏电极和像素电极，且源漏电极中的一极与像素电极相连；
    在所述衬底上生成覆盖所述源漏电极、有源层和像素电极的透明钝化层，并形成源极接触孔；
    在所述钝化层表面生成一金属导电布线层，并光刻及刻蚀形成数据电极和互连线，数据电极通过互连线与源漏电极中的另一极电性连接。
  10. 根据权利要求4-7任一所述的显示面板的制备方法，其特征在于，所述数据电极在经过薄膜晶体管的路段线路宽度拓宽以使其覆盖在薄膜晶体管区域的钝化层上。
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DE112020005206T5 (de) 2019-10-29 2022-08-25 Nvidia Corporation Bestimmen der Objektorientierung aus einem Bild mit Maschinenlernen
DE112020005509T5 (de) 2019-11-08 2022-08-25 Nvidia Corporation Prozessor und system zum identifizieren von out-of-distribution- eingabedaten in neuronalen netzwerken
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DE102021131760A1 (de) 2020-12-07 2022-06-09 Nvidia Corporation Anwendungsprogrammierschnittstelle für berechnungen einesneuronalen netzes
DE102021132987A1 (de) 2020-12-29 2022-06-30 Nvidia Corporation Lokalisierung von rückhaltevorrichtungen
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CN113571586A (zh) * 2021-07-12 2021-10-29 沈阳工业大学 双掺杂源漏单晶体管同或门及制造方法
DE112022003428T5 (de) 2021-09-03 2024-05-08 Nvidia Corporation 5g-nr-softwareschnittstelle
DE112023000334T5 (de) 2022-02-15 2024-08-22 Nvidia Corporation Dynamische objektdetektion mit lidar-daten für autonome maschinensysteme und anwendungen
CN116400545A (zh) * 2023-04-17 2023-07-07 北京京东方显示技术有限公司 电子纸基板及其制备方法、电子纸显示装置
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CN119584568A (zh) * 2024-10-12 2025-03-07 清华大学 用于提升铟镓锌氧化物薄膜晶体管迁移率的制备方法

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