WO2016199428A1 - Switch device - Google Patents

Switch device Download PDF

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Publication number
WO2016199428A1
WO2016199428A1 PCT/JP2016/002808 JP2016002808W WO2016199428A1 WO 2016199428 A1 WO2016199428 A1 WO 2016199428A1 JP 2016002808 W JP2016002808 W JP 2016002808W WO 2016199428 A1 WO2016199428 A1 WO 2016199428A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
relay
switch
control signal
switch device
Prior art date
Application number
PCT/JP2016/002808
Other languages
French (fr)
Japanese (ja)
Inventor
岡田　洋
知士 久保
Original Assignee
パナソニックＩｐマネジメント株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
Priority to JP2017523115A priority Critical patent/JP6817582B2/en
Priority to CN201680033447.6A priority patent/CN107710617B/en
Publication of WO2016199428A1 publication Critical patent/WO2016199428A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
    • H01H9/54—Circuit arrangements not adapted to a particular application of the switching device and for which no provision exists elsewhere
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit

Definitions

  • the present invention generally relates to a switch device, and more particularly to a switch device having a mechanical relay and a semiconductor relay.
  • the direct current switch includes an electronic on / off switch inserted into a direct current path and a mechanical on / off switch connected in parallel to the electronic on / off switch.
  • the direct current switch includes a switch control circuit that controls a time difference between opening and closing of the mechanical opening / closing switch and the electronic opening / closing switch.
  • the switch control circuit performs control to close the mechanical on / off switch after a predetermined time after the electronic on / off switch is closed. As a result, this DC switch reduces the power loss of the electronic switch when the DC current path is made conductive.
  • the electronic opening / closing switch semiconductor relay
  • the mechanical opening / closing switch mechanical relay
  • the electronic opening / closing switch and the mechanical opening / closing switch are individually provided. It was necessary to control by giving a control signal. For this reason, the conventional example has a problem that it is difficult to control a hybrid relay combining a semiconductor relay and a mechanical relay with one control signal.
  • the present invention has been made in view of the above points, and an object thereof is to easily control a hybrid relay combining a semiconductor relay and a mechanical relay with one control signal.
  • the switch device includes a semiconductor relay, a mechanical relay, and a control circuit.
  • the semiconductor relay opens and closes a power feeding path from a power source to a load.
  • the mechanical relay has a contact portion electrically connected in parallel with the semiconductor relay, and opens and closes the power feeding path by turning on and off the contact portion in accordance with a control signal input from the outside.
  • the control circuit receives the control signal and controls the semiconductor relay.
  • the semiconductor relay has a semiconductor switch.
  • the semiconductor switch opens and closes the power supply path by turning on / off according to the charge accumulated in the capacitive component.
  • the control circuit is configured to control the semiconductor switch so that the timing at which the semiconductor switch is turned off is delayed from the timing at which the contact portion of the mechanical relay is turned on from off.
  • the switch device 1 As shown in FIGS. 1 and 2, the switch device 1 according to Embodiment 1 of the present invention includes a semiconductor relay 2, a mechanical relay 3, and a control circuit 4.
  • the semiconductor relay 2 opens and closes a power feeding path from the power source A1 to the load B1.
  • the mechanical relay 3 includes a contact portion 32 that is electrically connected in parallel with the semiconductor relay 2, and opens and closes the power supply path by turning the contact portion 32 on and off according to a control signal input from the outside.
  • the control circuit 4 receives the control signal and controls the semiconductor relay 2.
  • the semiconductor relay 2 has a semiconductor switch 2B.
  • the semiconductor switch 2B opens and closes the power feeding path by turning on / off according to the electric charge accumulated in the capacitance component (capacitor 42).
  • the control circuit 4 is configured to control the semiconductor switch 2B so that the timing at which the semiconductor switch 2B is turned off is delayed from the timing at which the contact portion 32 of the mechanical relay 3 is turned off.
  • the switch device 1 of the present embodiment will be described in detail.
  • the ON signal among the control signals is input means “the control signal becomes high level”.
  • an OFF signal is input from among the control signals” means “the control signal becomes low level”.
  • the switch device 1 includes a pair of input terminals 101 and 102 (first input terminal 101 and second input terminal 102) and a pair of output terminals 111 and 112 (first output terminal). 111 and a second output terminal 112).
  • a pair of input terminals 201 and 202 (first input terminal 201 and second input terminal 202) of the semiconductor relay 2 are electrically connected to the pair of input terminals 101 and 102 via the control circuit 4.
  • a pair of input terminals 301 and 302 (first input terminal 301 and second input terminal 302) of the mechanical relay 3 are electrically connected to the pair of input terminals 101 and 102.
  • the pair of output terminals 111 and 112 include a pair of output terminals 211 and 212 (first output terminal 211 and second output terminal 212) of the semiconductor relay 2 and a pair of output terminals 311 and 312 (mechanical relay 3).
  • the first output terminal 311 and the second output terminal 312) are electrically connected. That is, the mechanical relay 3 is electrically connected to the semiconductor relay 2 in parallel.
  • the switch device 1 of this embodiment is turned on when at least one of the semiconductor relay 2 and the mechanical relay 3 is turned on. Moreover, the switch apparatus 1 of this embodiment is turned off when both the semiconductor relay 2 and the mechanical relay 3 are turned off.
  • a control signal is input to the pair of input terminals 101 and 102 from, for example, a microcomputer.
  • a Zener diode ZD1 is electrically connected between the pair of input terminals 101 and 102 so that an excessive voltage is not input.
  • a power source A1 and a load B1 are electrically connected to the pair of output terminals 111 and 112. Therefore, if the pair of output terminals 111 and 112 are non-conductive (switch device 1 is off), power is not supplied from the power source A1 to the load B1. Further, when the pair of output terminals 111 and 112 are electrically connected (the switch device 1 is turned on), power is supplied from the power source A1 to the load B1. That is, the switch device 1 of the present embodiment opens and closes the power feeding path from the power source A1 to the load B1.
  • a DC power source is used as the power source A1, but an AC power source may be used.
  • the load B1 is, for example, an electric vehicle (Electric Vehicle: EV).
  • the load B1 may be, for example, a security device, an amusement device, a medical device, a storage battery system, a heater, a DC motor, or the like.
  • the power source A1 is an AC power source
  • the load B1 is configured by a load that operates by being supplied with AC power.
  • the power source A1 is a DC power source
  • the load B1 is configured by a load that operates by being supplied with DC power.
  • the load B1 may be a resistance load or an inductive load.
  • load B1 is a coil which a switch has, for example, and is an inductive load.
  • the semiconductor relay 2 is a so-called non-contact relay and includes a light emitting element 2A, a semiconductor switch 2B, and a light receiving element 2C.
  • the light emitting element 2A and the semiconductor switch 2B are electrically insulated from each other. That is, in the switch device 1 of this embodiment, the semiconductor relay 2 uses the light emitting element 2A and the light receiving element 2C to electrically connect the pair of input ends 201 and 202 and the pair of output ends 211 and 212. Insulated.
  • the semiconductor relay 2 includes insulating portions 2A and 2C that electrically insulate the primary side (the pair of input terminals 101 and 102 side) from the secondary side (the pair of output terminals 111 and 112 side). It can be said that.
  • the insulating portions 2A and 2C may have other configurations.
  • the semiconductor relay 2 is configured to electrically insulate between the pair of input ends 201 and 202 and the pair of output ends 211 and 212 by using a capacitor instead of the light emitting element 2A and the light receiving element 2C. May be.
  • the semiconductor relay 2 needs to further include a drive circuit for driving the semiconductor switch 2B.
  • the light emitting element 2A is configured to convert an electric signal input to the pair of input ends 201 and 202 into light.
  • the light emitting element 2A is a light emitting diode.
  • the light emitting diode has an anode electrically connected to the first input end 201 and a cathode electrically connected to the second input end 202.
  • the light emitting element 2 ⁇ / b> A emits light upon receiving an ON signal among control signals input to the pair of input terminals 201 and 202. Further, the light emitting element 2A does not emit light while receiving an off signal among the control signals. Note that the number of light emitting diodes constituting the light emitting element 2A is not limited to one, and may be plural.
  • the current adjusting resistor 11 is electrically connected in series to the light emitting element 2A. This resistor 11 prevents an excessive current from flowing through the light emitting element 2A.
  • the light receiving element 2C is configured to receive a light emitted from the light emitting element 2A and generate a photovoltaic power.
  • the light receiving element 2C is configured by a photodiode array formed by electrically connecting a plurality of photodiodes in series.
  • the semiconductor switch 2B is an n-channel enhancement type MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor).
  • the gate of the semiconductor switch 2B is electrically connected to one end on the high potential side of the light receiving element 2C.
  • the drain of the semiconductor switch 2B is electrically connected to the first output terminal 111.
  • the source of the semiconductor switch 2B is electrically connected to one end on the low potential side of the light receiving element 2C and the second output terminal 112.
  • the semiconductor switch 2B is configured to be turned on / off according to the charge accumulated in the gate capacitance.
  • the “gate capacitance” means a capacitor (generally referred to as “gate input capacitance”) existing between the gate and source of the semiconductor switch 2B and a capacitor (generally referred to as “gate capacitance”) between the gate and drain. Output capacity).
  • the semiconductor switch 2B there is one semiconductor switch 2B, but two semiconductor switches may be used. That is, when the power source A1 is an AC power source, the switch device 1 requires two semiconductor switches 2B.
  • the semiconductor switch 2B is an enhancement type MOSFET, but may be a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor).
  • the semiconductor relay 2 further includes a semiconductor element 2D and a resistor 2E as a charge / discharge path for charging and discharging the gate capacitance of the semiconductor switch 2B.
  • the semiconductor element 2D is an n-channel depletion type MOSFET.
  • the drain of the semiconductor element 2D is electrically connected to one end on the high potential side of the light receiving element 2C.
  • the gate of the semiconductor element 2D is electrically connected to one end on the low potential side of the light receiving element 2C.
  • the source of the semiconductor element 2D is electrically connected to one end on the low potential side of the light receiving element 2C via the resistor 2E.
  • the resistor 2E is electrically connected between the gate and source of the semiconductor element 2D.
  • the switch device 1 further includes a control circuit 4 and a varistor VR1.
  • the varistor VR1 is electrically connected between the pair of output ends 211 and 212.
  • the varistor VR1 protects the semiconductor switch 2B from an excessive back electromotive force applied between the pair of output terminals 211 and 212 when the switch device 1 is turned off.
  • the varistor VR1 is not necessary when the load B1 is a resistance load.
  • the control circuit 4 has a delay circuit 5 and a buffer circuit 6.
  • the delay circuit 5 includes a resistor 41 and a capacitor 42.
  • the resistor 41 is electrically connected between the first input terminal 101 and the input terminal of the buffer circuit 6.
  • the capacitor 42 is electrically connected between the connection point between the resistor 41 and the input end of the buffer circuit 6 and the second input terminal 102.
  • the delay circuit 5 is configured to delay a control signal input to the pair of input terminals 101 and 102 and input the delayed control signal to the pair of input terminals 201 and 202 of the semiconductor relay 2. For this reason, in the switch apparatus 1 of this embodiment, the timing at which the control signal is input to the semiconductor relay 2 can be delayed from the timing at which the control signal is input to the mechanical relay 3.
  • the buffer circuit 6 is electrically connected between the output terminal on the high voltage side of the delay circuit 5 and the first input terminal 201 of the semiconductor relay 2.
  • a control signal delayed by the delay circuit 5 is input to the buffer circuit 6.
  • the buffer circuit 6 does not output the control signal until the voltage of the input control signal reaches the threshold voltage, and outputs the control signal when the threshold voltage is reached. For example, when an ON signal among the control signals is input to the buffer circuit 6, the buffer circuit 6 outputs an ON signal when the voltage of the ON signal exceeds the threshold voltage. In addition, when an off signal among the control signals is input to the buffer circuit 6, the buffer circuit 6 outputs an off signal when the voltage of the off signal falls below the threshold voltage.
  • the buffer circuit 6 is configured to receive a control signal via the delay circuit 5 and output the control signal when the voltage of the control signal reaches the threshold voltage. Therefore, the buffer circuit 6 converts the control signal whose voltage gradually changes according to the time constant of the delay circuit 5 into a rectangular wave control signal, and outputs the converted control signal to the light emitting element 2A. For this reason, in the switch device 1 of the present embodiment, since the control signal whose voltage gradually changes with the passage of time is not input to the semiconductor relay 2, the time for which the semiconductor switch 2B operates in the active region can be shortened. . As a result, in the switch device 1 of the present embodiment, the stability of the operation of the semiconductor switch 2B can be improved.
  • the light receiving element 2C in response to the light emitted from the light emitting element 2A, the light receiving element 2C generates a photovoltaic power. Then, when a current flows from the light receiving element 2C to the semiconductor element 2D and the resistor 2E, a voltage drop occurs in the resistor 2E, and the semiconductor element 2D is turned off by this voltage drop. For this reason, a current flows from the light receiving element 2C to the gate of the semiconductor switch 2B, the gate capacitance of the semiconductor switch 2B is charged, and the semiconductor switch 2B is turned on. As a result, the pair of output terminals 111 and 112 are electrically connected.
  • the capacitor 42 of the delay circuit 5 starts to discharge. For this reason, the voltage of the control signal via the delay circuit 5 gradually decreases from the high level to the low level as time elapses.
  • the buffer circuit 6 outputs the off signal, so that the light emitting element 2A does not emit light. .
  • the semiconductor switch 2B opens and closes the power supply path from the power source A1 to the load B1 by turning on / off according to the charge accumulated in the capacitance component (capacitor 42).
  • the semiconductor relay 2 opens and closes the power feeding path from the power source A1 to the load B1 in accordance with a control signal input from the outside.
  • the semiconductor relay 2 includes the light emitting element 2A and the light receiving element 2C.
  • the semiconductor switch 2B is configured to be turned on / off by the photovoltaic force generated by the light receiving element 2C.
  • the switch device 1 according to the present embodiment has an advantage that the potential difference between the input and the output hardly affects the on / off of the semiconductor switch 2B. Note that whether or not to adopt the configuration for the semiconductor relay 2 is arbitrary.
  • the semiconductor relay 2 is not limited to the circuit configuration shown in FIG.
  • the semiconductor switch 2B may be configured to be turned on / off according to the presence or absence of light emitted from the light emitting element 2A.
  • the mechanical relay 3 is a so-called contact relay (for example, an electromagnetic relay), and includes a coil 31 and a contact portion 32.
  • the coil 31 has a first end electrically connected to the first input end 301 and a second end electrically connected to the second input end 302. The coil 31 is excited when a control signal is input to the pair of input ends 301 and 302.
  • the contact portion 32 has a first end electrically connected to the first output end 311 and a second end electrically connected to the second output end 312.
  • the contact part 32 includes a fixed contact and a movable contact.
  • the fixed contact and the movable contact are opened and closed according to the excitation / de-excitation of the coil 31.
  • the contact part 32 is off because the movable contact is away from the fixed contact.
  • the contact part 32 is comprised so that when the coil 31 is excited, a movable contact contacts a fixed contact, and it switches on.
  • the mechanical relay 3 mechanically switches on / off of the contact portion 32 in accordance with a control signal input to the pair of input terminals 301 and 302, thereby connecting or not connecting the pair of output terminals 111 and 112. Switch continuity.
  • the mechanical relay 3 opens and closes the power feeding path from the power source A1 to the load B1 by turning on / off the contact portion 32 according to the control signal.
  • the “contact voltage” shown in FIG. 3 is a voltage applied between the pair of output terminals 111 and 112.
  • the “first current” shown in FIG. 3 is a current flowing through the pair of output terminals 211 and 212 of the semiconductor relay 2.
  • the “second current” shown in FIG. 3 is a current flowing through the pair of output terminals 311 and 312 of the mechanical relay 3.
  • the contact portion 32 of the mechanical relay 3 is turned on at time t11 (> t10) after a predetermined time from time t10. Turn on. For this reason, between the pair of output terminals 311 and 312 is conducted, the second current flows. Then, since the pair of output terminals 111 and 112 are also connected, the power supply path from the power source A1 to the load B1 is closed, and a current flows through the load B1. In the present embodiment, since the load B1 is an inductive load, the second current gradually increases from time t11 to time t12 (> t11). When the load B1 is a resistance load, the second current rises sharply at time t11.
  • the switch device 1 of this embodiment compared with the case where the power supply path is closed only by the semiconductor relay 2 without using the mechanical relay 3, the power loss and heat generation at the on-resistance of the semiconductor switch 2B are reduced.
  • the energization current can be increased.
  • the “energization current” is a current that flows between the pair of output terminals 111 and 112 when the power supply path from the power source A1 to the load B1 is closed.
  • the semiconductor switch 2B is not turned off, so that the power supply voltage is not applied between the pair of output terminals 111 and 112. For this reason, in the switch device 1 of the present embodiment, compared to the case where the semiconductor switch 2B of the semiconductor relay 2 is turned off before the contact part 32 of the mechanical relay 3, an arc is less likely to occur when the contact part 32 is turned off.
  • the contact portion 32 is turned off before the semiconductor switch 2B. It is desirable to be controlled.
  • this control is referred to as “priority off control”.
  • the turn-off time of the semiconductor switch 2B is shorter than the return time of the contact part 32, the semiconductor switch 2B is turned off before the contact part 32.
  • control circuit 4 controls the semiconductor switch 2B to delay the timing at which the semiconductor switch 2B is turned off from the timing at which the contact portion 32 of the mechanical relay 3 is turned from on to off. It is configured as follows. For this reason, in the switch apparatus 1 of this embodiment, priority OFF control is realizable by one control signal, without controlling the semiconductor relay 2 and the mechanical relay 3 separately.
  • the control circuit 4 controls the semiconductor switch 2B to delay the timing at which the semiconductor switch 2B is turned on from the timing at which the contact portion 32 of the mechanical relay 3 is turned on from off. It is configured as follows. For this reason, in the switch apparatus 1 of this embodiment, when a pair of output terminals 111 and 112 conduct
  • the switch device 1 according to the present embodiment includes the control circuit 4, complicated control such as individually controlling the semiconductor relay 2 and the mechanical relay 3 and shifting the respective off timings is unnecessary. is there. That is, the switch device 1 of the present embodiment can easily control a hybrid relay in which the semiconductor relay 2 and the mechanical relay 3 are combined with one control signal.
  • the switch apparatus 1 of this embodiment is the structure which the semiconductor switch 2B (contact part 32) turns on when a control signal is a high level
  • another structure may be sufficient. That is, the switch device 1 of the present embodiment may be configured such that the semiconductor switch 2B (contact portion 32) is turned on when the control signal is at a low level.
  • the ON signal among the control signals is input means “the control signal becomes low level”.
  • the OFF signal of the control signal is not input” means “the control signal becomes high level”.
  • a switch device 1A according to a modification of the first embodiment of the present invention will be described with reference to FIG.
  • the switch device 1 ⁇ / b> A of this modification is different from the switch device 1 of the first embodiment in that a control circuit 4 ⁇ / b> A is provided instead of the control circuit 4. Since the configuration excluding the control circuit 4A in the switch device 1A of the present modification is the same as that of the switch device 1 of the first embodiment, the description thereof is omitted here.
  • the control circuit 4 ⁇ / b> A has a delay circuit 5 ⁇ / b> A instead of the delay circuit 5.
  • the delay circuit 5A further includes a diode 43 and resistors 44 and 45 in addition to the resistor 41 and the capacitor 42 of the delay circuit 5.
  • the resistance value of the resistor 41 is smaller than the resistance value of the resistor 41 in the delay circuit 5 of the first embodiment.
  • the diode 43 has an anode electrically connected to the first input terminal 101 and a cathode electrically connected to the resistor 41.
  • the resistor 44 is electrically connected to the capacitor 42 in parallel.
  • the resistance value of the resistor 44 is larger than the resistance value of the resistor 41.
  • the resistor 45 is electrically connected to the capacitor 42 in series. The resistance value of the resistor 45 is approximately the same as the resistance value of the resistor 41.
  • the delay circuit 5A when an ON signal among the control signals is input between the pair of input terminals 101 and 102, in the delay circuit 5A, the resistance value of the resistor 41 is greater than the resistance value of the resistor 41 in the delay circuit 5 of the first embodiment. Since it is small, the time constant is smaller than that of the delay circuit 5. Therefore, the delay time of the on signal by the control circuit 4A is shorter than the delay time of the on signal by the control circuit 4 of the first embodiment.
  • the delay circuit 5A prevents the charge accumulated in the capacitor 42 from being discharged to the mechanical relay 3 by the diode 43. ing. Further, in the delay circuit 5A, the time for discharging the charge accumulated in the capacitor 42 is made relatively long by the resistor 44 connected in parallel to the capacitor 42 and the resistor 45 connected in series to the capacitor 42. Therefore, the delay time of the off signal by the control circuit 4A is longer than the delay time of the on signal by the control circuit 4A.
  • the switch device 1A of the present modification utilizes the characteristic that the turn-on time of the semiconductor switch 2B of the semiconductor relay 2 is shorter than the operation time of the contact part 32 of the mechanical relay 3. That is, the delay time of the ON signal by the control circuit 4A is made shorter than the difference between the turn-on time of the semiconductor switch 2B and the operation time of the contact part 32. For this reason, in the switch device 1A of the present modification, even when the ON signal is delayed by the control circuit 4A, the timing at which the semiconductor switch 2B is turned from OFF to ON is made earlier than the timing at which the contact portion 32 is turned from OFF to ON. Is possible.
  • the delay time of the off signal is made longer than the delay time of the on signal by the control circuit 4A. For this reason, in the switch device 1A of the present modification, as with the control circuit 4 of the first embodiment, the timing at which the semiconductor switch 2B is turned from on to off can be delayed from the timing at which the contact portion 32 is turned from on to off. Is possible.
  • the contact portion 32 of the mechanical relay 3 is not turned on. Thereafter, at time t23 (> t22), which is a predetermined time after time t22, the contact portion 32 of the mechanical relay 3 is turned on.
  • time t23 (> t22), which is a predetermined time after time t22, the contact portion 32 of the mechanical relay 3 is turned on.
  • the contact voltage becomes a voltage corresponding to the voltage drop due to the on-resistance between the drain and source of the semiconductor switch 2B, so it is compared with the maximum voltage of the power supply voltage. And small.
  • the inrush current that can be generated when the contact portion 32 is turned on can be reduced as compared with the case where the power supply path is closed only by the mechanical relay 3 without using the semiconductor relay 2. .
  • time t26 (> t25) when a further time elapses from time t25, the semiconductor switch 2B of the semiconductor relay 2 is turned off by inputting an off signal to the semiconductor relay 2 via the control circuit 4A. Then, since the pair of output terminals 111 and 112 become non-conductive, the power supply path from the power source A1 to the load B1 is opened, and no current flows through the load B1. Note that the time from time t26 to time 27 (> t26) is the time during which the varistor VR1 is functioning.
  • the switch device 1 ⁇ / b> A when the ON signal among the control signals is input to the pair of input terminals 101 and 102, the semiconductor of the semiconductor relay 2 is preceded by the contact portion 32 of the mechanical relay 3. It is desirable to control the switch 2B to be turned on. Hereinafter, this control is referred to as “priority on control”.
  • priority on control is realized by using the control circuit 4A while utilizing the characteristic that the turn-on time of the semiconductor switch 2B is shorter than the operation time of the contact part 32. .
  • the control circuit 4A controls the semiconductor switch 2B so that the timing at which the semiconductor switch 2B is turned on is earlier than the timing at which the contact portion 32 of the mechanical relay 3 is turned on. It is configured as follows. For this reason, in the switch device 1A of the present modification, priority on control can be realized by one control signal without individually controlling the semiconductor relay 2 and the mechanical relay 3. Further, in the switch device 1A of the present modification example, the priority off control is also realized by using the control circuit 4A as in the control circuit 4 of the first embodiment.
  • the switch device 1A of the present modification includes the control circuit 4A, complicated control such as individually controlling the semiconductor relay 2 and the mechanical relay 3 to shift the on / off timings. Is unnecessary. That is, the switch device 1 ⁇ / b> A of the present modification can easily control a hybrid relay in which the semiconductor relay 2 and the mechanical relay 3 are combined with one control signal.
  • the switch device 1B As shown in FIG. 6, the switch device 1B according to the second embodiment of the present invention includes a semiconductor relay 2, a mechanical relay 3, and a control circuit 4B.
  • the semiconductor relay 2 is electrically connected to a power feeding path from the power source A1 to the load B1, and opens and closes the power feeding path according to a first control signal input from the outside.
  • the mechanical relay 3 is electrically connected in parallel with the semiconductor relay 2 and opens and closes the power feeding path according to a second control signal input from the outside.
  • the semiconductor relay 2 has semiconductor switches 23 and 24.
  • the semiconductor switches 23 and 24 open and close the power supply path by being turned on / off according to the first control signal. Further, the semiconductor switches 23 and 24 are configured to be turned on / off according to the electric charge accumulated in the capacitance component (gate capacitance).
  • the control circuit 4B includes a charge / discharge path 25 and an impedance circuit 26.
  • the charge / discharge path 25 charges and discharges the gate capacitance of the semiconductor switches 23 and 24.
  • the impedance circuit 26 is electrically connected to the charge / discharge path 25.
  • the impedance circuit 26 includes an impedance element 261 and is configured to connect the first path S1 to the charge / discharge path 25 when an ON signal is input from among the control signals (first control signals). Furthermore, the impedance circuit 26 is configured to connect the charge / discharge path 25 to the second path S2 including the impedance element 261 when an off signal is input from among the control signals (first control signals).
  • the switch device 1B of the present embodiment will be described in detail. However, in the switch device 1B of the present embodiment, the description of the parts common to the switch device 1 of the first embodiment is omitted. In the switch device 1B of the present embodiment, an AC power source is used as the power source A1, but a DC power source may be used.
  • the ON signal is input from among the first control signals (second control signals)” means “the first control signal (second control signal) becomes high level”.
  • the off signal of the first control signal (second control signal) is input means that “the first control signal (second control signal) becomes low level”.
  • the control signal is input to the pair of input terminals 201 and 202 of the semiconductor relay 2 as the first control signal.
  • the control signal is input to the pair of input terminals 301 and 302 of the mechanical relay 3 as the second control signal. That is, in the switch device 1B of the present embodiment, the first control signal and the second control signal are the same. In other words, the first control signal and the second control signal have the same period and the same phase. Of course, the first control signal and the second control signal may be different control signals.
  • the semiconductor relay 2 is a so-called non-contact relay, and has a light emitting element 21, a light receiving element 22, and two semiconductor switches 23 and 24.
  • the light emitting element 21 is configured to convert an electric signal input to the pair of input ends 201 and 202 into light.
  • the light emitting element 21 is a light emitting diode.
  • the light emitting diode has an anode electrically connected to the first input end 201 and a cathode electrically connected to the second input end 202.
  • the light emitting element 21 emits light in response to the first control signal input to the pair of input ends 201 and 202. Note that the number of light emitting diodes constituting the light emitting element 21 is not limited to one and may be plural.
  • the first control signal and the second control signal are the same as described above.
  • the current adjusting resistor 11 is electrically connected between the first input terminal 101 and the first input terminal 201 of the semiconductor relay 2.
  • the resistor 11 prevents an excessive current from flowing through the light emitting element 21. Note that when the first control signal and the second control signal are individually input to the semiconductor relay 2 and the mechanical relay 3, the resistor 11 is not necessary.
  • the light receiving element 22 is configured to receive a light emitted from the light emitting element 21 and generate a photovoltaic power.
  • the light receiving element 22 is configured by a photodiode array in which a plurality of photodiodes are electrically connected in series.
  • the anode is electrically connected to one end on the high potential side of the charge / discharge path 25 and the cathode is electrically connected to one end on the low potential side of the charge / discharge path 25.
  • the semiconductor switches 23 and 24 are both n-channel enhancement type MOSFETs.
  • the gates of the semiconductor switches 23 and 24 are electrically connected to one end on the high potential side of the light receiving element 22.
  • the sources of the semiconductor switches 23 and 24 are electrically connected to one end on the low potential side of the light receiving element 22 via the impedance circuit 26.
  • the drain of the semiconductor switch 23 is electrically connected to the first output terminal 111.
  • the drain of the semiconductor switch 24 is electrically connected to the second output terminal 112. That is, the semiconductor switches 23 and 24 are electrically connected in series between the pair of output terminals 111 and 112.
  • the semiconductor switches 23 and 24 are both configured to be turned on / off according to the electric charge accumulated in the capacitance component (gate capacitance).
  • the “gate capacitance” is a capacitor existing between the gate and the source of the semiconductor switches 23 and 24 and a capacitor existing between the gate and the drain.
  • the switch apparatus 1B of this embodiment although there are two semiconductor switches (23, 24), there may be one. That is, when the power source A1 is an AC power source, the switch device 1 requires two semiconductor switches (23, 24). On the other hand, when the power source A1 is a DC power source, the switch device 1B requires one high-potential side semiconductor switch (one of 23 and 24).
  • the semiconductor switches (23, 24) are enhancement type MOSFETs, but may be semiconductor elements such as IGBTs.
  • the control circuit 4B has a charge / discharge path 25 and an impedance circuit 26.
  • the charge / discharge path 25 is configured to charge and discharge the gate capacitance of the semiconductor switches 23 and 24.
  • the charge / discharge path 25 includes a resistor 251 that is electrically connected in parallel with the light receiving element 22.
  • the function of the charge / discharge path 25 will be briefly described.
  • a photoelectromotive force is generated in the light receiving element 22
  • a current flows from the light receiving element 22 to the gates of the semiconductor switches 23 and 24, and the gate capacitances of the semiconductor switches 23 and 24 are charged.
  • the gate capacitances of the semiconductor switches 23 and 24 are discharged via the resistor 251 of the charge / discharge path 25.
  • route 25 is comprised including the resistance 251
  • another structure may be sufficient.
  • the charge / discharge path 25 may include a semiconductor element 252 and a resistor 253 as shown in FIG.
  • the semiconductor element 252 is an n-channel depletion type MOSFET.
  • the drain of the semiconductor element 252 is electrically connected to one end on the high potential side of the light receiving element 22.
  • the gate of the semiconductor element 252 is electrically connected to one end on the low potential side of the light receiving element 22.
  • the source of the semiconductor element 252 is electrically connected to one end on the low potential side of the light receiving element 22 through the resistor 253.
  • the resistor 253 is electrically connected between the gate and source of the semiconductor element 252.
  • the function of the charge / discharge path 25 will be briefly described.
  • a photoelectromotive force is generated in the light receiving element 22
  • a current flows from the light receiving element 22 to the semiconductor element 252 and the resistor 253.
  • a voltage drop occurs in the resistor 253, and the semiconductor element 252 is turned off by this voltage drop. Therefore, a current flows from the light receiving element 22 to the gates of the semiconductor switches 23 and 24, and the gate capacitances of the semiconductor switches 23 and 24 are charged.
  • no photoelectromotive force is generated in the light receiving element 22, no voltage drop occurs in the resistor 253, and the semiconductor element 252 is turned on. For this reason, the gate capacitances of the semiconductor switches 23 and 24 are discharged through a path through the semiconductor element 252.
  • the impedance circuit 26 includes an impedance element 261 and a switch 262.
  • the impedance element 261 is electrically connected between one end on the low potential side of the light receiving element 22 and the sources of the semiconductor switches 23 and 24.
  • the switch 262 is electrically connected to the impedance element 261 in parallel.
  • the impedance circuit 26 is configured to switch the path through which the current flows to the first path S1 via the switch 262 when an ON signal of the first control signals is input to the pair of input terminals 201 and 202. Further, the impedance circuit 26 is configured to switch the path through which the current flows to the second path S2 via the impedance element 261 when an off signal of the first control signals is input to the pair of input terminals 201 and 202. ing.
  • the impedance circuit 26 is configured to connect the charge / discharge path 25 that charges and discharges the gate capacitance of the semiconductor switches 23 and 24 to the first path S1 when an ON signal is input from among the first control signals.
  • the impedance circuit 26 is configured to connect the charge / discharge path 25 to the second path S2 including the impedance element 261 when an off signal is input from the first control signal.
  • the impedance circuit 26 includes a resistor R1 (impedance element 261) and a diode D1 (switch 262).
  • the resistor R ⁇ b> 1 is electrically connected between one end on the low potential side of the light receiving element 22 and the sources of the semiconductor switches 23 and 24.
  • the diode D1 is electrically connected in parallel with the resistor R1.
  • the diode D1 has an anode electrically connected to the sources of the semiconductor switches 23 and 24 and a cathode electrically connected to one end of the light receiving element 22 on the low potential side.
  • the operation of the semiconductor relay 2 will be described.
  • the light emitting element 21 emits light.
  • the light receiving element 22 in response to the light emitted from the light emitting element 21, the light receiving element 22 generates photovoltaic power.
  • the pair of output terminals 111 and 112 are electrically connected.
  • the light emitting element 21 When the off signal of the first control signals is input to the pair of input terminals 201 and 202, the light emitting element 21 does not emit light. For this reason, the light receiving element 22 does not generate photovoltaic power. Then, the gate capacitances of the semiconductor switches 23 and 24 are discharged through the resistor 251 of the charge / discharge path 25 and the second path S2 of the impedance circuit 26, and the semiconductor switches 23 and 24 are turned off. As a result, the pair of output terminals 111 and 112 become non-conductive.
  • the semiconductor relay 2 switches on / off of the semiconductor switches 23 and 24 according to the first control signal input to the pair of input terminals 201 and 202, thereby connecting the pair of output terminals 111 and 112. Switch non-conduction.
  • the semiconductor relay 2 opens and closes the power supply path from the power source A1 to the load B1 by turning on / off the semiconductor switches 23 and 24 according to the first control signal.
  • the semiconductor relay 2 uses the light emitting element 21 and the light receiving element 22 to electrically connect the pair of input ends 201 and 202 and the pair of output ends 211 and 212. Insulated. That is, the semiconductor relay 2 includes the insulating portions 21 and 22 that electrically insulate the primary side (the pair of input terminals 101 and 102 side) from the secondary side (the pair of output terminals 111 and 112 side). It can be said.
  • the insulating portions 21 and 22 may have other configurations.
  • the semiconductor relay 2 is configured to electrically insulate between the pair of input terminals 201 and 202 and the pair of output terminals 211 and 212 by using a capacitor instead of the light emitting element 21 and the light receiving element 22. May be. When using a capacitor, the semiconductor relay 2 needs to further include a drive circuit for driving the semiconductor switches 23 and 24.
  • FIG. 10 shows the operation of the switch device 1B of the present embodiment when the power source A1 is a DC power source.
  • the operation is the same as that when the power source A1 is an AC power source, and the description thereof is omitted here.
  • the “power supply voltage” shown in FIGS. 9 and 10 is the output voltage of the power supply A1.
  • the “control signal” shown in FIGS. 9 and 10 is a generic term for the first control signal and the second control signal.
  • the contact voltage becomes a voltage corresponding to the voltage drop due to the on-resistance between the drain and source of the semiconductor switches 23 and 24.
  • the inrush current that can be generated when the contact portion 32 is turned on can be reduced as compared with the case where the power supply path is closed only by the mechanical relay 3 without using the semiconductor relay 2. .
  • the contact resistance of the contact portion 32 is smaller than the on-resistance of the semiconductor switches 23 and 24, most of the current flowing from the power source A1 to the load B1 flows through the contact portion 32.
  • the power loss and heat generation at the on-resistance of the semiconductor switches 23 and 24 are small compared to the case where the power supply path is closed only by the semiconductor relay 2 without using the mechanical relay 3.
  • the energization current can be increased.
  • the switch device 1B of the present embodiment an arc is generated when the contact portion 32 is turned off, compared to the case where the semiconductor switches 23 and 24 of the semiconductor relay 2 are turned off before the contact portion 32 of the mechanical relay 3. hard. This is particularly effective when the power source A1 is a DC power source.
  • the switch device 1 ⁇ / b> B of the present embodiment has the semiconductor relay 2 semiconductor prior to the contact portion 32 of the mechanical relay 3 when an ON signal among the control signals is input to the pair of input terminals 101 and 102. It is desirable to control the switches 23 and 24 to be turned on. That is, it is desirable that the switch device 1B of the present embodiment can execute the priority on control. Therefore, the switch device 1B of the present embodiment utilizes the characteristic that the turn-on time of the semiconductor switches 23 and 24 of the semiconductor relay 2 is shorter than the operation time of the contact portion 32 of the mechanical relay 3. For this reason, in the switch device 1B of the present embodiment, the priority on control can be realized by one control signal without individually controlling the semiconductor relay 2 and the mechanical relay 3.
  • the switch device 1B of the present embodiment when the off signal among the control signals is input to the pair of input terminals 101 and 102, the contact portion 32 is provided before the semiconductor switches 23 and 24. It is desirable to be controlled to turn off. That is, it is desirable that the switch device 1B of the present embodiment can perform priority off control.
  • the turn-off time of the semiconductor switches 23 and 24 is shorter than the return time of the contact portion 32, the semiconductor switches 23 and 24 are turned off before the contact portion 32.
  • the switch device 1B of the present embodiment when an off signal is input from the control signal (first control signal), the gate capacitances of the semiconductor switches 23 and 24 are discharged through the second path S2 of the impedance circuit 26. To do. That is, by discharging the gate capacitances of the semiconductor switches 23 and 24 via the impedance element 261, the time constant is increased so that the turn-on time of the semiconductor switches 23 and 24 is longer than the return time of the contact portion 32. Yes. For this reason, in the switch apparatus 1B of this embodiment, priority off control is realizable by one control signal, without controlling the semiconductor relay 2 and the mechanical relay 3 separately.
  • the turn-on time of the semiconductor switches 23 and 24 may be longer than the operation time of the contact part 32. Therefore, in the switch device 1B of the present embodiment, when an ON signal is input from among the control signals (first control signals), the gate capacitances of the semiconductor switches 23 and 24 are set via the first path S1 of the impedance circuit 26. Charge. That is, when an ON signal is input from among the control signals, the gate capacitances of the semiconductor switches 23 and 24 are charged without going through the impedance element 261, so that the turn-on time of the semiconductor switches 23 and 24 is prevented from becoming long. be able to.
  • control circuit 4B controls the semiconductor switches 23 and 24, so that the contact point 32 of the mechanical relay 3 is turned off from the on time when the semiconductor switches 23 and 24 are turned off. It is configured to be delayed from the timing. In the present embodiment, the control circuit 4B controls the semiconductor switches 23 and 24, so that the contact point 32 of the mechanical relay 3 is turned on from the off time when the semiconductor switches 23 and 24 are turned on. It is configured to be earlier than the timing.
  • the switch device 1B of the present embodiment has the gate capacitances of the semiconductor switches 23 and 24 via the second path S2 of the impedance circuit 26 when an ON signal is input from among the control signals (first control signals). It may be configured to charge.
  • the control circuit 4B controls the semiconductor switches 23 and 24 so that the timing at which the semiconductor switches 23 and 24 are turned on is set to be higher than the timing at which the contact portion 32 of the mechanical relay 3 is turned on from off. It will be delayed.
  • the switch device 1B of the present embodiment includes the control circuit 4B having the charge / discharge path 25 and the impedance circuit 26.
  • the priority on control and the priority off control are realized by one control signal without individually controlling the semiconductor relay 2 and the mechanical relay 3. Can do.
  • the semiconductor relay 2 may be individually controlled with the first control signal and the mechanical relay 3 may be individually controlled with the second control signal. That is, the switch device 1B of the present embodiment can increase the degree of freedom of control.
  • the semiconductor relay 2 and the mechanical relay 3 are controlled by one control signal.
  • the first control signal and the second control signal are the same.
  • this configuration there is an advantage that complicated control such as shifting the timing of controlling each of the semiconductor relay 2 and the mechanical relay 3 is unnecessary, and control becomes easy. That is, in this configuration, a hybrid relay in which the semiconductor relay 2 and the mechanical relay 3 are combined can be easily controlled with one control signal. Note that whether or not to adopt the configuration is arbitrary.
  • the semiconductor relay 2 includes a light emitting element 21 and a light receiving element 22.
  • the semiconductor switches 23 and 24 are configured to be turned on / off by the photovoltaic force generated by the light receiving element 22.
  • the switch device 1 ⁇ / b> B of this embodiment has an advantage that the potential difference between the input and output hardly affects the on / off of the semiconductor switches 23 and 24. Note that whether or not to adopt the configuration for the semiconductor relay 2 is arbitrary.
  • the impedance circuit 26 is not limited to the configuration shown in FIG. 8, and may have other configurations.
  • the impedance circuit 26 may include a resistor R1 (impedance element 261) and a switching element Q1 (switch 262).
  • the resistor R1 is electrically connected between one end on the low potential side of the light receiving element 22 and the sources of the semiconductor switches 23 and 24, similarly to the configuration shown in FIG.
  • the switching element Q1 is an n-channel enhancement type MOSFET.
  • the gate of the switching element Q1 is electrically connected to one end of the light receiving element 22 on the high potential side.
  • the drain of the switching element Q1 is electrically connected to the sources of the semiconductor switches 23 and 24.
  • the source of the switching element Q1 is electrically connected to one end of the light receiving element 22 on the low potential side.
  • the impedance circuit 26 may include a resistor R1 (impedance element 261), a capacitor C1 (impedance element 261), and a diode D1 (switch 262).
  • the resistor R1 and the diode D1 are the same as those shown in FIG.
  • Capacitor C1 is electrically connected in parallel with resistor R1.
  • the impedance element 261 may include a capacitive element (here, the capacitor C1).
  • the turn-off time of the semiconductor switches 23 and 24 can be more effectively increased as compared with the case where the impedance element 261 is configured only by a resistor.
  • the impedance element 261 is configured by the resistor R1 and the capacitor C1, but may be configured by only the capacitor C1.
  • the switch device 1B of the present embodiment has a configuration in which the semiconductor switches 23 and 24 (contact point portion 32) are turned on when the first control signal (second control signal) is at a high level, but the other configuration. May be. That is, the switch device 1B of the present embodiment may be configured such that the semiconductor switches 23 and 24 (contact points 32) are turned on when the first control signal (second control signal) is at a low level.
  • the ON signal is input from among the first control signals (second control signals)” means “the first control signal (second control signal) is at a low level”.
  • the off signal of the first control signal (second control signal) is input” means “the first control signal (second control signal) becomes high level”.
  • the switch device 1B of the present embodiment may further include the control circuit 4 of the first embodiment and the control circuit 4A of a modification of the first embodiment. Also in this case, it is possible to realize the priority on control and the priority off control with one control signal without individually controlling the semiconductor relay 2 and the mechanical relay 3.
  • the switch device (1, 1A, 1B) includes a semiconductor relay (2), a mechanical relay (3), a control circuit (4, 4). 4A, 4B).
  • the semiconductor relay (2) opens and closes a power feeding path from the power source (A1) to the load (B1).
  • the mechanical relay (3) has a contact portion (32) electrically connected in parallel with the semiconductor relay (2), and turns on / off the contact portion (32) according to a control signal input from the outside. This opens and closes the feed path.
  • the control circuit (4, 4A, 4B) receives the control signal and controls the semiconductor relay (2).
  • the semiconductor relay (2) has semiconductor switches (2B, 23, 24).
  • the semiconductor switches (2B, 23, 24) open / close the power supply path by turning on / off according to the electric charge accumulated in the capacitive component.
  • the control circuit (4, 4A, 4B) controls the semiconductor switch (2B, 23, 24) so that the timing at which the semiconductor switch (2B, 23, 24) is turned off is turned on.
  • the contact portion (32) is configured to be delayed from the timing when the contact portion (32) is turned off.
  • the control circuit (4A, 4B) controls the semiconductor switch (2B, 23, 24),
  • the timing at which the semiconductor switch (2B, 23, 24) is turned on from off is configured to be earlier than the timing at which the contact portion (32) of the mechanical relay (3) is turned on from off.
  • the control circuit (4) controls the semiconductor switch (2B) so that the semiconductor switch (2B) is turned off.
  • the timing of turning on is configured to be delayed from the timing of turning on the contact portion (32) of the mechanical relay (3).
  • the semiconductor relay (2) has a primary side and a secondary side. It further has an insulating part (2A, 2C, 21, 22) for electrical insulation.
  • control circuit (4, 4A) is provided on the primary side to delay the control signal, A delay circuit (5, 5A) for outputting the control signal to the semiconductor relay (2).
  • the control circuit (4, 4A) receives a control signal via the delay circuit (5, 5A). And a buffer circuit (6) configured to output the control signal when the voltage of the control signal reaches the threshold voltage.
  • the switch device (1B) according to the seventh aspect of the present invention further includes a charge / discharge path (25) for charging and discharging the capacitive component according to the control signal in any of the fourth to sixth aspects.
  • the control circuit (4B) includes an impedance circuit (26) provided on the secondary side and electrically connected to the charge / discharge path (25).
  • the impedance circuit (26) has an impedance element (261).
  • the impedance circuit (26) connects the charge / discharge path (25) to the first path (S1) when an ON signal is input from among the control signals, and charges / discharges when an OFF signal is input from among the control signals.
  • the path (25) is configured to be connected to the second path (S2) including the impedance element (261).
  • the impedance element (261) includes a capacitive element (capacitor (C1)).
  • the insulating portion (21, 22) receives the control signal and emits light (21), A light receiving element (22) that generates a photovoltaic force in response to light emitted from the light emitting element (21).
  • the switch device (1, 1A, 1B) includes the control circuit (4, 4A, 4B), the semiconductor relay (2) and the mechanical relay (3) can be provided with a semiconductor relay ( 2) A time difference between opening and closing of the mechanical relay (3) can be provided. Therefore, the present invention can easily control a hybrid relay in which the semiconductor relay (2) and the mechanical relay (3) are combined with one control signal.

Abstract

The present invention addresses the problem of easily controlling, by means of one control signal, a hybrid relay wherein a semiconductor relay and a mechanical relay are combined. A switch device (1) is provided with a semiconductor relay (2), a mechanical relay (3), and a control circuit (4). The semiconductor relay (2) opens/closes a power supply path. The mechanical relay (3) has a contact section (32) to be electrically connected in parallel to the semiconductor relay (2), and opens/closes the power supply path by turning on/off the contact section (32) corresponding to a control signal. The semiconductor relay (2) has a semiconductor switch (2B). The control circuit (4) is configured such that, by controlling the semiconductor switch (2B) by receiving the control signal, a timing at which the semiconductor switch (2B) is turned off from being turned on is delayed from the timing at which the contact section (32) of the mechanical relay (3) is turned off from being tuned on.

Description

スイッチ装置Switch device
　本発明は、一般にスイッチ装置に関し、より詳細には、メカニカルリレーと半導体リレーとを有するスイッチ装置に関する。 The present invention generally relates to a switch device, and more particularly to a switch device having a mechanical relay and a semiconductor relay.
　従来、直流電流が流れる直流電流路を開路または閉路とする直流スイッチが知られており、たとえば文献１（日本国特許出願公開番号２０１２－２８１９３）に開示されている。この直流スイッチは、直流電流路に挿入される電子的開閉スイッチと、電子的開閉スイッチに対して並列に接続される機械的開閉スイッチとを備える。また、この直流スイッチは、機械的開閉スイッチと電子的開閉スイッチとの相互の開閉の時間差を制御するスイッチ制御回路とを備える。 Conventionally, a DC switch that opens or closes a DC current path through which a DC current flows is known, and is disclosed in, for example, Document 1 (Japanese Patent Application Publication No. 2012-28193). The direct current switch includes an electronic on / off switch inserted into a direct current path and a mechanical on / off switch connected in parallel to the electronic on / off switch. The direct current switch includes a switch control circuit that controls a time difference between opening and closing of the mechanical opening / closing switch and the electronic opening / closing switch.
　そして、スイッチ制御回路は、電子的開閉スイッチが閉路とされた所定時間後に、機械的開閉スイッチを閉路とする制御を行う。これにより、この直流スイッチは、直流電流路を導通とする場合における電子的開閉スイッチの電力損失を小さくしている。 The switch control circuit performs control to close the mechanical on / off switch after a predetermined time after the electronic on / off switch is closed. As a result, this DC switch reduces the power loss of the electronic switch when the DC current path is made conductive.
　しかしながら、上記従来例では、電子的開閉スイッチ（半導体リレー）と機械的開閉スイッチ（メカニカルリレー）との相互の開閉の時間差を設けるためには、電子的開閉スイッチと機械的開閉スイッチとに個別に制御信号を与えて制御する必要があった。このため、従来例は、半導体リレー及びメカニカルリレーを組み合わせたハイブリッドリレーを１つの制御信号で制御することが困難であるという問題があった。 However, in the above conventional example, in order to provide a time difference between the opening / closing of the electronic opening / closing switch (semiconductor relay) and the mechanical opening / closing switch (mechanical relay), the electronic opening / closing switch and the mechanical opening / closing switch are individually provided. It was necessary to control by giving a control signal. For this reason, the conventional example has a problem that it is difficult to control a hybrid relay combining a semiconductor relay and a mechanical relay with one control signal.
　本発明は、上記の点に鑑みてなされており、半導体リレー及びメカニカルリレーを組み合わせたハイブリッドリレーを、１つの制御信号で容易に制御することを目的とする。 The present invention has been made in view of the above points, and an object thereof is to easily control a hybrid relay combining a semiconductor relay and a mechanical relay with one control signal.
　本発明の一態様に係るスイッチ装置は、半導体リレーと、メカニカルリレーと、制御回路とを備える。前記半導体リレーは、電源から負荷への給電路を開閉する。前記メカニカルリレーは、前記半導体リレーと並列に電気的に接続される接点部を有し、外部から入力される制御信号に応じて前記接点部をオン／オフすることにより前記給電路を開閉する。前記制御回路は、前記制御信号を受けて前記半導体リレーを制御する。前記半導体リレーは、半導体スイッチを有する。前記半導体スイッチは、容量成分に蓄積される電荷に応じてオン／オフすることで前記給電路を開閉する。前記制御回路は、前記半導体スイッチを制御することで、前記半導体スイッチがオンからオフになるタイミングを、前記メカニカルリレーの前記接点部がオンからオフになるタイミングよりも遅らせるように構成されている。 The switch device according to one embodiment of the present invention includes a semiconductor relay, a mechanical relay, and a control circuit. The semiconductor relay opens and closes a power feeding path from a power source to a load. The mechanical relay has a contact portion electrically connected in parallel with the semiconductor relay, and opens and closes the power feeding path by turning on and off the contact portion in accordance with a control signal input from the outside. The control circuit receives the control signal and controls the semiconductor relay. The semiconductor relay has a semiconductor switch. The semiconductor switch opens and closes the power supply path by turning on / off according to the charge accumulated in the capacitive component. The control circuit is configured to control the semiconductor switch so that the timing at which the semiconductor switch is turned off is delayed from the timing at which the contact portion of the mechanical relay is turned on from off.
本発明の実施形態１に係るスイッチ装置を示す概略図である。It is the schematic which shows the switch apparatus which concerns on Embodiment 1 of this invention. 同上のスイッチ装置を用いた回路の概略図である。It is the schematic of the circuit using a switch apparatus same as the above. 同上のスイッチ装置の動作説明図である。It is operation | movement explanatory drawing of a switch apparatus same as the above. 本発明の実施形態１の変形例に係るスイッチ装置を示す概略図である。It is the schematic which shows the switch apparatus which concerns on the modification of Embodiment 1 of this invention. 同上のスイッチ装置の動作説明図である。It is operation | movement explanatory drawing of a switch apparatus same as the above. 本発明の実施形態２に係るスイッチ装置を示す概略図である。It is the schematic which shows the switch apparatus which concerns on Embodiment 2 of this invention. 同上のスイッチ装置における充放電経路の一例を示す図である。It is a figure which shows an example of the charging / discharging path | route in a switch apparatus same as the above. 同上のスイッチ装置におけるインピーダンス回路の一例を示す図である。It is a figure which shows an example of the impedance circuit in a switch apparatus same as the above. 電源が交流電源である場合における、同上のスイッチ装置の動作説明図である。It is operation | movement explanatory drawing of a switch apparatus same as the above when a power supply is an alternating current power supply. 電源が直流電源である場合における、同上のスイッチ装置の動作説明図である。It is operation | movement explanatory drawing of a switch apparatus same as the above when a power supply is a DC power supply. 同上のスイッチ装置におけるインピーダンス回路の一例を示す図である。It is a figure which shows an example of the impedance circuit in a switch apparatus same as the above. 同上のスイッチ装置におけるインピーダンス回路の他の一例を示す図である。It is a figure which shows another example of the impedance circuit in a switch apparatus same as the above.
　以下、本発明の実施形態１、実施形態１の変形例、及び実施形態２に係るスイッチ装置について詳細に説明する。ただし、以下に説明する構成は、本発明の一例に過ぎず、本発明は下記の構成に限定されることはなく、これらの構成以外であっても、本発明に係る技術的思想を逸脱しない範囲であれば、設計等に応じて種々の変更が可能である。 Hereinafter, the switch device according to Embodiment 1, Embodiment 1 of the present invention, and Embodiment 2 of the present invention will be described in detail. However, the configuration described below is merely an example of the present invention, and the present invention is not limited to the following configuration, and the technical idea according to the present invention does not depart from the configurations other than these configurations. Within the range, various changes can be made according to the design and the like.
　（実施形態１）
　本発明の実施形態１に係るスイッチ装置１は、図１、図２に示すように、半導体リレー２と、メカニカルリレー３と、制御回路４とを備えている。半導体リレー２は、電源Ａ１から負荷Ｂ１への給電路を開閉する。メカニカルリレー３は、半導体リレー２と並列に電気的に接続される接点部３２を有し、外部から入力される制御信号に応じて接点部３２をオン／オフすることにより給電路を開閉する。制御回路４は、制御信号を受けて半導体リレー２を制御する。 (Embodiment 1)
As shown in FIGS. 1 and 2, the switch device 1 according to Embodiment 1 of the present invention includes a semiconductor relay 2, a mechanical relay 3, and a control circuit 4. The semiconductor relay 2 opens and closes a power feeding path from the power source A1 to the load B1. The mechanical relay 3 includes a contact portion 32 that is electrically connected in parallel with the semiconductor relay 2, and opens and closes the power supply path by turning the contact portion 32 on and off according to a control signal input from the outside. The control circuit 4 receives the control signal and controls the semiconductor relay 2.
　半導体リレー２は、半導体スイッチ２Ｂを有している。半導体スイッチ２Ｂは、容量成分（キャパシタ４２）に蓄積される電荷に応じてオン／オフすることで給電路を開閉する。制御回路４は、半導体スイッチ２Ｂを制御することで、半導体スイッチ２Ｂがオンからオフになるタイミングを、メカニカルリレー３の接点部３２がオンからオフになるタイミングよりも遅らせるように構成されている。 The semiconductor relay 2 has a semiconductor switch 2B. The semiconductor switch 2B opens and closes the power feeding path by turning on / off according to the electric charge accumulated in the capacitance component (capacitor 42). The control circuit 4 is configured to control the semiconductor switch 2B so that the timing at which the semiconductor switch 2B is turned off is delayed from the timing at which the contact portion 32 of the mechanical relay 3 is turned off.
　＜構成＞
　以下、本実施形態のスイッチ装置１について詳細に説明する。以下の説明では、「制御信号のうちオン信号が入力される」とは「制御信号がハイレベルになる」ことを意味する。また、「制御信号のうちオフ信号が入力される」とは「制御信号がローレベルになる」ことを意味する。 <Configuration>
Hereinafter, the switch device 1 of the present embodiment will be described in detail. In the following description, “the ON signal among the control signals is input” means “the control signal becomes high level”. Further, “an OFF signal is input from among the control signals” means “the control signal becomes low level”.
　本実施形態のスイッチ装置１は、図１に示すように、一対の入力端子１０１，１０２（第１入力端子１０１、第２入力端子１０２）と、一対の出力端子１１１，１１２（第１出力端子１１１、第２出力端子１１２）とを備えている。一対の入力端子１０１，１０２には、制御回路４を介して、半導体リレー２の一対の入力端２０１，２０２（第１入力端２０１、第２入力端２０２）が電気的に接続されている。また、一対の入力端子１０１，１０２には、メカニカルリレー３の一対の入力端３０１，３０２（第１入力端３０１、第２入力端３０２）が電気的に接続されている。また、一対の出力端子１１１，１１２には、半導体リレー２の一対の出力端２１１，２１２（第１出力端２１１、第２出力端２１２）と、メカニカルリレー３の一対の出力端３１１，３１２（第１出力端３１１、第２出力端３１２）とが電気的に接続されている。つまり、メカニカルリレー３は、半導体リレー２に並列に電気的に接続されている。 As shown in FIG. 1, the switch device 1 according to the present embodiment includes a pair of input terminals 101 and 102 (first input terminal 101 and second input terminal 102) and a pair of output terminals 111 and 112 (first output terminal). 111 and a second output terminal 112). A pair of input terminals 201 and 202 (first input terminal 201 and second input terminal 202) of the semiconductor relay 2 are electrically connected to the pair of input terminals 101 and 102 via the control circuit 4. A pair of input terminals 301 and 302 (first input terminal 301 and second input terminal 302) of the mechanical relay 3 are electrically connected to the pair of input terminals 101 and 102. The pair of output terminals 111 and 112 include a pair of output terminals 211 and 212 (first output terminal 211 and second output terminal 212) of the semiconductor relay 2 and a pair of output terminals 311 and 312 (mechanical relay 3). The first output terminal 311 and the second output terminal 312) are electrically connected. That is, the mechanical relay 3 is electrically connected to the semiconductor relay 2 in parallel.
　本実施形態のスイッチ装置１は、半導体リレー２及びメカニカルリレー３の少なくともいずれか一方がオンすることでオンになる。また、本実施形態のスイッチ装置１は、半導体リレー２及びメカニカルリレー３の両方がオフすることでオフになる。 The switch device 1 of this embodiment is turned on when at least one of the semiconductor relay 2 and the mechanical relay 3 is turned on. Moreover, the switch apparatus 1 of this embodiment is turned off when both the semiconductor relay 2 and the mechanical relay 3 are turned off.
　一対の入力端子１０１，１０２には、たとえばマイコン（マイクロコンピュータ）から制御信号が入力される。また、一対の入力端子１０１，１０２間には、過大な電圧が入力されないように、ツェナーダイオードＺＤ１が電気的に接続されている。 A control signal is input to the pair of input terminals 101 and 102 from, for example, a microcomputer. A Zener diode ZD1 is electrically connected between the pair of input terminals 101 and 102 so that an excessive voltage is not input.
　一対の出力端子１１１，１１２には、図２に示すように、電源Ａ１及び負荷Ｂ１が電気的に接続されている。したがって、一対の出力端子１１１，１１２間が非導通（スイッチ装置１がオフ）であれば、電源Ａ１から負荷Ｂ１には電力が供給されない。また、一対の出力端子１１１，１１２間が導通（スイッチ装置１がオン）すると、電源Ａ１から負荷Ｂ１に電力が供給される。つまり、本実施形態のスイッチ装置１は、電源Ａ１から負荷Ｂ１への給電路を開閉する。なお、本実施形態のスイッチ装置１では、電源Ａ１として直流電源を用いているが、交流電源を用いてもよい。 As shown in FIG. 2, a power source A1 and a load B1 are electrically connected to the pair of output terminals 111 and 112. Therefore, if the pair of output terminals 111 and 112 are non-conductive (switch device 1 is off), power is not supplied from the power source A1 to the load B1. Further, when the pair of output terminals 111 and 112 are electrically connected (the switch device 1 is turned on), power is supplied from the power source A1 to the load B1. That is, the switch device 1 of the present embodiment opens and closes the power feeding path from the power source A1 to the load B1. In the switch device 1 of the present embodiment, a DC power source is used as the power source A1, but an AC power source may be used.
　負荷Ｂ１は、たとえば電気自動車（Electric Vehicle：EV）である。その他、負荷Ｂ１は、たとえばセキュリティ機器、アミューズメント機器、医療機器や蓄電池システム、ヒータ、ＤＣモータなどであってもよい。負荷Ｂ１は、電源Ａ１が交流電源であれば、交流電力を供給されることにより動作する負荷で構成される。また、負荷Ｂ１は、電源Ａ１が直流電源であれば、直流電力を供給されることにより動作する負荷で構成される。また、負荷Ｂ１は、抵抗負荷であってもよいし、誘導性負荷であってもよい。本実施形態では、負荷Ｂ１は、たとえば開閉器の有するコイルであり、誘導性負荷である。 The load B1 is, for example, an electric vehicle (Electric Vehicle: EV). In addition, the load B1 may be, for example, a security device, an amusement device, a medical device, a storage battery system, a heater, a DC motor, or the like. If the power source A1 is an AC power source, the load B1 is configured by a load that operates by being supplied with AC power. Further, if the power source A1 is a DC power source, the load B1 is configured by a load that operates by being supplied with DC power. Further, the load B1 may be a resistance load or an inductive load. In this embodiment, load B1 is a coil which a switch has, for example, and is an inductive load.
　半導体リレー２は、いわゆる無接点リレーであり、発光素子２Ａと、半導体スイッチ２Ｂと、受光素子２Ｃとを備えている。発光素子２Ａと、半導体スイッチ２Ｂとは、互いに電気的に絶縁されている。つまり、本実施形態のスイッチ装置１では、半導体リレー２は、発光素子２Ａ及び受光素子２Ｃを用いることで、一対の入力端２０１，２０２と一対の出力端２１１，２１２との間を電気的に絶縁している。言い換えれば、半導体リレー２は、１次側（一対の入力端子１０１，１０２側）と２次側（一対の出力端子１１１，１１２側）とを電気的に絶縁する絶縁部２Ａ，２Ｃを備えているといえる。 The semiconductor relay 2 is a so-called non-contact relay and includes a light emitting element 2A, a semiconductor switch 2B, and a light receiving element 2C. The light emitting element 2A and the semiconductor switch 2B are electrically insulated from each other. That is, in the switch device 1 of this embodiment, the semiconductor relay 2 uses the light emitting element 2A and the light receiving element 2C to electrically connect the pair of input ends 201 and 202 and the pair of output ends 211 and 212. Insulated. In other words, the semiconductor relay 2 includes insulating portions 2A and 2C that electrically insulate the primary side (the pair of input terminals 101 and 102 side) from the secondary side (the pair of output terminals 111 and 112 side). It can be said that.
　この絶縁部２Ａ，２Ｃは、他の構成であってもよい。たとえば、半導体リレー２は、発光素子２Ａ及び受光素子２Ｃの代わりにキャパシタを用いることで、一対の入力端２０１，２０２と一対の出力端２１１，２１２との間を電気的に絶縁する構成であってもよい。なお、キャパシタを用いる場合、半導体リレー２は、半導体スイッチ２Ｂを駆動するためのドライブ回路をさらに備える必要がある。 The insulating portions 2A and 2C may have other configurations. For example, the semiconductor relay 2 is configured to electrically insulate between the pair of input ends 201 and 202 and the pair of output ends 211 and 212 by using a capacitor instead of the light emitting element 2A and the light receiving element 2C. May be. When using a capacitor, the semiconductor relay 2 needs to further include a drive circuit for driving the semiconductor switch 2B.
　発光素子２Ａは、一対の入力端２０１，２０２に入力される電気信号を光に変換するように構成されている。本実施形態では、発光素子２Ａは、発光ダイオードである。発光ダイオードは、アノードが第１入力端２０１に、カソードが第２入力端２０２に電気的に接続されている。発光素子２Ａは、一対の入力端２０１，２０２に入力される制御信号のうちオン信号を受けて発光する。また、発光素子２Ａは、制御信号のうちオフ信号を受けている間は発光しない。なお、発光素子２Ａを構成する発光ダイオードの数は１つに限定されず、複数であってもよい。 The light emitting element 2A is configured to convert an electric signal input to the pair of input ends 201 and 202 into light. In the present embodiment, the light emitting element 2A is a light emitting diode. The light emitting diode has an anode electrically connected to the first input end 201 and a cathode electrically connected to the second input end 202. The light emitting element 2 </ b> A emits light upon receiving an ON signal among control signals input to the pair of input terminals 201 and 202. Further, the light emitting element 2A does not emit light while receiving an off signal among the control signals. Note that the number of light emitting diodes constituting the light emitting element 2A is not limited to one, and may be plural.
　ここで、メカニカルリレー３を駆動するための制御信号のうちオン信号を半導体リレー２にそのまま入力すると、過大な電流が発光素子２Ａに流れてしまう虞がある。そこで、本実施形態のスイッチ装置１では、電流調整用の抵抗１１が発光素子２Ａに直列に電気的に接続されている。この抵抗１１により、発光素子２Ａに過大な電流が流れるのを防止している。 Here, if an ON signal among the control signals for driving the mechanical relay 3 is input to the semiconductor relay 2 as it is, an excessive current may flow to the light emitting element 2A. Therefore, in the switch device 1 of the present embodiment, the current adjusting resistor 11 is electrically connected in series to the light emitting element 2A. This resistor 11 prevents an excessive current from flowing through the light emitting element 2A.
　受光素子２Ｃは、発光素子２Ａが発する光を受けて光起電力を発生するように構成されている。本実施形態では、受光素子２Ｃは、複数のフォトダイオードを直列に電気的に接続してなるフォトダイオードアレイで構成されている。 The light receiving element 2C is configured to receive a light emitted from the light emitting element 2A and generate a photovoltaic power. In the present embodiment, the light receiving element 2C is configured by a photodiode array formed by electrically connecting a plurality of photodiodes in series.
　半導体スイッチ２Ｂは、ｎチャネルのエンハンスメント型ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）である。半導体スイッチ２Ｂのゲートは、受光素子２Ｃの高電位側の一端に電気的に接続されている。また、半導体スイッチ２Ｂのドレインは、第１出力端子１１１に電気的に接続されている。また、半導体スイッチ２Ｂのソースは、受光素子２Ｃの低電位側の一端及び第２出力端子１１２に電気的に接続されている。半導体スイッチ２Ｂは、ゲート容量に蓄積される電荷に応じてオン／オフするように構成される。なお、「ゲート容量」とは、半導体スイッチ２Ｂのゲート－ソース間に存在するキャパシタ（一般的に、「ゲート入力容量」という）、及びゲート－ドレイン間に存在するキャパシタ（一般的に、「ゲート出力容量」という）である。 The semiconductor switch 2B is an n-channel enhancement type MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor). The gate of the semiconductor switch 2B is electrically connected to one end on the high potential side of the light receiving element 2C. The drain of the semiconductor switch 2B is electrically connected to the first output terminal 111. The source of the semiconductor switch 2B is electrically connected to one end on the low potential side of the light receiving element 2C and the second output terminal 112. The semiconductor switch 2B is configured to be turned on / off according to the charge accumulated in the gate capacitance. The “gate capacitance” means a capacitor (generally referred to as “gate input capacitance”) existing between the gate and source of the semiconductor switch 2B and a capacitor (generally referred to as “gate capacitance”) between the gate and drain. Output capacity).
　なお、本実施形態では、半導体スイッチ２Ｂは１つであるが、２つであってもよい。つまり、電源Ａ１が交流電源である場合、スイッチ装置１は、２つの半導体スイッチ２Ｂを必要とする。また、本実施形態では、半導体スイッチ２Ｂはエンハンスメント型ＭＯＳＦＥＴであるが、たとえばＩＧＢＴ（Insulated Gate Bipolar Transistor）等の半導体素子であってもよい。 In the present embodiment, there is one semiconductor switch 2B, but two semiconductor switches may be used. That is, when the power source A1 is an AC power source, the switch device 1 requires two semiconductor switches 2B. In the present embodiment, the semiconductor switch 2B is an enhancement type MOSFET, but may be a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor).
　半導体リレー２は、半導体スイッチ２Ｂのゲート容量を充電及び放電するための充放電経路として、半導体素子２Ｄと、抵抗２Ｅとをさらに備えている。半導体素子２Ｄは、ｎチャネルのデプレッション型ＭＯＳＦＥＴである。半導体素子２Ｄのドレインは、受光素子２Ｃの高電位側の一端に電気的に接続されている。半導体素子２Ｄのゲートは、受光素子２Ｃの低電位側の一端に電気的に接続されている。また、半導体素子２Ｄのソースは、抵抗２Ｅを介して受光素子２Ｃの低電位側の一端に電気的に接続されている。言い換えれば、抵抗２Ｅは、半導体素子２Ｄのゲート－ソース間に電気的に接続されている。 The semiconductor relay 2 further includes a semiconductor element 2D and a resistor 2E as a charge / discharge path for charging and discharging the gate capacitance of the semiconductor switch 2B. The semiconductor element 2D is an n-channel depletion type MOSFET. The drain of the semiconductor element 2D is electrically connected to one end on the high potential side of the light receiving element 2C. The gate of the semiconductor element 2D is electrically connected to one end on the low potential side of the light receiving element 2C. The source of the semiconductor element 2D is electrically connected to one end on the low potential side of the light receiving element 2C via the resistor 2E. In other words, the resistor 2E is electrically connected between the gate and source of the semiconductor element 2D.
　スイッチ装置１は、制御回路４と、バリスタ（Varistor）ＶＲ１とをさらに備えている。バリスタＶＲ１は、一対の出力端２１１，２１２間に電気的に接続されている。バリスタＶＲ１は、スイッチ装置１がオフするときに一対の出力端２１１，２１２間に印加される過大な逆起電力から半導体スイッチ２Ｂを保護している。なお、バリスタＶＲ１は、負荷Ｂ１が抵抗負荷である場合、不要である。 The switch device 1 further includes a control circuit 4 and a varistor VR1. The varistor VR1 is electrically connected between the pair of output ends 211 and 212. The varistor VR1 protects the semiconductor switch 2B from an excessive back electromotive force applied between the pair of output terminals 211 and 212 when the switch device 1 is turned off. The varistor VR1 is not necessary when the load B1 is a resistance load.
　制御回路４は、遅延回路５と、バッファ回路６とを有している。遅延回路５は、抵抗４１と、キャパシタ４２とを備えている。抵抗４１は、第１入力端子１０１とバッファ回路６の入力端との間に電気的に接続されている。キャパシタ４２は、抵抗４１及びバッファ回路６の入力端の接続点と、第２入力端子１０２との間に電気的に接続されている。遅延回路５は、一対の入力端子１０１，１０２に入力される制御信号を遅延させ、遅延した制御信号を半導体リレー２の一対の入力端２０１，２０２に入力するように構成されている。このため、本実施形態のスイッチ装置１では、制御信号が半導体リレー２に入力されるタイミングを、制御信号がメカニカルリレー３に入力されるタイミングよりも遅らせることができる。 The control circuit 4 has a delay circuit 5 and a buffer circuit 6. The delay circuit 5 includes a resistor 41 and a capacitor 42. The resistor 41 is electrically connected between the first input terminal 101 and the input terminal of the buffer circuit 6. The capacitor 42 is electrically connected between the connection point between the resistor 41 and the input end of the buffer circuit 6 and the second input terminal 102. The delay circuit 5 is configured to delay a control signal input to the pair of input terminals 101 and 102 and input the delayed control signal to the pair of input terminals 201 and 202 of the semiconductor relay 2. For this reason, in the switch apparatus 1 of this embodiment, the timing at which the control signal is input to the semiconductor relay 2 can be delayed from the timing at which the control signal is input to the mechanical relay 3.
　バッファ回路６は、遅延回路５の高圧側の出力端と、半導体リレー２の第１入力端２０１との間に電気的に接続されている。バッファ回路６には、遅延回路５により遅延した制御信号が入力される。そして、バッファ回路６は、入力された制御信号の電圧が閾値電圧に達するまでは制御信号を出力せず、閾値電圧に達すると制御信号を出力する。たとえば、制御信号のうちオン信号がバッファ回路６に入力される場合、オン信号の電圧が閾値電圧を上回ると、バッファ回路６がオン信号を出力する。また、制御信号のうちオフ信号がバッファ回路６に入力される場合、オフ信号の電圧が閾値電圧を下回ると、バッファ回路６がオフ信号を出力する。 The buffer circuit 6 is electrically connected between the output terminal on the high voltage side of the delay circuit 5 and the first input terminal 201 of the semiconductor relay 2. A control signal delayed by the delay circuit 5 is input to the buffer circuit 6. The buffer circuit 6 does not output the control signal until the voltage of the input control signal reaches the threshold voltage, and outputs the control signal when the threshold voltage is reached. For example, when an ON signal among the control signals is input to the buffer circuit 6, the buffer circuit 6 outputs an ON signal when the voltage of the ON signal exceeds the threshold voltage. In addition, when an off signal among the control signals is input to the buffer circuit 6, the buffer circuit 6 outputs an off signal when the voltage of the off signal falls below the threshold voltage.
　つまり、バッファ回路６は、遅延回路５を介して制御信号が入力され、制御信号の電圧が閾値電圧に達すると制御信号を出力するように構成されている。したがって、バッファ回路６は、遅延回路５の時定数に応じて緩やかに電圧が変化する制御信号を、矩形波状の制御信号に変換し、変換した制御信号を発光素子２Ａへ出力する。このため、本実施形態のスイッチ装置１では、半導体リレー２に時間経過に伴って緩やかに電圧が変化する制御信号が入力されないので、半導体スイッチ２Ｂが能動領域で動作する時間を短くすることができる。その結果、本実施形態のスイッチ装置１では、半導体スイッチ２Ｂの動作の安定性を向上させることができる。 That is, the buffer circuit 6 is configured to receive a control signal via the delay circuit 5 and output the control signal when the voltage of the control signal reaches the threshold voltage. Therefore, the buffer circuit 6 converts the control signal whose voltage gradually changes according to the time constant of the delay circuit 5 into a rectangular wave control signal, and outputs the converted control signal to the light emitting element 2A. For this reason, in the switch device 1 of the present embodiment, since the control signal whose voltage gradually changes with the passage of time is not input to the semiconductor relay 2, the time for which the semiconductor switch 2B operates in the active region can be shortened. . As a result, in the switch device 1 of the present embodiment, the stability of the operation of the semiconductor switch 2B can be improved.
　以下、半導体リレー２の動作について説明する。一対の入力端子１０１，１０２に制御信号のうちオン信号が入力されると、遅延回路５のキャパシタ４２に電荷が蓄積され始める。このため、遅延回路５を介した制御信号の電圧は、ローレベルからハイレベルへと時間経過に伴って緩やかに上昇する。そして、キャパシタ４２に電荷が十分に蓄積され、遅延回路５を介したオン信号の電圧がバッファ回路６の閾値電圧に達すると、バッファ回路６がオン信号を出力することにより、発光素子２Ａが発光する。 Hereinafter, the operation of the semiconductor relay 2 will be described. When an ON signal among the control signals is input to the pair of input terminals 101 and 102, charge starts to be accumulated in the capacitor 42 of the delay circuit 5. For this reason, the voltage of the control signal via the delay circuit 5 gradually increases from the low level to the high level as time elapses. When the charge is sufficiently accumulated in the capacitor 42 and the voltage of the ON signal through the delay circuit 5 reaches the threshold voltage of the buffer circuit 6, the buffer circuit 6 outputs the ON signal, whereby the light emitting element 2A emits light. To do.
　すると、発光素子２Ａの発する光を受けて受光素子２Ｃが光起電力を発生する。そして、受光素子２Ｃから半導体素子２Ｄ及び抵抗２Ｅに電流が流れることで、抵抗２Ｅにおいて電圧降下が生じ、この電圧降下により半導体素子２Ｄがオフする。このため、受光素子２Ｃから半導体スイッチ２Ｂのゲートに電流が流れ込み、半導体スイッチ２Ｂのゲート容量が充電され、半導体スイッチ２Ｂがオンする。これにより、一対の出力端子１１１，１１２間が導通する。 Then, in response to the light emitted from the light emitting element 2A, the light receiving element 2C generates a photovoltaic power. Then, when a current flows from the light receiving element 2C to the semiconductor element 2D and the resistor 2E, a voltage drop occurs in the resistor 2E, and the semiconductor element 2D is turned off by this voltage drop. For this reason, a current flows from the light receiving element 2C to the gate of the semiconductor switch 2B, the gate capacitance of the semiconductor switch 2B is charged, and the semiconductor switch 2B is turned on. As a result, the pair of output terminals 111 and 112 are electrically connected.
　一対の入力端子１０１，１０２に制御信号のうちオフ信号が入力されると、遅延回路５のキャパシタ４２が放電し始める。このため、遅延回路５を介した制御信号の電圧は、ハイレベルからローレベルへと時間経過に伴って緩やかに下降する。そして、キャパシタ４２が十分に放電され、遅延回路５を介したオフ信号の電圧がバッファ回路６の閾値電圧に達すると、バッファ回路６がオフ信号を出力することにより、発光素子２Ａが発光しなくなる。 When an off signal of the control signals is input to the pair of input terminals 101 and 102, the capacitor 42 of the delay circuit 5 starts to discharge. For this reason, the voltage of the control signal via the delay circuit 5 gradually decreases from the high level to the low level as time elapses. When the capacitor 42 is sufficiently discharged and the voltage of the off signal through the delay circuit 5 reaches the threshold voltage of the buffer circuit 6, the buffer circuit 6 outputs the off signal, so that the light emitting element 2A does not emit light. .
　すると、受光素子２Ｃが光起電力を発生しなくなるため、抵抗２Ｅでの電圧降下が生じなくなり、半導体素子２Ｄがオンする。これにより、半導体スイッチ２Ｂのゲート容量が、半導体素子２Ｄを介した経路で放電されるため、半導体スイッチ２Ｂがオフする。これにより、一対の出力端子１１１，１１２間が非導通となる。 Then, since the light receiving element 2C does not generate photovoltaic power, a voltage drop at the resistor 2E does not occur, and the semiconductor element 2D is turned on. As a result, the gate capacitance of the semiconductor switch 2B is discharged through the path through the semiconductor element 2D, and the semiconductor switch 2B is turned off. As a result, the pair of output terminals 111 and 112 become non-conductive.
　つまり、半導体スイッチ２Ｂは、容量成分（キャパシタ４２）に蓄積される電荷に応じてオン／オフすることにより、電源Ａ１から負荷Ｂ１への給電路を開閉する。言い換えれば、半導体リレー２は、外部から入力される制御信号に応じて、電源Ａ１から負荷Ｂ１への給電路を開閉する。 That is, the semiconductor switch 2B opens and closes the power supply path from the power source A1 to the load B1 by turning on / off according to the charge accumulated in the capacitance component (capacitor 42). In other words, the semiconductor relay 2 opens and closes the power feeding path from the power source A1 to the load B1 in accordance with a control signal input from the outside.
　上述のように、半導体リレー２は、発光素子２Ａと、受光素子２Ｃとを備えている。そして、半導体スイッチ２Ｂは、受光素子２Ｃの発生する光起電力によりオン／オフするように構成されている。このため、本実施形態のスイッチ装置１では、入出力間の電位差が半導体スイッチ２Ｂのオン／オフに影響し難いという利点がある。なお、半導体リレー２に当該構成を採用するか否かは任意である。 As described above, the semiconductor relay 2 includes the light emitting element 2A and the light receiving element 2C. The semiconductor switch 2B is configured to be turned on / off by the photovoltaic force generated by the light receiving element 2C. For this reason, the switch device 1 according to the present embodiment has an advantage that the potential difference between the input and the output hardly affects the on / off of the semiconductor switch 2B. Note that whether or not to adopt the configuration for the semiconductor relay 2 is arbitrary.
　なお、半導体リレー２は、図１に示す回路構成に限定されない。たとえば、半導体リレー２においては、半導体スイッチ２Ｂは、発光素子２Ａの発する光の有無に応じてオン／オフするように構成されていればよい。 The semiconductor relay 2 is not limited to the circuit configuration shown in FIG. For example, in the semiconductor relay 2, the semiconductor switch 2B may be configured to be turned on / off according to the presence or absence of light emitted from the light emitting element 2A.
　メカニカルリレー３は、いわゆる有接点リレー（たとえば、電磁リレー）であり、コイル３１と、接点部３２とを備えている。コイル３１は、その第１端が第１入力端３０１に、第２端が第２入力端３０２に電気的に接続されている。コイル３１は、一対の入力端３０１，３０２に制御信号が入力されると励磁する。 The mechanical relay 3 is a so-called contact relay (for example, an electromagnetic relay), and includes a coil 31 and a contact portion 32. The coil 31 has a first end electrically connected to the first input end 301 and a second end electrically connected to the second input end 302. The coil 31 is excited when a control signal is input to the pair of input ends 301 and 302.
　接点部３２は、その第１端が第１出力端３１１に、第２端が第２出力端３１２に電気的に接続されている。接点部３２は、固定接点と、可動接点とを備えている。固定接点と可動接点との間は、コイル３１の励磁・非励磁に応じて開閉する。本実施形態では、接点部３２は、コイル３１が励磁されていないときは、可動接点が固定接点から離れているためにオフである。そして、接点部３２は、コイル３１が励磁されると、可動接点が固定接点に接触することにより、オンに切り替わるように構成されている。 The contact portion 32 has a first end electrically connected to the first output end 311 and a second end electrically connected to the second output end 312. The contact part 32 includes a fixed contact and a movable contact. The fixed contact and the movable contact are opened and closed according to the excitation / de-excitation of the coil 31. In this embodiment, when the coil 31 is not excited, the contact part 32 is off because the movable contact is away from the fixed contact. And the contact part 32 is comprised so that when the coil 31 is excited, a movable contact contacts a fixed contact, and it switches on.
　つまり、メカニカルリレー３は、一対の入力端３０１，３０２に入力される制御信号に応じて接点部３２のオン／オフを機械的に切り替えることで、一対の出力端子１１１，１１２間の導通・非導通を切り替える。言い換えれば、メカニカルリレー３は、制御信号に応じて接点部３２がオン／オフすることで、電源Ａ１から負荷Ｂ１への給電路を開閉する。 In other words, the mechanical relay 3 mechanically switches on / off of the contact portion 32 in accordance with a control signal input to the pair of input terminals 301 and 302, thereby connecting or not connecting the pair of output terminals 111 and 112. Switch continuity. In other words, the mechanical relay 3 opens and closes the power feeding path from the power source A1 to the load B1 by turning on / off the contact portion 32 according to the control signal.
　＜動作＞
　以下、本実施形態のスイッチ装置１の動作について図３を用いて説明する。ここで、図３に示す「接点電圧」は、一対の出力端子１１１，１１２間に印加される電圧である。また、図３に示す「第１電流」は、半導体リレー２の一対の出力端２１１，２１２を流れる電流である。そして、図３に示す「第２電流」は、メカニカルリレー３の一対の出力端３１１，３１２を流れる電流である。 <Operation>
Hereinafter, the operation of the switch device 1 of the present embodiment will be described with reference to FIG. Here, the “contact voltage” shown in FIG. 3 is a voltage applied between the pair of output terminals 111 and 112. Further, the “first current” shown in FIG. 3 is a current flowing through the pair of output terminals 211 and 212 of the semiconductor relay 2. The “second current” shown in FIG. 3 is a current flowing through the pair of output terminals 311 and 312 of the mechanical relay 3.
　まず、時刻ｔ１０において、一対の入力端子１０１，１０２に制御信号のうちオン信号が入力されると、時刻ｔ１０から所定時間後である時刻ｔ１１（＞ｔ１０）において、メカニカルリレー３の接点部３２がオンする。このため、一対の出力端３１１，３１２間が導通し、第２電流が流れる。すると、一対の出力端子１１１，１１２間も導通するため、電源Ａ１から負荷Ｂ１への給電路が閉じ、負荷Ｂ１に電流が流れる。本実施形態では、負荷Ｂ１が誘導性負荷であるため、第２電流は、時刻ｔ１１から時刻ｔ１２（＞ｔ１１）にかけて徐々に増大する。なお、負荷Ｂ１が抵抗負荷である場合、第２電流は、時刻ｔ１１において急峻に立ち上がる。 First, when an ON signal among the control signals is input to the pair of input terminals 101 and 102 at time t10, the contact portion 32 of the mechanical relay 3 is turned on at time t11 (> t10) after a predetermined time from time t10. Turn on. For this reason, between the pair of output terminals 311 and 312 is conducted, the second current flows. Then, since the pair of output terminals 111 and 112 are also connected, the power supply path from the power source A1 to the load B1 is closed, and a current flows through the load B1. In the present embodiment, since the load B1 is an inductive load, the second current gradually increases from time t11 to time t12 (> t11). When the load B1 is a resistance load, the second current rises sharply at time t11.
　時刻ｔ１２では、制御回路４によりオン信号が遅延していることから、半導体リレー２にオン信号が未だ入力されておらず、半導体リレー２の半導体スイッチ２Ｂはオンしていない。その後、時刻ｔ１２から、さらに時間が経過した時刻ｔ１３（＞ｔ１２）になると、制御回路４を介して半導体リレー２にオン信号が入力されることにより、半導体リレー２の半導体スイッチ２Ｂがオンする。このとき、接点部３２の接触抵抗は、半導体スイッチ２Ｂのオン抵抗と比較して小さいため、電源Ａ１から負荷Ｂ１へ流れる電流の殆どが接点部３２を介して流れる。このため、本実施形態のスイッチ装置１では、メカニカルリレー３を用いずに半導体リレー２のみで給電路を閉じる場合と比較して、半導体スイッチ２Ｂのオン抵抗での電力損失及び発熱が小さくなり、通電電流を大きくすることができる。なお、「通電電流」とは、電源Ａ１から負荷Ｂ１への給電路が閉じているときに、一対の出力端子１１１，１１２間を流れる電流である。 At time t12, since the ON signal is delayed by the control circuit 4, the ON signal is not yet input to the semiconductor relay 2, and the semiconductor switch 2B of the semiconductor relay 2 is not ON. Thereafter, at time t13 (> t12) when a further time elapses from time t12, an on signal is input to the semiconductor relay 2 via the control circuit 4, whereby the semiconductor switch 2B of the semiconductor relay 2 is turned on. At this time, since the contact resistance of the contact portion 32 is smaller than the on-resistance of the semiconductor switch 2B, most of the current flowing from the power source A1 to the load B1 flows through the contact portion 32. For this reason, in the switch device 1 of this embodiment, compared with the case where the power supply path is closed only by the semiconductor relay 2 without using the mechanical relay 3, the power loss and heat generation at the on-resistance of the semiconductor switch 2B are reduced. The energization current can be increased. The “energization current” is a current that flows between the pair of output terminals 111 and 112 when the power supply path from the power source A1 to the load B1 is closed.
　次に、時刻ｔ１４（＞ｔ１３）において、一対の入力端子１０１，１０２に制御信号のうちオフ信号が入力されると、時刻ｔ１４から所定時間後である時刻ｔ１５（＞ｔ１４）にメカニカルリレー３の接点部３２がオフする。すると、一対の出力端３１１，３１２間が非導通になることから、第２電流が流れなくなり、第１電流が流れる。この時点では、制御回路４によりオフ信号が遅延していることから、半導体リレー２にオフ信号が未だ入力されておらず、半導体リレー２の半導体スイッチ２Ｂはオフしていない。 Next, at time t14 (> t13), when an off signal of the control signals is input to the pair of input terminals 101 and 102, the mechanical relay 3 is turned on at time t15 (> t14), which is a predetermined time after time t14. The contact part 32 is turned off. Then, since the pair of output terminals 311 and 312 becomes non-conductive, the second current does not flow and the first current flows. At this time, since the off signal is delayed by the control circuit 4, the off signal is not yet input to the semiconductor relay 2, and the semiconductor switch 2B of the semiconductor relay 2 is not off.
　その後、時刻ｔ１５から、さらに時間が経過した時刻ｔ１６（＞ｔ１５）になると、制御回路４を介して半導体リレー２にオフ信号が入力されることにより、半導体リレー２の半導体スイッチ２Ｂがオフする。すると、一対の出力端子１１１，１１２間が非導通になるため、電源Ａ１から負荷Ｂ１への給電路が開き、負荷Ｂ１に電流が流れなくなる。本実施形態では、負荷Ｂ１が誘導性負荷であるため、瞬間的に逆起電力が発生するが、時刻ｔ１６から時刻ｔ１７（＞ｔ１６）にかけてバリスタＶＲ１が機能することにより、接点電圧は過大な電圧とはならない。 Thereafter, at time t16 (> t15) when a further time elapses from time t15, an off signal is input to the semiconductor relay 2 via the control circuit 4, whereby the semiconductor switch 2B of the semiconductor relay 2 is turned off. Then, since the pair of output terminals 111 and 112 become non-conductive, the power supply path from the power source A1 to the load B1 is opened, and no current flows through the load B1. In this embodiment, since the load B1 is an inductive load, a counter electromotive force is generated instantaneously. However, the contactor voltage is an excessive voltage due to the function of the varistor VR1 from time t16 to time t17 (> t16). It will not be.
　ここで、メカニカルリレー３の接点部３２がオフする際には、半導体スイッチ２Ｂがオフしていないので、一対の出力端子１１１，１１２間には電源電圧が印加されていない。このため、本実施形態のスイッチ装置１では、半導体リレー２の半導体スイッチ２Ｂがメカニカルリレー３の接点部３２よりも先にオフする場合と比較して、接点部３２のオフ時にアークが生じ難い。 Here, when the contact portion 32 of the mechanical relay 3 is turned off, the semiconductor switch 2B is not turned off, so that the power supply voltage is not applied between the pair of output terminals 111 and 112. For this reason, in the switch device 1 of the present embodiment, compared to the case where the semiconductor switch 2B of the semiconductor relay 2 is turned off before the contact part 32 of the mechanical relay 3, an arc is less likely to occur when the contact part 32 is turned off.
　上述のように、本実施形態のスイッチ装置１では、一対の入力端子１０１，１０２に制御信号のうちオフ信号が入力されるときは、半導体スイッチ２Ｂよりも先に接点部３２がオフするように制御されるのが望ましい。以下では、この制御を「優先オフ制御」という。ここで、通常であれば、半導体スイッチ２Ｂのターンオフ時間は、接点部３２の復帰時間よりも短くなるため、半導体スイッチ２Ｂが接点部３２よりも先にオフしてしまう。 As described above, in the switch device 1 according to the present embodiment, when the off signal among the control signals is input to the pair of input terminals 101 and 102, the contact portion 32 is turned off before the semiconductor switch 2B. It is desirable to be controlled. Hereinafter, this control is referred to as “priority off control”. Here, normally, since the turn-off time of the semiconductor switch 2B is shorter than the return time of the contact part 32, the semiconductor switch 2B is turned off before the contact part 32.
　そこで、本実施形態では、制御回路４は、半導体スイッチ２Ｂを制御することで、半導体スイッチ２Ｂがオンからオフになるタイミングを、メカニカルリレー３の接点部３２がオンからオフになるタイミングよりも遅らせるように構成されている。このため、本実施形態のスイッチ装置１では、半導体リレー２及びメカニカルリレー３を個別に制御せずとも、１つの制御信号により優先オフ制御を実現することができる。 Therefore, in this embodiment, the control circuit 4 controls the semiconductor switch 2B to delay the timing at which the semiconductor switch 2B is turned off from the timing at which the contact portion 32 of the mechanical relay 3 is turned from on to off. It is configured as follows. For this reason, in the switch apparatus 1 of this embodiment, priority OFF control is realizable by one control signal, without controlling the semiconductor relay 2 and the mechanical relay 3 separately.
　また、本実施形態では、制御回路４は、半導体スイッチ２Ｂを制御することで、半導体スイッチ２Ｂがオフからオンになるタイミングを、メカニカルリレー３の接点部３２がオフからオンになるタイミングよりも遅らせるように構成されている。このため、本実施形態のスイッチ装置１では、一対の出力端子１１１，１１２間が導通する際に、半導体スイッチ２Ｂに瞬間的に過大な電流が流れるのを防ぐことができる。なお、当該構成を採用するか否かは任意である。 In the present embodiment, the control circuit 4 controls the semiconductor switch 2B to delay the timing at which the semiconductor switch 2B is turned on from the timing at which the contact portion 32 of the mechanical relay 3 is turned on from off. It is configured as follows. For this reason, in the switch apparatus 1 of this embodiment, when a pair of output terminals 111 and 112 conduct | electrically_connect, it can prevent that an excessive electric current flows into the semiconductor switch 2B instantaneously. Note that whether or not to adopt the configuration is arbitrary.
　＜効果＞
　上述のように、本実施形態のスイッチ装置１では、制御回路４を備えていることから、半導体リレー２及びメカニカルリレー３を個別に制御して各々のオフタイミングをずらすといった複雑な制御が不要である。つまり、本実施形態のスイッチ装置１は、半導体リレー２及びメカニカルリレー３を組み合わせたハイブリッドリレーを、１つの制御信号により容易に制御することができる。 <Effect>
As described above, since the switch device 1 according to the present embodiment includes the control circuit 4, complicated control such as individually controlling the semiconductor relay 2 and the mechanical relay 3 and shifting the respective off timings is unnecessary. is there. That is, the switch device 1 of the present embodiment can easily control a hybrid relay in which the semiconductor relay 2 and the mechanical relay 3 are combined with one control signal.
　なお、本実施形態のスイッチ装置１は、制御信号がハイレベルのときに半導体スイッチ２Ｂ（接点部３２）がオンする構成であるが、他の構成であってもよい。すなわち、本実施形態のスイッチ装置１は、制御信号がローレベルのときに半導体スイッチ２Ｂ（接点部３２）がオンするように構成されていてもよい。この場合、「制御信号のうちオン信号が入力される」とは「制御信号がローレベルになる」ことを意味する。さらに、「制御信号のうちオフ信号が入力されなくなる」とは「制御信号がハイレベルになる」ことを意味する。 In addition, although the switch apparatus 1 of this embodiment is the structure which the semiconductor switch 2B (contact part 32) turns on when a control signal is a high level, another structure may be sufficient. That is, the switch device 1 of the present embodiment may be configured such that the semiconductor switch 2B (contact portion 32) is turned on when the control signal is at a low level. In this case, “the ON signal among the control signals is input” means “the control signal becomes low level”. Further, “the OFF signal of the control signal is not input” means “the control signal becomes high level”.
　（実施形態１の変形例）
　以下、本発明の実施形態１の変形例に係るスイッチ装置１Ａについて図４を用いて説明する。本変形例のスイッチ装置１Ａは、制御回路４の代わりに、制御回路４Ａを備えている点で実施形態１のスイッチ装置１と相違している。なお、本変形例のスイッチ装置１Ａのうち制御回路４Ａを除く構成は、実施形態１のスイッチ装置１と同じであるので、ここでは説明を省略する。 (Modification of Embodiment 1)
Hereinafter, a switch device 1A according to a modification of the first embodiment of the present invention will be described with reference to FIG. The switch device 1 </ b> A of this modification is different from the switch device 1 of the first embodiment in that a control circuit 4 </ b> A is provided instead of the control circuit 4. Since the configuration excluding the control circuit 4A in the switch device 1A of the present modification is the same as that of the switch device 1 of the first embodiment, the description thereof is omitted here.
　＜構成＞
　図４に示すように、制御回路４Ａは、遅延回路５の代わりに、遅延回路５Ａを有している。遅延回路５Ａは、遅延回路５の抵抗４１と、キャパシタ４２とに加え、ダイオード４３と、抵抗４４，４５とをさらに備えている。また、遅延回路５Ａにおいて、抵抗４１の抵抗値は、実施形態１の遅延回路５における抵抗４１の抵抗値よりも小さくなっている。ダイオード４３は、アノードが第１入力端子１０１に、カソードが抵抗４１に電気的に接続されている。抵抗４４は、キャパシタ４２に並列に電気的に接続されている。抵抗４４の抵抗値は、抵抗４１の抵抗値よりも大きくなっている。抵抗４５は、キャパシタ４２に直列に電気的に接続されている。抵抗４５の抵抗値は、抵抗４１の抵抗値と同程度である。 <Configuration>
As shown in FIG. 4, the control circuit 4 </ b> A has a delay circuit 5 </ b> A instead of the delay circuit 5. The delay circuit 5A further includes a diode 43 and resistors 44 and 45 in addition to the resistor 41 and the capacitor 42 of the delay circuit 5. In the delay circuit 5A, the resistance value of the resistor 41 is smaller than the resistance value of the resistor 41 in the delay circuit 5 of the first embodiment. The diode 43 has an anode electrically connected to the first input terminal 101 and a cathode electrically connected to the resistor 41. The resistor 44 is electrically connected to the capacitor 42 in parallel. The resistance value of the resistor 44 is larger than the resistance value of the resistor 41. The resistor 45 is electrically connected to the capacitor 42 in series. The resistance value of the resistor 45 is approximately the same as the resistance value of the resistor 41.
　ここで、一対の入力端子１０１，１０２間に制御信号のうちオン信号が入力されるとき、遅延回路５Ａでは、抵抗４１の抵抗値が実施形態１の遅延回路５における抵抗４１の抵抗値よりも小さくなっていることから、遅延回路５よりも時定数が小さい。したがって、制御回路４Ａによるオン信号の遅延時間は、実施形態１の制御回路４によるオン信号の遅延時間よりも短くなっている。 Here, when an ON signal among the control signals is input between the pair of input terminals 101 and 102, in the delay circuit 5A, the resistance value of the resistor 41 is greater than the resistance value of the resistor 41 in the delay circuit 5 of the first embodiment. Since it is small, the time constant is smaller than that of the delay circuit 5. Therefore, the delay time of the on signal by the control circuit 4A is shorter than the delay time of the on signal by the control circuit 4 of the first embodiment.
　また、一対の入力端子１０１，１０２間に制御信号のうちオフ信号が入力されるとき、遅延回路５Ａでは、キャパシタ４２に蓄積された電荷がメカニカルリレー３へと放電するのをダイオード４３により防止している。さらに、遅延回路５Ａでは、キャパシタ４２に並列に接続された抵抗４４、及びキャパシタ４２に直列に接続された抵抗４５により、キャパシタ４２に蓄積された電荷が放電する時間を比較的長くしている。したがって、制御回路４Ａによるオフ信号の遅延時間は、制御回路４Ａによるオン信号の遅延時間よりも長くなっている。 Also, when an off signal of the control signals is input between the pair of input terminals 101 and 102, the delay circuit 5A prevents the charge accumulated in the capacitor 42 from being discharged to the mechanical relay 3 by the diode 43. ing. Further, in the delay circuit 5A, the time for discharging the charge accumulated in the capacitor 42 is made relatively long by the resistor 44 connected in parallel to the capacitor 42 and the resistor 45 connected in series to the capacitor 42. Therefore, the delay time of the off signal by the control circuit 4A is longer than the delay time of the on signal by the control circuit 4A.
　本変形例のスイッチ装置１Ａでは、半導体リレー２の半導体スイッチ２Ｂのターンオン時間が、メカニカルリレー３の接点部３２の動作時間と比較して短いという特性を利用している。つまり、制御回路４Ａによるオン信号の遅延時間を、半導体スイッチ２Ｂのターンオン時間と接点部３２の動作時間との差分よりも短くしている。このため、本変形例のスイッチ装置１Ａでは、オン信号が制御回路４Ａにより遅延しても、半導体スイッチ２Ｂがオフからオンになるタイミングを、接点部３２がオフからオンになるタイミングよりも早めることが可能である。また、本変形例のスイッチ装置１Ａでは、制御回路４Ａにより、オン信号の遅延時間よりもオフ信号の遅延時間を長くしている。このため、本変形例のスイッチ装置１Ａでは、実施形態１の制御回路４と同様に、半導体スイッチ２Ｂがオンからオフになるタイミングを、接点部３２がオンからオフになるタイミングよりも遅らせることが可能である。 The switch device 1A of the present modification utilizes the characteristic that the turn-on time of the semiconductor switch 2B of the semiconductor relay 2 is shorter than the operation time of the contact part 32 of the mechanical relay 3. That is, the delay time of the ON signal by the control circuit 4A is made shorter than the difference between the turn-on time of the semiconductor switch 2B and the operation time of the contact part 32. For this reason, in the switch device 1A of the present modification, even when the ON signal is delayed by the control circuit 4A, the timing at which the semiconductor switch 2B is turned from OFF to ON is made earlier than the timing at which the contact portion 32 is turned from OFF to ON. Is possible. In the switch device 1A of the present modification, the delay time of the off signal is made longer than the delay time of the on signal by the control circuit 4A. For this reason, in the switch device 1A of the present modification, as with the control circuit 4 of the first embodiment, the timing at which the semiconductor switch 2B is turned from on to off can be delayed from the timing at which the contact portion 32 is turned from on to off. Is possible.
　＜動作＞
　以下、本変形例のスイッチ装置１Ａの動作について図５を用いて説明する。まず、時刻ｔ２０において、一対の入力端子１０１，１０２に制御信号のうちオン信号が入力されると、時刻ｔ２０から所定時間後である時刻ｔ２１（＞ｔ２０）において、半導体リレー２の半導体スイッチ２Ｂがオンする。このため、一対の出力端３１１，３１２間が導通し、第１電流が流れる。すると、一対の出力端子１１１，１１２間も導通するため、電源Ａ１から負荷Ｂ１への給電路が閉じ、負荷Ｂ１に電流が流れる。本実施形態では、負荷Ｂ１が誘導性負荷であるため、第１電流は、時刻ｔ２１から時刻ｔ２２（＞ｔ２１）にかけて徐々に増大する。なお、負荷Ｂ１が抵抗負荷である場合、第１電流は、時刻ｔ２１において急峻に立ち上がる。 <Operation>
Hereinafter, the operation of the switch device 1A of the present modification will be described with reference to FIG. First, when an ON signal among the control signals is input to the pair of input terminals 101 and 102 at time t20, the semiconductor switch 2B of the semiconductor relay 2 is turned on at time t21 (> t20), which is a predetermined time after time t20. Turn on. For this reason, between the pair of output terminals 311 and 312 is conducted, the first current flows. Then, since the pair of output terminals 111 and 112 are also connected, the power supply path from the power source A1 to the load B1 is closed, and a current flows through the load B1. In the present embodiment, since the load B1 is an inductive load, the first current gradually increases from time t21 to time t22 (> t21). When the load B1 is a resistance load, the first current rises sharply at time t21.
　この時点では、メカニカルリレー３の接点部３２はオンしていない。その後、時刻ｔ２２から所定時間後である時刻ｔ２３（＞ｔ２２）において、メカニカルリレー３の接点部３２がオンする。ここで、メカニカルリレー３の接点部３２がオンする際に、接点電圧は、半導体スイッチ２Ｂのドレイン－ソース間のオン抵抗での電圧降下に応じた電圧となるため、電源電圧の最大電圧と比較して小さい。このため、本変形例のスイッチ装置１Ａでは、半導体リレー２を用いずにメカニカルリレー３のみで給電路を閉じる場合と比較して、接点部３２のオン時に生じ得る突入電流を小さくすることができる。 At this time, the contact portion 32 of the mechanical relay 3 is not turned on. Thereafter, at time t23 (> t22), which is a predetermined time after time t22, the contact portion 32 of the mechanical relay 3 is turned on. Here, when the contact portion 32 of the mechanical relay 3 is turned on, the contact voltage becomes a voltage corresponding to the voltage drop due to the on-resistance between the drain and source of the semiconductor switch 2B, so it is compared with the maximum voltage of the power supply voltage. And small. For this reason, in the switch device 1A of the present modification, the inrush current that can be generated when the contact portion 32 is turned on can be reduced as compared with the case where the power supply path is closed only by the mechanical relay 3 without using the semiconductor relay 2. .
　次に、時刻ｔ２４（＞ｔ２３）において、一対の入力端子１０１，１０２に制御信号のうちオフ信号が入力されると、時刻ｔ２４から所定時間後である時刻ｔ２５（＞ｔ２４）にメカニカルリレー３の接点部３２がオフする。すると、一対の出力端３１１，３１２間が非導通になることから、第２電流が流れなくなり、第１電流が流れる。この時点では、制御回路４Ａによりオフ信号が遅延していることから、半導体リレー２にオフ信号が未だ入力されておらず、半導体リレー２の半導体スイッチ２Ｂはオフしていない。 Next, at time t24 (> t23), when an off signal of the control signals is input to the pair of input terminals 101 and 102, the mechanical relay 3 is turned on at time t25 (> t24), which is a predetermined time after time t24. The contact part 32 is turned off. Then, since the pair of output terminals 311 and 312 becomes non-conductive, the second current does not flow and the first current flows. At this time, since the OFF signal is delayed by the control circuit 4A, the OFF signal is not yet input to the semiconductor relay 2, and the semiconductor switch 2B of the semiconductor relay 2 is not OFF.
　その後、時刻ｔ２５から、さらに時間が経過した時刻ｔ２６（＞ｔ２５）になると、制御回路４Ａを介して半導体リレー２にオフ信号が入力されることにより、半導体リレー２の半導体スイッチ２Ｂがオフする。すると、一対の出力端子１１１，１１２間が非導通になるため、電源Ａ１から負荷Ｂ１への給電路が開き、負荷Ｂ１に電流が流れなくなる。なお、時刻ｔ２６から時刻２７（＞ｔ２６）までは、バリスタＶＲ１が機能している時間である。 Thereafter, at time t26 (> t25) when a further time elapses from time t25, the semiconductor switch 2B of the semiconductor relay 2 is turned off by inputting an off signal to the semiconductor relay 2 via the control circuit 4A. Then, since the pair of output terminals 111 and 112 become non-conductive, the power supply path from the power source A1 to the load B1 is opened, and no current flows through the load B1. Note that the time from time t26 to time 27 (> t26) is the time during which the varistor VR1 is functioning.
　上述のように、本変形例のスイッチ装置１Ａでは、一対の入力端子１０１，１０２に制御信号のうちオン信号を入力するときは、メカニカルリレー３の接点部３２よりも先に半導体リレー２の半導体スイッチ２Ｂがオンするように制御されるのが望ましい。以下では、この制御を「優先オン制御」という。 As described above, in the switch device 1 </ b> A according to the present modification, when the ON signal among the control signals is input to the pair of input terminals 101 and 102, the semiconductor of the semiconductor relay 2 is preceded by the contact portion 32 of the mechanical relay 3. It is desirable to control the switch 2B to be turned on. Hereinafter, this control is referred to as “priority on control”.
　本変形例のスイッチ装置１Ａでは、半導体スイッチ２Ｂのターンオン時間が接点部３２の動作時間と比較して短いという特性を利用しつつ、制御回路４Ａを用いることで、優先オン制御を実現している。つまり、本変形例では、制御回路４Ａは、半導体スイッチ２Ｂを制御することで、半導体スイッチ２Ｂがオフからオンになるタイミングを、メカニカルリレー３の接点部３２がオフからオンになるタイミングよりも早めるように構成されている。このため、本変形例のスイッチ装置１Ａでは、半導体リレー２及びメカニカルリレー３を個別に制御せずとも、１つの制御信号により優先オン制御を実現することができる。また、本変形例のスイッチ装置１Ａでは、実施形態１の制御回路４と同様に、制御回路４Ａを用いることで、優先オフ制御も実現している。 In the switch device 1A of the present modification, priority on control is realized by using the control circuit 4A while utilizing the characteristic that the turn-on time of the semiconductor switch 2B is shorter than the operation time of the contact part 32. . In other words, in the present modification, the control circuit 4A controls the semiconductor switch 2B so that the timing at which the semiconductor switch 2B is turned on is earlier than the timing at which the contact portion 32 of the mechanical relay 3 is turned on. It is configured as follows. For this reason, in the switch device 1A of the present modification, priority on control can be realized by one control signal without individually controlling the semiconductor relay 2 and the mechanical relay 3. Further, in the switch device 1A of the present modification example, the priority off control is also realized by using the control circuit 4A as in the control circuit 4 of the first embodiment.
　＜効果＞
　上述のように、本変形例のスイッチ装置１Ａでは、制御回路４Ａを備えていることから、半導体リレー２及びメカニカルリレー３を個別に制御して各々のオン／オフのタイミングをずらすといった複雑な制御が不要である。つまり、本変形例のスイッチ装置１Ａは、半導体リレー２及びメカニカルリレー３を組み合わせたハイブリッドリレーを、１つの制御信号で容易に制御することができる。 <Effect>
As described above, since the switch device 1A of the present modification includes the control circuit 4A, complicated control such as individually controlling the semiconductor relay 2 and the mechanical relay 3 to shift the on / off timings. Is unnecessary. That is, the switch device 1 </ b> A of the present modification can easily control a hybrid relay in which the semiconductor relay 2 and the mechanical relay 3 are combined with one control signal.
　（実施形態２）
　本発明の実施形態２に係るスイッチ装置１Ｂは、図６に示すように、半導体リレー２と、メカニカルリレー３と、制御回路４Ｂとを備える。半導体リレー２は、電源Ａ１から負荷Ｂ１への給電路に電気的に接続され、外部から入力される第１制御信号に応じて給電路を開閉する。メカニカルリレー３は、半導体リレー２と並列に電気的に接続され、外部から入力される第２制御信号に応じて給電路を開閉する。 (Embodiment 2)
As shown in FIG. 6, the switch device 1B according to the second embodiment of the present invention includes a semiconductor relay 2, a mechanical relay 3, and a control circuit 4B. The semiconductor relay 2 is electrically connected to a power feeding path from the power source A1 to the load B1, and opens and closes the power feeding path according to a first control signal input from the outside. The mechanical relay 3 is electrically connected in parallel with the semiconductor relay 2 and opens and closes the power feeding path according to a second control signal input from the outside.
　半導体リレー２は、半導体スイッチ２３，２４を有する。半導体スイッチ２３，２４は、第１制御信号に応じてオン／オフすることで給電路を開閉する。また、半導体スイッチ２３，２４は、容量成分（ゲート容量）に蓄積される電荷に応じてオン／オフするように構成される。 The semiconductor relay 2 has semiconductor switches 23 and 24. The semiconductor switches 23 and 24 open and close the power supply path by being turned on / off according to the first control signal. Further, the semiconductor switches 23 and 24 are configured to be turned on / off according to the electric charge accumulated in the capacitance component (gate capacitance).
　制御回路４Ｂは、充放電経路２５と、インピーダンス回路２６とを有する。充放電経路２５は、半導体スイッチ２３，２４のゲート容量を充電及び放電する。インピーダンス回路２６は、充放電経路２５に電気的に接続される。また、インピーダンス回路２６は、インピーダンス素子２６１を有し、制御信号（第１制御信号）のうちオン信号が入力されると充放電経路２５に第１経路Ｓ１を接続するように構成される。さらに、インピーダンス回路２６は、制御信号（第１制御信号）のうちオフ信号が入力されると充放電経路２５をインピーダンス素子２６１を含む第２経路Ｓ２に接続するように構成される。 The control circuit 4B includes a charge / discharge path 25 and an impedance circuit 26. The charge / discharge path 25 charges and discharges the gate capacitance of the semiconductor switches 23 and 24. The impedance circuit 26 is electrically connected to the charge / discharge path 25. The impedance circuit 26 includes an impedance element 261 and is configured to connect the first path S1 to the charge / discharge path 25 when an ON signal is input from among the control signals (first control signals). Furthermore, the impedance circuit 26 is configured to connect the charge / discharge path 25 to the second path S2 including the impedance element 261 when an off signal is input from among the control signals (first control signals).
　＜構成＞
　以下、本実施形態のスイッチ装置１Ｂについて詳細に説明する。ただし、本実施形態のスイッチ装置１Ｂにおいて、実施形態１のスイッチ装置１と共通する部分については、説明を省略する。なお、本実施形態のスイッチ装置１Ｂでは、電源Ａ１として交流電源を用いているが、直流電源を用いてもよい。 <Configuration>
Hereinafter, the switch device 1B of the present embodiment will be described in detail. However, in the switch device 1B of the present embodiment, the description of the parts common to the switch device 1 of the first embodiment is omitted. In the switch device 1B of the present embodiment, an AC power source is used as the power source A1, but a DC power source may be used.
　また、以下の説明では、「第１制御信号（第２制御信号）のうちオン信号が入力される」とは「第１制御信号（第２制御信号）がハイレベルになる」ことを意味する。さらに、「第１制御信号（第２制御信号）のうちオフ信号が入力される」とは「第１制御信号（第２制御信号）がローレベルになる」ことを意味する。 Further, in the following description, “the ON signal is input from among the first control signals (second control signals)” means “the first control signal (second control signal) becomes high level”. . Furthermore, “the off signal of the first control signal (second control signal) is input” means that “the first control signal (second control signal) becomes low level”.
　本実施形態では、制御信号は、半導体リレー２の一対の入力端２０１，２０２に第１制御信号として入力される。また、本実施形態では、制御信号は、メカニカルリレー３の一対の入力端３０１，３０２に第２制御信号として入力される。つまり、本実施形態のスイッチ装置１Ｂでは、第１制御信号と第２制御信号とは、同じである。言い換えれば、第１制御信号及び第２制御信号は、周期が互いに同一であり、かつ位相が互いに同一である。もちろん、第１制御信号と第２制御信号とは、互いに異なる制御信号であってもよい。 In the present embodiment, the control signal is input to the pair of input terminals 201 and 202 of the semiconductor relay 2 as the first control signal. In the present embodiment, the control signal is input to the pair of input terminals 301 and 302 of the mechanical relay 3 as the second control signal. That is, in the switch device 1B of the present embodiment, the first control signal and the second control signal are the same. In other words, the first control signal and the second control signal have the same period and the same phase. Of course, the first control signal and the second control signal may be different control signals.
　半導体リレー２は、いわゆる無接点リレーであり、発光素子２１と、受光素子２２と、２つの半導体スイッチ２３，２４とを有している。 The semiconductor relay 2 is a so-called non-contact relay, and has a light emitting element 21, a light receiving element 22, and two semiconductor switches 23 and 24.
　発光素子２１は、一対の入力端２０１，２０２に入力される電気信号を光に変換するように構成されている。本実施形態のスイッチ装置１では、発光素子２１は発光ダイオードである。発光ダイオードは、アノードが第１入力端２０１に、カソードが第２入力端２０２に電気的に接続されている。発光素子２１は、一対の入力端２０１，２０２に入力される第１制御信号を受けて発光する。なお、発光素子２１を構成する発光ダイオードの数は１つに限定されず、複数であってもよい。 The light emitting element 21 is configured to convert an electric signal input to the pair of input ends 201 and 202 into light. In the switch device 1 of the present embodiment, the light emitting element 21 is a light emitting diode. The light emitting diode has an anode electrically connected to the first input end 201 and a cathode electrically connected to the second input end 202. The light emitting element 21 emits light in response to the first control signal input to the pair of input ends 201 and 202. Note that the number of light emitting diodes constituting the light emitting element 21 is not limited to one and may be plural.
　ここで、本実施形態のスイッチ装置１Ｂでは、上述のように第１制御信号及び第２制御信号が同じである。このため、本実施形態のスイッチ装置１Ｂでは、第１入力端子１０１と半導体リレー２の第１入力端２０１との間に、電流調整用の抵抗１１が電気的に接続されている。この抵抗１１により、発光素子２１に過大な電流が流れるのを防止している。なお、第１制御信号と第２制御信号とを個別に半導体リレー２及びメカニカルリレー３に入力する場合には、抵抗１１は不要である。 Here, in the switch device 1B of the present embodiment, the first control signal and the second control signal are the same as described above. For this reason, in the switch device 1 </ b> B of the present embodiment, the current adjusting resistor 11 is electrically connected between the first input terminal 101 and the first input terminal 201 of the semiconductor relay 2. The resistor 11 prevents an excessive current from flowing through the light emitting element 21. Note that when the first control signal and the second control signal are individually input to the semiconductor relay 2 and the mechanical relay 3, the resistor 11 is not necessary.
　受光素子２２は、発光素子２１が発する光を受けて光起電力を発生するように構成されている。本実施形態のスイッチ装置１Ｂでは、受光素子２２は、複数のフォトダイオードを直列に電気的に接続してなるフォトダイオードアレイで構成されている。フォトダイオードアレイは、アノードが充放電経路２５の高電位側の一端に、カソードが充放電経路２５の低電位側の一端に電気的に接続されている。 The light receiving element 22 is configured to receive a light emitted from the light emitting element 21 and generate a photovoltaic power. In the switch device 1B of the present embodiment, the light receiving element 22 is configured by a photodiode array in which a plurality of photodiodes are electrically connected in series. In the photodiode array, the anode is electrically connected to one end on the high potential side of the charge / discharge path 25 and the cathode is electrically connected to one end on the low potential side of the charge / discharge path 25.
　半導体スイッチ２３，２４は、いずれもｎチャネルのエンハンスメント型ＭＯＳＦＥＴである。半導体スイッチ２３，２４のゲートは、受光素子２２の高電位側の一端に電気的に接続されている。半導体スイッチ２３，２４のソースは、インピーダンス回路２６を介して、受光素子２２の低電位側の一端に電気的に接続されている。また、半導体スイッチ２３のドレインは、第１出力端子１１１に電気的に接続されている。半導体スイッチ２４のドレインは、第２出力端子１１２に電気的に接続されている。つまり、半導体スイッチ２３，２４は、一対の出力端子１１１，１１２間に直列に電気的に接続されている。 The semiconductor switches 23 and 24 are both n-channel enhancement type MOSFETs. The gates of the semiconductor switches 23 and 24 are electrically connected to one end on the high potential side of the light receiving element 22. The sources of the semiconductor switches 23 and 24 are electrically connected to one end on the low potential side of the light receiving element 22 via the impedance circuit 26. The drain of the semiconductor switch 23 is electrically connected to the first output terminal 111. The drain of the semiconductor switch 24 is electrically connected to the second output terminal 112. That is, the semiconductor switches 23 and 24 are electrically connected in series between the pair of output terminals 111 and 112.
　半導体スイッチ２３，２４は、いずれも容量成分（ゲート容量）に蓄積される電荷に応じてオン／オフするように構成される。なお、「ゲート容量」とは、半導体スイッチ２３，２４のゲート－ソース間に存在するキャパシタ、及びゲート－ドレイン間に存在するキャパシタである。 The semiconductor switches 23 and 24 are both configured to be turned on / off according to the electric charge accumulated in the capacitance component (gate capacitance). The “gate capacitance” is a capacitor existing between the gate and the source of the semiconductor switches 23 and 24 and a capacitor existing between the gate and the drain.
　なお、本実施形態のスイッチ装置１Ｂでは、半導体スイッチ（２３，２４）は２つであるが、１つであってもよい。つまり、電源Ａ１が交流電源である場合、スイッチ装置１は、２つの半導体スイッチ（２３，２４）を必要とする。一方、電源Ａ１が直流電源である場合、スイッチ装置１Ｂは、高電位側の半導体スイッチ（２３，２４のいずれか）を１つ必要とする。また、本実施形態のスイッチ装置１Ｂでは、半導体スイッチ（２３，２４）はエンハンスメント型ＭＯＳＦＥＴであるが、たとえばＩＧＢＴ等の半導体素子であってもよい。 In addition, in the switch apparatus 1B of this embodiment, although there are two semiconductor switches (23, 24), there may be one. That is, when the power source A1 is an AC power source, the switch device 1 requires two semiconductor switches (23, 24). On the other hand, when the power source A1 is a DC power source, the switch device 1B requires one high-potential side semiconductor switch (one of 23 and 24). In the switch device 1B of this embodiment, the semiconductor switches (23, 24) are enhancement type MOSFETs, but may be semiconductor elements such as IGBTs.
　制御回路４Ｂは、充放電経路２５と、インピーダンス回路２６とを有している。充放電経路２５は、半導体スイッチ２３，２４のゲート容量を充電及び放電するように構成されている。本実施形態のスイッチ装置１Ｂでは、充放電経路２５は、受光素子２２と並列に電気的に接続される抵抗２５１を含んで構成されている。 The control circuit 4B has a charge / discharge path 25 and an impedance circuit 26. The charge / discharge path 25 is configured to charge and discharge the gate capacitance of the semiconductor switches 23 and 24. In the switch device 1B of the present embodiment, the charge / discharge path 25 includes a resistor 251 that is electrically connected in parallel with the light receiving element 22.
　以下、充放電経路２５の機能について簡単に説明する。受光素子２２に光起電力が発生すると、受光素子２２から半導体スイッチ２３，２４のゲートに電流が流れ込み、半導体スイッチ２３，２４のゲート容量が充電される。受光素子２２に光起電力が発生しなくなると、充放電経路２５の抵抗２５１を介して半導体スイッチ２３，２４のゲート容量が放電される。 Hereinafter, the function of the charge / discharge path 25 will be briefly described. When a photoelectromotive force is generated in the light receiving element 22, a current flows from the light receiving element 22 to the gates of the semiconductor switches 23 and 24, and the gate capacitances of the semiconductor switches 23 and 24 are charged. When no photoelectromotive force is generated in the light receiving element 22, the gate capacitances of the semiconductor switches 23 and 24 are discharged via the resistor 251 of the charge / discharge path 25.
　ところで、本実施形態のスイッチ装置１Ｂでは、充放電経路２５は抵抗２５１を含んで構成されているが、他の構成であってもよい。たとえば、充放電経路２５は、図７に示すように、半導体素子２５２と、抵抗２５３とを含んで構成されていてもよい。半導体素子２５２は、ｎチャネルのデプレッション型ＭＯＳＦＥＴである。半導体素子２５２のドレインは、受光素子２２の高電位側の一端に電気的に接続されている。半導体素子２５２のゲートは、受光素子２２の低電位側の一端に電気的に接続されている。また、半導体素子２５２のソースは、抵抗２５３を介して受光素子２２の低電位側の一端に電気的に接続されている。言い換えれば、抵抗２５３は、半導体素子２５２のゲート－ソース間に電気的に接続されている。 By the way, in the switch apparatus 1B of this embodiment, although the charging / discharging path | route 25 is comprised including the resistance 251, another structure may be sufficient. For example, the charge / discharge path 25 may include a semiconductor element 252 and a resistor 253 as shown in FIG. The semiconductor element 252 is an n-channel depletion type MOSFET. The drain of the semiconductor element 252 is electrically connected to one end on the high potential side of the light receiving element 22. The gate of the semiconductor element 252 is electrically connected to one end on the low potential side of the light receiving element 22. The source of the semiconductor element 252 is electrically connected to one end on the low potential side of the light receiving element 22 through the resistor 253. In other words, the resistor 253 is electrically connected between the gate and source of the semiconductor element 252.
　この充放電経路２５の機能について簡単に説明する。受光素子２２に光起電力が発生すると、受光素子２２から半導体素子２５２及び抵抗２５３に電流が流れる。すると、抵抗２５３において電圧降下が生じ、この電圧降下により半導体素子２５２がオフする。このため、受光素子２２から半導体スイッチ２３，２４のゲートに電流が流れ込み、半導体スイッチ２３，２４のゲート容量が充電される。受光素子２２に光起電力が発生しなくなると、抵抗２５３での電圧降下が生じなくなり、半導体素子２５２がオンする。このため、半導体スイッチ２３，２４のゲート容量は、半導体素子２５２を介した経路で放電される。 The function of the charge / discharge path 25 will be briefly described. When a photoelectromotive force is generated in the light receiving element 22, a current flows from the light receiving element 22 to the semiconductor element 252 and the resistor 253. Then, a voltage drop occurs in the resistor 253, and the semiconductor element 252 is turned off by this voltage drop. Therefore, a current flows from the light receiving element 22 to the gates of the semiconductor switches 23 and 24, and the gate capacitances of the semiconductor switches 23 and 24 are charged. When no photoelectromotive force is generated in the light receiving element 22, no voltage drop occurs in the resistor 253, and the semiconductor element 252 is turned on. For this reason, the gate capacitances of the semiconductor switches 23 and 24 are discharged through a path through the semiconductor element 252.
　インピーダンス回路２６は、インピーダンス素子２６１と、スイッチ２６２とを有している。インピーダンス素子２６１は、受光素子２２の低電位側の一端と、半導体スイッチ２３，２４のソースとの間に電気的に接続されている。スイッチ２６２は、インピーダンス素子２６１に並列に電気的に接続されている。インピーダンス回路２６は、一対の入力端２０１，２０２に第１制御信号のうちオン信号が入力されると、電流が流れる経路を、スイッチ２６２を介する第１経路Ｓ１に切り替えるように構成されている。また、インピーダンス回路２６は、一対の入力端２０１，２０２に第１制御信号のうちオフ信号が入力されると、電流が流れる経路を、インピーダンス素子２６１を介する第２経路Ｓ２に切り替えるように構成されている。言い換えれば、インピーダンス回路２６は、第１制御信号のうちオン信号が入力されると、半導体スイッチ２３，２４のゲート容量を充電及び放電する充放電経路２５を第１経路Ｓ１に接続するように構成されている。また、インピーダンス回路２６は、第１制御信号のうちオフ信号が入力されると充放電経路２５をインピーダンス素子２６１を含む第２経路Ｓ２に接続するように構成されている。 The impedance circuit 26 includes an impedance element 261 and a switch 262. The impedance element 261 is electrically connected between one end on the low potential side of the light receiving element 22 and the sources of the semiconductor switches 23 and 24. The switch 262 is electrically connected to the impedance element 261 in parallel. The impedance circuit 26 is configured to switch the path through which the current flows to the first path S1 via the switch 262 when an ON signal of the first control signals is input to the pair of input terminals 201 and 202. Further, the impedance circuit 26 is configured to switch the path through which the current flows to the second path S2 via the impedance element 261 when an off signal of the first control signals is input to the pair of input terminals 201 and 202. ing. In other words, the impedance circuit 26 is configured to connect the charge / discharge path 25 that charges and discharges the gate capacitance of the semiconductor switches 23 and 24 to the first path S1 when an ON signal is input from among the first control signals. Has been. The impedance circuit 26 is configured to connect the charge / discharge path 25 to the second path S2 including the impedance element 261 when an off signal is input from the first control signal.
　インピーダンス回路２６の具体的な回路構成の一例を図８に示す。このインピーダンス回路２６は、抵抗Ｒ１（インピーダンス素子２６１）と、ダイオードＤ１（スイッチ２６２）とで構成される。抵抗Ｒ１は、受光素子２２の低電位側の一端と、半導体スイッチ２３，２４のソースとの間に電気的に接続される。ダイオードＤ１は、抵抗Ｒ１と並列に電気的に接続される。また、ダイオードＤ１は、アノードが半導体スイッチ２３，２４のソースに、カソードが受光素子２２の低電位側の一端に電気的に接続される。 An example of a specific circuit configuration of the impedance circuit 26 is shown in FIG. The impedance circuit 26 includes a resistor R1 (impedance element 261) and a diode D1 (switch 262). The resistor R <b> 1 is electrically connected between one end on the low potential side of the light receiving element 22 and the sources of the semiconductor switches 23 and 24. The diode D1 is electrically connected in parallel with the resistor R1. The diode D1 has an anode electrically connected to the sources of the semiconductor switches 23 and 24 and a cathode electrically connected to one end of the light receiving element 22 on the low potential side.
　この構成では、一対の入力端２０１，２０２に第１制御信号のうちオン信号が入力されると、半導体スイッチ２３，２４のゲート容量を充電するように電流が流れるため、ダイオードＤ１を介する経路（つまり、第１経路Ｓ１）に電流が流れる。また、一対の入力端２０１，２０２に第１制御信号のうちオフ信号が入力されると、半導体スイッチ２３，２４のゲート容量を放電するように電流が流れるため、抵抗Ｒ１を介する経路（つまり、第２経路Ｓ２）に電流が流れる。 In this configuration, when an ON signal of the first control signals is input to the pair of input terminals 201 and 202, a current flows so as to charge the gate capacitances of the semiconductor switches 23 and 24. Therefore, a path through the diode D1 ( That is, a current flows through the first path S1). In addition, when an off signal of the first control signal is input to the pair of input terminals 201 and 202, a current flows so as to discharge the gate capacitance of the semiconductor switches 23 and 24. Therefore, a path through the resistor R1 (that is, A current flows through the second path S2).
　以下、半導体リレー２の動作について説明する。一対の入力端２０１，２０２に第１制御信号のうちオン信号が入力されると、発光素子２１が発光する。すると、発光素子２１の発する光を受けて受光素子２２が光起電力を発生する。そして、受光素子２２からインピーダンス回路２６の第１経路Ｓ１を介して半導体スイッチ２３，２４のゲートに電流が流れ込むことで半導体スイッチ２３，２４のゲート容量が充電され、半導体スイッチ２３，２４がオンする。これにより、一対の出力端子１１１，１１２間が導通する。 Hereinafter, the operation of the semiconductor relay 2 will be described. When an ON signal among the first control signals is input to the pair of input terminals 201 and 202, the light emitting element 21 emits light. Then, in response to the light emitted from the light emitting element 21, the light receiving element 22 generates photovoltaic power. Then, current flows from the light receiving element 22 to the gates of the semiconductor switches 23 and 24 through the first path S1 of the impedance circuit 26, whereby the gate capacitances of the semiconductor switches 23 and 24 are charged and the semiconductor switches 23 and 24 are turned on. . As a result, the pair of output terminals 111 and 112 are electrically connected.
　一対の入力端２０１，２０２に第１制御信号のうちオフ信号が入力されると、発光素子２１が発光しなくなる。このため、受光素子２２が光起電力を発生しなくなる。すると、半導体スイッチ２３，２４のゲート容量が、充放電経路２５の抵抗２５１及びインピーダンス回路２６の第２経路Ｓ２を介して放電され、半導体スイッチ２３，２４がオフする。これにより、一対の出力端子１１１，１１２間が非導通となる。 When the off signal of the first control signals is input to the pair of input terminals 201 and 202, the light emitting element 21 does not emit light. For this reason, the light receiving element 22 does not generate photovoltaic power. Then, the gate capacitances of the semiconductor switches 23 and 24 are discharged through the resistor 251 of the charge / discharge path 25 and the second path S2 of the impedance circuit 26, and the semiconductor switches 23 and 24 are turned off. As a result, the pair of output terminals 111 and 112 become non-conductive.
　つまり、半導体リレー２は、一対の入力端２０１，２０２に入力される第１制御信号に応じて半導体スイッチ２３，２４のオン／オフを切り替えることで、一対の出力端子１１１，１１２間の導通・非導通を切り替える。言い換えれば、半導体リレー２は、第１制御信号に応じて半導体スイッチ２３，２４がオン／オフすることで、電源Ａ１から負荷Ｂ１への給電路を開閉する。 That is, the semiconductor relay 2 switches on / off of the semiconductor switches 23 and 24 according to the first control signal input to the pair of input terminals 201 and 202, thereby connecting the pair of output terminals 111 and 112. Switch non-conduction. In other words, the semiconductor relay 2 opens and closes the power supply path from the power source A1 to the load B1 by turning on / off the semiconductor switches 23 and 24 according to the first control signal.
　なお、本実施形態のスイッチ装置１Ｂでは、半導体リレー２は、発光素子２１及び受光素子２２を用いることで、一対の入力端２０１，２０２と一対の出力端２１１，２１２との間を電気的に絶縁している。つまり、半導体リレー２は、１次側（一対の入力端子１０１，１０２側）と２次側（一対の出力端子１１１，１１２側）とを電気的に絶縁する絶縁部２１，２２を備えているといえる。この絶縁部２１，２２は、他の構成であってもよい。たとえば、半導体リレー２は、発光素子２１及び受光素子２２の代わりにキャパシタを用いることで、一対の入力端２０１，２０２と一対の出力端２１１，２１２との間を電気的に絶縁する構成であってもよい。なお、キャパシタを用いる場合、半導体リレー２は、半導体スイッチ２３，２４を駆動するためのドライブ回路をさらに備える必要がある。 In the switch device 1B of the present embodiment, the semiconductor relay 2 uses the light emitting element 21 and the light receiving element 22 to electrically connect the pair of input ends 201 and 202 and the pair of output ends 211 and 212. Insulated. That is, the semiconductor relay 2 includes the insulating portions 21 and 22 that electrically insulate the primary side (the pair of input terminals 101 and 102 side) from the secondary side (the pair of output terminals 111 and 112 side). It can be said. The insulating portions 21 and 22 may have other configurations. For example, the semiconductor relay 2 is configured to electrically insulate between the pair of input terminals 201 and 202 and the pair of output terminals 211 and 212 by using a capacitor instead of the light emitting element 21 and the light receiving element 22. May be. When using a capacitor, the semiconductor relay 2 needs to further include a drive circuit for driving the semiconductor switches 23 and 24.
　＜動作＞
　以下、本実施形態のスイッチ装置１Ｂの動作について図９を用いて説明する。なお、図１０には、電源Ａ１が直流電源である場合における本実施形態のスイッチ装置１Ｂの動作を示しているが、電源Ａ１が交流電源である場合と同様であるので、ここでは説明を省略する。ここで、図９、図１０に示す「電源電圧」は、電源Ａ１の出力電圧である。また、図９、図１０に示す「制御信号」は、第１制御信号及び第２制御信号の総称である。 <Operation>
Hereinafter, the operation of the switch device 1B of the present embodiment will be described with reference to FIG. FIG. 10 shows the operation of the switch device 1B of the present embodiment when the power source A1 is a DC power source. However, the operation is the same as that when the power source A1 is an AC power source, and the description thereof is omitted here. To do. Here, the “power supply voltage” shown in FIGS. 9 and 10 is the output voltage of the power supply A1. Moreover, the “control signal” shown in FIGS. 9 and 10 is a generic term for the first control signal and the second control signal.
　まず、時刻ｔ０において、一対の入力端子１０１，１０２に制御信号のうちオン信号が入力されると、半導体リレー２の半導体スイッチ２３，２４がオンする。このため、一対の出力端２１１，２１２間が導通し、第１電流が流れる。すると、一対の出力端子１１１，１１２間も導通するため、電源Ａ１から負荷Ｂ１への給電路が閉じ、負荷Ｂ１に電流が流れる。この時点では、メカニカルリレー３の接点部３２はオンしていない。その後、時刻ｔ０から所定時間後である時刻ｔ１（＞ｔ０）において、メカニカルリレー３の接点部３２がオンする。 First, at time t0, when an ON signal among the control signals is input to the pair of input terminals 101 and 102, the semiconductor switches 23 and 24 of the semiconductor relay 2 are turned ON. For this reason, between the pair of output ends 211 and 212 is conducted, the first current flows. Then, since the pair of output terminals 111 and 112 are also connected, the power supply path from the power source A1 to the load B1 is closed, and a current flows through the load B1. At this time, the contact portion 32 of the mechanical relay 3 is not turned on. Thereafter, at time t1 (> t0), which is a predetermined time after time t0, the contact portion 32 of the mechanical relay 3 is turned on.
　ここで、メカニカルリレー３の接点部３２がオンする際に、接点電圧は、半導体スイッチ２３，２４のドレイン－ソース間のオン抵抗での電圧降下に応じた電圧となるため、電源電圧の最大電圧と比較して小さい。このため、本実施形態のスイッチ装置１Ｂでは、半導体リレー２を用いずにメカニカルリレー３のみで給電路を閉じる場合と比較して、接点部３２のオン時に生じ得る突入電流を小さくすることができる。また、接点部３２の接触抵抗は、半導体スイッチ２３，２４のオン抵抗と比較して小さいため、電源Ａ１から負荷Ｂ１へ流れる電流の殆どが接点部３２を介して流れる。このため、本実施形態のスイッチ装置１Ｂでは、メカニカルリレー３を用いずに半導体リレー２のみで給電路を閉じる場合と比較して、半導体スイッチ２３，２４のオン抵抗での電力損失及び発熱が小さくなり、通電電流を大きくすることができる。 Here, when the contact portion 32 of the mechanical relay 3 is turned on, the contact voltage becomes a voltage corresponding to the voltage drop due to the on-resistance between the drain and source of the semiconductor switches 23 and 24. Small compared to For this reason, in the switch device 1B of the present embodiment, the inrush current that can be generated when the contact portion 32 is turned on can be reduced as compared with the case where the power supply path is closed only by the mechanical relay 3 without using the semiconductor relay 2. . Further, since the contact resistance of the contact portion 32 is smaller than the on-resistance of the semiconductor switches 23 and 24, most of the current flowing from the power source A1 to the load B1 flows through the contact portion 32. For this reason, in the switch device 1B of the present embodiment, the power loss and heat generation at the on-resistance of the semiconductor switches 23 and 24 are small compared to the case where the power supply path is closed only by the semiconductor relay 2 without using the mechanical relay 3. Thus, the energization current can be increased.
　次に、時刻ｔ２（＞ｔ１）において、一対の入力端子１０１，１０２に制御信号のうちオフ信号が入力されると、時刻ｔ２から所定時間後である時刻ｔ３（＞ｔ２）にメカニカルリレー３の接点部３２がオフする。すると、一対の出力端３１１，３１２間が非導通になることから、第２電流が流れなくなり、第１電流が流れる。この時点では、半導体リレー２の半導体スイッチ２３，２４はオフしていない。その後、時刻ｔ３からさらに所定時間後である時刻ｔ４（＞ｔ３）において、半導体リレー２の半導体スイッチ２３，２４がオフする。すると、一対の出力端子１１１，１１２間が非導通になるため、電源Ａ１から負荷Ｂ１への給電路が開き、負荷Ｂ１に電流が流れなくなる。 Next, when an off signal of the control signals is input to the pair of input terminals 101 and 102 at time t2 (> t1), the mechanical relay 3 is turned on at time t3 (> t2), which is a predetermined time after time t2. The contact part 32 is turned off. Then, since the pair of output terminals 311 and 312 becomes non-conductive, the second current does not flow and the first current flows. At this time, the semiconductor switches 23 and 24 of the semiconductor relay 2 are not turned off. Thereafter, at time t4 (> t3), which is a predetermined time after time t3, the semiconductor switches 23 and 24 of the semiconductor relay 2 are turned off. Then, since the pair of output terminals 111 and 112 become non-conductive, the power supply path from the power source A1 to the load B1 is opened, and no current flows through the load B1.
　ここで、メカニカルリレー３の接点部３２がオフする際には、半導体スイッチ２３，２４がオフしていないので、一対の出力端子１１１，１１２間には電源電圧が印加されていない。このため、本実施形態のスイッチ装置１Ｂでは、半導体リレー２の半導体スイッチ２３，２４がメカニカルリレー３の接点部３２よりも先にオフする場合と比較して、接点部３２のオフ時にアークが生じ難い。これは、電源Ａ１が直流電源である場合に、とくに有効である。 Here, when the contact portion 32 of the mechanical relay 3 is turned off, the power supply voltage is not applied between the pair of output terminals 111 and 112 because the semiconductor switches 23 and 24 are not turned off. For this reason, in the switch device 1B of the present embodiment, an arc is generated when the contact portion 32 is turned off, compared to the case where the semiconductor switches 23 and 24 of the semiconductor relay 2 are turned off before the contact portion 32 of the mechanical relay 3. hard. This is particularly effective when the power source A1 is a DC power source.
　上述のように、本実施形態のスイッチ装置１Ｂは、一対の入力端子１０１，１０２に制御信号のうちオン信号を入力するときは、メカニカルリレー３の接点部３２よりも先に半導体リレー２の半導体スイッチ２３，２４がオンするように制御されるのが望ましい。つまり、本実施形態のスイッチ装置１Ｂは、優先オン制御を実行できるのが望ましい。そこで、本実施形態のスイッチ装置１Ｂでは、半導体リレー２の半導体スイッチ２３，２４のターンオン時間が、メカニカルリレー３の接点部３２の動作時間と比較して短いという特性を利用している。このため、本実施形態のスイッチ装置１Ｂでは、半導体リレー２及びメカニカルリレー３を個別に制御せずとも、１つの制御信号により優先オン制御を実現することができる。 As described above, the switch device 1 </ b> B of the present embodiment has the semiconductor relay 2 semiconductor prior to the contact portion 32 of the mechanical relay 3 when an ON signal among the control signals is input to the pair of input terminals 101 and 102. It is desirable to control the switches 23 and 24 to be turned on. That is, it is desirable that the switch device 1B of the present embodiment can execute the priority on control. Therefore, the switch device 1B of the present embodiment utilizes the characteristic that the turn-on time of the semiconductor switches 23 and 24 of the semiconductor relay 2 is shorter than the operation time of the contact portion 32 of the mechanical relay 3. For this reason, in the switch device 1B of the present embodiment, the priority on control can be realized by one control signal without individually controlling the semiconductor relay 2 and the mechanical relay 3.
　また、本実施形態のスイッチ装置１Ｂでは、上述のように、一対の入力端子１０１，１０２に制御信号のうちオフ信号が入力されるときは、半導体スイッチ２３，２４よりも先に接点部３２がオフするように制御されるのが望ましい。つまり、本実施形態のスイッチ装置１Ｂは、優先オフ制御を実行できるのが望ましい。ここで、通常であれば、半導体スイッチ２３，２４のターンオフ時間は、接点部３２の復帰時間よりも短くなるため、半導体スイッチ２３，２４が接点部３２よりも先にオフしてしまう。 Further, in the switch device 1B of the present embodiment, as described above, when the off signal among the control signals is input to the pair of input terminals 101 and 102, the contact portion 32 is provided before the semiconductor switches 23 and 24. It is desirable to be controlled to turn off. That is, it is desirable that the switch device 1B of the present embodiment can perform priority off control. Here, normally, since the turn-off time of the semiconductor switches 23 and 24 is shorter than the return time of the contact portion 32, the semiconductor switches 23 and 24 are turned off before the contact portion 32.
　そこで、本実施形態のスイッチ装置１Ｂでは、制御信号（第１制御信号）のうちオフ信号が入力されると、インピーダンス回路２６の第２経路Ｓ２を介して半導体スイッチ２３，２４のゲート容量を放電する。つまり、インピーダンス素子２６１を介して半導体スイッチ２３，２４のゲート容量を放電することにより、時定数を大きくし、半導体スイッチ２３，２４のターンオン時間が接点部３２の復帰時間よりも長くなるようにしている。このため、本実施形態のスイッチ装置１Ｂでは、半導体リレー２及びメカニカルリレー３を個別に制御せずとも、１つの制御信号により優先オフ制御を実現することができる。 Therefore, in the switch device 1B of the present embodiment, when an off signal is input from the control signal (first control signal), the gate capacitances of the semiconductor switches 23 and 24 are discharged through the second path S2 of the impedance circuit 26. To do. That is, by discharging the gate capacitances of the semiconductor switches 23 and 24 via the impedance element 261, the time constant is increased so that the turn-on time of the semiconductor switches 23 and 24 is longer than the return time of the contact portion 32. Yes. For this reason, in the switch apparatus 1B of this embodiment, priority off control is realizable by one control signal, without controlling the semiconductor relay 2 and the mechanical relay 3 separately.
　ただし、インピーダンス素子２６１を介して半導体スイッチ２３，２４のゲート容量を充電させると、半導体スイッチ２３，２４のターンオン時間が接点部３２の動作時間よりも長くなる虞がある。そこで、本実施形態のスイッチ装置１Ｂでは、制御信号（第１制御信号）のうちオン信号が入力されるときは、インピーダンス回路２６の第１経路Ｓ１を介して半導体スイッチ２３，２４のゲート容量を充電する。つまり、制御信号のうちオン信号が入力されるときは、インピーダンス素子２６１を介さずに半導体スイッチ２３，２４のゲート容量が充電されるので、半導体スイッチ２３，２４のターンオン時間が長くなるのを防ぐことができる。 However, if the gate capacitances of the semiconductor switches 23 and 24 are charged via the impedance element 261, the turn-on time of the semiconductor switches 23 and 24 may be longer than the operation time of the contact part 32. Therefore, in the switch device 1B of the present embodiment, when an ON signal is input from among the control signals (first control signals), the gate capacitances of the semiconductor switches 23 and 24 are set via the first path S1 of the impedance circuit 26. Charge. That is, when an ON signal is input from among the control signals, the gate capacitances of the semiconductor switches 23 and 24 are charged without going through the impedance element 261, so that the turn-on time of the semiconductor switches 23 and 24 is prevented from becoming long. be able to.
　つまり、本実施形態では、制御回路４Ｂは、半導体スイッチ２３，２４を制御することで、半導体スイッチ２３，２４がオンからオフになるタイミングを、メカニカルリレー３の接点部３２がオンからオフになるタイミングよりも遅らせるように構成されている。また、本実施形態では、制御回路４Ｂは、半導体スイッチ２３，２４を制御することで、半導体スイッチ２３，２４がオフからオンになるタイミングを、メカニカルリレー３の接点部３２がオフからオンになるタイミングよりも早めるように構成されている。 That is, in the present embodiment, the control circuit 4B controls the semiconductor switches 23 and 24, so that the contact point 32 of the mechanical relay 3 is turned off from the on time when the semiconductor switches 23 and 24 are turned off. It is configured to be delayed from the timing. In the present embodiment, the control circuit 4B controls the semiconductor switches 23 and 24, so that the contact point 32 of the mechanical relay 3 is turned on from the off time when the semiconductor switches 23 and 24 are turned on. It is configured to be earlier than the timing.
　もちろん、本実施形態のスイッチ装置１Ｂは、制御信号（第１制御信号）のうちオン信号が入力されるときに、インピーダンス回路２６の第２経路Ｓ２を介して半導体スイッチ２３，２４のゲート容量を充電するように構成されていてもよい。この構成では、制御回路４Ｂは、半導体スイッチ２３，２４を制御することで、半導体スイッチ２３，２４がオフからオンになるタイミングを、メカニカルリレー３の接点部３２がオフからオンになるタイミングよりも遅らせる構成となる。 Of course, the switch device 1B of the present embodiment has the gate capacitances of the semiconductor switches 23 and 24 via the second path S2 of the impedance circuit 26 when an ON signal is input from among the control signals (first control signals). It may be configured to charge. In this configuration, the control circuit 4B controls the semiconductor switches 23 and 24 so that the timing at which the semiconductor switches 23 and 24 are turned on is set to be higher than the timing at which the contact portion 32 of the mechanical relay 3 is turned on from off. It will be delayed.
　＜効果＞
　上述のように、本実施形態のスイッチ装置１Ｂは、充放電経路２５及びインピーダンス回路２６を有する制御回路４Ｂを備えている。そして、本実施形態のスイッチ装置１Ｂでは、制御回路４Ｂを備えることにより、半導体リレー２及びメカニカルリレー３を個別に制御せずとも、１つの制御信号で優先オン制御及び優先オフ制御を実現することができる。そして、本実施形態のスイッチ装置１Ｂでは、半導体リレー２を第１制御信号で、メカニカルリレー３を第２制御信号で個別に制御してもよい。つまり、本実施形態のスイッチ装置１Ｂは、制御の自由度を高くすることができる。 <Effect>
As described above, the switch device 1B of the present embodiment includes the control circuit 4B having the charge / discharge path 25 and the impedance circuit 26. In the switch device 1B of the present embodiment, by providing the control circuit 4B, the priority on control and the priority off control are realized by one control signal without individually controlling the semiconductor relay 2 and the mechanical relay 3. Can do. In the switch device 1B of the present embodiment, the semiconductor relay 2 may be individually controlled with the first control signal and the mechanical relay 3 may be individually controlled with the second control signal. That is, the switch device 1B of the present embodiment can increase the degree of freedom of control.
　とくに、本実施形態のスイッチ装置１Ｂでは、半導体リレー２及びメカニカルリレー３は、１つの制御信号により制御される。言い換えれば、本実施形態のスイッチ装置１Ｂでは、第１制御信号及び第２制御信号が同じである。この構成では、半導体リレー２及びメカニカルリレー３の各々を制御するタイミングをずらすといった複雑な制御が不要であり、制御が容易になるという利点がある。つまり、この構成では、半導体リレー２及びメカニカルリレー３を組み合わせたハイブリッドリレーを、１つの制御信号で容易に制御することができる。なお、当該構成を採用するか否かは任意である。 In particular, in the switch device 1B of the present embodiment, the semiconductor relay 2 and the mechanical relay 3 are controlled by one control signal. In other words, in the switch device 1B of the present embodiment, the first control signal and the second control signal are the same. In this configuration, there is an advantage that complicated control such as shifting the timing of controlling each of the semiconductor relay 2 and the mechanical relay 3 is unnecessary, and control becomes easy. That is, in this configuration, a hybrid relay in which the semiconductor relay 2 and the mechanical relay 3 are combined can be easily controlled with one control signal. Note that whether or not to adopt the configuration is arbitrary.
　また、本実施形態のスイッチ装置１Ｂでは、半導体リレー２は、発光素子２１と、受光素子２２とを備えている。そして、半導体スイッチ２３，２４は、受光素子２２の発生する光起電力によりオン／オフするように構成されている。このため、本実施形態のスイッチ装置１Ｂでは、入出力間の電位差が半導体スイッチ２３，２４のオン／オフに影響し難いという利点がある。なお、半導体リレー２に当該構成を採用するか否かは任意である。 Further, in the switch device 1B of the present embodiment, the semiconductor relay 2 includes a light emitting element 21 and a light receiving element 22. The semiconductor switches 23 and 24 are configured to be turned on / off by the photovoltaic force generated by the light receiving element 22. For this reason, the switch device 1 </ b> B of this embodiment has an advantage that the potential difference between the input and output hardly affects the on / off of the semiconductor switches 23 and 24. Note that whether or not to adopt the configuration for the semiconductor relay 2 is arbitrary.
　ところで、インピーダンス回路２６は、図８に示す構成に限定されず、他の構成であってもよい。たとえば、インピーダンス回路２６は、図１１に示すように、抵抗Ｒ１（インピーダンス素子２６１）と、スイッチング素子Ｑ１（スイッチ２６２）とで構成されていてもよい。 Incidentally, the impedance circuit 26 is not limited to the configuration shown in FIG. 8, and may have other configurations. For example, as shown in FIG. 11, the impedance circuit 26 may include a resistor R1 (impedance element 261) and a switching element Q1 (switch 262).
　抵抗Ｒ１は、図８に示す構成と同様に、受光素子２２の低電位側の一端と、半導体スイッチ２３，２４のソースとの間に電気的に接続される。スイッチング素子Ｑ１は、ｎチャネルのエンハンスメント型ＭＯＳＦＥＴである。スイッチング素子Ｑ１のゲートは、受光素子２２の高電位側の一端に電気的に接続されている。スイッチング素子Ｑ１のドレインは、半導体スイッチ２３，２４のソースに電気的に接続されている。スイッチング素子Ｑ１のソースは、受光素子２２の低電位側の一端に電気的に接続されている。 The resistor R1 is electrically connected between one end on the low potential side of the light receiving element 22 and the sources of the semiconductor switches 23 and 24, similarly to the configuration shown in FIG. The switching element Q1 is an n-channel enhancement type MOSFET. The gate of the switching element Q1 is electrically connected to one end of the light receiving element 22 on the high potential side. The drain of the switching element Q1 is electrically connected to the sources of the semiconductor switches 23 and 24. The source of the switching element Q1 is electrically connected to one end of the light receiving element 22 on the low potential side.
　この構成では、一対の入力端２０１，２０２に第１制御信号のうちオン信号が入力されると、スイッチング素子Ｑ１がオンするため、スイッチング素子Ｑ１を介する経路（つまり、第１経路Ｓ１）に電流が流れる。また、一対の入力端２０１，２０２に第１制御信号のうちオフ信号が入力されると、スイッチング素子Ｑ１がオフするため、抵抗Ｒ１を介する経路（つまり、第２経路Ｓ２）に電流が流れる。 In this configuration, when an ON signal among the first control signals is input to the pair of input terminals 201 and 202, the switching element Q1 is turned on, and thus a current flows through the path through the switching element Q1 (that is, the first path S1). Flows. Further, when an off signal of the first control signals is input to the pair of input terminals 201 and 202, the switching element Q1 is turned off, and thus a current flows through a path via the resistor R1 (that is, the second path S2).
　また、インピーダンス回路２６は、たとえば図１２に示すように、抵抗Ｒ１（インピーダンス素子２６１）と、キャパシタＣ１（インピーダンス素子２６１）と、ダイオードＤ１（スイッチ２６２）とで構成されていてもよい。抵抗Ｒ１及びダイオードＤ１は、図８に示す構成と同様である。キャパシタＣ１は、抵抗Ｒ１に並列に電気的に接続される。 Further, as shown in FIG. 12, for example, the impedance circuit 26 may include a resistor R1 (impedance element 261), a capacitor C1 (impedance element 261), and a diode D1 (switch 262). The resistor R1 and the diode D1 are the same as those shown in FIG. Capacitor C1 is electrically connected in parallel with resistor R1.
　つまり、インピーダンス素子２６１は、容量素子（ここでは、キャパシタＣ１）を含んでいてもよい。この構成では、インピーダンス素子２６１を単に抵抗のみで構成する場合と比較して、より効果的に半導体スイッチ２３，２４のターンオフ時間を長くすることができる。なお、図１２に示す構成では、インピーダンス素子２６１は、抵抗Ｒ１及びキャパシタＣ１で構成されているが、キャパシタＣ１のみで構成されていてもよい。 That is, the impedance element 261 may include a capacitive element (here, the capacitor C1). In this configuration, the turn-off time of the semiconductor switches 23 and 24 can be more effectively increased as compared with the case where the impedance element 261 is configured only by a resistor. In the configuration shown in FIG. 12, the impedance element 261 is configured by the resistor R1 and the capacitor C1, but may be configured by only the capacitor C1.
　なお、本実施形態のスイッチ装置１Ｂは、第１制御信号（第２制御信号）がハイレベルのときに半導体スイッチ２３，２４（接点部３２）がオンする構成であるが、他の構成であってもよい。すなわち、本実施形態のスイッチ装置１Ｂは、第１制御信号（第２制御信号）がローレベルのときに半導体スイッチ２３，２４（接点部３２）がオンするように構成されていてもよい。この場合、「第１制御信号（第２制御信号）のうちオン信号が入力される」とは「第１制御信号（第２制御信号）がローレベルになる」ことを意味する。さらに、「第１制御信号（第２制御信号）のうちオフ信号が入力される」とは「第１制御信号（第２制御信号）がハイレベルになる」ことを意味する。 Note that the switch device 1B of the present embodiment has a configuration in which the semiconductor switches 23 and 24 (contact point portion 32) are turned on when the first control signal (second control signal) is at a high level, but the other configuration. May be. That is, the switch device 1B of the present embodiment may be configured such that the semiconductor switches 23 and 24 (contact points 32) are turned on when the first control signal (second control signal) is at a low level. In this case, “the ON signal is input from among the first control signals (second control signals)” means “the first control signal (second control signal) is at a low level”. Furthermore, “the off signal of the first control signal (second control signal) is input” means “the first control signal (second control signal) becomes high level”.
　ところで、本実施形態のスイッチ装置１Ｂは、実施形態１の制御回路４や実施形態１の変形例の制御回路４Ａをさらに備えていてもよい。この場合も、半導体リレー２及びメカニカルリレー３を個別に制御せずとも、１つの制御信号で優先オン制御及び優先オフ制御を実現することが可能である。 Incidentally, the switch device 1B of the present embodiment may further include the control circuit 4 of the first embodiment and the control circuit 4A of a modification of the first embodiment. Also in this case, it is possible to realize the priority on control and the priority off control with one control signal without individually controlling the semiconductor relay 2 and the mechanical relay 3.
　以上述べた実施形態から明らかなように、本発明の第１の態様に係るスイッチ装置（１，１Ａ，１Ｂ）は、半導体リレー（２）と、メカニカルリレー（３）と、制御回路（４，４Ａ，４Ｂ）とを備えている。半導体リレー（２）は、電源（Ａ１）から負荷（Ｂ１）への給電路を開閉する。メカニカルリレー（３）は、半導体リレー（２）と並列に電気的に接続される接点部（３２）を有し、外部から入力される制御信号に応じて接点部（３２）をオン／オフすることにより給電路を開閉する。制御回路（４，４Ａ，４Ｂ）は、制御信号を受けて半導体リレー（２）を制御する。 As is clear from the embodiment described above, the switch device (1, 1A, 1B) according to the first aspect of the present invention includes a semiconductor relay (2), a mechanical relay (3), a control circuit (4, 4). 4A, 4B). The semiconductor relay (2) opens and closes a power feeding path from the power source (A1) to the load (B1). The mechanical relay (3) has a contact portion (32) electrically connected in parallel with the semiconductor relay (2), and turns on / off the contact portion (32) according to a control signal input from the outside. This opens and closes the feed path. The control circuit (4, 4A, 4B) receives the control signal and controls the semiconductor relay (2).
　半導体リレー（２）は、半導体スイッチ（２Ｂ，２３，２４）を有している。半導体スイッチ（２Ｂ，２３，２４）は、容量成分に蓄積される電荷に応じてオン／オフすることで給電路を開閉する。制御回路（４，４Ａ，４Ｂ）は、半導体スイッチ（２Ｂ，２３，２４）を制御することで、半導体スイッチ（２Ｂ，２３，２４）がオンからオフになるタイミングを、メカニカルリレー（３）の接点部（３２）がオンからオフになるタイミングよりも遅らせるように構成されている。 The semiconductor relay (2) has semiconductor switches (2B, 23, 24). The semiconductor switches (2B, 23, 24) open / close the power supply path by turning on / off according to the electric charge accumulated in the capacitive component. The control circuit (4, 4A, 4B) controls the semiconductor switch (2B, 23, 24) so that the timing at which the semiconductor switch (2B, 23, 24) is turned off is turned on. The contact portion (32) is configured to be delayed from the timing when the contact portion (32) is turned off.
　また、本発明の第２の態様に係るスイッチ装置（１Ａ，１Ｂ）では、第１の態様において、制御回路（４Ａ，４Ｂ）は、半導体スイッチ（２Ｂ，２３，２４）を制御することで、半導体スイッチ（２Ｂ，２３，２４）がオフからオンになるタイミングを、メカニカルリレー（３）の接点部（３２）がオフからオンになるタイミングよりも早めるように構成されている。 In the switch device (1A, 1B) according to the second aspect of the present invention, in the first aspect, the control circuit (4A, 4B) controls the semiconductor switch (2B, 23, 24), The timing at which the semiconductor switch (2B, 23, 24) is turned on from off is configured to be earlier than the timing at which the contact portion (32) of the mechanical relay (3) is turned on from off.
　また、本発明の第３の態様に係るスイッチ装置（１）では、第１の態様において、制御回路（４）は、半導体スイッチ（２Ｂ）を制御することで、半導体スイッチ（２Ｂ）がオフからオンになるタイミングを、メカニカルリレー（３）の接点部（３２）がオフからオンになるタイミングよりも遅らせるように構成されている。 In the switch device (1) according to the third aspect of the present invention, in the first aspect, the control circuit (4) controls the semiconductor switch (2B) so that the semiconductor switch (2B) is turned off. The timing of turning on is configured to be delayed from the timing of turning on the contact portion (32) of the mechanical relay (3).
　また、本発明の第４の態様に係るスイッチ装置（１，１Ａ，１Ｂ）では、第１～第３のいずれかの態様において、半導体リレー（２）は、１次側と２次側とを電気的に絶縁する絶縁部（２Ａ，２Ｃ，２１，２２）をさらに有する。 In the switch device (1, 1A, 1B) according to the fourth aspect of the present invention, in any of the first to third aspects, the semiconductor relay (2) has a primary side and a secondary side. It further has an insulating part (2A, 2C, 21, 22) for electrical insulation.
　また、本発明の第５の態様に係るスイッチ装置（１，１Ａ）では、第４の態様において、制御回路（４，４Ａ）は、１次側に設けられて、制御信号を遅延させ、遅延した制御信号を半導体リレー（２）に出力する遅延回路（５，５Ａ）を有する。 In the switch device (1, 1A) according to the fifth aspect of the present invention, in the fourth aspect, the control circuit (4, 4A) is provided on the primary side to delay the control signal, A delay circuit (5, 5A) for outputting the control signal to the semiconductor relay (2).
　また、本発明の第６の態様に係るスイッチ装置（１，１Ａ）では、第５の態様において、制御回路（４，４Ａ）は、遅延回路（５，５Ａ）を介して制御信号が入力され、制御信号の電圧が閾値電圧に達すると制御信号を出力するように構成されているバッファ回路（６）をさらに有する。 In the switch device (1, 1A) according to the sixth aspect of the present invention, in the fifth aspect, the control circuit (4, 4A) receives a control signal via the delay circuit (5, 5A). And a buffer circuit (6) configured to output the control signal when the voltage of the control signal reaches the threshold voltage.
　また、本発明の第７の態様に係るスイッチ装置（１Ｂ）は、第４～第６のいずれかの態様において、制御信号に応じて容量成分を充電及び放電する充放電経路（２５）をさらに備える。制御回路（４Ｂ）は、２次側に設けられて、充放電経路（２５）に電気的に接続されるインピーダンス回路（２６）を有する。インピーダンス回路（２６）は、インピーダンス素子（２６１）を有する。そして、インピーダンス回路（２６）は、制御信号のうちオン信号が入力されると充放電経路（２５）を第１経路（Ｓ１）に接続し、制御信号のうちオフ信号が入力されると充放電経路（２５）をインピーダンス素子（２６１）を含む第２経路（Ｓ２）に接続するように構成されている。 The switch device (1B) according to the seventh aspect of the present invention further includes a charge / discharge path (25) for charging and discharging the capacitive component according to the control signal in any of the fourth to sixth aspects. Prepare. The control circuit (4B) includes an impedance circuit (26) provided on the secondary side and electrically connected to the charge / discharge path (25). The impedance circuit (26) has an impedance element (261). The impedance circuit (26) connects the charge / discharge path (25) to the first path (S1) when an ON signal is input from among the control signals, and charges / discharges when an OFF signal is input from among the control signals. The path (25) is configured to be connected to the second path (S2) including the impedance element (261).
　また、本発明の第８の態様に係るスイッチ装置（１Ｂ）では、第７の態様において、インピーダンス素子（２６１）は、容量素子（キャパシタ（Ｃ１））を含む。 In the switch device (1B) according to the eighth aspect of the present invention, in the seventh aspect, the impedance element (261) includes a capacitive element (capacitor (C1)).
　また、本発明の第９の態様に係るスイッチ装置（１Ｂ）では、第７又は第８の態様において、絶縁部（２１，２２）は、制御信号を受けて発光する発光素子（２１）と、発光素子（２１）の発する光に応じて光起電力を発生する受光素子（２２）とを備える。 Further, in the switch device (1B) according to the ninth aspect of the present invention, in the seventh or eighth aspect, the insulating portion (21, 22) receives the control signal and emits light (21), A light receiving element (22) that generates a photovoltaic force in response to light emitted from the light emitting element (21).
　スイッチ装置（１，１Ａ，１Ｂ）は、制御回路（４，４Ａ，４Ｂ）を備えることにより、半導体リレー（２）とメカニカルリレー（３）とに個別に制御信号を与えずとも、半導体リレー（２）とメカニカルリレー（３）との相互の開閉の時間差を設けることができる。したがって、本発明は、半導体リレー（２）及びメカニカルリレー（３）を組み合わせたハイブリッドリレーを、１つの制御信号で容易に制御することができる。
  Since the switch device (1, 1A, 1B) includes the control circuit (4, 4A, 4B), the semiconductor relay (2) and the mechanical relay (3) can be provided with a semiconductor relay ( 2) A time difference between opening and closing of the mechanical relay (3) can be provided. Therefore, the present invention can easily control a hybrid relay in which the semiconductor relay (2) and the mechanical relay (3) are combined with one control signal.

Claims (9)

  1. 　電源から負荷への給電路を開閉する半導体リレーと、
    　前記半導体リレーと並列に電気的に接続される接点部を有し、外部から入力される制御信号に応じて前記接点部をオン／オフすることにより前記給電路を開閉するメカニカルリレーと、
    　前記制御信号を受けて前記半導体リレーを制御する制御回路とを備え、
    　前記半導体リレーは、
    　容量成分に蓄積される電荷に応じてオン／オフすることで前記給電路を開閉する半導体スイッチを有し、
    　前記制御回路は、前記半導体スイッチを制御することで、前記半導体スイッチがオンからオフになるタイミングを、前記メカニカルリレーの前記接点部がオンからオフになるタイミングよりも遅らせるように構成されていることを特徴とするスイッチ装置。     A semiconductor relay that opens and closes the power supply path from the power source to the load;
    A mechanical relay that has a contact portion electrically connected in parallel with the semiconductor relay, and opens and closes the power supply path by turning on and off the contact portion according to a control signal input from the outside;
    A control circuit for receiving the control signal and controlling the semiconductor relay;
    The semiconductor relay is
    A semiconductor switch that opens and closes the power supply path by turning on and off according to the charge accumulated in the capacitive component;
    The control circuit is configured to control the semiconductor switch to delay the timing at which the semiconductor switch is turned on from the timing at which the contact portion of the mechanical relay is turned from on to off. A switch device characterized by.
  2. 　前記制御回路は、前記半導体スイッチを制御することで、前記半導体スイッチがオフからオンになるタイミングを、前記メカニカルリレーの前記接点部がオフからオンになるタイミングよりも早めるように構成されていることを特徴とする請求項１記載のスイッチ装置。 The control circuit is configured to control the semiconductor switch so that the timing at which the semiconductor switch is turned on is earlier than the timing at which the contact portion of the mechanical relay is turned on from off. The switch device according to claim 1.
  3. 　前記制御回路は、前記半導体スイッチを制御することで、前記半導体スイッチがオフからオンになるタイミングを、前記メカニカルリレーの前記接点部がオフからオンになるタイミングよりも遅らせるように構成されていることを特徴とする請求項１記載のスイッチ装置。 The control circuit is configured to control the semiconductor switch to delay the timing at which the semiconductor switch is turned on from the timing at which the contact portion of the mechanical relay is turned on from off. The switch device according to claim 1.
  4. 　前記半導体リレーは、１次側と２次側とを電気的に絶縁する絶縁部をさらに有することを特徴とする請求項１乃至３のいずれか１項に記載のスイッチ装置。 The switch device according to any one of claims 1 to 3, wherein the semiconductor relay further includes an insulating portion that electrically insulates the primary side and the secondary side.
  5. 　前記制御回路は、前記１次側に設けられて、前記制御信号を遅延させ、遅延した前記制御信号を前記半導体リレーに出力する遅延回路を有することを特徴とする請求項４記載のスイッチ装置。 5. The switch device according to claim 4, wherein the control circuit includes a delay circuit provided on the primary side, delaying the control signal, and outputting the delayed control signal to the semiconductor relay.
  6. 　前記制御回路は、前記遅延回路を介して前記制御信号が入力され、前記制御信号の電圧が閾値電圧に達すると前記制御信号を出力するように構成されているバッファ回路をさらに有することを特徴とする請求項５に記載のスイッチ装置。 The control circuit further includes a buffer circuit configured to receive the control signal via the delay circuit and to output the control signal when the voltage of the control signal reaches a threshold voltage. The switch device according to claim 5.
  7. 　前記制御信号に応じて前記容量成分を充電及び放電する充放電経路をさらに備え、
    　前記制御回路は、前記２次側に設けられて、前記充放電経路に電気的に接続されるインピーダンス回路を有し、
    　前記インピーダンス回路は、インピーダンス素子を有し、前記制御信号のうちオン信号が入力されると前記充放電経路を第１経路に接続し、前記制御信号のうちオフ信号が入力されると前記充放電経路を前記インピーダンス素子を含む第２経路に接続するように構成されていることを特徴とする請求項４乃至６のいずれか１項に記載のスイッチ装置。     A charge / discharge path for charging and discharging the capacitance component in response to the control signal;
    The control circuit includes an impedance circuit provided on the secondary side and electrically connected to the charge / discharge path;
    The impedance circuit includes an impedance element, and connects the charge / discharge path to the first path when an ON signal is input from among the control signals, and charges / discharges when an OFF signal is input from among the control signals. The switch device according to claim 4, wherein the switch device is configured to connect a route to a second route including the impedance element.
  8. 　前記インピーダンス素子は、容量素子を含むことを特徴とする請求項７記載のスイッチ装置。 The switch device according to claim 7, wherein the impedance element includes a capacitive element.
  9. 　前記絶縁部は、
    　前記制御信号を受けて発光する発光素子と、
    　前記発光素子の発する光に応じて光起電力を発生する受光素子とを備えることを特徴とする請求項７又は８に記載のスイッチ装置。     The insulating part is
    A light emitting element that emits light in response to the control signal;
    The switch device according to claim 7, further comprising: a light receiving element that generates a photovoltaic power according to light emitted from the light emitting element.
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