WO2016192321A1 - Procédé et dispositif de correction d'ambiguïté de phase, et support de stockage informatique - Google Patents

Procédé et dispositif de correction d'ambiguïté de phase, et support de stockage informatique Download PDF

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Publication number
WO2016192321A1
WO2016192321A1 PCT/CN2015/094926 CN2015094926W WO2016192321A1 WO 2016192321 A1 WO2016192321 A1 WO 2016192321A1 CN 2015094926 W CN2015094926 W CN 2015094926W WO 2016192321 A1 WO2016192321 A1 WO 2016192321A1
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WO
WIPO (PCT)
Prior art keywords
phase
blur correction
subframe
phase blur
training sequence
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Application number
PCT/CN2015/094926
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English (en)
Chinese (zh)
Inventor
秦文平
何开江
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深圳市中兴微电子技术有限公司
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Publication of WO2016192321A1 publication Critical patent/WO2016192321A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying

Definitions

  • the invention relates to a phase blur correction technology, in particular to a phase blur correction method and device, and a computer storage medium.
  • Optical fiber transmission has a core position in long-distance transmission networks due to its large throughput, low unit capacity and high reliability.
  • the cost of fiber construction is high. How to use limited fiber resources to increase data throughput is a goal that network operators are pursuing.
  • DSP Digital Signal Processing
  • QPSK Quadrature Phase Shift Keying
  • phase blurring occurs due to a specific algorithm. How to monitor and correct the phase ambiguity effect of this QPSK adjustment mode, and implement it on the ASIC, so that low power consumption and configurability need to be solved.
  • an embodiment of the present invention provides a phase blur correction method and apparatus, and a computer storage medium.
  • the received data is subjected to QPSK phase blur correction using the phase blur correction factor.
  • the phase correction correction factor is used to perform QPSK phase blur correction on the received data, including:
  • the data received in parallel is buffered by the signal
  • the QPSK phase blur correction is performed on the delayed buffer data by using the calculated phase blur correction factor.
  • the phase blur correction factor is obtained by comparing the phase of the frame header symbol of the subframe with the phase of the known subframe header, including:
  • the phase blur correction factor is calculated by the difference between the calculated phase and the phase of the known sub-frame header.
  • the method further includes:
  • the position where the QPSK phase blur correction is performed is determined by the control of the effective depth of the buffer unit, and the position of the QPSK phase blur correction is between any symbols from the previous subframe to the current subframe.
  • the method further includes:
  • the input signal is signal gated by an enable signal to remove the invalid transition.
  • the receiving unit is configured to receive a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values;
  • a determining unit configured to determine a frame header position of each subframe in the training sequence
  • phase blur correction factor unit configured to obtain a phase blur correction factor by comparing a phase of the frame header symbol of the subframe with a phase of a known subframe frame header
  • a correction unit configured to perform QPSK phase blur correction on the received data by using the phase blur correction factor.
  • the correcting unit includes:
  • a cache subunit configured to buffer data received in parallel
  • a calculating subunit configured to calculate a phase blur correction factor according to the received data when the frame header indication signal of the subframe is valid
  • the correction subunit is configured to perform QPSK phase blur correction on the delayed buffered data using the calculated phase blur correction factor.
  • the phase blur correction factor unit is further configured to calculate a phase of each symbol in the frame header of the sub-frame in parallel; and calculate a difference between the calculated phase and the phase of the known sub-frame header. A phase blur correction factor is obtained.
  • the device further includes:
  • a first control unit configured to determine, by a control of an effective depth of the buffer unit, a position where the QPSK phase blur correction is performed, where the position of the QPSK phase blur correction is between any symbol between the previous subframe and the current subframe .
  • the device includes:
  • a second control unit configured to enable an input signal by an enable signal when the subframe header is not reached The signal is gated to remove invalid transitions.
  • the computer storage medium provided by the embodiment of the present invention stores a computer program for executing the phase blur correction method described above.
  • the QPSK phase blur is corrected by inserting a training sequence on the transmitting side and detecting the training sequence on the receiving side.
  • the training sequence sent by the sending side is received, where the training sequence includes multiple subframes, and the length and segmentation of each subframe in the training sequence are configured as set values; and the frame header of each subframe in the training sequence is determined.
  • a phase blur correction factor obtained by comparing a phase of the frame header symbol of the subframe with a phase of a known subframe header; using the phase blur correction factor to perform quadrature phase shift keying on the received data QPSK phase blur correction.
  • the length of the training sequence is fixed, the interval may be fixed, or may be fixed in segments, the content of the training sequence is configurable, and is also known to the receiving end.
  • the position for phase correction is configurable, and compensation can be performed from any position before the previous subframe and before the current subframe.
  • the phase blur correction factor is calculated by using a parallel circuit to minimize the calculation delay, thereby reducing the data buffer depth and reducing the circuit area.
  • the power consumption of the device is further reduced by methods such as signal gating.
  • FIG. 1 is a schematic flow chart of a phase blur correction method according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a training sequence according to an embodiment of the present invention.
  • FIG. 3 is a block diagram of a circuit for calculating a phase blur correction factor according to an embodiment of the present invention
  • variable depth buffer 4 is a schematic diagram of a variable depth buffer for performing stepwise selection on an input side according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a variable depth buffer for performing stepwise selection on an output side according to an embodiment of the present invention
  • Figure 6 is a general block diagram of a correction circuit in accordance with an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a phase blur correction apparatus according to an embodiment of the present invention.
  • phase blur correction method includes the following steps:
  • Step 101 Receive a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values.
  • an optical transport network (OTN) network using a QSPK modulation mode is required to insert a special training sequence on the transmitting side in order to correct the phase ambiguity introduced by the QPSK frequency offset and the phase offset adjustment algorithm at the receiving end. That is, a so-called sub-frame is constructed.
  • the design of the training sequence has the following characteristics:
  • the high throughput of the OTN 100G DSP chip is under the current technical conditions, the main frequency of a single set of circuits can not be processed, and multiple sets of parallel circuits are needed for processing.
  • the length of the training sequence and the length of the internal subframe are designed as integer multiples of the number of parallel circuits, which can effectively reduce the processing difficulty.
  • the overhead caused by the training sequence must be less than 1%.
  • the length and segmentation of each subframe can be flexibly matched, and the ratio of the length of the training sequence can be selected before and after the subframe is inserted into the training sequence to facilitate the selection of the PLL.
  • there are a plurality of subframes there are a plurality of subframes. The ratio of the frame length before and after the insertion of the sub-frame is small enough to facilitate the selection of the Phase Locked Loop (PLL) and reduce its cost.
  • PLL Phase Locked Loop
  • Figure 2 is one of the frame structures produced in accordance with the above constraints.
  • Step 102 Determine a frame header position of each subframe in the training sequence.
  • the structure of the training sequence is transparent to the receiving side. Therefore, pick up After receiving the frame header of the training sequence, the receiving side can locate the frame header position of each subframe, and can obtain the phase blur correction factor by calculating the phase of the frame header symbol of the subframe and comparing with the phase of the known subframe frame header. And then perform QPSK phase blur correction on the received data.
  • Step 103 Obtain a phase blur correction factor by comparing the phase of the frame header symbol of the subframe with the phase of the known subframe header.
  • the position of the QPSK phase blur correction is determined by the control of the effective depth of the buffer unit, and the position of the QPSK phase blur correction is between any symbols from the previous subframe to the current subframe.
  • the input signal is gated by the enable signal to remove the invalid jump.
  • the phase is calculated in parallel for each symbol in the frame header of the sub-frame; and the phase blur correction factor is calculated by calculating the difference between the phase and the phase of the known sub-frame header.
  • the input signal is gated by the enable signal EN to remove the invalid jump.
  • the phase of the sub-frame header is calculated in parallel, the difference between the phase and the known phase is calculated, the radians are adjusted to the range of 2 ⁇ , and the unit vector is obtained, and then the unit vector is accumulated to obtain a vector. Then, the phase is obtained, and finally the correction factor is determined.
  • the use of parallel circuits sacrifices a small amount of resources in the factor calculation unit, in exchange for the significant resource savings of the signal buffer unit.
  • the embodiment of the present invention supports the data before the subframe. Correction is made, and the correction can start from any symbol between the previous subframe and the current subframe. The flexibility of this calibration starting point is achieved by the control of the effective depth of the buffer unit.
  • FIG. 4 is a variable depth buffer selected step by step on the input side
  • FIG. 5 is a variable depth buffer selected step by step on the output side, with respect to a common variable depth buffer uniformly selected on the output side
  • FIG. 4 and FIG. 5 are more advantageous for the ASIC (Application Specific Integrated Circuit) routing, which reduces the possibility of wiring congestion.
  • ASIC Application Specific Integrated Circuit
  • Step 104 Perform quadrature phase shift keying QPSK phase blur correction on the received data by using the phase blur correction factor.
  • the data received in parallel is buffered; when the header indication signal of the subframe is valid, the phase fuzzy correction factor is calculated according to the received data; and the calculated phase fuzzy correction factor is used.
  • the QPSK phase blur correction is performed on the delayed buffer data.
  • Fig. 6 is an overall block diagram of the correction circuit. The following only describes the correction process of the X polarization state, and the Y polarization state is similar: the data entering in parallel enters the X polarization state signal buffer. Meanwhile, if the frame header indication signal is valid, the first 8 symbols of the input data are taken and sent to the X polarization state factor calculation module. The delayed data from the X-polarization signal buffer module is entered into the X-polarization phase correction module together with the correction factor calculated by the X-polarization factor calculation unit to perform QPSK phase blur correction.
  • the structure of the training sequence may be reselected according to the multiplication ratio of the PLL, and the length of the training sequence and the length of the subframe are equal to the number of parallel circuits of the circuit for implementation, and the starting point of the correction is flexible and configurable. And it is beneficial to ASIC implementation, and effectively controls the power consumption when the circuit is idling.
  • FIG. 7 is a phase blur correction apparatus according to an embodiment of the present invention. As shown in FIG. 7, the apparatus includes:
  • the receiving unit 71 is configured to receive a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values;
  • a determining unit 72 configured to determine a frame header position of each subframe in the training sequence
  • the phase blur correction factor unit 73 is configured to obtain a phase blur correction factor by comparing the phase of the frame header symbol of the subframe with the phase of the known subframe frame header;
  • the correcting unit 74 is configured to perform quadrature phase shift keying QPSK phase blur correction on the received data by using the phase blur correction factor.
  • the correcting unit 74 includes:
  • the buffer subunit 741 is configured to buffer the data received in parallel
  • the calculating subunit 742 is configured to calculate a phase blur correction factor according to the received data when the frame header indication signal of the subframe is valid;
  • the correction sub-unit 743 is configured to perform QPSK phase blur correction on the delayed buffer data using the calculated phase blur correction factor.
  • the phase blur correction factor unit 73 is further configured to calculate the phase of each symbol in the frame header of the sub-frame in parallel; and the difference between the calculated phase and the phase of the known sub-frame header, The phase blur correction factor is calculated.
  • the device further includes:
  • the first control unit 75 is configured to determine, by the control of the effective depth of the buffer unit, the position where the QPSK phase blur correction is performed, where the position of the QPSK phase blur correction is any symbol from the previous subframe to the current subframe. between.
  • the device includes:
  • the second control unit 76 is configured to perform signal gating on the input signal by the enable signal when the subframe frame header is not reached to remove the invalid jump.
  • each unit and its subunits in the phase blur correction apparatus shown in FIG. 7 can be understood by referring to the related description of the phase blur correction method described above.
  • the functions of each unit and its subunits in the phase blur correction apparatus shown in FIG. 7 can be realized by a program running on a processor, or can be realized by a specific logic circuit.
  • each unit module in the phase blur correction device may be implemented by a central processing unit.
  • CPU Central Processing Unit
  • DSP Digital Signal Processor
  • FPGA Field-Programmable Gate Array
  • the apparatus for tracking the service signaling may also be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a separate product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • program codes such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • an embodiment of the present invention further provides a computer storage medium, wherein a computer program for executing the phase blur correction method of the embodiment of the present invention is stored.
  • the disclosed method and smart device may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place.
  • the party may also be distributed to multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one second processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un procédé et un dispositif de correction d'ambiguïté de phase, ainsi qu'un support de stockage informatique. Le procédé consiste : à recevoir une séquence d'apprentissage transmise par un côté transmission, la séquence d'apprentissage comprenant une pluralité de sous-trames, et des longueurs et des segmentations de chaque sous-trame dans la séquence d'apprentissage étant configurées sous la forme de valeurs réglées ; à déterminer des positions d'en-têtes de trame de chaque sous-trame dans la séquence d'apprentissage ; à acquérir un facteur de correction d'ambiguïté de phase par calcul d'une phase de symbole d'en-tête de trame de la sous-trame et comparaison de cette dernière à une phase d'en-tête de sous-trame connue ; et à réaliser une correction d'ambiguïté de phase par modulation par déplacement de phase quadrivalente (QPSK) sur des données reçues par utilisation du facteur de correction d'ambiguïté de phase.
PCT/CN2015/094926 2015-06-03 2015-11-18 Procédé et dispositif de correction d'ambiguïté de phase, et support de stockage informatique WO2016192321A1 (fr)

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CN114116195A (zh) * 2021-10-11 2022-03-01 北京遥测技术研究所 一种基于mpi和多线程的qpsk解相位模糊器

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CN108667522B (zh) * 2017-03-30 2020-12-11 深圳市中兴微电子技术有限公司 一种实现相位跳变检测与纠正的方法及装置
CN110417427A (zh) * 2018-04-27 2019-11-05 晨星半导体股份有限公司 相位回复电路及方法

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Publication number Priority date Publication date Assignee Title
CN114116195A (zh) * 2021-10-11 2022-03-01 北京遥测技术研究所 一种基于mpi和多线程的qpsk解相位模糊器
CN114116195B (zh) * 2021-10-11 2024-05-14 北京遥测技术研究所 一种基于mpi和多线程的qpsk解相位模糊器

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