WO2016190127A1 - Capteur d'image, procédé de traitement et dispositif électronique - Google Patents

Capteur d'image, procédé de traitement et dispositif électronique Download PDF

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Publication number
WO2016190127A1
WO2016190127A1 PCT/JP2016/064211 JP2016064211W WO2016190127A1 WO 2016190127 A1 WO2016190127 A1 WO 2016190127A1 JP 2016064211 W JP2016064211 W JP 2016064211W WO 2016190127 A1 WO2016190127 A1 WO 2016190127A1
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Prior art keywords
pixel
pixels
processing unit
read
signal
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PCT/JP2016/064211
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English (en)
Japanese (ja)
Inventor
弘康 近藤
清茂 辻
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2016190127A1 publication Critical patent/WO2016190127A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present technology relates to an image sensor, a processing method, and an electronic device, and more particularly, to an image sensor, a processing method, and an electronic device that can prevent, for example, image quality deterioration.
  • VSL Vertical Signal Line
  • the pixel region of the pixel array unit having pixels arranged in a matrix is divided into two upper and lower pixel regions.
  • An image sensor (hereinafter also referred to as a divided VSL sensor) in which VSL is separately provided in each of the upper pixel region and the lower pixel region has been proposed (see, for example, Patent Document 1). ).
  • a column processing unit that processes a signal read from a pixel and outputs a pixel value is provided in each of the upper and lower pixel regions.
  • the pixel processing in the upper pixel region is processed in the column processing unit in the upper pixel region, and the pixels in the lower pixel region are processed in the column processing unit in the lower pixel region.
  • Signals can be processed, and pixel values can be output at high speed.
  • the interface with the split VSL sensor may be a low-speed interface due to restrictions on the processor and memory that make up the interface. In this case, with a low-speed interface, it may be difficult to receive pixel values output simultaneously by the column processing units in the upper and lower pixel regions.
  • pixel signal processing and pixel value output can be alternately performed by the column processing units in the upper and lower pixel regions.
  • the pixel values output from the divided VSL sensor can be received through a low-speed interface.
  • the pixel signal processing is performed, so that the division VSL sensor obtains.
  • the resulting image may have horizontal stripes, shading, etc., and the image quality may deteriorate.
  • the present technology has been made in view of such a situation, and is intended to prevent deterioration in image quality of an image.
  • An image sensor or an electronic apparatus includes a pixel array unit including a pixel that outputs a signal that is a pixel value of an image and a dummy pixel, and a first and a first that process a signal read from the pixel. 2 processing units, one of the first processing unit and the second processing unit processes a signal read from the pixel, and the other processing unit from the dummy pixel.
  • a pixel array unit including a pixel that outputs a signal that is a pixel value of an image and a dummy pixel, and a first and a first that process a signal read from the pixel.
  • a processing method includes a pixel array unit including pixels that output signals serving as pixel values of an image and dummy pixels, and first and second processing units that process signals read from the pixels.
  • One processing unit of the first and second processing units of the image sensor including the above processes a signal read from the pixel, and the other processing unit reads from the dummy pixel.
  • a processing method including processing the received signal.
  • An image sensor, a processing method, and an electronic device process a signal read from the pixel of a pixel array unit including a pixel that outputs a signal that is a pixel value of an image and a dummy pixel.
  • the signal read from the pixel is processed in one of the second processing units, and the signal read from the dummy pixel is processed in the other processing unit.
  • the image sensor may be an independent device or an internal block constituting one device.
  • FIG. 2 is a block diagram illustrating a configuration example of an image sensor 2.
  • FIG. 3 is a block diagram illustrating a detailed configuration example of a pixel access unit 11.
  • FIG. 3 is a circuit diagram illustrating a configuration example of a pixel 41.
  • FIG. 6 is a diagram illustrating an example of the operation of the pixel access unit 11.
  • FIG. It is a timing chart explaining operation of column processing parts 23N and 23S. It is a timing chart explaining the fall of a power supply voltage which arises when the column process part 23S starts operation
  • 6 is a diagram illustrating another example of the operation of the pixel access unit 11.
  • FIG. 6 is a diagram illustrating a first example of the operation of the pixel access unit 11.
  • FIG. It is a timing chart explaining operation of column processing parts 71N and 71S. 6 is a diagram illustrating a second example of the operation of the pixel access unit 11.
  • FIG. It is a timing chart explaining operation of column processing parts 71N and 71S. 11 is a diagram for explaining a third example of the operation of the pixel access unit 11.
  • FIG. It is a timing chart explaining operation of column processing parts 71N and 71S. 11 is a diagram for explaining a fourth example of the operation of the pixel access unit 11.
  • FIG. 1 is a block diagram illustrating a configuration example of an embodiment of a camera unit to which the present technology is applied.
  • the camera unit can capture both still images and moving images.
  • the camera unit includes an optical system 1, an image sensor 2, a memory 3, a signal processing unit 4, an output unit 5, and a control unit 6.
  • the optical system 1 has, for example, a zoom lens, a focus lens, a diaphragm, and the like (not shown), and makes light from the outside enter the image sensor 2.
  • the image sensor 2 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor that receives incident light from the optical system 1, performs photoelectric conversion, and outputs image data corresponding to the incident light from the optical system 1. To do.
  • CMOS Complementary Metal Oxide Semiconductor
  • the memory 3 temporarily stores image data output from the image sensor 2.
  • the signal processing unit 4 performs processing such as noise removal and white balance adjustment as signal processing using the image data stored in the memory 3 and supplies the processed signal to the output unit 5.
  • the output unit 5 outputs the image data from the signal processing unit 4.
  • the output unit 5 has a display (not shown) made of, for example, liquid crystal, and displays an image corresponding to the image data from the signal processing unit 4 as a so-called through image.
  • the output unit 5 includes a driver (not shown) that drives a recording medium such as a semiconductor memory, a magnetic disk, or an optical disk, and records the image data from the signal processing unit 4 on the recording medium.
  • a driver (not shown) that drives a recording medium such as a semiconductor memory, a magnetic disk, or an optical disk, and records the image data from the signal processing unit 4 on the recording medium.
  • the control unit 6 controls each block constituting the camera unit in accordance with a user operation or the like.
  • the image sensor 2 receives incident light from the optical system 1 and outputs image data according to the incident light.
  • the image data output from the image sensor 2 is supplied to and stored in the memory 3.
  • the image data stored in the memory 3 is subjected to signal processing by the signal processing unit 4, and the resulting image data is supplied to the output unit 5 and output.
  • FIG. 2 is a block diagram showing a configuration example of the image sensor 2 of FIG.
  • the image sensor 2 includes a pixel access unit 11, a column I / F (Interface) unit 12, a signal processing unit 13, and a timing control unit 14.
  • the pixel access unit 11 includes a pixel 41 (FIG. 3) that performs photoelectric conversion, accesses the pixel 41, and acquires and outputs a pixel value that is image data.
  • the pixel access unit 11 includes a pixel array unit 21, a row control unit 22, and column processing units 23N and 23S.
  • the pixel array unit 21 is configured by regularly arranging a plurality of pixels 41 that output electrical signals by photoelectric conversion in two dimensions.
  • the pixel array unit 21 reads out an electrical signal from the pixels 41 constituting the pixel array unit 21 under the control of the row control unit 22 and supplies it to the column processing units 23N and 23S.
  • the row control unit 22 performs access control for reading electrical signals from the pixels 41 of the pixel array unit 21.
  • the column processing units 23N and 23S perform processing such as AD (Analog-to-Digital) conversion and CDS (Correlated-Double Sampling) of the electric signal (voltage) read and supplied from the pixels 41 of the pixel array unit 21, The resulting digital signal is supplied (output) to the column I / F unit 12 as a pixel value.
  • AD Analog-to-Digital
  • CDS Correlated-Double Sampling
  • the column I / F unit 12 has a built-in memory (not shown), and temporarily stores pixel values from the pixel access unit 11 (column processing units 23N and 23S thereof), thereby receiving the pixel values.
  • the signal processing unit 13 performs, for example, pixel rearrangement, pixel centroid correction, and other necessary signal processing using the pixel values stored in the column I / F unit 12 (memory built therein). And output to the outside of the image sensor 2 (for example, the memory 3 (FIG. 1)).
  • the timing control unit 14 generates a timing signal for controlling the operation timing of each block constituting the image sensor 2 and supplies the timing signal to a necessary block.
  • FIG. 3 is a block diagram illustrating a detailed configuration example of the pixel access unit 11 of FIG.
  • the pixel access unit 11 includes the pixel array unit 21, the row control unit 22, and the column processing units 23N and 23S.
  • the pixel array section 21 is configured by regularly arranging two or more pixels 41 in two dimensions. In FIG. 2, two or more pixels 41 are arranged in a matrix.
  • the pixels 41 are arranged in a matrix, but the arrangement of the pixels 41 is not limited to the matrix arrangement. That is, for example, the pixels 41 may be arranged such that the even-numbered pixels 41 are arranged at a position shifted from the odd-numbered pixels 41 by a half of the horizontal interval between the pixels 41. it can.
  • the pixels 41 arranged in a two-dimensional manner are provided with, for example, a Bayer array color filter (not shown) as a predetermined color array.
  • a pixel 41 as a Gb pixel that receives G (Green) component light is located at the upper left
  • a pixel 41 as an R pixel that receives R (Red) component light is located at the upper right.
  • a pixel 41 as a Gr pixel that receives light of G component are arranged in the lower right, respectively.
  • a pixel is a basic unit, and the basic unit is repeatedly arranged horizontally and vertically.
  • the pixels 41 arranged in a two-dimensional manner are, for example, the pixels 41 in the upper pixel region 21N and the pixels in the lower pixel region 21S as the pixels of the first and second groups. 41.
  • VSLs are wired in the column direction (vertical direction) for each column of the pixels 41.
  • the VSL is divided into a VSL 42N in the upper pixel region 21N and a VSL 42S in the lower pixel region 21S, and the VSL 42N and 42S are not (physically) connected.
  • the VSL 42N in each column of the upper pixel region 21N is connected to the pixel 41 in the upper pixel region 21N and the upper column processing unit 23N in the left column of the VSL 42N.
  • the VSL 42S in each column of the lower pixel area 21S is connected to the pixel 41 in the lower pixel area 21S and the lower column processing unit 23S in the left column of the VSL 42S.
  • a pixel signal that is an electrical signal read from the pixel 41 in the upper pixel region 21N is supplied to the upper column processing unit 23N via the VSL 42N. Further, a pixel signal that is an electrical signal read from the pixel 41 in the lower pixel region 21S is supplied to the lower column processing unit 23S via the VSL 42S.
  • the VSL 42N in each column connected to the pixel 41 in the upper pixel region 21N is connected to the column processing unit 23N, and the VSL 42S in each column connected to the pixel 41 in the lower pixel region 21S.
  • the pixel access unit 11 includes, for example, one row of pixels 41 in the upper pixel region 21N and one row of pixels 41 in the lower pixel region 21S. The pixel signals can be read and processed simultaneously.
  • a pixel signal read from one row of pixels 41 in the upper pixel area 21N can be supplied to the column processing unit 23N via the VSL 42N for processing.
  • pixel signals read from one row of pixels 41 in the lower pixel region 21S can be supplied to the column processing unit 23S via the VSL 42S for processing.
  • pixel signals read from two rows of pixels 41 that is, one row of pixels 41 in the upper pixel region 21N and one row of pixels 41 in the lower pixel region 21S. Can be processed simultaneously.
  • control signal lines 43 are wired in the row direction (left-right direction) for each row of the pixels 41.
  • the control signal line 43 in each row is connected to the pixel 41 in the lower row of the control signal line 43 and the row control unit 22.
  • the row control unit 22 performs access control on the pixels 41 in each row by supplying (flowing) a control signal to the control signal line 43.
  • the column processing unit 23N includes, for example, the same number of ADCs (AD Converters) 51N as the number of columns of the pixels 41 constituting the pixel array unit 21.
  • the x-th ADC 51N performs AD conversion and CDS of the pixel signal supplied from the x-th column pixel 41 of the upper pixel region 21N via the x-th row VSL 42N.
  • the ADC 51N outputs a digital pixel signal as a pixel value obtained as a result of AD conversion or the like to the column I / F unit 12 (FIG. 2).
  • the column processing unit 23S has X ADCs 51S, which is the same number as the column number X of the pixels 41 constituting the pixel array unit 21, similarly to the column processing unit 23N.
  • the x-th ADC 51S is connected to the x-th column VSL 42S. Therefore, the x-th ADC 51S reads out from the x-th column pixel 41 of the lower pixel region 21S. The pixel signal is supplied via the VSL 42S in the x-th column.
  • the x-th ADC 51S performs AD conversion of a pixel signal supplied from the pixel 41 in the x-th column of the lower pixel region 21S via the VSL 42N in the x-th column.
  • the ADC 51S outputs a pixel value which is a digital pixel signal as a pixel value obtained as a result of AD conversion or the like to the column I / F unit 12 (FIG. 2).
  • one ADC 51N is provided for one column of pixels 41 in the column processing unit 23N.
  • one ADC 51N can be provided for a plurality of columns of pixels 41.
  • FIG. 4 is a circuit diagram illustrating a configuration example of the pixel 41.
  • 4 includes a pixel unit 61 and a reading unit 62.
  • the pixel unit 61 includes a PD (Photo diode) 63 and a FET (Field Effect Transistor) 64.
  • the pixel unit 61 receives light incident thereon and photoelectrically converts the light to output charges corresponding to the light.
  • the readout unit 62 includes an FET 65, an FD (Floating Diffusion) 66, and FETs 67 and 68, and reads out a pixel signal corresponding to the electric charge obtained in the pixel unit 61 from the pixel unit 61 onto the VSL 42N or 42S.
  • the FETs 64, 65, 67, and 68 are configured by NMOS (NNchannel Metal Oxide Semiconductor).
  • the PD 63 receives the incident light and performs photoelectric conversion for accumulating charges corresponding to the incident light.
  • the anode of the PD 63 is connected to the ground (grounded), and the cathode of the PD 63 is connected to the source of the FET 64.
  • the FET 64 is a transistor (Tr) for transferring the charge accumulated in the PD 63 from the PD 63 to the FD 66, and is also referred to as a transfer Tr 64 hereinafter.
  • the source of the transfer Tr 64 is connected to the cathode of the PD 63, and the drain of the transfer Tr 64 is connected to the gate of the FET 64 via the FD 66.
  • the gate of the transfer Tr 64 is connected to the control signal line 43, and the transfer pulse TRG is supplied to the gate of the transfer Tr 64 via the control signal line 43.
  • the transfer pulse TRG is one of the control signals that the row control unit 22 (FIG. 3) passes through the control signal line 43 in order to drive (access control) the pixel 41 via the control signal line 43. is there.
  • Control signals that the row control unit 22 (FIG. 3) passes through the control signal line 43 include a transfer pulse TRG, a reset pulse RST, and a selection pulse SEL, which will be described later.
  • the FET 65 is a transistor for resetting the electric charge (voltage (potential)) accumulated in the FD 66, and hereinafter also referred to as a reset Tr 65.
  • the drain of the reset Tr 65 is connected to the power supply Vdd, and the source is connected to the FD 66.
  • the gate of the reset Tr 65 is connected to the control signal line 43, and the reset pulse RST is supplied to the gate of the reset Tr 65 via the control signal line 43.
  • the FD 66 is a region formed at the connection point between the source of the FET 65 and the gate of the FET 67. In the FD 66, the charge supplied thereto is converted into a voltage as a pixel signal like a capacitor.
  • the FET 67 is a transistor for buffering (amplifying) the voltage of the FD 66, and hereinafter also referred to as an amplifying Tr 67.
  • the gate of the amplification Tr 67 is connected to the FD 66, and the drain of the amplification Tr 67 is connected to the power supply Vdd.
  • the source of the amplification Tr 67 is connected to the drain of the FET 68.
  • the FET 68 is an FET for selecting the output of the pixel signal (the voltage of the FD 66) to the VSL 42N or 42S, and is hereinafter also referred to as a selection Tr 68.
  • the source of the selected Tr 68 is connected to the VSL 42N or 42S.
  • the gate of the selection Tr 68 is connected to the control signal line 43, and the selection pulse SEL is supplied to the gate of the selection Tr 68 via the control signal line 43.
  • a current source (not shown) is connected to the VSLs 42N and 42S connected to the source of the selected Tr 68, and this current source and the amplified Tr 67 are SF (Source (Follower) via the selected Tr 68.
  • the circuit is configured. Therefore, the FD 66 is connected to the VSL 42N or 42S via the SF circuit.
  • the pixel 41 can be configured without the selection Tr 68.
  • the drain of the reset Tr 65 and the drain of the amplification Tr 67 are connected to the same power source Vdd, but the drain of the reset Tr 65 and the drain of the amplification Tr 67 may be connected to different power sources. it can.
  • the configuration of the pixel 41 for example, a configuration of a shared pixel in which a plurality of pixel units 61 such as four or eight is provided in the pixel 41 and the readout unit 62 is shared by the plurality of pixel units 61 is adopted. can do.
  • a plurality of FDs 66 such as two are provided in the reading unit 62, and one FD 66 of the two FDs 66 is shared by the pixel unit 61 that is half of the plurality of pixel units 61, and the other FD 66 is shared.
  • the FD 66 can be shared by the remaining half of the pixel unit 61.
  • the PD 63 receives light incident thereon and performs photoelectric conversion to start accumulation of electric charges according to the amount of received incident light.
  • the selection pulse SEL is at the H level and the selection Tr 68 is in the ON state.
  • the row control unit 22 temporarily sets the reset pulse RST to the H level (from the L (Low) level to the H (High) level), thereby turning the reset Tr 65 on temporarily.
  • the FD 66 When the reset Tr 65 is turned on, the FD 66 is connected to the power supply Vdd via the reset Tr 65, and the charge in the FD 66 is swept out to the power supply Vdd via the reset Tr 65 and reset.
  • the row control unit 22 After the charge of the FD 66 is reset, the row control unit 22 temporarily sets the transfer pulse TRG to the H level, whereby the transfer Tr 64 is temporarily turned on.
  • the transfer Tr 64 When the transfer Tr 64 is turned on, the charge stored in the PD 63 is transferred to the FD 66 after reset via the transfer Tr 64 and stored.
  • a voltage (potential) corresponding to the charge accumulated in the FD 66 is output as a pixel signal on the VSL 42N or 42S via the amplification Tr 67 and the selection Tr 68.
  • the reset level that is the pixel signal on the VSL 42N or 42S immediately after the pixel 41 is reset is AD-converted.
  • a level and a level to be a pixel value are AD-converted.
  • CDS Correlated Double Sampling
  • FIG. 5 is a diagram for explaining an example of the operation of the pixel access unit 11 of FIG.
  • the pixel array unit 21 is configured by eight rows of pixels 41, and the upper four rows of pixels 41 configure the upper pixel region 21 ⁇ / b> N and the lower four The pixels 41 in the row constitute the lower pixel region 21S. Therefore, in FIG. 5, one frame is composed of 8 (horizontal) lines.
  • FIG. 5 illustration of portions other than the pixel 41 of the pixel access unit 11 and the column processing units 23N and 23S is omitted.
  • the column processing units 23 ⁇ / b> N and 23 ⁇ / b> S include two pixels 41 in the upper pixel region 21 ⁇ / b> N and two pixels 41 in the lower pixel region 21 ⁇ / b> S. Pixel signals read from the pixels 41 in a row can be processed simultaneously.
  • the memory 3 (FIG. 1) as an interface with the image sensor 2 in FIG. 2 is a low-speed interface
  • the memory 3 is simultaneously processed by the column processing units 23N and 23S and output. It may be difficult to receive the pixel signal being processed.
  • pixel signal processing and output can be alternately performed by the column processing units 23N and 23S.
  • the pixel signals are alternately output from the column processing units 23N and 23S, the pixel signal output from the image sensor 2 can be received in the memory 3 that is a low-speed interface.
  • FIG. 5 shows an example of reading a pixel signal from the pixel 41 when the pixel processing and output are alternately performed by the column processing units 23N and 23S.
  • readout of pixel signals from the eight rows of pixels 41 constituting the pixel array unit 21 is performed alternately for the pixels 41 in the upper pixel region 21N and the pixels 41 in the lower pixel region 21S. Done in units.
  • the readout of the pixel signals constituting the frame is performed in the 8th row, the 1st row, the 7th row, and the 2nd row among the 8 rows of pixels 41 constituting the pixel array unit 21. This is performed in the readout order of the pixels 41 in the first, sixth, third, fifth, and fourth rows.
  • Pixel signals read from the pixels 41 in the first to fourth rows, which are the pixels 41 in the upper pixel area 21N, are supplied to the upper column processing unit 23N, and the pixels 41 in the lower pixel area 21S.
  • Pixel signals read from the pixels 41 in the eighth row are supplied to the lower column processing unit 23S.
  • the upper column processing unit 23N processes the pixel signals read from the pixels 41 in the first to fourth rows
  • the lower column processing unit 23S processes the pixels read from the pixels 41 in the fifth to eighth rows. The signal is processed.
  • the column processing unit 23N processes the pixel signal read from the pixels 41 in the upper pixel region 21N in units of rows, and the column processing unit 23S performs the unit of rows from the pixels 41 in the lower pixel region 21S.
  • the processing of the pixel signal read out in (3) is alternately performed.
  • FIG. 6 illustrates the column processing unit 23N when pixel signals are read out in units of rows alternately from the pixels 41 of the upper pixel region 21N and the lower pixel region 21S. It is a timing chart explaining operation of 23S.
  • the head timing signal is a signal that represents the start timing of processing of one line as an L level. The same applies to the drawings described later.
  • pixel signals are read out from the pixels 41 in the eighth row, the first row, the seventh row, the second row, the sixth row, the third row, the fifth row, and the fourth row. It is performed in the reading order (order).
  • the pixel signals read from the pixels 41 in the first to fourth rows are supplied to the upper column processing unit 23N and processed.
  • the pixel signals read from the pixels 41 in the fifth to eighth rows are supplied to the lower column processing unit 23S for processing.
  • the upper column processing unit 23N processes the pixel signals read from the pixels 41 in the first to fourth rows, so that the pixel signals are in the second, fourth, sixth, and eighth reading order timings. It operates when read from the pixels 41 in the first to fourth rows.
  • the upper column processing unit 23N does not process the pixel signals read from the pixels 41 in the fifth to eighth rows, the pixel signals are in the first, third, fifth, and seventh timings of reading order. , When reading from the pixels 41 in the 8th to 5th rows, respectively.
  • the lower column processing unit 23S processes the pixel signals read from the pixels 41 in the 5th to 8th rows, so that the pixel signals are read at the timing of the first, third, fifth and seventh reading orders. , Operates when read out from the pixels 41 in the 8th to 5th rows.
  • the lower column processing unit 23S does not process the pixel signals read from the pixels 41 in the first to fourth rows, the pixel signals are read in the second, fourth, sixth, and eighth timings of reading order. Thus, when reading from the pixels 41 in the first to fourth rows, the operation stops.
  • FIG. 7 is a timing chart for explaining the power supply voltage drop that occurs when the lower column processing unit 23S starts operation.
  • the power supply voltage of the column processing unit 23S is reduced from VDD by the IR drop due to the IR drop.
  • the power supply voltage of the column processing unit 23S varies until the settling time elapses after the column processing unit 23S enters the operating state.
  • the fluctuation of the power supply voltage of the column processing unit 23S affects the pixel signal processing in the column processing unit 23S, that is, for example, AD conversion of the pixel signal, and may cause an error in the AD conversion result. As a result, horizontal streaks, shading, etc. may occur in the image obtained by the image sensor 2 and the image quality may deteriorate.
  • FIG. 8 is a diagram for explaining another example of the operation of the pixel access unit 11 of FIG.
  • FIG. 8 shows another example of reading out the pixel signal from the pixel 41 when the processing and output of the pixel signal are alternately performed by the column processing units 23N and 23S.
  • pixel signals are read out in units of rows alternately for all the pixels 41 in the upper pixel region 21N and for all the pixels 41 in the lower pixel region 21S. .
  • the readout of the pixel signals constituting the frame is the 8th row, the 7th row, the 6th row, the 5th row, the 4th row among the 8 rows of pixels 41 constituting the pixel array unit 21. This is performed in the order of pixels 41 in the first, third, second, and first rows (reading order).
  • Pixel signals read from the pixels 41 in the first to fourth rows, which are the pixels 41 in the upper pixel area 21N, are supplied to the upper column processing unit 23N, and the pixels 41 in the lower pixel area 21S.
  • Pixel signals read from the pixels 41 in the eighth row are supplied to the lower column processing unit 23S.
  • the upper column processing unit 23N processes the pixel signals read from the pixels 41 in the first to fourth rows
  • the lower column processing unit 23S processes the pixels read from the pixels 41 in the fifth to eighth rows. The signal is processed.
  • the column processing unit 23S processes the pixel signals read out in units of rows from the pixels 41 in the lower pixel region 21S for all the pixels 41 in the lower pixel region 21S, and the column processing unit 23N
  • the pixel signals read from the pixels 41 in the upper pixel region 21N in units of rows are alternately processed for all the pixels 41 in the upper pixel region 21N.
  • pixel signals are read out in units of rows from all the pixels 41 in the upper pixel region 21N and from all the pixels 41 in the lower pixel region 21S. It is a timing chart explaining operation
  • pixel signals are read out from the pixels 41 in the eighth row, the seventh row, the sixth row, the fifth row, the fourth row, the third row, the second row, and the first row. Done in order.
  • the pixel signals read from the pixels 41 in the first to fourth rows are supplied to the upper column processing unit 23N and processed.
  • the pixel signals read from the pixels 41 in the fifth to eighth rows are supplied to the lower column processing unit 23S for processing.
  • the upper column processing unit 23N processes the pixel signals read from the pixels 41 in the first to fourth rows, so that the pixel signals are transferred to the fourth to first rows at the timing of the fifth to eighth reading orders. Operates when read from each pixel 41 of the eye.
  • the upper column processing unit 23N does not process the pixel signals read from the pixels 41 in the 5th to 8th rows, the pixel signals are 8th to 5th at the timing of the 1st to 4th readout order. Stops when reading from each pixel 41 in the row.
  • the lower column processing unit 23S processes the pixel signals read from the pixels 41 in the 5th to 8th rows, so that the pixel signals are 8th to 5th in the timing of the 1st to 4th readout order. It operates when it is read from each pixel 41 in the row.
  • the lower column processing unit 23S since the lower column processing unit 23S does not process the pixel signals read from the pixels 41 in the first to fourth rows, the pixel signals are read out at the timing of the fifth to eighth reading orders for the frame. When read from the pixels 41 in the fourth or first row, the operation stops.
  • the upper column processing unit 23N is in a stopped state until the pixel signal is read from the pixel 41 in the fifth row at the timing of the fourth readout order.
  • the upper column processing unit 23N changes from the stopped state to the operating state.
  • noise in a fixed pattern such as a step, a horizontal stripe, and shading is generated in a portion corresponding to the boundary between the upper pixel region 21N and the lower pixel region 21S of the image obtained by the image sensor 2.
  • noise in a fixed pattern such as a step, a horizontal stripe, and shading is generated in a portion corresponding to the boundary between the upper pixel region 21N and the lower pixel region 21S of the image obtained by the image sensor 2.
  • the pixel signal is read out from the pixel 41 in the bottom row of the eight rows 41 constituting the pixel array unit 21 toward the upper row.
  • the pixel signal can be read out, for example, from the first pixel 41 in the uppermost row toward the lower row.
  • the lower column processing unit 23S changes from the stopped state to the operating state.
  • the power supply voltage of the column processing unit 23S fluctuates, and the image quality of the image obtained by the image sensor 2 is deteriorated.
  • FIG. 10 is a block diagram showing another detailed configuration example of the pixel access unit 11 of FIG.
  • the pixel access unit 11 in FIG. 10 includes a pixel array unit 21, a row control unit 22, and column processing units 71N and 71S.
  • the pixel access unit 11 in FIG. 10 has the pixel array unit 21 and the row control unit 22 in common with the case of FIG.
  • the pixel access unit 11 of FIG. 10 is different from the case of FIG. 3 in that it has column processing units 71N and 71S instead of the column processing units 23N and 23S.
  • the pixel access unit 11 of FIG. 10 is different from the case of FIG. 3 in that the pixel array unit 21 has dummy pixels 81.
  • the pixel array unit 21 outputs pixel signals that are not employed in the pixel values that constitute the image, in addition to the pixels 41 that output pixel signals that are the pixel values that constitute the image (hereinafter also referred to as normal pixels) 41.
  • a dummy pixel (hereinafter also referred to as a dummy pixel) 81 is provided.
  • the uppermost pixel which is one row with the upper pixel region 21 ⁇ / b> N, is a dummy pixel 81.
  • the pixel in the lowermost row which is one row having the lower pixel region 21 ⁇ / b> S, is the dummy pixel 81.
  • the dummy pixel 81 it is effective to stabilize the operation of the image sensor 2 if a pixel having the same (equivalent) configuration as the normal pixel 41 is physically disposed.
  • the dummy pixel 81 is, for example, a light-shielded pixel (a pixel in which light incident on the PD 62 (FIG. 4) is blocked) for obtaining optical black. Can be adopted.
  • the dummy pixel 81 provided in the upper pixel region 21N is connected to the VSL 42N in the same manner as the normal pixel 41 in the upper pixel region 21N.
  • a pixel signal is read from the dummy pixel 81 provided in the upper pixel area 21N and supplied to the upper column processing unit 71N via the VSL 42N.
  • the dummy pixel 81 provided in the lower pixel region 21S is connected to the VSL 42S in the same manner as the normal pixel 41 in the lower pixel region 21S.
  • the pixel signal is read from the dummy pixel 81 provided in the lower pixel region 21S in the same manner as the normal pixel 41, and is supplied to the lower column processing unit 71S via the VSL 42S.
  • the column processing unit 71N reads out pixel signals from the normal pixels 41 in the upper pixel region 21N in units of rows and processes pixel signals supplied via the VSL 42N in the same manner as the column processing unit 23N.
  • the pixel signals read out from one row of the dummy pixels 81 and supplied via the VSL 42N are processed.
  • the column processing unit 71S reads pixel signals from the normal pixels 41 in the lower pixel region 21S in units of rows and processes the pixel signals supplied via the VSL 42S in the same manner as the column processing unit 23S. A pixel signal read from one row of dummy pixels 81 in the region 21N and supplied via the VSL 42S is processed.
  • the processing result of the pixel signal of the dummy pixel 81 in the column processing units 71N and 71S is not output from the image sensor 2.
  • the processing result of the pixel signal of the dummy pixel 81 in the column processing units 71N and 71S can also be output from the image sensor 2.
  • one of the column processing units 71N and 71S processes the pixel signal read from the normal pixel 41, and the other column processing unit The pixel signal read from the dummy pixel 81 is processed.
  • the other column processing unit processes the pixel signal read from the dummy pixel 81, the pixel signal read from the normal pixel 41 is processed in FIG. It is possible to prevent the fluctuation of the power supply voltage due to the IR drop as described. As a result, it is possible to prevent the image quality of the image obtained by the image sensor 2 from deteriorating due to fluctuations in the power supply voltage.
  • FIG. 11 is a diagram for explaining a first example of the operation of the pixel access unit 11 of FIG.
  • the pixel array unit 21 is configured by 10 rows of pixels, and the upper 5 rows of pixels constitute the upper pixel region 21N and the lower 5 rows. These pixels constitute the lower pixel region 21S.
  • the pixel in the top row of the five rows of pixels in the upper pixel region 21N is a dummy pixel 81, and the remaining four rows of pixels are normal pixels 41. Yes. Further, of the five rows of pixels in the lower pixel region 21 ⁇ / b> S, the pixel in the bottom row is a dummy pixel 81, and the remaining four rows of pixels are normal pixels 41.
  • the 2nd row of pixels of the 1st row and the 10th row are the dummy pixels 81, and the 8th row of pixels of the 2nd to 9th rows are usually This is a pixel 41.
  • one frame (image) is composed of pixel values obtained from the pixel signals of the normal pixels 41 in the 8th row of the 2nd to 9th rows, that is, the pixel values of 8 lines.
  • FIG. 11 illustrations of portions other than the normal pixel 41 and the dummy pixel 81 and the column processing units 71N and 71S of the pixel access unit 11 are omitted.
  • FIG. 11 shows an example of reading a pixel signal from the pixel 41 when pixel signal processing and output are alternately performed by the column processing units 71N and 71S.
  • pixel signals are read from the normal pixels 41 in the eight rows for each of the normal pixels 41 in the upper pixel region 21 ⁇ / b> N and the normal pixels 41 in the lower pixel region 21 ⁇ / b> S. It is done alternately.
  • pixel signals are read out from the dummy pixels 81 in the first row and the second row of the tenth row, the dummy pixels 81 in the upper pixel region 21N, and the dummy pixels 81 in the lower pixel region 21S. Are alternately performed in units of rows.
  • readout of the pixel signal from the normal pixel 41 is performed in the 9th row, the 2nd row, and the 8th row among the 10 rows of pixels (the normal pixel 41 and the dummy pixel 81) constituting the pixel array unit 21. This is performed in the order (reading order) of the normal pixels 41 in the 3rd, 3rd, 7th, 4th, 6th, and 5th rows.
  • pixel signals are read alternately from the dummy pixels 81 in the first row and the tenth row.
  • the pixel signals are read from the normal pixels 41 in the ninth to sixth rows of the lower pixel region 21S, that is, the reading order of the pixel signals from the normal pixels 41 is the first, third, fifth, and seventh.
  • the pixel signal is read out from the dummy pixel 81 in the upper pixel region 21N.
  • the reading order of the pixel signals from the normal pixels 41 is the second, fourth, sixth, and eighth readings.
  • the pixel signal is read from the dummy pixel 81 in the lower pixel region 21S.
  • the pixel signals read from the normal pixels 41 in the second to fifth rows in the upper pixel region 21N are supplied to the upper column processing unit 71N, and the normal pixels 41 in the sixth to ninth rows in the lower pixel region 21S.
  • the pixel signal read from is supplied to the lower column processing unit 71S.
  • the pixel signal read from the first row of dummy pixels 81 in the upper pixel region 21N is supplied to the upper column processing unit 71N and read from the tenth row of dummy pixels 81 in the lower pixel region 21S.
  • the output pixel signal is supplied to the lower column processing unit 71S.
  • the upper column processing unit 71N processes pixel signals read from the normal pixels 41 in the second to fifth rows, and the lower column processing unit 71S reads out the normal signals 41 in the sixth to ninth rows.
  • the processed pixel signal is processed.
  • the pixel signal read from the dummy pixel 81 in the first row is processed in the upper column processing unit 71N, and the pixel read from the dummy pixel 81 in the tenth row is processed in the lower column processing unit 71S.
  • the signal is processed.
  • the column processing unit 71 ⁇ / b> N processes the pixel signal read out in units of rows from the normal pixels 41 in the upper pixel region 21 ⁇ / b> N, and the column processing unit 71 ⁇ / b> S Processing pixel signals read out in units of rows from the normal pixels 41 in the pixel region 21S on the side is alternately performed.
  • FIG. 12 illustrates the column processing unit 71N in the case where pixel signal readout in units of rows is alternately performed from the pixels 41 of the upper pixel region 21N and the lower pixel region 21S. It is a timing chart explaining operation of 71S.
  • pixel signals are read out from the normal pixels 41 in the ninth row, the second row, the eighth row, the third row, the seventh row, the fourth row, the sixth row, and the fifth row. (In reading order).
  • the pixel signals read from the normal pixels 41 in the second to fifth rows at the timings of the second, fourth, sixth, and eighth reading orders are supplied to the upper column processing unit 71N for processing.
  • the pixel signals read from the normal pixels 41 in the sixth to ninth rows at the first, third, fifth, and seventh reading order timings are supplied to the lower column processing unit 71S for processing.
  • the pixel signals read from the dummy pixels 81 in the 10th row at the timings of the second, fourth, sixth and eighth reading orders are supplied to the lower column processing unit 71S for processing.
  • the pixel signals read from the dummy pixels 81 in the first row at the first, third, fifth, and seventh reading order timings are supplied to the upper column processing unit 71N for processing.
  • the upper column processing unit 71N processes the pixel signals read from the normal pixels 41 in the second to fifth rows, so that the pixel signals are read in the second, fourth, sixth, and eighth timings of reading order. It operates when read from the normal pixels 41 in the second to fifth rows.
  • the upper column processing unit 71N has a pixel signal of 1 at the timing of the first, third, fifth, and seventh reading orders. It also operates when it is read from the dummy pixel 81 in the row (the portion indicated by “operation (dummy)” in FIG. 12).
  • the lower column processing unit 71S processes the pixel signals read from the normal pixels 41 in the 6th to 9th rows, so that the pixel signals are read out in the first, third, fifth and seventh reading order timings. Thus, it operates when it is read from each of the pixels 41 in the ninth to sixth rows.
  • the lower column processing unit 71S has a pixel signal at the timing of the second, fourth, sixth, and eighth reading orders. It also operates when it is read from the dummy pixel 81 in the 10th row (the portion indicated by “Operation (Dummy)” in FIG. 12).
  • one of the column processing units 71N and 71S operates to process the pixel signals for one row read from the normal pixels 41. Meanwhile, the other column processing unit operates to process the pixel signals for one row read from the dummy pixels 81.
  • the column processing units 71N and 71S operate constantly, the column processing units 71N and 71S prevent the fluctuation of the power supply voltage that occurs when the column processing units 71N and 71S change from the stopped state to the operating state, and the image quality is deteriorated due to the fluctuation. Can be prevented.
  • FIG. 13 is a diagram for explaining a second example of the operation of the pixel access unit 11 of FIG.
  • FIG. 13 shows an example of reading a pixel signal from the normal pixel 41 when pixel signal processing and output are alternately performed by the column processing units 71N and 71S.
  • pixel signals are read in units of rows for all the normal pixels 41 in the upper pixel region 21 ⁇ / b> N and for all the normal pixels 41 in the lower pixel region 21 ⁇ / b> S. Are performed alternately.
  • the readout of the pixel signals constituting the frame is performed in the ninth row, the eighth row, the seventh row, the sixth row, and the fifth row among the eight rows of normal pixels 41 constituting the pixel array unit 21.
  • the process is repeated in the order of the normal pixels 41 in the fourth, fourth, third, and second lines.
  • the pixel signal is read from the normal pixel 41 as the first to eighth reading orders in the 9th, 8th, 7th, 6th, 5th, 4th, 3rd, Pixel signals are read from the normal pixels 41 in the second and second rows.
  • Pixels from the normal pixels 41 in the 9th, 8th, 7th, 6th, 5th, 4th, 3rd, and 2nd rows as readouts in the 1st to 8th readout order When the signal reading, that is, the reading of the pixel signal for one frame is completed, the reading of the pixel signal of the next frame is performed.
  • the readout of the pixel signal from the normal pixel 41 in the ninth row is performed again as the readout in the ninth readout order, and the readout of the pixel signal from the regular pixel 41 in the eighth row is performed as the readout in the tenth readout order.
  • the readout is performed again, and thereafter the pixel signal is read out from the normal pixel 41 in the same manner.
  • Pixel signals read from the normal pixels 41 in the second to fifth rows, which are the pixels 41 in the upper pixel region 21N, are supplied to the upper column processing unit 71N and are the normal pixels 41 in the lower pixel region 21S.
  • Pixel signals read from the normal pixels 41 in the sixth to ninth rows are supplied to the lower column processing unit 71S.
  • the upper column processing unit 71N processes pixel signals read from the normal pixels 41 in the second to fifth rows, and the lower column processing unit 71S reads out the normal signals 41 in the sixth to ninth rows.
  • the processed pixel signal is processed.
  • the column processing unit 71S processes the pixel signals read out in units of rows from the normal pixels 41 in the lower pixel region 21S for all the normal pixels 41 in the lower pixel region 21S, and column processing.
  • the unit 71N alternately processes pixel signals read out in units of rows from the normal pixels 41 in the upper pixel region 21N for all the normal pixels 41 in the upper pixel region 21N.
  • the pixel signal is read from the normal pixel 41 in the lower pixel region 21 ⁇ / b> S, that is, the normal pixels 41 in the 1st to 4, 9, 10,...
  • the pixel signal is read from the dummy pixel 81 in the upper pixel region 21N and supplied to the upper column processing unit 71N during the period in which the pixel signal is read from the upper pixel region 21N.
  • the pixel signal is read from the normal pixel 41 in the upper pixel region 21N, that is, the pixels from the normal pixel 41 in the fifth to eighth, 13,... During the period in which the signal is read, the pixel signal is read from the dummy pixel 81 in the lower pixel region 21S and is supplied to the lower column processing unit 71S.
  • reading of pixel signals in units of rows is performed from all the normal pixels 41 in the upper pixel region 21 ⁇ / b> N, and all the normal pixels in the lower pixel region 21 ⁇ / b> S.
  • 41 is a timing chart for explaining the operation of the column processing units 71N and 71S in the case where the process from 41 is performed alternately.
  • pixel signals are read out from the normal pixels 41 in the lower pixel region 21 ⁇ / b> S at the timing of the 1st to 4, 9, 10... It is supplied to the column processing unit 71S for processing.
  • a pixel signal is read from the dummy pixel 81 in the upper pixel region 21N and supplied to the upper column processing unit 71N for processing. Is done.
  • pixel signals are read from the normal pixels 41 in the upper pixel region 21N and supplied to the upper column processing unit 71N. Processed.
  • a pixel signal is read from the dummy pixel 81 in the lower pixel region 21S and supplied to the lower column processing unit 71S for processing. Is done.
  • the upper column processing unit 71N operates to process pixel signals read from the normal pixels 41 in the second to fifth rows at the timing of the fifth to eighth, thirteenth,. .
  • the upper column processing unit 71N operates to process the pixel signals read from the dummy pixels 81 in the first row at the timing of the 1st to 4, 9, 10,. (In FIG. 14, a portion indicated by “operation (dummy)”).
  • the lower column processing unit 71S processes the pixel signals read from the normal pixels 41 in the 6th to 9th rows at the timing of the 1st to 4, 9, 10,. To work.
  • the lower column processing unit 71S operates to process the pixel signal read from the dummy pixel 81 in the 10th row at the timing of the fifth to eighth, thirteenth,.
  • FIG. 14 shows a portion indicated by “operation (dummy)”.
  • one of the column processing units 71N and 71S operates to process pixel signals for one row read from the normal pixels 41. Meanwhile, the other column processing unit operates to process the pixel signals for one row read from the dummy pixels 81.
  • the column processing units 71N and 71S operate constantly, the column processing units 71N and 71S prevent the fluctuation of the power supply voltage that occurs when the column processing units 71N and 71S change from the stopped state to the operating state, and the image quality is deteriorated due to the fluctuation. Can be prevented.
  • the pixel signal is read out from the normal pixels 41 in the bottom row out of the eight normal pixels 41 configuring the pixel array unit 21 toward the upper row.
  • the pixel signal can be read out from the uppermost normal pixel 41 toward the lower row.
  • FIG. 15 is a diagram for explaining a third example of the operation of the pixel access unit 11 of FIG.
  • FIG. 15 shows an example of reading out a pixel signal from the normal pixel 41 when pixel signal processing and output are alternately performed by the column processing units 71N and 71S.
  • pixel signals are read from the normal pixels 41 in the same manner as in FIG. 13, the ninth row, the eighth row, the seventh row, the sixth row, the fifth row, the fourth row, the third row, This is repeated in the order of the normal pixels 41 in the row.
  • the readout of the pixel signal from the normal pixel 41 in the ninth row is performed again as the readout in the ninth readout order, and the readout of the pixel signal from the regular pixel 41 in the eighth row is performed as the readout in the tenth readout order.
  • the readout is performed again, and thereafter the pixel signal is read out from the normal pixel 41 in the same manner.
  • the pixels from the dummy pixel 81 in the upper pixel region 21N are covered over the entire period in which the pixel signal is read from the normal pixel 41 in the lower pixel region 21S. Signals are read out and supplied to the upper column processing unit 71N.
  • the pixel signal from the dummy pixel 81 in the lower pixel region 21S is read over the entire period in which the pixel signal is read from the normal pixel 41 in the upper pixel region 21N. Is read out and supplied to the lower column processing unit 71S.
  • both the column processing units 71N and 71S are always in an operating state.
  • the pixel signal is read from the normal pixel 41 in one of the upper pixel region 21N and the lower pixel region 21S, and the other The pixel signal is read from the dummy pixel 81 only immediately before the pixel signal is read from the normal pixel 41 in the pixel area.
  • reading of pixel signals in units of rows is performed from all the normal pixels 41 in the upper pixel region 21 ⁇ / b> N, and all the normal pixels in the lower pixel region 21 ⁇ / b> S.
  • 41 is a timing chart for explaining the operation of the column processing units 71N and 71S in the case where the process from 41 is performed alternately.
  • the pixel signal is read from the normal pixel 41 in the lower pixel region 21 ⁇ / b> S at the timing of the first to fourth, ninth, tenth,. It is supplied to the column processing unit 71S for processing.
  • the pixel signal is read out from the dummy pixel 81 in the upper pixel region 21N and supplied to the upper column processing unit 71N for processing.
  • the pixel signal is read from the normal pixel 41 in the upper pixel region 21N and supplied to the upper column processing unit 71N. Processed.
  • the pixel signal is read out from the dummy pixel 81 in the lower pixel region 21S and supplied to the lower column processing unit 71S for processing. .
  • the lower column processing unit 71S operates to process pixel signals read from the normal pixels 41 in the lower pixel region 21S. .
  • the lower column processing unit 71S does not operate. To stop.
  • the lower column processing unit 71S also stops at the timing of the sixth and seventh reading orders.
  • the lower column processing unit 71S starts operation to process the pixel signal read from the dummy pixel 81 in the lower pixel region 21S (FIG. 16). In FIG. 5, the portion indicated by “operation (dummy)”.
  • the lower column processing unit 71S operates to process the pixel signal read from the normal pixel 41 in the lower pixel region 21S.
  • the power supply voltage of the lower column processing unit 71S is stable at the timing of the ninth reading order. ing. Therefore, it is possible to prevent the deterioration of the image quality due to the fluctuation of the power supply voltage.
  • the upper column processing unit 71N starts the operation in order to process the pixel signal read from the dummy pixel 81 in the upper pixel region 21N (in FIG. 16, “Operation (dummy)”)
  • the upper column processing unit 71N operates to process the pixel signal read from the normal pixel 41 in the upper pixel region 21N.
  • the power supply voltage of the upper column processing unit 71N is stable at the timing of the fifth reading order. . Therefore, it is possible to prevent the deterioration of the image quality due to the fluctuation of the power supply voltage.
  • the upper column processing unit 71N stops without operating. To do.
  • the upper column processing unit 71N starts reading pixels signals from the normal pixels 41 in the lower pixel region 21S, and then the pixels from all the normal pixels 41 in the lower pixel region 21S.
  • a predetermined time of the first end timing t2 at which the signal reading ends for example, up to the first pre-end timing t1 that is the previous pixel signal processing time for one line (hereinafter also referred to as line processing time)
  • the operation is stopped for a while.
  • the upper column processing unit 71N starts operation from the first pre-end timing t1, and is read from the dummy pixel 81 from the first pre-end timing t1 to the first end timing t2.
  • the processed pixel signal is processed.
  • the upper column processing unit 71N processes the pixel signal read from the normal pixel 41 in the upper pixel region 21N after the first end timing t2.
  • the lower column processing unit 71S starts reading the pixel signal from the normal pixel 41 in the upper pixel region 21N (from timing t2), and then from all the normal pixels 41 in the upper pixel region 21N. The operation is stopped for a predetermined time of the second end timing t4 when the reading of the pixel signal ends, for example, until a second pre-end timing t3 that is one line processing time before.
  • the lower column processing unit 71S starts the operation from the second pre-end timing t3, and reads from the dummy pixel 81 from the second pre-end timing t3 to the second end timing t4.
  • the processed pixel signal is processed.
  • the lower column processing unit 71S processes the pixel signal read from the normal pixel 41 in the lower pixel region 21S after the second end timing t4.
  • the upper column processing unit 71N starts processing the pixel signal read from the dummy pixel 81 from the first pre-end timing t1 that is one line processing time before the first end timing t2. Therefore, the power supply voltage is stabilized by the first end timing t2.
  • the upper column processing unit 71N can process a pixel signal read from the normal pixel 41 in the upper pixel region 21N after the first end timing t2 in a state where the power supply voltage is stable. It is possible to prevent image quality deterioration due to fluctuations in the power supply voltage.
  • the lower column processing unit 71S starts processing the pixel signal read from the dummy pixel 81 from the second pre-end timing t3 that is one line processing time before the second end timing t4. Therefore, the power supply voltage is stabilized by the second end timing t4.
  • the lower column processing unit 71N can process a pixel signal read from the normal pixel 41 in the lower pixel region 21S after the second end timing t4 in a state where the power supply voltage is stable. Therefore, it is possible to prevent image quality deterioration due to fluctuations in the power supply voltage.
  • the upper column processing unit 71N stops operating until the first pre-end timing t1 after the reading of the pixel signal from the normal pixel 41 in the lower pixel region 21S is started.
  • the lower column processing unit 71S stops operating until the second pre-end timing t3 after reading of the pixel signal from the normal pixel 41 in the upper pixel region 21N is started.
  • the interval between the first pre-end timing t1 that is the timing at which the upper column processing unit 71N starts the operation (processing of the pixel signal read from the dummy pixel 81) and the first end timing t2 is 0.
  • a variable time longer than the line processing time can be set.
  • the interval between the first pre-end timing t1 and the first end timing t2 can be set to the minimum necessary time for the power supply voltage to stabilize after the upper column processing unit 71N starts operating, for example. .
  • the interval between the first pre-end timing t1 and the first end timing t2 can be set in consideration of both a viewpoint for stabilizing the power supply voltage and a viewpoint for suppressing an increase in power consumption, for example. it can.
  • FIG. 17 is a diagram illustrating a fourth example of the operation of the pixel access unit 11 of FIG.
  • FIG. 17 shows an example of reading out a pixel signal from the normal pixel 41 when pixel signal processing and output are alternately performed by the column processing units 71N and 71S.
  • the pixel signal is read from the pixel 41, the pixel signal is read from the dummy pixel 81 in the lower pixel region 21S and supplied to the lower column processing unit 71S.
  • pixel signals are read out in the same manner as in FIG. 15 except that pixel signals are not read from the dummy pixels 81 in the lower pixel region 21S.
  • the image sensor 2 can be configured without providing the dummy pixel 81 in the lower pixel region 21S. .
  • FIG. 18 is a timing chart for explaining the operations of the column processing units 71N and 71S when the pixel signals described in FIG. 17 are read.
  • the timing at which the reading of the pixel signal from the normal pixel 41 in the lower pixel area 21S switches to the reading of the pixel signal from the normal pixel 41 in the upper pixel area 21N is the pixel signal of the image of one frame.
  • the intermediate timing of the reading period in this embodiment, it is a reading period for 8 lines and is also referred to as a frame reading period hereinafter).
  • the timing at which the reading of the pixel signal from the normal pixel 41 in the upper pixel area 21N is switched to the reading of the pixel signal from the normal pixel 41 in the lower pixel area 21S is the end of the frame reading period. Is the timing.
  • next frame reading period starts immediately after the end of the frame reading period and a case where the next frame reading period starts after a predetermined period such as several line processing time.
  • the predetermined period is also referred to as a preparation period.
  • the lower column processing unit 71S starts operation after the end of the frame readout period. Then, after the start of the next frame readout period, the pixel signal read from the normal pixel 41 in the lower pixel region 21S can be processed.
  • the lower column processing unit 71S starts operation after the end of the frame readout period, so that the power supply voltage is stabilized during the preparation period.
  • the lower column processing unit 71S processes the pixel signal read from the normal pixel 41 in the lower pixel region 21S in the next frame reading period after the preparation period in a state where the power supply voltage is stable. Therefore, it is possible to prevent deterioration in image quality due to fluctuations in power supply voltage.
  • FIG. 18 is a timing chart showing the operation of the column processing units 71N and 71S when there is a preparation period between the end of the frame readout period and the start of the next frame readout period as described above.
  • the lower column processing unit 71S operates to process the pixel signals read from the normal pixels 41 in the lower pixel region 21S.
  • the lower column processing unit 71S does not operate. To stop.
  • the lower column processing unit 71S also stops at the timing of the sixth to eighth reading orders.
  • the preparation period is a two-line processing time.
  • the preparation period is not limited to the two-line processing time.
  • the lower column processing unit 71S starts operation during the preparation period, but the pixel signal to be processed is not supplied. However, in the preparation period, a pixel signal can be read from the dummy pixel 81 in the lower pixel region 21S, and the pixel signal can be processed by the lower column processing unit 71S.
  • the lower column processing unit 71S processes the pixel signal read from the normal pixel 41 in the lower pixel region 21S.
  • the power supply of the lower column processing unit 71S is used at the timing of the ninth readout order.
  • the voltage is stable. Therefore, it is possible to prevent the deterioration of the image quality due to the fluctuation of the power supply voltage.
  • the upper column processing unit 71N starts an operation in order to process the pixel signal read from the dummy pixel 81 in the upper pixel region 21N (in FIG. 18, “Operation (dummy)”)
  • the upper column processing unit 71N operates to process the pixel signal read from the normal pixel 41 in the upper pixel region 21N.
  • the power supply voltage of the upper column processing unit 71N is stable at the timing of the fifth reading order. . Therefore, it is possible to prevent the deterioration of the image quality due to the fluctuation of the power supply voltage.
  • the upper column processing unit 71N then reads from the dummy pixel 81 in the upper pixel region 21N. The operation is stopped until the timing of the readout order (in this embodiment, the 12th readout order) for processing the output pixel signal.
  • the upper column processing unit 71N receives the first end when performing the upward reading.
  • the operation is started from the first timing t1 before the end of the line processing time of the timing t2, the pixel signal read from the dummy pixel 81 is processed, and the lower column processing unit 71S is started from the preparation period.
  • FIG. 19 is a diagram illustrating a usage example in which the above-described image sensor 2 is used.
  • the image sensor 2 (or the camera unit having the image sensor 2) described above is used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays as follows. be able to.
  • Devices for taking images for viewing such as digital cameras and mobile devices with camera functions
  • Devices used for traffic such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc.
  • Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ⁇ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc.
  • Equipment used for medical and health care ⁇ Security equipment such as security surveillance cameras and personal authentication cameras ⁇ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports-Equipment used for sports such as action cameras and wearable cameras for sports applications-Used for agriculture such as cameras for monitoring the condition of fields and crops apparatus
  • the grouping of the normal pixels 41 in the pixel array unit 21 is limited to the grouping in which the normal pixels 41 are divided into the normal pixels 41 in the upper pixel region 21N and the normal pixels 41 in the lower pixel region 21S. It is not a thing.
  • the normal pixels 41 of the pixel array unit 21 can be grouped into, for example, odd-numbered normal pixels 41 and even-numbered normal pixels 41.
  • the pixel signal read from the normal pixel 41 in one of the odd and even rows is processed by one of the column processing units 71N and 71S, and the other row is processed.
  • the pixel signal read from the normal pixel 41 can be processed by the other column processing unit.
  • the pixel array unit 21 (the normal pixel 41) can be divided into two or more areas including an upper pixel area 21N and a lower pixel area 21S.
  • a column processing unit can be provided for each of the three or more regions.
  • the present technology performs AD conversion other than column parallel AD conversion, for example, area AD conversion. It can also be applied to an image sensor.
  • a processing unit that performs processing such as AD conversion is provided for each predetermined area, and the processing unit in each area is responsible for AD conversion of pixel signals of normal pixels in the area.
  • the present invention can be applied to an image sensor that performs the above.
  • AD conversion for example, in each area, AD conversion for each pixel can be performed simultaneously for E areas.
  • E areas are grouped into a first group and a second group of E / 2 areas, and each of the first and second groups is divided into E / 2.
  • AD conversion of the predetermined unit can be performed alternately between the first group and the second group.
  • a dummy pixel is provided in each area in addition to the normal pixel, and the processing unit of one of the first and second groups is caused to process a signal read from the normal pixel, while the other
  • the signals read from the dummy pixels can be processed by the processing units of the groups.
  • this technique can take the following structures.
  • a pixel array unit having pixels that output signals serving as pixel values of an image and dummy pixels; And first and second processing units for processing signals read from the pixels, One of the first and second processing units processes a signal read from the pixel, and the other processing unit processes a signal read from the dummy pixel.
  • the first processing unit processes signals read in the predetermined unit from the pixels of the first group;
  • the first processing unit processing signals read in the predetermined unit from the pixels of the first group for all of the pixels of the first group; Alternately, the second processing unit performs processing on the signals read from the second group of pixels in the predetermined unit for all of the pixels of the second group. Perform The image sensor according to ⁇ 2>.
  • the first processing unit includes: The first end before the predetermined end time of the first end timing at which the signal reading from all the pixels of the second group ends after the signal reading from the pixels of the second group starts.
  • the image sensor according to ⁇ 4> wherein signals read from the pixels of the first group are processed after the first end timing.
  • the second processing unit includes: A second end that is a predetermined time before a second end timing at which reading of signals from all of the pixels of the first group ends after reading of signals from the pixels of the first group starts Stop operation until the previous timing, Start the operation from the second pre-end timing and process the signal read from the dummy pixel until the second end timing, The image sensor according to ⁇ 6>, wherein signals read from the pixels of the second group are processed after the second end timing.
  • the pixels of the first and second groups are pixels in the upper half and the lower half of the pixel array unit, respectively.
  • the uppermost row and the lowermost row of the pixel array unit are the dummy pixels,
  • the first processing unit processes a signal read from the dummy pixel in the uppermost row;
  • a pixel array unit having pixels that output signals serving as pixel values of an image and dummy pixels;
  • One of the first and second processing units of an image sensor including a first and a second processing unit that processes a signal read from the pixel is read from the pixel
  • a processing method including processing a signal and the other processing unit processing a signal read from the dummy pixel.
  • An optical system that collects the light;
  • An image sensor that receives light and captures an image,
  • the image sensor is A pixel array unit having pixels that output signals serving as pixel values of an image and dummy pixels;
  • first and second processing units for processing signals read from the pixels, One of the first and second processing units processes a signal read from the pixel, and the other processing unit processes a signal read from the dummy pixel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente technologie se rapporte à un capteur d'image, à un procédé de traitement, et à un dispositif électronique, qui permettent d'éviter une détérioration d'une qualité d'image. Une unité de matrice de pixels comporte un pixel à partir duquel un signal qui devient une valeur de pixel d'une image est fourni en sortie, et un pixel factice. Une unité de traitement de première et seconde unités de traitement traite un signal lu à partir du pixel, et l'autre unité de traitement traite un signal lu à partir du pixel factice. Cette technologie est applicable, par exemple, à un capteur d'image pour capturer une image.
PCT/JP2016/064211 2015-05-28 2016-05-13 Capteur d'image, procédé de traitement et dispositif électronique WO2016190127A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009171128A (ja) * 2008-01-15 2009-07-30 Konica Minolta Opto Inc 固体撮像素子及びそれを用いた固体撮像装置
JP2010098516A (ja) * 2008-10-16 2010-04-30 Sony Corp 撮像素子およびその制御方法並びにカメラ
JP2011040807A (ja) * 2009-08-06 2011-02-24 Toshiba Corp 固体撮像装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009171128A (ja) * 2008-01-15 2009-07-30 Konica Minolta Opto Inc 固体撮像素子及びそれを用いた固体撮像装置
JP2010098516A (ja) * 2008-10-16 2010-04-30 Sony Corp 撮像素子およびその制御方法並びにカメラ
JP2011040807A (ja) * 2009-08-06 2011-02-24 Toshiba Corp 固体撮像装置

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