WO2016190116A1 - Dispositif d'imagerie à semi-conducteurs, procédé de commande de dispositif d'imagerie à semi-conducteurs et dispositif électronique - Google Patents

Dispositif d'imagerie à semi-conducteurs, procédé de commande de dispositif d'imagerie à semi-conducteurs et dispositif électronique Download PDF

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Publication number
WO2016190116A1
WO2016190116A1 PCT/JP2016/064086 JP2016064086W WO2016190116A1 WO 2016190116 A1 WO2016190116 A1 WO 2016190116A1 JP 2016064086 W JP2016064086 W JP 2016064086W WO 2016190116 A1 WO2016190116 A1 WO 2016190116A1
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signal
pixel region
unit
row
output
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PCT/JP2016/064086
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English (en)
Japanese (ja)
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茂 齊藤
清茂 辻
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ソニー株式会社
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present technology relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device.
  • a solid-state image signal can be added between pixel regions.
  • the present invention relates to an imaging device, a driving method of a solid-state imaging device, and an electronic apparatus.
  • a plurality of unit pixels are arranged in a matrix in a pixel array section, and each unit pixel is connected to a vertical signal line for each column.
  • the vertical signal line has parasitic resistance and parasitic capacitance, and when these values increase, the readout time of the pixel signal increases. As a result, the pixel signal readout time and the charge accumulation time are shifted between the rows of the pixel array portion.
  • the CMOS image sensor has increased in number of pixels and the light receiving area has been increased, and the parasitic resistance and parasitic capacitance of the vertical signal line tend to increase.
  • CMOS image sensor that reduces the parasitic resistance and parasitic capacitance of the vertical signal line by dividing the pixel array part into two pixel regions in the vertical direction and electrically dividing the vertical signal line in the pixel array part.
  • Patent Document 1 a CMOS image sensor that reduces the parasitic resistance and parasitic capacitance of the vertical signal line by dividing the pixel array part into two pixel regions in the vertical direction and electrically dividing the vertical signal line in the pixel array part.
  • an analog signal output from a unit pixel via a vertical signal line is converted into a digital value by an ADC (analog / digital conversion circuit), and the obtained digital value is converted between unit pixels in a plurality of rows.
  • a CMOS image sensor that realizes a high frame rate without reducing sensitivity by adding and reading has been proposed (for example, see Patent Document 2).
  • Patent Document 2 does not consider dividing the pixel array portion as in Patent Document 1. Therefore, in Patent Document 2, it is not assumed that pixel signals are added between the divided pixel regions.
  • the present technology makes it possible to add pixel signals between pixel regions without degrading image quality when the pixel array unit is divided into a plurality of pixel regions.
  • a plurality of effective pixel areas in which unit pixels used for image generation are arranged in a matrix are arranged in a column direction, and a vertical signal line is provided for each column of the effective pixel areas.
  • the vertical signal line is not connected between the effective pixel regions, and the pixel array unit is provided so as to correspond to each effective pixel region, and at least unit pixels that are not used for generating the image are provided.
  • a plurality of dummy pixel regions arranged in one row a row driving unit that drives the effective pixel region and unit pixels of the dummy pixel region in units of rows, and each set of the effective pixel region and the dummy pixel region
  • An analog signal provided correspondingly and output from the unit pixel of the row selected by the row driving unit via the vertical signal line is converted into a digital signal for each column, and a plurality of rows
  • a plurality of column processing units capable of adding and outputting digital signals of unit pixels; and a signal processing unit for processing digital signals output from the column processing units, wherein r1 row of the first effective pixel region When adding the pixel signal of the eye and the pixel signal of the r2th row of the second effective pixel region, the row driving unit starts with the first pixel corresponding to the first effective pixel region from the unit pixel of the r1th row.
  • a first analog signal is output to the first column processing unit, a second analog signal is output from the first dummy pixel region corresponding to the first effective pixel region to the first column processing unit, and the r2
  • a third analog signal is output from the unit pixel in the row to the second column processing unit corresponding to the second effective pixel region, and the second dummy pixel region corresponding to the second effective pixel region is output from the second dummy pixel region.
  • 4th analog in the 2nd column processing part The first column processing unit outputs a first digital signal corresponding to the first analog signal, and a second digital signal corresponding to the second analog signal. And the second column processing unit outputs a third digital signal corresponding to the third analog signal and does not output a fourth digital signal corresponding to the fourth analog signal.
  • the signal processor adds and outputs the first digital signal and the third digital signal.
  • the first column processing unit is configured to perform analog / digital conversion of the first analog signal and the second analog signal within a first horizontal scanning period, and after the first horizontal scanning period.
  • the first digital signal is output within the second horizontal scanning period, and the second column processing unit causes the third analog signal and the fourth digital signal to be output within the second horizontal scanning period.
  • the third digital signal can be output within the third horizontal scanning period following the second horizontal scanning period.
  • the first column processing unit includes a first analog / digital conversion unit including a first memory for each column, and the second column processing unit includes a second analog including a second memory.
  • / Digital conversion unit is provided for each column, and the first analog / digital conversion unit converts the first analog signal into the first digital signal within the first horizontal scanning period, and Storing a first digital signal in the first memory, converting the second analog signal into the second digital signal, and erasing the second digital signal without storing it in the first memory;
  • the first digital signal is output from the first memory within the second horizontal scanning period, and the second analog / digital conversion unit is configured to output the first digital signal within the second horizontal scanning period.
  • the third analog signal is converted to the third analog signal.
  • the third digital signal is stored in the second memory, the fourth analog signal is converted into the fourth digital signal, and the fourth digital signal is converted into the second digital signal.
  • the third digital signal can be output from the second memory during the third horizontal scanning period without being stored in the memory.
  • the pixel signals of the unit pixels for a row (a ⁇ 1) of the first effective pixel region and the pixel signals of the unit pixels for b row (b ⁇ 1) of the second effective pixel region are added.
  • the row driving unit outputs a fifth analog signal to the first column processing unit from the unit pixels corresponding to the a row in the first effective pixel region, and the unit of the first dummy pixel region
  • a sixth analog signal for b rows is output from the pixel to the first column processing unit
  • a seventh analog signal is output from the unit pixel for b rows in the second effective pixel region to the second column processing unit.
  • a signal is output, and the second column processing unit is controlled to output an eighth analog signal for a row from the unit pixel of the second dummy pixel region, and the first column processing unit , Outputs a fifth digital signal indicating a value obtained by adding the fifth analog signals for a rows
  • the second column processing unit does not output the sixth digital signal corresponding to the sixth analog signal for b rows, and adds a value obtained by adding the seventh analog signal for b rows to the second column processing unit.
  • the seventh digital signal is output, the eighth digital signal corresponding to the eighth analog signal for a rows is not output, and the signal processing unit has the fifth digital signal and the seventh digital signal output. Can be added and output.
  • the pixel array unit is configured by the first effective pixel region, the second effective pixel region, the first dummy pixel region, and the second dummy pixel region, and the first dummy pixel region.
  • the first effective pixel region, the second effective pixel region, and the second dummy pixel region can be arranged in the column direction in this order.
  • the pixel array unit can be disposed on a first substrate, and the dummy pixel regions and the column processing units can be disposed on a second substrate stacked on the first substrate.
  • a plurality of effective pixel regions in which unit pixels used for generating an image are arranged in a matrix are arranged in a column direction, and each column of the effective pixel regions is arranged.
  • a unit that is provided to correspond to each effective pixel region and a pixel array unit in which vertical signal lines are wired and the vertical signal line is not connected between the effective pixel regions, and is not used for generating the image A plurality of dummy pixel regions in which pixels are arranged in at least one row; a row driving unit that drives the effective pixel region and unit pixels of the dummy pixel region in units of rows; and each of the effective pixel region and the dummy pixel region.
  • a solid-state imaging device comprising: a plurality of column processing units that can add and output digital signals of unit pixels in a plurality of rows; and a signal processing unit that processes digital signals output from the column processing units.
  • a second analog pixel region corresponding to the second effective pixel region is output by outputting a third analog signal from the unit pixel in the r2th row to a second column processing unit corresponding to the second effective pixel region.
  • the first column processing unit outputs a first digital signal corresponding to the first analog signal, and outputs a second digital signal corresponding to the second analog signal. Without outputting the third digital signal corresponding to the third analog signal from the second column processing unit, without outputting the fourth digital signal corresponding to the fourth analog signal, The signal processing unit adds the first digital signal and the third digital signal and outputs the result.
  • a plurality of effective pixel areas in which unit pixels used for image generation are arranged in a matrix are arranged in a column direction, and a vertical signal line is provided for each column of the effective pixel areas.
  • At least one unit pixel that is provided so as to correspond to each of the effective pixel regions and the pixel array portion that is wired and the vertical signal line is not connected between the effective pixel regions, and is not used for generating the image.
  • An analog signal output from the unit pixel in the row selected by the row driving unit via the vertical signal line is converted into a digital signal for each column, and a plurality of rows
  • a plurality of column processing units capable of adding and outputting digital signals of pixels; and a signal processing unit for processing digital signals output from the column processing units, and the r1th row of the first effective pixel region
  • the row driving unit outputs the first effective pixel region corresponding to the first effective pixel region from the unit pixel of the r1 row.
  • a first analog signal is output to the column processing unit, a second analog signal is output from the first dummy pixel region corresponding to the first effective pixel region to the first column processing unit, and the r2 rows
  • a third analog signal is output from the unit pixel of the eye to the second column processing unit corresponding to the second effective pixel region, and the second dummy pixel region corresponding to the second effective pixel region is output from the second dummy pixel region.
  • the fourth analog signal to the column processor The first column processing unit outputs a first digital signal corresponding to the first analog signal, and outputs a second digital signal corresponding to the second analog signal.
  • the second column processing unit outputs a third digital signal corresponding to the third analog signal, does not output a fourth digital signal corresponding to the fourth analog signal
  • the signal processing unit includes a solid-state imaging device that adds and outputs the first digital signal and the third digital signal.
  • the r1 A first analog signal is output from the unit pixel in the row to the first column processing unit corresponding to the first effective pixel region, and from the first dummy pixel region corresponding to the first effective pixel region, the first analog signal is output.
  • a second analog signal is output to the first column processing unit, and a third analog signal is output from the unit pixel in the r2th row to the second column processing unit corresponding to the second effective pixel region,
  • a fourth analog signal is output from the second dummy pixel region corresponding to the second effective pixel region to the second column processing unit, and the first analog signal is output from the first column processing unit.
  • the corresponding first digital signal is output
  • the second digital signal corresponding to the second analog signal is not output, and the third digital signal corresponding to the third analog signal is output from the second column processing unit, and the fourth digital signal is output.
  • the fourth digital signal corresponding to the analog signal is not output, and the first digital signal and the third digital signal are added and output from the signal processing unit.
  • pixel signals when the pixel array unit is divided into a plurality of pixel regions, pixel signals can be added between the pixel regions without degrading the image quality.
  • FIG. 6 is a schematic block diagram which shows the structural example of the CMOS image sensor which concerns on one embodiment of this technique. It is a schematic block diagram which shows the structural example of a pixel array part. It is a schematic block diagram which shows the specific structural example of a part of column processing circuit and control part.
  • 6 is a timing chart for explaining an operation in a normal frame rate mode. 6 is a timing chart for explaining an operation in a normal frame rate mode. 6 is a timing chart for explaining an operation in a high-speed frame rate mode. 6 is a timing chart for explaining an operation in a high-speed frame rate mode. It is a timing chart for demonstrating operation
  • FIG. 1 It is a schematic block diagram which shows the structural example of a CMOS image sensor in the case of dividing
  • Embodiment 2 modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order. 1. Embodiment 2. FIG. Modified example 2. Examples of using solid-state imaging devices
  • FIG. 1 is a schematic block diagram showing an embodiment of a CMOS image sensor 10 to which the present technology is applied.
  • FIG. 2 is a schematic block diagram illustrating a configuration example of the pixel array unit 11 of the CMOS image sensor 10. In FIG. 1 and FIG. 2, description of signal lines and the like for driving each unit pixel is omitted as appropriate.
  • the CMOS image sensor 10 is configured to include a pixel array unit 11, a row driving circuit 12, column processing circuits 13a and 13b, column driving circuits 14a and 14b, a control unit 15, and a correction unit 16.
  • the pixel array unit 11, the row drive circuit 12, the column processing circuits 13a and 13b, the column drive circuits 14a and 14b, the control unit 15, and the correction unit 16 are integrated on the same substrate, for example.
  • the pixel array unit 11 is a pixel region that receives incident light.
  • ⁇ N + 2R ⁇ (rows) ⁇ M (columns) unit pixels are arranged in a matrix.
  • Such a CMOS image sensor 10 is called an XY address type CMOS image sensor.
  • the vertical signal line is divided at the center. Accordingly, the pixel array unit 11 is divided into an upper pixel region 11a and a lower pixel region 11b in the column direction (vertical direction) and has a two-stage configuration.
  • the pixel area 11a is further divided into an effective pixel area 21a and a dummy pixel area 22a
  • the pixel area 11b is further divided into an effective pixel area 21a and a dummy pixel area 22a.
  • the dummy pixel region 22a, the effective pixel region 21a, the effective pixel region 21b, and the dummy pixel region 22b are arranged in the column direction in this order.
  • the effective pixel region 21a and the effective pixel region 21b are arranged so as to be adjacent to each other in the column direction (vertical direction), and the last row of the effective pixel region 21a and the first row of the effective pixel region 21b are adjacent to each other.
  • the dummy pixel region 22a is disposed on the opposite side to the effective pixel region 21b so as to be adjacent to the effective pixel region 21a in the column direction, and the last row of the dummy pixel region 22a and the first row of the effective pixel region 21a are adjacent to each other.
  • the dummy pixel region 22b is arranged on the opposite side to the effective pixel region 21a so as to be adjacent to the effective pixel region 21b in the column direction, and the last row of the effective pixel region 21b and the first row of the dummy pixel region 22b are adjacent to each other.
  • the column processing circuit 13a is arranged so as to be adjacent to the dummy pixel region 22a in the column direction on the side opposite to the effective pixel region 21a.
  • the column drive circuit 14a is disposed on the opposite side to the dummy pixel region 22a so as to be adjacent to the column processing circuit 13a in the column direction.
  • the column processing circuit 13b is arranged so as to be adjacent to the dummy pixel region 22b in the column direction on the side opposite to the effective pixel region 21b.
  • the column driving circuit 14b is disposed adjacent to the column processing circuit 13b in the column direction on the side opposite to the dummy pixel region 22a.
  • an effective pixel region 21 a region obtained by combining the effective pixel region 21a and the effective pixel region 21b is referred to as an effective pixel region 21.
  • N (row) ⁇ M (column) unit pixels are arranged in a matrix.
  • N / 2 (row) ⁇ M (column) unit pixels are arranged in a matrix. Then, image data output from the CMOS image sensor 10 is generated using pixel signals output from the unit pixels in the effective pixel region 21.
  • R (row) ⁇ M (column) unit pixels are arranged in a matrix.
  • the dummy pixel region 22a and the dummy pixel region 22b are shielded from light, and the pixel signals output from the unit pixels in the dummy pixel region 22a and the dummy pixel region 22b are used to generate image data output from the CMOS image sensor 10. Not used.
  • a dummy pixel region 22 In addition, hereinafter, when it is not necessary to distinguish the dummy pixel region 22a and the dummy pixel region 22b, they are simply referred to as a dummy pixel region 22.
  • the unit pixel in the effective pixel area 21 is also referred to as an effective pixel PE.
  • the effective pixels PE are distinguished by coordinates as in the effective pixel PE (i, j). Note that the coordinates of the effective pixel PE at the upper left corner of the effective pixel area 21 are (1, 1), and the coordinates of the effective pixel PE at the lower right corner are (M, N).
  • the effective pixel region 21a effective pixels PE from the effective pixel PE (1, 1) to the effective pixel PE (M, N / 2) are arranged in a matrix.
  • the effective pixel region 21b effective pixels PE from the effective pixel PE (1, ⁇ N / 2 ⁇ +1) to the effective pixel PE (M, N) are arranged in a matrix.
  • the unit pixel in the dummy pixel region 22a is also referred to as a dummy pixel PDa.
  • the dummy pixels PDa are individually distinguished, the dummy pixels PDa are distinguished by coordinates as in the dummy pixel PDa (i, j). Note that the coordinates of the dummy pixel PDa at the upper left corner of the dummy pixel region 22a are (1, 1), and the coordinates of the dummy pixel PDa at the lower right corner are (M, R).
  • the unit pixel in the dummy pixel region 22b is also referred to as a dummy pixel PDb.
  • the dummy pixels PDb are individually distinguished, the dummy pixels PDb (i, j) are distinguished by coordinates.
  • the coordinates of the dummy pixel PDb at the upper left corner of the dummy pixel region 22b are (1, 1), and the coordinates of the dummy pixel PDb at the lower right corner are (M, R).
  • a dummy pixel PD when it is not necessary to distinguish between the dummy pixel PDa and the dummy pixel PDb, they are referred to as a dummy pixel PD. Furthermore, hereinafter, when it is not necessary to distinguish the effective pixel PE and the dummy pixel PD, they are referred to as a unit pixel P.
  • unit pixel P in addition to a photoelectric conversion element (for example, photodiode), for example, the electric charge obtained by photoelectrically converting with the photoelectric conversion element concerned is FD (floating diffusion) part.
  • FD floating diffusion
  • Each unit pixel P is provided with a color filter of Gr (green), R (red), B (blue), and Gb (green), and detects a color corresponding to the color filter of each color.
  • the pixel array unit 11 is a Bayer pixel array.
  • an R unit pixel P (effective pixel PE (1, 1)) is arranged in the first column and first row of the effective pixel region 21, and a Gr unit pixel P (effective pixel) is arranged in the second column and first row.
  • PE (2, 1)) is arranged.
  • the Gb unit pixel P (effective pixel PE (1, 2)) is arranged in the first column and the second row
  • the B unit pixel P (effective pixel PE (2, 2)) is arranged in the second column and the second row. Is arranged.
  • pixel blocks composed of 2 ⁇ 2 unit pixels P are arranged in a matrix.
  • vertical signal lines 23a-1 to 23a-M are wired for each column.
  • vertical signal lines 23b-1 to 23b-M are wired for each column in the pixel region 11b.
  • One end of the vertical signal line 23a-i is connected to the column processing circuit 13a, and one end of the vertical signal line 23b-i is connected to the column processing circuit 13b.
  • the vertical signal lines in the same column that is, the other end of the vertical signal line 23a-i and the other end of the vertical signal line 23b-i are electrically disconnected. In other words, the vertical signal line is not electrically connected between the pixel region 11a and the pixel region 11b.
  • the unit pixel P in the pixel area 11a (effective pixel area 21a and dummy pixel area 22a) and the unit pixel P in the pixel area 11b (effective pixel area 21b and dummy pixel area 22b) are connected to the vertical signal of the connection destination.
  • the lines are different.
  • the analog voltage signal (pixel signal) output from the unit pixel P in the pixel area 11a is processed by the column processing circuit 13a.
  • the analog voltage signal (pixel signal) output from the unit pixel P in the pixel region 11b is processed by the column processing circuit 13b.
  • the row driving circuit 12 drives the unit pixel P of the pixel array unit 11 for each row. For example, the row drive circuit 12 selects a row of unit pixels P to be driven based on a row selection signal SVDR from the control unit 15.
  • the row driving circuit 12 applies a reset signal to a reset signal line (not shown), applies a transfer signal to a transfer signal line (not shown), and applies a selection signal to a selection signal line (not shown).
  • the unit pixels P arranged in the same row are driven.
  • the column processing circuit 13a is a signal processing unit that performs AD conversion, correlated double sampling (CDS) processing, and the like on an analog pixel signal input from the unit pixel P of the pixel region 11a.
  • the column processing circuit 13a performs an addition process (hereinafter referred to as a vertical addition process) of the pixel signals of the unit pixels P in a plurality of rows of the pixel area 11a.
  • the column processing circuit 13a is provided with switches 73a-1 to 73-M for the vertical signal lines 23a-1 to 23a-M, respectively.
  • the switches 73a-1 to 73a-M can be individually opened and closed, and the digital pixel signals in the column in which the switches are turned on are output to the control unit 15 via the horizontal signal line 24a.
  • the column processing circuit 13b performs the same processing as the column processing circuit 13a on the analog pixel signal input from the unit pixel P in the pixel region 11b.
  • the column processing circuit 13b is provided with switches 73b-1 to 73-M for the vertical signal lines 23b-1 to 23b-M, respectively.
  • the switches 73b-1 to 73b-M can be individually opened and closed, and the digital pixel signal of the column in which the switch is turned on is output to the control unit 15 via the horizontal signal line 24b.
  • the column drive circuit 14a is configured by, for example, a shift register.
  • the column drive circuit 14a reads out the pixel signal of the unit pixel P held in the column processing circuit 13a for each column based on the column selection signal SHDRa of the control unit 15.
  • the column drive circuit 14b also reads out the pixel signal of the unit pixel P held in the column processing circuit 13b for each column based on the column selection signal SHDRb of the control unit 15.
  • the control unit 15 is configured to include a control circuit and a signal processing circuit.
  • the control unit 15 supplies a row selection signal SVDR to the row drive circuit 12, supplies a column selection signal SHDRa to the column drive circuit 14a, and supplies a column selection signal SHDRb to the column drive circuit 14b.
  • the control unit 15 performs a process such as amplification on the pixel signal input from the column processing circuit 13 a via the horizontal signal line 24 a and outputs the processed pixel signal to the correction unit 16.
  • the control unit 15 performs processing such as amplification on the pixel signal input from the column processing circuit 13b via the horizontal signal line 24b, and outputs the processed pixel signal to the correction unit 16.
  • the control unit 15 adds the pixel signal input from the column processing circuit 13a and the pixel signal input from the column processing circuit 13b as necessary, and outputs the pixel signal after the addition to the correction unit 16.
  • the correction unit 16 corrects the deviation (distortion) of the gain and the offset voltage generated in the pixel signals in the same column.
  • the vertical signal line 23 when it is not necessary to distinguish the vertical signal line 23a from the vertical signal line 23b, they are simply referred to as the vertical signal line 23.
  • the horizontal signal line 24 when there is no need to distinguish between the horizontal signal line 24a and the horizontal signal line 24b, they are simply referred to as the horizontal signal line 24.
  • FIG. 3 shows a specific configuration example of part of the column processing circuit 13b and the control unit 15. Note that the column processing circuit 13a has the same configuration as the column processing circuit 13b, and the description and illustration thereof are omitted.
  • DAC 52b is provided for the column processing circuit 13b, and a DAC 52a (not shown) having the same configuration is provided for the column processing circuit 13a.
  • the timing control circuit 51 Based on the master clock signal MCK, the timing control circuit 51 generates a clock signal, a control signal, and the like that serve as a reference for operations of the row drive circuit 12, the column processing circuits 13a and 13b, the column drive circuits 14a and 14b, the DACs 52a and 52b, and the like. Generate and supply to each part.
  • the DAC 52b generates the reference voltage Vrefb based on the clock signal CK supplied from the timing control circuit 51 under the control of the control signal CS1b from the timing control circuit 51.
  • the reference voltage Vrefb is a voltage signal having a so-called ramp (RAMP) waveform whose level changes in an inclined manner as time elapses.
  • the DAC 52b supplies the generated reference voltage Vrefb to ADCs (Analog / Digital Conversion Circuits) 61b-1 to 61b-M of the column processing circuit 13b.
  • ADCs 61b-1 to 61b-M are provided for each pixel column of the pixel array unit 11, that is, for the vertical signal lines 23b-1 to 23b-M, respectively.
  • the ADCs 61b-1 to 61b-M convert an analog signal output for each column from each unit pixel P in the pixel region 11b into a digital signal and output the digital signal.
  • Each of the ADCs 61b-1 to 61b-M can perform AD conversion (analog / digital conversion) operation corresponding to each operation mode of the normal frame rate mode and the high-speed frame rate mode.
  • the normal frame rate mode is an operation mode in which all information of the effective pixel PE is read by the progressive scanning method.
  • the high-speed frame rate mode is an operation mode in which the exposure time of the unit pixel P is set to 1 / N (for example, 1/2) and the frame rate is set to N times (for example, twice) compared to the normal frame rate mode. is there.
  • the switching of the operation mode is executed by control by control signals CS2b and CS3b given from the timing control circuit 51.
  • instruction information for switching between the normal frame rate mode and the high-speed frame rate mode is given to the timing control circuit 51 from an external system controller (not shown).
  • the ADCs 61b-1 to 61b-M all have the same configuration, and the configuration of the ADC 61b-1 will be described here.
  • the ADC 61b-1 includes a comparator 71b-1, an up / down counter (U / D CNT) 72b-1, a switch 73b-1, and a memory device 74b-1.
  • the comparator 71b-1 includes a signal voltage Vx of the vertical signal line 23b-1 corresponding to an analog pixel signal output from each unit pixel P in the first column of the pixel region 11b, and a reference voltage Vrefb supplied from the DAC 52b. And compare.
  • the output signal Vco of the comparator 71b-1 becomes “H” level when the reference voltage Vrefb is larger than the signal voltage Vx, for example, and becomes “L” level when the reference voltage Vrefb is equal to or lower than the signal voltage Vx. Become.
  • the up / down counter 72b-1 is composed of an asynchronous counter, for example.
  • the up / down counter 72b-1 performs down-counting or up-counting in synchronization with the clock signal CK simultaneously supplied from the timing control circuit 51 to the DAC 52b under the control of the control signal CS2b from the timing control circuit 51. .
  • the length of the period during which the output signal Vco is at the H level in the comparison period from the start of the comparison operation in the comparator 71b-1 to the end of the comparison operation (hereinafter referred to as comparison signal output time) is measured. .
  • the switch 73b-1 is switched between an on (closed) state and an off (open) state under the control of the control signal CS3b from the timing control circuit 51.
  • the switch 73b-1 is turned on, the count value of the up / down counter 72b-1 is transferred to the memory device 74b-1 via the switch 73b-1.
  • an analog signal supplied from each unit pixel P in the first column of the pixel region 11b via the vertical signal line 23b-1 is n bits by the comparator 71b-1 and the up / down counter 72b-1. And is stored in the memory device 74b-1.
  • the digital signals stored in the memory devices 74b-1 to 74b-M are sequentially read out to the horizontal signal line 24b and are sent to the control unit 15 via the horizontal signal line 24b. Is output.
  • the ADC 61b-1 can selectively transfer the count value of the up / down counter 72b-1 to the memory device 74b-1 via the switch 73b-1. Therefore, the ADC 61b-1 can independently control the count operation of the up / down counter 72b-1 and the operation of reading the count value of the up / down counter 72b-1 to the horizontal signal line 24b. .
  • the column processing circuit 13a (not shown) is configured to include ADCs 61a-1 to 61a-M, similarly to the column processing circuit 13b.
  • the ADCs 61a-1 to 61a-M include comparators 71a-1 to 71a-M, up / down counters 72a-1 to 72a-M, and switches 73a-1 to 73a. -M and memory devices 74a-1 to 74a-M.
  • ADCs 61a-1 to 61a-M comparators 71a-1 to 71a-M, up / down counters 72a-1 to 72a-M, switches 73a-1 to 73a-M, and memory devices 74a-1 to 74a
  • comparators 71a-1 to 71a-M comparators 71a-1 to 71a-M
  • up / down counters 72a-1 to 72a-M switches 73a-1 to 73a-M
  • memory devices 74a-1 to 74a When it is not necessary to individually distinguish -M, they are simply referred to as ADC 61a, comparator 71a, up / down counter 72a, switch 73a, and memory device 74a.
  • ADC 61 when it is not necessary to distinguish between the ADC 61a and the ADC 61b, they are simply referred to as ADC 61.
  • comparator 71a and the comparator 71b they are simply referred to as a comparator 71.
  • up / down counter 72a and the up / down counter 72b they are simply referred to as the up / down counter 72.
  • switch 73a and the switch 73b they are simply referred to as a switch 73.
  • the memory device 74a and the memory device 74b when there is no need to distinguish between the memory device 74a and the memory device 74b, they are simply referred to as the memory device 74.
  • FIG. 4 shows a time series of the mode control signal, the reset control signal, the reference voltage Vrefb, the signal voltage Vx of the vertical signal line 23b, the output signal Vco of the comparator 71b, the clock signal CK, and the count value of the up / down counter 72b. It shows the transition of.
  • the mode control signal and the reset control signal are included in the control signal CS2b supplied from the timing control circuit 51 to the up / down counter 72b.
  • the mode control signal is a signal for setting whether the up / down counter 72b is to count up or down. For example, when the mode control signal is at “H” level, the up / down counter 72b performs up-counting, and when the mode control signal is at “L” level, the up / down counter 72b performs down-counting.
  • the reset control signal is a signal for resetting the count value of the up / down counter 72b.
  • FIG. 5 shows a vertical synchronization signal VS indicating one frame period, a horizontal synchronization signal HS indicating a horizontal scanning period, a row selection signal supplied from the row driving circuit 12 to each unit pixel P of the pixel array unit 11 for each row, The time-series transition of the AD conversion period, the data latch signal, and the signal output from the memory device 74b to the horizontal signal line 24b is shown.
  • the data latch signal is included in the control signal CS3b supplied from the timing control circuit 51 to the switch 73b.
  • the switch 73b is turned on (closed) when the data latch signal is input, and is turned off (open) when the data latch signal is not input.
  • the column processing circuit 13b and the column driving circuit 14b mainly read out the pixel signal of the unit pixel P in the pixel region 11b will be described.
  • the same operation is performed when the column processing circuit 13a and the column driving circuit 14a read out the pixel signal of the unit pixel P in the pixel region 11a. Further, the reading operation for each column of the pixel region 11a and each column of the pixel region 11b is performed in parallel.
  • a description of a specific operation of the unit pixel P is omitted, but as is well known, a reset operation and a transfer operation are performed in the unit pixel P.
  • the reset operation the potential of the FD portion when reset to a predetermined potential is output from the unit pixel P to the vertical signal line 23b as a reset component.
  • the transfer operation the potential of the FD portion when the photoelectric conversion charge is transferred from the photoelectric conversion element is output as a signal component from the unit pixel P to the vertical signal line 23b.
  • a row j in the pixel region 11b is selected by row scanning by the row driving circuit 12, and after the first reading operation from the unit pixel P of the selected row j to each vertical signal line 23b is stabilized, the DAC 52b
  • the reference voltage Vrefb is supplied to the comparator 71b of each ADC 61b.
  • the comparator 71b performs a comparison operation between the signal voltage Vx of each vertical signal line 23b and the reference voltage Vrefb.
  • the clock signal CK is supplied from the timing control circuit 51 to each up / down counter 72b.
  • the mode control signal supplied from the timing control circuit 51 to each up / down counter 72b is set to L level.
  • the up / down counter 72b measures the comparison signal output time of the comparator 71b during the first read operation based on the clock signal CK by the down-count operation.
  • the output signal Vco of the comparator 71b is inverted from the “H” level to the “L” level.
  • the up / down counter 72b stops the down-counting operation and obtains a count value (digital value) corresponding to the first comparison signal output time in the comparator 71b. Hold.
  • the reset component ⁇ V of the unit pixel P is read.
  • This reset component ⁇ V includes fixed pattern noise that varies for each unit pixel P as an offset.
  • the signal component Vsig corresponding to the amount of incident light for each unit pixel P is read out by the same operation as the readout operation of the first reset component ⁇ V. That is, after the second reading from the unit pixel P of the selected row j to the vertical signal line 23b is stabilized, the reference voltage Vrefb is supplied from the DAC 52b to each comparator 71b of each ADC 61b, and at the same time from the timing control circuit 51.
  • a clock signal CK is supplied to each up / down counter 72b.
  • the mode control signal supplied from the timing control circuit 51 to each up / down counter 72b is set to H level.
  • the comparator 71b performs a comparison operation between each signal voltage Vx of the vertical signal line 23b and the reference voltage Vrefb.
  • the second comparison signal output time in the comparator 71b is measured by the up / down counter 72b by the up-counting operation contrary to the first time.
  • the count operation of the up / down counter 72b is set to the down count operation for the first time and the up count operation for the second time, so that the up / down counter 72b automatically (second comparison signal output time). )-(First comparison signal output time) is subtracted.
  • the reference voltage Vrefb becomes equal to the signal voltage Vx of the vertical signal line 23b
  • the polarity of the output signal Vco of the comparator 71b is inverted, and the counting operation of the up / down counter 72b is stopped in response to the polarity inversion.
  • the up / down counter 72b holds a count value (digital value) corresponding to the result of the subtraction process of (second comparison signal output time) ⁇ (first comparison signal output time).
  • the up / down counter 72b holds an n-bit count value.
  • a data latch signal is input from the timing control circuit 51 to each switch 73b and the switch 73b is turned on, the count value (digital signal) of the up / down counter 72b is transferred to the memory device 74b via the switch 73b.
  • the digital signal stored in each memory device 74b is output to the controller 15 for each column via the n-bit width horizontal signal line 24b.
  • the up / down counter 72b needs to be reset before the up / down counter 72b executes the count operation.
  • the up / down counter operation of the (j + 1) th row is performed without resetting the up / down counter 72b, the initial value of the up / down counter 72b becomes the AD conversion result of the previous jth row. If the same operation is repeated as it is, the up / down counter 72b holds the addition result of the jth and j + 1th rows.
  • the above operation is sequentially repeated for each row in each column of the pixel region 11a and each column of the pixel region 11b, thereby generating a two-dimensional image.
  • each ADC 61 includes a memory device 74, as shown in the timing chart of FIG. 5, AD conversion of an analog pixel signal and reading of a digital signal after AD conversion to the horizontal signal line 24 are performed. Can be performed in parallel. Specifically, each ADC 61 transfers the digital signal after AD conversion of the unit pixel P in the j-th row to the memory device 74 and outputs the digital signal to the control unit 15 through the horizontal signal line 24 while the next j + 1-th row. AD conversion of the analog pixel signal of the unit pixel P of the eye can be executed in parallel.
  • FIGS. 4 is a timing chart similar to FIG. 6, and FIG. 5 is a timing chart similar to FIG.
  • the column processing circuit 13b and the column driving circuit 14b mainly read the pixel signal of the unit pixel P in the pixel region 11b will be described.
  • the same operation is performed when the column processing circuit 13a and the column driving circuit 14a read out the pixel signal of the unit pixel P in the pixel region 11a. Further, the reading operation for each column of the pixel region 11a and each column of the pixel region 11b is performed in parallel.
  • the up / down counter 72b can hold the count value therein. Using the data holding characteristic of the up / down counter 72b, the up / down counter 72b performs vertical addition processing of the AD conversion value (digital signal) of the unit pixel P between a plurality of rows (for example, j row and j + 1 row). Is realized.
  • the up / down counter 72b is not reset, and the operation proceeds to the pixel signal reading operation of the unit pixel P of the j + 1-th row, and the same reading operation as that of the j-th row is performed. repeat.
  • the ADC 61b can output a digital signal indicating a value Vsig1 + Vsig2 obtained by vertically adding the signal components of the unit pixels P for the two rows of the jth and j + 1th rows.
  • each ADC 61 transfers a digital signal indicating the added value of the count value after AD conversion of the unit pixels P in the j-th row and the j + 1-th row to the memory device 74b and to the control unit 15 through the horizontal signal line 24b. While outputting, AD conversion of the pixel signals of the unit pixels P in the (j + 2) th row and the (j + 3) th row is executed in parallel.
  • the high-speed frame rate mode from the viewpoint of the number of read pixel information, it is the same as performing thinning-out readout (skipping readout) in half in the vertical direction.
  • the pixel information is doubled from the viewpoint of the amount of information about one pixel information. Therefore, even if the exposure time of the unit pixel P is set to 1 ⁇ 2 in order to improve the frame rate by, for example, twice, the digital value is vertically added between the unit pixels P for two rows at the time of AD conversion. Thus, the information amount for one piece of pixel information is doubled. As a result, the sensitivity does not decrease compared to the normal frame rate mode.
  • the up / down counter 72 is built in the ADC 61 and the addition processing is performed by the up / down counter 72, a high-precision addition operation can be realized without using an external memory device or adding a circuit. can do.
  • the vertical signal line is not connected between the effective pixel region 21a and the effective pixel region 21b of the pixel array unit 11, and is electrically separated. Therefore, the pixel signal of the unit pixel P in the effective pixel area 21a and the pixel signal of the unit pixel P in the effective pixel area 21b cannot be added in the ADC 61.
  • the pixel signal of the unit pixel P in the effective pixel area 21a and the pixel signal of the unit pixel P in the effective pixel area 21b are displayed in the high-speed frame rate mode. It may be necessary to add.
  • the pixel signal of the unit pixel P in the N / 2th row which is the last row of the effective pixel region 21a, and the ⁇ N / 2 ⁇ that is the first row of the effective pixel region 21b
  • the timing chart of FIG. 8 is the same timing chart as FIG.
  • the signal component of the unit pixel P in the N / 2 row is Vsig3
  • the reset component is ⁇ V3
  • the signal component of the unit pixel P in the ⁇ N / 2 ⁇ +1 row is Vsig4, and the reset component is ⁇ V4.
  • the up / down counter 72a has (second comparison signal output time) ⁇ (first comparison signal output time).
  • ⁇ V3 A count value of Vsig3 is held.
  • the timing control circuit 51 inputs a data latch signal to the switch 73a and turns on the switch 73a.
  • the count value representing the signal component Vsig3 is transferred from the up / down counter 72a to the memory device 74a via the switch 73a.
  • the pixel signal of the unit pixel P in any row of the dummy pixel region 22a (hereinafter referred to as a dummy row) is read.
  • the count value representing the component obtained by adding the signal component Vsig3 of the unit pixel P in the N / 2th row and the signal component of the unit pixel P in the dummy row is held in the up / down counter 72a.
  • the timing control circuit 51 inputs a reset control signal to the up / down counter 72a to reset the count value of the up / down counter 72a. That is, the pixel signal in the dummy row is transferred to the memory device 74a and erased without being stored. Therefore, the digital signal indicating the signal component Vsig3 of the pixel signal of the unit pixel P in the last row (N / 2 row) of the effective pixel region 21a remains stored in the memory device 74a.
  • the above processing is performed within one horizontal scanning period.
  • the timing control circuit 51 inputs a data latch signal to the switch 73b and turns on the switch 73b.
  • the count value representing the signal component Vsig4 is transferred from the up / down counter 72b to the memory device 74b via the switch 73b.
  • the up / down counter 72b holds a count value representing a component obtained by adding the signal component Vsig4 of the unit pixel P in the ⁇ N / 2 ⁇ +1 row and the signal component of the unit pixel P in the dummy row.
  • the timing control circuit 51 inputs a reset control signal to the up / down counter 72b to reset the count value of the up / down counter 72b. That is, the pixel signal in the dummy row is transferred to the memory device 74b and erased without being stored. Accordingly, the digital signal indicating the signal component Vsig4 of the pixel signal of the unit pixel P in the first row ( ⁇ N / 2 ⁇ +1 row) of the effective pixel region 21b remains stored in the memory device 74b.
  • a digital signal indicating the signal component Vsig3 of the unit pixel P of N / 2 rows stored in each memory device 74a is transmitted through the horizontal signal line 24a by the column scanning by the column driving circuit 14a. And output to the control unit 15 for each column.
  • the above processing is performed within one horizontal scanning period.
  • AD conversion and vertical conversion of the signal components of the unit pixels P in ⁇ N / 2 ⁇ +2 rows and ⁇ N / 2 ⁇ +3 rows are performed. Addition is performed.
  • a digital signal indicating the signal component Vsig4 of the unit pixel P in ⁇ N / 2 ⁇ +1 row stored in each memory device 74b is applied to the horizontal signal line 24b by column scanning by the column driving circuit 14b. And output to the control unit 15 for each column.
  • control unit 15 adds the digital signal indicating the signal component Vsig3 of the unit pixel P in the N / 2th row and the digital signal indicating the signal component Vsig4 of the unit pixel P in the ⁇ N / 2 ⁇ + 1th row. Output.
  • the pixel signal of the unit pixel P in the pixel area 11a and the pixel signal of the unit pixel P in the pixel area 11b can be vertically added and output. Accordingly, it is possible to obtain a pixel signal obtained by vertically adding a digital signal actually obtained without performing an interpolation process or the like, thereby preventing deterioration in image quality.
  • the same processing as the vertical addition processing of other rows can be executed except that the pixel signal of the dummy row is read and the timing of reading the count value of the up / down counter 72 is different. As a result, it is possible to prevent deterioration in image quality due to a change in signal characteristics due to special processing or operation.
  • the present technology is not limited to the combination of the last row of the effective pixel region 21a and the first row of the effective pixel region 21b, and is vertical between any row of the effective pixel region 21a and any row of the effective pixel region 21b. It can also be applied to the case of addition. For example, in the Bayer parallel shown in FIG. 2, pixels of the same color are arranged every other row, and therefore, for example, vertical addition between odd rows and even rows may be performed. Also in this case, vertical addition can be performed, for example, between the last odd row of the effective pixel region 21a and the first odd row of the effective pixel region 21b by the same method as described above.
  • the present technology can be applied to the case of performing vertical addition of three lines or more. For example, when vertical addition of a + b rows is performed, a pixel signal of unit pixels P for the last a rows of the effective pixel region 21a and a pixel signal of unit pixels P for the first b rows of the effective pixel region 21b are obtained.
  • a and b are integers of 1 or more
  • a + b is an integer of 3 or more.
  • the pixel signal of the unit pixel P corresponding to the last a rows of the effective pixel region 21a is read.
  • the read pixel signals are added by the up / down counter 72a and then stored in the memory device 74a.
  • the pixel signal of the p unit pixel P for b rows in the dummy pixel region 22a is read.
  • pixel signals of the same dummy row may be read b times, or pixel signals of dummy rows for b rows may be read.
  • the read pixel signal is reset without being transferred from the up / down counter 72a to the memory device 74a.
  • the above processing is performed within one horizontal scanning period.
  • pixel signals of the unit pixels P for the first b rows of the effective pixel region 21b are read.
  • the read pixel signals are added by the up / down counter 72b and then stored in the memory device 74b.
  • the pixel signal of the unit pixel P for a row in the dummy pixel region 22b is read.
  • pixel signals in the same dummy row may be read a times, or pixel signals in dummy rows for a rows may be read.
  • the read pixel signal is reset without being transferred from the up / down counter 72b to the memory device 74b.
  • a digital signal representing the vertical addition value of the unit pixels P for the last a rows of the effective pixel region 21a stored in the memory device 74a is sent to the control unit 15 via the horizontal signal line 24a. Transferred.
  • the above processing is performed within one horizontal scanning period.
  • pixel signals of the unit pixels P from the b + 1th row to the a + 2bth row of the effective pixel region 21b are read.
  • the read pixel signals are added by the up / down counter 72b and then stored in the memory device 74b.
  • a digital signal representing the vertical addition value of the unit pixels P for the first b rows of the effective pixel region 21b stored in the memory device 74b is sent to the control unit 15 via the horizontal signal line 24b. Transferred.
  • control unit 15 adds the digital signal obtained by adding the pixel signals of the unit pixels P for the last a rows of the effective pixel region 21a and the pixel signal of the unit pixels P for the first b rows of the effective pixel region 21b.
  • the digital signal is added and output.
  • the readout of the pixel signal of the N / 2 row and the readout order of the pixel signal of the dummy row are reversed, the readout of the pixel signal of the ⁇ N / 2 ⁇ +1 row, and the dummy It is possible to reverse the readout order of the pixel signals in the row.
  • the present technology can also be applied to a case where the pixel array unit is divided into three or more pixel regions in units of rows in the column direction (vertical direction).
  • the pixel array unit is divided into three or more pixel regions in units of rows in the column direction (vertical direction).
  • the resulting image will have line defects.
  • the CMOS image sensor has a multilayer structure.
  • the CMOS image sensor 100 has a structure in which a substrate 101 and a substrate 102 are stacked.
  • a pixel array unit 111 is formed on the substrate 101.
  • the pixel array unit 111 is divided into n effective pixel regions 121-1 to 121-n in the column direction (vertical direction).
  • the effective pixel regions 121-1 to 121-n are each provided with a vertical signal line (not shown) for each column, and no vertical signal line is connected between the effective pixel regions.
  • dummy pixel regions 131-1 to 131-n On the substrate 102, dummy pixel regions 131-1 to 131-n, column processing circuits 132-1 to 132-n, and column drive circuits 133-1 to 133-n are formed.
  • the column processing circuit 132-j and the column driving circuit 133-j are provided so as to correspond to a set of the effective pixel region 121-j and the dummy pixel region 131-j.
  • the column processing circuits 132-1 to 132-n have, for example, the same configuration as the column processing circuit 13b in FIG.
  • the column drive circuits 133-1 to 133-n have the same configuration as the column drive circuits 14a and 14b in FIG.
  • dummy pixel regions 131-1 to 131-n can be individually provided for the effective pixel regions 121-1 to 121-n of the pixel array unit 111, respectively. Further, since the dummy pixel regions 131-1 to 131-n are provided in a region different from the pixel array unit 111, there is no defect in a row in the generated image.
  • the pixel signals of the unit pixels P in different effective pixel areas can be vertically added by the same method as described above.
  • the column driving circuit is not necessarily provided for each column processing circuit.
  • the column driving circuits may be combined into one to drive a plurality of column processing circuits from one column driving circuit.
  • the dummy pixel region can be configured by one pixel row.
  • the present technology is not limited to application to a CMOS image sensor. That is, the present technology can be applied to all XY address type solid-state imaging devices in which unit pixels are two-dimensionally arranged in a matrix.
  • the present technology is not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and captures it as an image, but a solid-state that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. Applicable to all imaging devices.
  • the solid-state imaging device may be formed as a single chip, or may be in a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.
  • FIG. 10 is a diagram illustrating a usage example of the above-described solid-state imaging device.
  • the solid-state imaging device described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.
  • Devices for taking images for viewing such as digital cameras and mobile devices with camera functions
  • Devices used for traffic such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc.
  • Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ⁇ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc.
  • Equipment used for medical and health care ⁇ Security equipment such as security surveillance cameras and personal authentication cameras ⁇ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports, such as action cameras and wearable cameras for sports applications, etc.
  • Equipment used for agriculture such as cameras for monitoring the condition of fields and crops
  • FIG. 11 is a block diagram illustrating a configuration example of an electronic device 200 that is an example of an electronic device to which the present technology is applied.
  • the electronic device 200 includes a solid-state imaging device (element chip) 201, an optical lens 202, a shutter device 203, a drive circuit 204, and a signal processing circuit 205.
  • a solid-state imaging device 201 for example, the above-described CMOS image sensor 10 or the CMOS image sensor 100 is provided.
  • the optical lens 202 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 201. Thereby, signal charges are accumulated in the solid-state imaging device 201 for a certain period.
  • the shutter device 203 controls a light irradiation period and a light shielding period for the solid-state imaging device 201.
  • the drive circuit 204 supplies a drive signal for controlling the signal transfer operation of the solid-state imaging device 201 and the shutter operation of the shutter device 203.
  • the solid-state imaging device 201 performs signal transfer by a drive signal (timing signal) supplied from the drive circuit 204.
  • the signal processing circuit 205 performs various types of signal processing on the signal output from the solid-state imaging device 201.
  • the video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.
  • the present technology can take the following configurations.
  • a plurality of effective pixel regions in which unit pixels used for image generation are arranged in a matrix are arranged in a column direction, and a vertical signal line is wired for each column of the effective pixel region, and the vertical signal line is the effective pixel region.
  • a pixel array unit that is not connected between, A plurality of dummy pixel regions that are provided so as to correspond to each of the effective pixel regions and in which at least one row of unit pixels that are not used for generating the image is arranged; A row driving unit for driving unit pixels of the effective pixel region and the dummy pixel region in units of rows; Analog signals output from the unit pixels of the row selected by the row driving unit via the vertical signal line are provided for each column, corresponding to each set of the effective pixel region and the dummy pixel region.
  • a plurality of column processing units capable of converting into digital signals and adding and outputting digital signals of a plurality of rows of unit pixels; and A signal processing unit for processing a digital signal output from each of the column processing units, When adding the pixel signal in the r1 row of the first effective pixel region and the pixel signal in the r2 row of the second effective pixel region, The row driving unit outputs a first analog signal from the unit pixel in the r1th row to a first column processing unit corresponding to the first effective pixel region, and corresponds to the first effective pixel region.
  • a second analog signal is output from the first dummy pixel region to the first column processing unit, and the second column processing unit corresponding to the second effective pixel region is supplied from the unit pixel in the r2 row to the second column processing unit.
  • 3 analog signal, and control to output the fourth analog signal from the second dummy pixel region corresponding to the second effective pixel region to the second column processing unit The first column processing unit outputs a first digital signal corresponding to the first analog signal, does not output a second digital signal corresponding to the second analog signal, The second column processing unit outputs a third digital signal corresponding to the third analog signal, does not output a fourth digital signal corresponding to the fourth analog signal, The signal processing unit adds and outputs the first digital signal and the third digital signal.
  • the first column processing unit performs analog / digital conversion of the first analog signal and the second analog signal within a first horizontal scanning period, and performs the first / second conversion after the first horizontal scanning period. Outputting the first digital signal within two horizontal scanning periods;
  • the second column processing unit performs analog / digital conversion of the third analog signal and the fourth analog signal within the second horizontal scanning period, and performs the next to the second horizontal scanning period.
  • the solid-state imaging device according to (1), wherein the third digital signal is output within a third horizontal scanning period.
  • the first column processing unit includes a first analog / digital conversion unit including a first memory for each column
  • the second column processing unit includes a second analog / digital conversion unit including a second memory for each column
  • the first analog / digital conversion unit converts the first analog signal into the first digital signal within the first horizontal scanning period, and converts the first digital signal into the first memory.
  • the second analog signal is converted into the second digital signal, the second digital signal is erased without being stored in the first memory, and the second horizontal signal is stored within the second horizontal scanning period.
  • the second analog / digital conversion unit converts the third analog signal into the third digital signal within the second horizontal scanning period, and converts the third digital signal into the second memory.
  • the fourth analog signal is converted into the fourth digital signal, the fourth digital signal is erased without being stored in the second memory, and the third horizontal scanning period is reached.
  • the pixel signals of the unit pixels for a row (a ⁇ 1) of the first effective pixel region and the pixel signals of the unit pixels for b row (b ⁇ 1) of the second effective pixel region are added. If The row driving unit outputs a fifth analog signal to the first column processing unit from unit pixels corresponding to a rows in the first effective pixel region, and from the unit pixels in the first dummy pixel region.
  • a sixth analog signal for b rows is output to the first column processing unit, and a seventh analog signal is output to the second column processing unit from unit pixels for b rows in the second effective pixel region.
  • a unit pixel in the second dummy pixel region is controlled to output an eighth row analog signal to the second column processing unit;
  • the first column processing unit outputs a fifth digital signal indicating a value obtained by adding the fifth analog signals for a rows, and outputs a sixth digital signal corresponding to the sixth analog signals for b rows.
  • No digital signal output The second column processing unit outputs a seventh digital signal indicating a value obtained by adding the seventh analog signals for b rows and outputs an eighth digital signal corresponding to the eighth analog signals for a rows.
  • the solid-state imaging device according to any one of (1) to (3), wherein the signal processing unit adds and outputs the fifth digital signal and the seventh digital signal.
  • the pixel array unit includes the first effective pixel region, the second effective pixel region, the first dummy pixel region, and the second dummy pixel region, and the first dummy pixel region.
  • the first effective pixel region, the second effective pixel region, and the second dummy pixel region are arranged so as to be arranged in the column direction in this order.
  • the pixel array unit is disposed on a first substrate; Each said dummy pixel area
  • a plurality of effective pixel regions in which unit pixels used for image generation are arranged in a matrix are arranged in a column direction, and a vertical signal line is wired for each column of the effective pixel region, and the vertical signal line is the effective pixel region.
  • a pixel array unit that is not connected between, A plurality of dummy pixel regions that are provided so as to correspond to each of the effective pixel regions and in which at least one row of unit pixels that are not used for generating the image is arranged; A row driving unit for driving unit pixels of the effective pixel region and the dummy pixel region in units of rows; Analog signals output from the unit pixels of the row selected by the row driving unit via the vertical signal line are provided for each column, corresponding to each set of the effective pixel region and the dummy pixel region.
  • a plurality of column processing units capable of converting into digital signals and adding and outputting digital signals of a plurality of rows of unit pixels; and
  • a solid-state imaging device comprising: a signal processing unit that processes a digital signal output from each of the column processing units, When adding the pixel signal in the r1 row of the first effective pixel region and the pixel signal in the r2 row of the second effective pixel region, A first analog signal is output from the unit pixel in the r1 row to a first column processing unit corresponding to the first effective pixel region; A second analog signal is output from the first dummy pixel region corresponding to the first effective pixel region to the first column processing unit; A third analog signal is output from the unit pixel in the r2 row to a second column processing unit corresponding to the second effective pixel region; A fourth analog signal is output from the second dummy pixel region corresponding to the second effective pixel region to the second column processing unit; From the first column processing unit, a first digital signal corresponding to the first analog signal is output,
  • a plurality of effective pixel regions in which unit pixels used for image generation are arranged in a matrix are arranged in a column direction, and a vertical signal line is wired for each column of the effective pixel region, and the vertical signal line is the effective pixel region.
  • a pixel array unit that is not connected between, A plurality of dummy pixel regions that are provided so as to correspond to each of the effective pixel regions and in which at least one row of unit pixels that are not used for generating the image is arranged; A row driving unit for driving unit pixels of the effective pixel region and the dummy pixel region in units of rows; Analog signals output from the unit pixels of the row selected by the row driving unit via the vertical signal line are provided for each column, corresponding to each set of the effective pixel region and the dummy pixel region.
  • a plurality of column processing units capable of converting into digital signals and adding and outputting digital signals of a plurality of rows of unit pixels; and A signal processing unit for processing a digital signal output from each of the column processing units, When adding the pixel signal in the r1 row of the first effective pixel region and the pixel signal in the r2 row of the second effective pixel region, The row driving unit outputs a first analog signal from the unit pixel in the r1th row to a first column processing unit corresponding to the first effective pixel region, and corresponds to the first effective pixel region.
  • a second analog signal is output from the first dummy pixel region to the first column processing unit, and the second column processing unit corresponding to the second effective pixel region is supplied from the unit pixel in the r2 row to the second column processing unit.
  • 3 analog signal, and control to output the fourth analog signal from the second dummy pixel region corresponding to the second effective pixel region to the second column processing unit The first column processing unit outputs a first digital signal corresponding to the first analog signal, does not output a second digital signal corresponding to the second analog signal, The second column processing unit outputs a third digital signal corresponding to the third analog signal, does not output a fourth digital signal corresponding to the fourth analog signal,
  • An electronic apparatus comprising: a solid-state imaging device, wherein the signal processing unit adds and outputs the first digital signal and the third digital signal.
  • CMOS image sensor 11 pixel array section, 11a, 11b pixel area, 12 row drive circuit, 13a, 13b column processing circuit, 14a, 14b column drive circuit, 15 control section, 16 correction section, 21a, 21b effective pixel area, 22a, 22b dummy pixel area, 23a-1 to 23a-M, 23b-1 to 23b-M vertical signal line, 24a, 24b horizontal signal line, 51 timing control circuit, 52a, 52b DAC, 61a-1 to 61a-M , 61b-1 to 61b-M ADC, 71a-1 to 71a-M, 71b-1 to 71b-M comparator, 72a-1 to 72a-M, 72b-1 to 72b-M up / down counter, 73a- 1 to 73a-M, 73b-1 to 73b- Switch, 74a-1 to 74a-M, 74b-1 to 74b-M memory device, 100 CMOS image sensor, 101, 102 substrate, 111 pixel array

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Abstract

L'invention concerne un dispositif d'imagerie à semi-conducteurs, un procédé de commande du dispositif d'imagerie à semi-conducteurs et un dispositif électronique, selon lesquels des signaux de pixels peuvent être additionnés entre des zones de pixels sans provoquer de détérioration de la qualité d'image. Lors de l'addition de signaux de pixels de rangée r1 d'une première zone de pixels efficaces et de signaux de pixels de rangée r2 d'une seconde zone de pixels efficaces, un premier signal analogique est délivré en sortie d'un pixel unitaire de rangée r1 à une première unité de traitement de colonnes, un deuxième signal analogique est délivré en sortie d'une première zone de pixels fictifs à la première unité de traitement de colonnes, un troisième signal analogique est délivré en sortie d'un pixel unitaire de rangée r2 à une seconde unité de traitement de colonnes, un quatrième signal analogique est délivré en sortie d'une seconde zone de pixels fictifs à la seconde unité de traitement de colonnes, un premier signal numérique est délivré en sortie par la première unité de traitement de colonnes, un troisième signal numérique est délivré en sortie par la seconde unité de traitement de colonnes sans délivrance en sortie d'un deuxième signal numérique, et le premier signal numérique et le troisième signal numérique sont additionnés et délivrés en sortie par une unité de traitement de signaux sans délivrance en sortie d'un quatrième signal numérique. La présente invention peut être appliquée, par exemple, à un dispositif d'imagerie à semi-conducteurs.
PCT/JP2016/064086 2015-05-26 2016-05-12 Dispositif d'imagerie à semi-conducteurs, procédé de commande de dispositif d'imagerie à semi-conducteurs et dispositif électronique WO2016190116A1 (fr)

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WO2018131521A1 (fr) * 2017-01-12 2018-07-19 ソニーセミコンダクタソリューションズ株式会社 Élément de capture d'image et instrument électronique
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JP2021150800A (ja) * 2020-03-18 2021-09-27 株式会社リコー 光電変換装置、画像読取装置、画像形成装置、及び撮像システム

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JP2004194248A (ja) * 2002-12-13 2004-07-08 Chinon Ind Inc 撮像素子及び撮像装置
JP2006033453A (ja) * 2004-07-16 2006-02-02 Sony Corp データ処理方法並びに物理量分布検知の半導体装置および電子機器
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WO2018131521A1 (fr) * 2017-01-12 2018-07-19 ソニーセミコンダクタソリューションズ株式会社 Élément de capture d'image et instrument électronique
CN110291414A (zh) * 2017-02-21 2019-09-27 索尼半导体解决方案公司 距离测量装置和距离测量方法
CN110291414B (zh) * 2017-02-21 2023-11-28 索尼半导体解决方案公司 距离测量装置和距离测量方法
WO2019193799A1 (fr) * 2018-04-04 2019-10-10 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteurs
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