WO2016180003A1 - 触控电路、触控面板及显示装置 - Google Patents

触控电路、触控面板及显示装置 Download PDF

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Publication number
WO2016180003A1
WO2016180003A1 PCT/CN2015/095372 CN2015095372W WO2016180003A1 WO 2016180003 A1 WO2016180003 A1 WO 2016180003A1 CN 2015095372 W CN2015095372 W CN 2015095372W WO 2016180003 A1 WO2016180003 A1 WO 2016180003A1
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WIPO (PCT)
Prior art keywords
signal
node
potential
touch
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/095372
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English (en)
French (fr)
Inventor
黄飞
乔赟
李付强
李成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US15/129,176 priority Critical patent/US10198135B2/en
Publication of WO2016180003A1 publication Critical patent/WO2016180003A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04106—Multi-sensing digitiser, i.e. digitiser using at least two different sensing technologies simultaneously or alternatively, e.g. for detecting pen and finger, for saving power or for improving position detection

Definitions

  • the present disclosure relates to a touch circuit, a touch panel, and a display device.
  • the touch screen can be divided into an add-on touch panel, an on-cell touch panel, and an in-cell touch panel according to the composition structure.
  • the external touch screen is produced by separately separating the touch screen from the display screen, and then being bonded together to become a touch screen display function.
  • the external touch screen has the disadvantages of high production cost, low light transmittance, and thick module.
  • the in-cell touch screen embeds the touch electrodes of the touch screen inside the display screen, which can reduce the overall thickness of the module, and can greatly reduce the manufacturing cost of the touch screen, and is favored by major panel manufacturers.
  • the mutual capacitive touch screen has become the mainstream of the development of the embedded touch screen technology by virtue of its high sensitivity and multi-touch advantages.
  • the in-cell touch panel is a device in which a touch scan line and a touch sensor line in the touch screen are integrated in the display screen, such as a touch scan line and a touch sensor line integrated in a liquid crystal display (LCD). Or in an Organic Light Emitting Device (OLED).
  • LCD liquid crystal display
  • OLED Organic Light Emitting Device
  • a touch driving circuit for outputting a touch scan signal to a touch scan line is generally integrated on the array substrate to eliminate the trace of the display frame area, thereby realizing a narrow frame design of the large size display screen.
  • the embodiments of the present disclosure provide a touch control circuit, a touch panel, and a display device, which are used to solve the problem that the touch circuit structure in the prior art is complicated and consumes a large amount of power.
  • the embodiment of the present disclosure provides a touch control circuit, including: an input module, a reset module, a pull-up module, a pull-down module, a pull-down control module, and a touch signal output module, where:
  • the control end of the input module is connected to the input signal input end, the input end is connected to the first reference signal end, and the output end is connected to the first node, and the input module is configured to be under the control of the input signal end a signal of the first reference signal end is provided to the first node;
  • the control end of the reset module is connected to the reset signal end, the input end is connected to the second reference signal end, and the output end is connected to the first node; the reset module is configured to control the reset signal end a signal of the second reference signal end is provided to the first node;
  • the control end of the pull-up module is connected to the first node, the input end is connected to the first clock signal end, and the output end is connected to the control signal output end; the pull-up module is used for the potential at the first node When the first potential is, the signal of the first clock signal end is provided to the control signal output end;
  • the control end of the pull-down module is connected to the second node, the input end is connected to the third reference signal end, and the output end is connected to the control signal output end;
  • the pull-down module is used for the potential of the second node At a potential, the signal of the third reference signal end is provided to the control signal output end;
  • the pull-down control module is respectively connected to the second clock signal end, the first node node and the second node; the pull-down control module is configured to, under the control of the second clock signal end, the second a signal of the clock signal end is supplied to the second node, and when the potential of the first node is the first potential, the potential of the second node is controlled to be a second potential, and the potential of the second node is the first At a potential, controlling the potential of the first node to be a second potential;
  • the first input end of the touch signal output module is connected to the control signal output end, the second input end is connected to the high frequency signal end, and the third input end is connected to the common voltage signal end;
  • the touch signal output module For outputting a high frequency signal or a common voltage signal to the touch signal output end under the control of the output end of the control signal;
  • the first potential is a high potential
  • the second potential is a low potential
  • the first potential is a low potential
  • the second potential is a high potential
  • the input signal terminal outputs an effective pulse signal
  • the first clock signal end and the second clock signal end alternately output a first potential signal
  • the pull-down control module includes: a first pull-down control unit, a second pull-down control unit, and a third pull-down control unit;
  • the control end and the input end of the first pull-down control unit are both connected to the second clock signal end, and the output end is connected to the second node;
  • the first pull-down control unit is used for controlling at the second clock signal end And providing a signal of the second clock signal end to the second node;
  • a control end of the second pull-down control unit is connected to the first node, an input end is connected to the third reference signal end, and an output end is connected to the second node;
  • the second pull-down control unit is configured to be in the When the potential of the first node is the first potential, the signal of the third reference signal end is provided to the second node;
  • the control end of the third pull-down control unit is connected to the second node, the input end is connected to the third reference signal end, and the output end is connected to the first node; the third pull-down control unit is used to When the potential of the second node is the first potential, the signal of the third reference signal end is provided to the first node.
  • the pull-down control module further includes: a fourth pull-down control unit;
  • a control end of the fourth pull-down control unit is connected to the control signal output end, an input end is connected to the third reference signal end, and an output end is connected to the second node; the fourth pull-down control unit is used for And when the potential of the output end of the control signal is the first potential, the signal of the third reference signal end is provided to the second node.
  • the first pull-down control unit includes: a first switching transistor
  • the first switching transistor has a gate and a source connected to the second clock signal end, and a drain connected to the first node.
  • the second pull-down control unit includes: a second switching transistor
  • the second switching transistor has a gate connected to the first node, a source connected to the third reference signal end, and a drain connected to the second node.
  • the third pull-down control unit includes: a third switching transistor
  • the third switching transistor has a gate connected to the second node, a source connected to the third reference signal terminal, and a drain connected to the first node.
  • the fourth pull-down control unit includes: a fourth switching transistor
  • the fourth switching transistor has a gate connected to the control signal output terminal, a source connected to the third reference signal terminal, and a drain connected to the second node.
  • the touch signal output module includes: a high frequency signal output unit, a common voltage signal output unit, a pull up unit, and a pull down unit; among them,
  • the control end of the pull-up unit is a first input end of the touch signal output module, the input end is connected to the low-frequency signal end, and the output end is connected to the third node; the pull-up unit is used for the control signal When the potential of the output terminal is the first potential, the signal of the low frequency signal end is provided to the third node;
  • the control end of the pull-down unit is connected to the cut-off signal end, the input end is connected to the third node, and the output end is connected to the third reference signal end, and the pull-down unit is used under the control of the cut-off signal end, Providing a signal of the third reference signal end to the third node;
  • the control end of the high-frequency signal output unit is connected to the third node, the input end is a second input end of the touch signal output module, and the output end is connected to the touch signal output end;
  • the signal output unit is configured to control the output of the touch signal to output a high frequency signal when the potential of the third node is the first potential;
  • the common voltage signal output unit is connected between the third node, the third reference signal end, the fourth reference signal end, the common voltage signal end, and the touch signal output end, the common The voltage signal output unit is configured to control the touch signal output end to output a common voltage signal when the potential of the third node is the second potential.
  • the pull-up unit includes: a fifth switch transistor
  • the fifth switching transistor has a gate connected to the control signal output terminal, a source connected to the low frequency signal end, and a drain connected to the third node.
  • the pull-down unit includes: a sixth switching transistor
  • the sixth switching transistor has a gate connected to the cut-off signal end, a source connected to the third reference signal end, and a drain connected to the third node.
  • the high frequency signal output unit includes: a seventh switching transistor and a first capacitor; wherein
  • the seventh switching transistor has a gate connected to the third node, a source connected to the high frequency signal end, and a drain connected to the touch signal output end;
  • the first capacitor is connected between the gate and the drain of the seventh switching transistor.
  • the common voltage signal output unit includes: an eighth switching transistor and a ninth switching transistor; wherein
  • the eighth switching transistor has a gate connected to the fourth reference signal end, a source connected to the common voltage signal end, and a drain connected to the touch signal output end;
  • the ninth switching transistor has a gate connected to the third node, a source connected to the third reference signal terminal, and a drain connected to the fourth reference signal terminal.
  • the input module includes: a tenth switch transistor; wherein
  • the tenth switching transistor has a gate connected to the input signal terminal, a source connected to the first reference signal end, and a drain connected to the first node.
  • the reset module includes: an eleventh switch transistor; wherein
  • the eleventh switching transistor has a gate connected to the reset signal end, a source connected to the second reference signal end, and a drain connected to the first node.
  • the pull-up module includes: a twelfth switching transistor and a second capacitor; wherein
  • the twelfth switching transistor has a gate connected to the first node, a source connected to the first clock signal end, and a drain connected to the control signal output end;
  • the second capacitor is connected between the gate and the drain of the twelfth switching transistor.
  • the pull-down module includes: a thirteenth switching transistor; wherein
  • the thirteenth switching transistor has a gate connected to the second node, a source connected to the third reference signal end, and a drain connected to the control signal output end.
  • the embodiment of the present disclosure further provides a touch panel, including the touch control circuit provided by the plurality of embodiments of the present disclosure
  • control signal output ends of the other touch circuits are connected to the reset signal terminals of the adjacent upper-level touch circuits;
  • control signal output ends of the other touch circuits are connected to the signal input terminals of the adjacent lower touch circuits.
  • an embodiment of the present disclosure provides a display device including the above touch panel provided by an embodiment of the present disclosure.
  • the touch control circuit, the touch panel and the display device include: an input module, a reset module, a pull-up module, a pull-down module, a pull-down control module, and a touch signal output module; wherein the input module is used in The signal of the first reference signal end is supplied to the first node under the control of the input signal end; the reset module is configured to provide the signal of the second reference signal end to the control at the reset signal end a node; the pull-up module is configured to provide a signal of the first clock signal end to the control signal output end when the potential of the first node is the first potential; and the pull-down module is configured to when the potential of the second node is the first potential Providing a signal of the third reference signal end to the control signal output end; the pull-down control module is configured to provide the signal of the second clock signal end to the second node under the control of the second clock signal end, and the potential at the first node is first At the potential, the potential of the second node is controlled to be
  • the touch control circuit to output the touch signal
  • the touch control circuit is configured by using the thin film transistor to construct the transmission gate, the inverter, and the three-state gate circuit.
  • the touch circuit has a simple structure and low power consumption.
  • 1 is a schematic structural view of a commonly used touch circuit
  • FIG. 2 is a schematic structural diagram of a touch circuit provided in an embodiment of the present disclosure
  • 3a is a schematic structural diagram of a touch circuit provided in another embodiment of the present disclosure.
  • 3b is a schematic structural diagram of a touch circuit provided in still another embodiment of the present disclosure.
  • FIG. 4a is a schematic structural diagram of a specific circuit of a touch circuit according to an embodiment of the present disclosure
  • 4b is a schematic structural diagram of another specific circuit of the touch circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another specific circuit of the touch circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another specific circuit of the touch circuit according to an embodiment of the present disclosure.
  • FIG. 6a is a schematic diagram showing the operation timing of the touch circuit shown in FIG. 5a;
  • 6b is a schematic diagram showing the operation timing of the touch circuit shown in FIG. 5b;
  • FIG. 7a and 7b are schematic diagrams showing the operation timings of sequentially outputting touch signals by the cascaded touch circuits provided by the embodiments of the present disclosure.
  • FIG. 1 is a schematic structural view of a conventional touch circuit.
  • ICs external drivers
  • the number of touch scan lines Txn increases.
  • the number of traces for transmitting touch scan signals to the touch scan line Txn is correspondingly increased, thereby increasing the space occupied by the traces, thereby limiting the in-line technology on the large-sized and narrow-frame display.
  • the touch circuit includes: an input module 1 , a reset module 2 , a pull-up module 3 , a pull-down module 4 , a pull-down control module 5 , and a touch signal output module 6 .
  • the control terminal of the input module 1 is connected to the input signal input terminal, the input terminal is connected to the first reference signal terminal Vref1, and the output terminal is connected to the first node P1.
  • the input module 1 is configured to provide a signal of the first reference signal terminal Vref1 to the first node P1 under the control of the input signal terminal Input.
  • the control terminal of the reset module 2 is connected to the reset signal terminal Reset, the input terminal is connected to the second reference signal terminal Vref2, and the output terminal is connected to the first node P1.
  • the reset module 2 is configured to provide the signal of the second reference signal terminal Vref2 to the first node P1 under the control of the reset signal terminal Reset.
  • the control terminal of the pull-up module 3 is connected to the first node P1, the input terminal is connected to the first clock signal terminal CK, and the output terminal is connected to the control signal output terminal OUT.
  • the pull-up module 3 is configured to supply the signal of the first clock signal terminal CK to the control signal output terminal OUT when the potential of the first node P1 is the first potential.
  • the control terminal of the pull-down module 4 is connected to the second node P2, the input terminal is connected to the third reference signal terminal Vref3, and the output terminal is connected to the control signal output terminal OUT.
  • the pull-down module 4 is configured to supply the signal of the third reference signal terminal Vref3 to the control signal output terminal OUT when the potential of the second node P2 is the first potential.
  • Each end of the pull-down control module 5 is connected to the second clock signal terminal CKB, the first node node P1 and the second node P2, respectively.
  • the pull-down control module 5 is configured to provide a signal of the second clock signal terminal CKB to the second node P2 under the control of the second clock signal terminal CKB, and control the second node when the potential of the first node P1 is the first potential
  • the potential of P2 is the second potential, and when the potential of the second node P2 is the first potential, the potential of the first node P1 is controlled to be the second potential.
  • the first input end of the touch signal output module 6 is connected to the control signal output terminal OUT, the second input end is connected to the high frequency signal terminal TH, and the third input end is connected to the common voltage signal terminal Vcom.
  • the touch signal output module 6 is configured to output a high frequency signal or a common voltage signal to the touch signal output terminal TX under the control of the control signal output terminal OUT;
  • the first potential When the effective pulse signal of the input signal terminal Input is a high potential signal, the first potential is high, The second potential is a low potential; when the effective pulse signal of the input signal terminal is a low potential signal, the first potential is a low potential, the second potential is a high potential; and when the input signal terminal Input starts to output a valid pulse signal, the first clock
  • the signal terminal CK and the second clock signal terminal CKB alternately output the first potential signal.
  • the touch control circuit includes: an input module, a reset module, a pull-up module, a pull-down module, a pull-down control module, and a touch signal output module; wherein the input module is configured to be controlled under the control of the input signal end a signal of a reference signal end is provided to the first node; a reset module is configured to provide a signal of the second reference signal end to the first node at the control of the reset signal end; and the pull-up module is configured to: when the potential of the first node is the first potential, Providing a signal of the first clock signal end to the control signal output end; the pull-down module is configured to provide a signal of the third reference signal end to the control signal output end when the potential of the second node is the first potential; the pull-down control module is configured to Under the control of the second clock signal end, the signal of the second clock signal end is supplied to the second node, and when the potential of the first node is the first potential, the potential of the second node is controlled
  • the touch control circuit provided by the embodiment of the present disclosure has a simple structure and low power consumption, as compared with the touch circuit in which the transmission gate, the inverter, and the tri-state gate circuit are formed by using a plurality of thin film transistors.
  • the signal of the first reference signal end is a high potential
  • the second reference signal end and the first The signals of the three reference signal terminals are all low potential; when the effective pulse signal of the input signal terminal Input is a low potential signal, the signal of the first reference signal end is low, and the signals of the second reference signal end and the third reference signal end are both high. Potential.
  • FIG. 3a is a schematic structural diagram of a touch circuit provided in another embodiment of the present disclosure.
  • the pull-down control module 5 may include a first pull-down control unit 51, a second pull-down control unit 52, and a third pull-down control unit 53.
  • control terminal and the input terminal of the first pull-down control unit 51 are both connected to the second clock signal terminal CKB, and the output terminal is connected to the second node P2.
  • the first pull-down control unit 51 is configured to provide the signal of the second clock signal terminal CKB to the second node P2 under the control of the second clock signal terminal CKB.
  • the control end of the second pull-down control unit 52 is connected to the first node P1, and the input end and the third reference letter
  • the terminal Vref3 is connected, and the output terminal is connected to the second node P2.
  • the second pull-down control unit 52 is configured to provide a signal of the third reference signal terminal Vref3 to the second node P2 when the potential of the first node P1 is the first potential.
  • the control end of the third pull-down control unit 53 is connected to the second node P2, the input end is connected to the third reference signal terminal Vref3, and the output end is connected to the first node P1.
  • the third pull-down control unit 53 is configured to provide the signal of the third reference signal terminal Vref3 to the first node P1 when the potential of the second node P2 is the first potential.
  • the second pull-down control unit when the potential of the first node is the first potential, the second pull-down control unit provides the signal of the third reference signal end to the second node, so that the second The potential of the node is the second potential; and the first pull-down control unit supplies the signal of the second clock signal to the second node when the signal of the second clock signal is the first potential, so that the potential of the second node is the first a potential; when the potential of the second node is the first potential, the third pull-down control unit supplies the signal of the third reference signal end to the first node, so that the potential of the first node is the second potential; thereby implementing the first node and At the same time, the second node has only one node whose potential is the first potential, thereby ensuring a normal stable output of the control signal output terminal.
  • FIG. 3b is a schematic structural diagram of a touch circuit provided in still another embodiment of the present disclosure.
  • the pull-down control module 5 may further include: a fourth pull-down control unit 54.
  • the control terminal of the fourth pull-down control unit 54 is connected to the control signal output terminal OUT, the input terminal is connected to the third reference signal terminal Vref3, and the output terminal is connected to the second node P2.
  • the fourth pull-down control unit 54 is configured to provide the signal of the third reference signal terminal Vref3 to the second node P2 when the potential of the control signal output terminal OUT is the first potential, thereby further ensuring the stability of the signal at the output of the control signal. .
  • the first pull-down control unit 51 may include: a first switching transistor T1.
  • the gate and the source of the first switching transistor T1 are both connected to the second clock signal terminal CKB, and the drain is connected to the first node P1.
  • the above touch circuit provided by the embodiment of the present disclosure is as shown in FIG. 4a.
  • the first switching transistor T1 when the effective pulse signal of the input signal terminal Input is a high potential signal, the first switching transistor T1 is an N-type transistor.
  • the first switching transistor T1 when the effective pulse signal of the input signal terminal Input is a low potential signal, the first switching transistor T1 is a P-type transistor.
  • the N-type transistor is in an on state when its gate potential is low, and is in an off state when its gate potential is high; the P-type transistor is in an on state when its gate potential is low. It is in an off state when its gate potential is high.
  • the foregoing is only a specific structure of the first pull-down control unit in the touch control circuit.
  • the specific structure of the first pull-down control unit is not limited to the foregoing structure provided by the embodiment of the present disclosure, and may also be a technology in the field. Other structures known to the person are not limited herein.
  • the second pull-down control unit 52 may include: a second switching transistor T2.
  • the gate of the second switching transistor T2 is connected to the first node P1, the source is connected to the third reference signal terminal Vref3, and the drain is connected to the second node P2.
  • the signal of the third reference signal end is provided to the second node.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the second switching transistor T2 is an N-type transistor.
  • the second switching transistor T2 when the effective pulse signal of the input signal terminal Input is a low potential signal, the second switching transistor T2 is a P-type transistor.
  • the above is only a specific structure of the second pull-down control unit in the touch control circuit.
  • the specific structure of the second pull-down control unit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures are not limited here.
  • the third pull-down control unit 53 may include: a third switching transistor T3.
  • the gate of the third switching transistor T3 is connected to the second node P2, the source is connected to the third reference signal terminal Vref3, and the drain is connected to the first node P1.
  • the signal of the third reference signal end is provided to the first node.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the third switching transistor T3 is an N-type transistor. Or, as shown in FIG. 4b, when the input signal terminal Input is effective pulse signal When it is a low potential signal, the third switching transistor T3 is a P-type transistor.
  • the above is only a specific structure of the third pull-down control unit in the touch control circuit.
  • the specific structure of the third pull-down control unit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures are not limited here.
  • the fourth pull-down control unit 54 may include: a fourth switching transistor T4.
  • the gate of the fourth switching transistor T4 is connected to the control signal output terminal OUT, the source is connected to the third reference signal terminal Vref3, and the drain is connected to the second node P2.
  • the fourth switching transistor when the fourth switching transistor is in an on state under the control of the control signal output end, the signal of the third reference signal end is provided to the second node.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the fourth switching transistor T4 is an N-type transistor.
  • the fourth switching transistor T4 when the effective pulse signal of the input signal terminal Input is a low potential signal, the fourth switching transistor T4 is a P-type transistor.
  • the above is only a specific structure of the fourth pull-down control unit in the touch control circuit.
  • the specific structure of the fourth pull-down control unit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures are not limited here.
  • the touch signal output module 6 may include: a high frequency signal output unit 61, a common voltage signal output unit 62, and a pull up unit. 63 and a pull down unit 64.
  • the control terminal of the pull-up unit 63 is a first input end of the touch signal output module 6, the input end is connected to the low-frequency signal terminal TL, the output terminal is connected to the third node P3, and the pull-up unit 63 is used at the control signal output terminal OUT.
  • the potential is the first potential
  • the signal of the low frequency signal terminal TL is supplied to the third node P3.
  • the control terminal of the pull-down unit 64 is connected to the cut-off signal terminal END, the input terminal is connected to the third node P3, and the output terminal is connected to the third reference signal terminal Vref3.
  • the pull-down unit 64 is configured to provide the signal of the third reference signal terminal Vref3 to the third node P3 under the control of the cutoff signal terminal END.
  • the control end of the high-frequency signal output unit 61 is connected to the third node P3.
  • the input end is the second input end of the touch signal output module 6, and the output end is connected to the touch signal output end TX.
  • the high frequency signal output unit 61 is configured to control the output of the touch signal output terminal TX when the potential of the third node P3 is the first potential High frequency signal.
  • the common voltage signal output unit 62 is connected between the third node P3, the third reference signal terminal Vref3, the fourth reference signal terminal Vref4, the common voltage signal terminal Vcom, and the touch signal output terminal TX.
  • the common voltage signal output unit 62 is configured to control the touch signal output terminal TX to output a common voltage signal when the potential of the third node P3 is the second potential.
  • the pull-up unit when the potential of the output end of the control signal is the first potential, the pull-up unit provides the signal of the low-frequency signal end to the third node, and the signal input by the pull-down unit at the cut-off signal end.
  • the first potential is, the signal of the third reference signal end is supplied to the third node; when the potential of the third node is the first potential, the high-frequency signal is outputted by the control signal output terminal; the common voltage signal is output;
  • the output unit controls the touch signal output end to output a common voltage signal when the potential of the third node is the second potential, thereby implementing the touch signal output module to select the output high frequency signal or the common voltage signal under the control of the control signal output end.
  • the pulse width of the low frequency signal input by the low frequency signal terminal is at least twice the pulse width of the high frequency signal input by the high frequency signal terminal.
  • the pulse width of the low-frequency signal input by the low-frequency signal terminal samples and selects the output high-frequency signal of the touch signal output end, and determines the output of the high-frequency signal every time the touch signal output end outputs.
  • the pull-up unit 63 may include: a fifth switching transistor T5.
  • the gate of the fifth switching transistor T5 is connected to the control signal output terminal OUT, the source is connected to the low frequency signal terminal TL, and the drain is connected to the third node P3.
  • the fifth switching transistor T5 when the effective pulse signal of the input signal terminal Input is a high potential signal, the fifth switching transistor T5 is an N type. Transistor. Or, as shown in Figure 4b, when the input signal terminal Input is valid pulse letter When the number is a low potential signal, the fifth switching transistor T5 is a P-type transistor.
  • the above is only a specific structure of the pull-up unit in the touch control circuit.
  • the specific structure of the pull-up unit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. There is no limit here.
  • the pull-down unit 64 may include: a sixth switching transistor T6.
  • the gate of the sixth switching transistor T6 is connected to the off signal terminal END, the source is connected to the third reference signal terminal Vref3, and the drain is connected to the third node P3.
  • the sixth switching transistor T6 when the sixth switching transistor T6 is in an on state under the control of the off signal terminal END, the signal of the third reference signal terminal Vref3 is supplied to the third node P3.
  • the sixth switching transistor T6 when the effective pulse signal of the input signal terminal Input is a high potential signal, the sixth switching transistor T6 is N-type. Transistor.
  • the sixth switching transistor T6 when the effective pulse signal of the input signal terminal Input is a low potential signal, the sixth switching transistor T6 is a P-type transistor.
  • the above is only a specific structure of the pull-down unit in the touch circuit.
  • the specific structure of the pull-down unit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. Not limited.
  • the high frequency signal output unit 61 may include a seventh switching transistor T7 and a first capacitor C1.
  • the gate of the seventh switching transistor T7 is connected to the third node P3, the source is connected to the high frequency signal terminal TH, and the drain is connected to the touch signal output terminal TX.
  • the first capacitor C1 is connected between the gate and the drain of the seventh switching transistor T7.
  • the seventh switching transistor when the seventh switching transistor is in an on state under the control of the third node P3, the signal of the high frequency signal terminal TH is supplied to the touch signal output terminal TX, thereby The touch signal output terminal TX outputs a high frequency signal.
  • the sixth switching transistor T6 when the effective pulse signal of the input signal terminal Input is a high potential signal, the sixth switching transistor T6 is N-type. Transistor.
  • the sixth switching transistor T6 when the effective pulse signal of the input signal terminal Input is a low potential signal, the sixth switching transistor T6 is a P-type transistor.
  • the above is only an example to illustrate the specific structure of the high frequency signal output unit in the touch circuit, and the specific implementation
  • the specific structure of the high-frequency signal output unit is not limited to the above-described structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art, which is not limited herein.
  • the common voltage signal output unit 62 may include an eighth switching transistor T8 and a ninth switching transistor T9.
  • the gate of the eighth switching transistor T8 is connected to the fourth reference signal terminal Vref4, the source is connected to the common voltage signal terminal Vcom, and the drain is connected to the touch signal output terminal TX;
  • the gate of the ninth switching transistor T9 is connected to the third node P3, the source is connected to the third reference signal terminal Vref3, and the drain is connected to the fourth reference signal terminal Vref4.
  • the ninth switching transistor T9 when the potential of the third node is the first potential, the ninth switching transistor T9 is in an on state, and the turned on ninth switching transistor T9 is a gate of the eighth switching transistor T8.
  • the pole and the third reference signal end are turned on by Vref3, so that the eighth switching transistor T8 is turned off, and the size of the ninth switching transistor T9 tube is large, so that the function of dividing the voltage can be increased, and the eighth switch can be pulled down well.
  • the gate voltage of the transistor T8 ensures that the eighth switching transistor T8 is in a completely off state.
  • the ninth switching transistor T9 When the potential of the third node P3 is the second potential, the ninth switching transistor T9 is in an off state, and since the gate of the eighth switching transistor T8 is connected to the fourth reference signal terminal, the eighth switching transistor T8 is in an on state.
  • the eighth switch crystal T8 tube conducts the common voltage signal end and the touch signal output end, so that the touch signal output end outputs a common voltage signal.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the eighth switching transistor T8 and the ninth switching transistor T9 is an N-type transistor.
  • the eighth switching transistor T8 and the ninth switching transistor T9 are P-type transistors.
  • the common voltage signal output unit 62 may further include: a third capacitor C3.
  • the third capacitor C3 is connected between the gate and the drain of the eighth switching transistor T8.
  • the third capacitor C3 mainly functions as a filter and a voltage regulator to ensure the stability of the output end of the touch signal.
  • the common voltage signal output unit 62 may further include: a fourteenth switching transistor T14.
  • the gate and the source of the fourteenth switching transistor T14 are both connected to the fourth reference signal terminal Vref4, and the drain is connected to the gate of the eighth switching transistor T8 and the drain of the ninth switching transistor T9, respectively.
  • the fourteenth switching transistor T14 connects the fourth reference signal terminal Vref4 and the gate of the eighth switching transistor T8 and the ninth switching transistor T9 in a diode connection manner.
  • the drain connection is always in the normally open state.
  • the ninth switching transistor T9 is in the off state, the signal input from the fourth reference signal terminal Vref4 is supplied to the gate of the eighth switching transistor T8, the eighth switching transistor T8 is turned on, and the eighth switching transistor is turned on.
  • the T8 turns on the common voltage signal terminal Vcom and the touch signal output terminal TX, so that the touch signal output terminal TX outputs a common voltage signal.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 5a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the fourteenth switching transistor T14 is an N-type transistor. .
  • the fourteenth switching transistor T14 when the effective pulse signal of the input signal terminal Input is a low potential signal, the fourteenth switching transistor T14 is a P-type transistor.
  • the above is only a specific structure of the common voltage signal output unit in the touch circuit.
  • the specific structure of the common voltage signal output unit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures are not limited here.
  • the input module 1 may include: a tenth switching transistor T10.
  • the gate of the tenth switching transistor T10 is connected to the input signal terminal Input, the source is connected to the first reference signal terminal Vref1, and the drain is connected to the first node P1.
  • the tenth switching transistor T10 when the tenth switching transistor T10 is in an on state under the control of the input signal terminal, the signal of the first reference signal terminal Vref1 is supplied to the first node P1.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the tenth switching transistor T10 is an N-type transistor.
  • the tenth switching transistor T10 when the effective pulse signal of the input signal terminal Input is a low potential signal, the tenth switching transistor T10 is a P-type transistor.
  • the specific structure of the input module is not limited to the above structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. Not limited.
  • the reset module 2 may include: an eleventh switching transistor T11.
  • the gate of the eleventh switching transistor T11 is connected to the reset signal end Reset, the source and the second reference
  • the signal terminal Vref2 is connected, and the drain is connected to the first node P1.
  • the eleventh switching transistor T11 when the eleventh switching transistor T11 is in an on state under the control of the reset signal terminal, the signal of the second reference signal terminal is supplied to the first node.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the eleventh switching transistor T11 is an N-type transistor. .
  • the eleventh switching transistor T11 when the effective pulse signal of the input signal terminal Input is a low potential signal, the eleventh switching transistor T11 is a P-type transistor.
  • the above is only a specific structure of the reset module in the touch circuit.
  • the specific structure of the reset module is not limited to the above structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. Not limited.
  • the pull-up module 3 may include a twelfth switching transistor T12 and a second capacitor C2.
  • the gate of the twelfth switching transistor T12 is connected to the first node P1, the source is connected to the first clock signal terminal CK, and the drain is connected to the control signal output terminal OUT.
  • the second capacitor C2 is connected between the gate and the drain of the twelfth switching transistor T12.
  • the twelfth switching transistor T12 when the twelfth switching transistor T12 is in an on state under the control of the first node P1, the signal of the first clock signal terminal is supplied to the control signal output terminal.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the twelfth switching transistor T12 is an N-type transistor. .
  • the twelfth switching transistor T12 when the effective pulse signal of the input signal terminal Input is a low potential signal, the twelfth switching transistor T12 is a P-type transistor.
  • the above is only a specific structure of the pull-up module in the touch control circuit.
  • the specific structure of the pull-up module is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. There is no limit here.
  • the pull-down module 4 may include: a thirteenth switching transistor T13.
  • the gate of the thirteenth switching transistor T13 is connected to the second node P2, the source is connected to the third reference signal terminal Vref3, and the drain is connected to the control signal output terminal OUT.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a, when the effective pulse signal of the input signal terminal Input is a high potential signal, the thirteenth switching transistor T13 is an N-type transistor. .
  • the thirteenth switching transistor T13 when the effective pulse signal of the input signal terminal Input is a low potential signal, the thirteenth switching transistor T13 is a P-type transistor.
  • the pull-down module 4 may further include: a fourth capacitor C4.
  • the fourth capacitor C4 is connected between the gate and the drain of the thirteenth switching transistor T13.
  • the fourth capacitor C4 mainly functions as a filter and a voltage regulator to ensure the stability of the output of the control signal.
  • the above is only a specific structure of the pull-down module in the touch circuit.
  • the specific structure of the pull-down module is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. Not limited.
  • the switching transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited herein. .
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the source and the drain of these switching transistors are interchangeable according to the type of transistor and the input signal, and no distinction is made here.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4a and FIG. 5a, when the effective pulse signal of the input signal is a high potential signal, all the switching transistors are N-type transistors; as shown in FIG. 4b and FIG. 5b. When the effective pulse signal of the input signal is a low potential signal, all switching transistors are P-type transistors. Therefore, the integrated touch circuit design of the single transistor structure is provided. Compared with the touch circuit formed by the N-type transistor and the P-type transistor in the prior art, the touch control circuit provided by the embodiment of the present disclosure is reliable in development. High in performance, simple in structure, and small in number of switching transistors, saving space for design and facilitating narrow frame of display products.
  • each module can be configured by using N-type thin film transistors, that is, a total of fourteen NMOS transistors and four capacitors are required to form a touch circuit, and thus the display panel is used to drive the display panel.
  • the N-type thin film transistor driving circuit for realizing the display function has better matching, and the touch circuit is constructed by using a plurality of thin film transistors to construct a transmission gate, an inverter, and a tri-state gate circuit.
  • the touch circuit provided by the disclosed embodiment has a small number of N-type thin film transistors. Therefore, the touch control circuit provided by the embodiment of the present disclosure has a simple structure and low power consumption.
  • an embodiment of the present disclosure provides a touch panel including a plurality of the touch circuits provided by the embodiments of the present disclosure.
  • control signal output ends of the other touch circuits are connected to the reset signal ends of the adjacent upper-level touch circuits;
  • control signal output ends of the other touch circuits are connected to the signal input terminals of the adjacent lower touch circuits.
  • FIG. 6a is a schematic diagram showing the operation timing of the touch circuit shown in FIG. 5a
  • FIG. 6b is a schematic diagram showing the operation timing of the touch circuit shown in FIG. 5b.
  • the effective pulse signal of the input signal terminal Input is a high potential signal
  • the first potential is a high potential
  • the second potential is a low potential
  • the first reference signal terminal Vref1 and the fourth reference signal terminal are The signal of Vref4 is high
  • the signals of the second reference signal terminal Vref2 and the third reference signal terminal Vref3 are low
  • all the switching transistors are N-type transistors
  • FIG. 6a the corresponding input and output timing diagram is shown in FIG. 6a. Specifically, two stages of T1 and T2 in the input-output timing diagram shown in FIG. 6a are selected.
  • the turned-on tenth switching transistor T10 supplies the signal of the high potential first reference signal terminal Vref1 to the first node P1, so that the potential of the first node P1 is high, thereby making the twelfth switching transistor T12 and the second switch Transistor T2 is turned on.
  • the turned-on second switching transistor T2 supplies the signal of the low potential third reference signal terminal Vref3 to the second node P2, so that the potential of the second node P2 is low, the third switching transistor T3 and the thirteenth switching transistor T13 cutoff.
  • the turned-on fourth switching transistor T4 connects the low potential third reference signal terminal Vref3 with the second node P2, further ensuring that the potential of the second node P2 is low, and the turned-on fifth switching transistor T5 will be the low frequency signal terminal.
  • the turned-on ninth switching transistor T9 turns on the low potential third reference signal terminal Vref3 and the gate of the eighth switching transistor T8 and The drain of the fourteen switching transistor T14 is connected, so that the eighth switching transistor T8 is turned off, and the turned-on seventh switching transistor T7 connects the high-frequency signal terminal TH to the touch signal output terminal TX, so that the touch signal output terminal TX is The pulse width of the low frequency signal input by the low frequency signal terminal TL outputs a high frequency signal.
  • the above T1 phase is a stage in which the touch signal output terminal TX outputs a high frequency signal.
  • the turned-on third switching transistor T3 supplies the signal of the low potential third reference signal terminal Vref3 to the first node P1, and the turned-on thirteenth switching transistor T13 controls the signal output terminal OUT and the low potential third reference signal.
  • the turned-on sixth switching transistor T6 supplies the signal of the low potential third reference signal terminal Vref3 to the third node P3, and therefore, the potential of the third node P3 is low, and the ninth switching transistor T9 and the seventh switching transistor T7 cutoff.
  • the gate of the eighth switching transistor T8 passes through the fourteenth switching transistor T14 and the fourth reference signal terminal Vref4 of the high potential. Connected, so the eighth switching transistor T8 is turned on. The turned-on eighth switching transistor T8 turns on the common voltage signal terminal VCOM and the touch signal output terminal TX, so that the touch signal output terminal TX outputs a common voltage signal.
  • the above T2 phase is a stage in which the touch signal output terminal TX outputs a common voltage signal.
  • the touch signal output terminal will always output the common voltage signal until the effective pulse signal of the signal input terminal Input is a high potential signal.
  • the above process is a working process in which a touch circuit respectively outputs a high frequency signal and a common voltage signal.
  • a touch circuit respectively outputs a high frequency signal and a common voltage signal.
  • each level of the touch circuit follows the above working process.
  • the high-frequency signal or the common voltage signal is respectively output, as shown in FIG. 7a, finally realizing the function of the touch circuit outputting the high-frequency signal step by step, that is, the process of the touch panel progressive touch scanning is realized.
  • the effective pulse signal of the input signal terminal Input is a low potential signal
  • the first potential is a low potential
  • the second potential is a high potential
  • the signal of the reference signal terminal Vref4 is low
  • the signals of the second reference signal terminal Vref2 and the third reference signal terminal Vref3 are high
  • all the switching transistors are N-type transistors
  • the corresponding input and output timing diagram is as shown in FIG. 6b. Specifically, two stages of T1 and T2 in the input-output timing diagram shown in FIG. 6b are selected.
  • the turned-on tenth switching transistor T10 connects the low potential first reference signal terminal Vref1 with the first node P1, so that the potential of the first node P1 is low, so that the twelfth switching transistor T12 and the second switching transistor T2 are led. through.
  • the turned-on second switching transistor T2 connects the high potential third reference signal terminal Vref3 with the second node P2, so that the potential of the second node P2 is high, and the third switching transistor T3 and the thirteenth switching transistor T13 are turned off. .
  • the turned-on fourth switching transistor T4 connects the high potential third reference signal terminal Vref3 with the second node P2, further ensuring that the potential of the second node P2 is high, and the turned-on fifth switching transistor T5 will be the low frequency signal terminal.
  • the turned-on ninth switching transistor T9 connects the high potential third reference signal terminal Vref3 with the gate of the eighth switching transistor T8 and the drain of the fourteenth switching transistor T14, so that the eighth switching transistor T8 is turned off and turned on.
  • the seventh switching transistor T7 connects the high-frequency signal terminal TH to the touch signal output terminal TX, so that the touch signal output terminal TX outputs a high-frequency signal according to the pulse width of the low-frequency signal input by the low-frequency signal terminal TL.
  • the above T1 phase is a stage in which the touch signal output terminal TX outputs a low frequency signal.
  • the turned-on third switching transistor T3 supplies the signal of the high potential third reference signal terminal Vref3 to the first node P1, and the turned-on thirteenth switching transistor T13 connects the control signal output terminal OUT with the high potential high potential third.
  • the reference signal terminal Vref3 is connected, therefore, the potential of the control signal output terminal OUT is high, so
  • the potential, the ninth switching transistor T9 and the seventh switching transistor T7 are turned off.
  • the gate of the eighth switching transistor T8 passes through the fourteenth switching transistor T14 and the fourth reference signal terminal Vref4 of the low potential. Connected, so the eighth switching transistor T8 is turned on. The turned-on eighth switching transistor T8 connects the common voltage signal terminal VCOM to the touch signal output terminal TX, so that the touch signal output terminal TX outputs a common voltage signal.
  • the above T2 phase is a stage in which the touch signal output terminal TX outputs a common voltage signal.
  • the touch signal output terminal will always output the common voltage signal until the effective pulse signal of the signal input terminal Input is a low potential signal.
  • the above process is a working process in which a touch circuit respectively outputs a high frequency signal and a common voltage signal.
  • a touch circuit respectively outputs a high frequency signal and a common voltage signal.
  • each level of the touch circuit follows the above working process.
  • the high frequency signal or the common voltage signal is respectively output, as shown in FIG. 7b, finally realizing the function of the touch circuit outputting the high frequency signal step by step, that is, the process of the touch panel progressive touch scanning is realized.
  • an embodiment of the present disclosure provides a display device, including the above touch panel provided by an embodiment of the present disclosure.
  • the display device can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the principle of the display device is similar to that of the touch circuit. Therefore, the implementation of the display device can be referred to the implementation of the above touch circuit, and the repeated description is omitted.
  • the touch circuit, the touch panel and the display device provided by the embodiments of the present disclosure realize the function of outputting a touch signal by the touch circuit, and the transmission gate and the reverse phase are required to be used in the prior art.
  • the touch circuit provided by the embodiment of the present disclosure has a simple structure and low power consumption.

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Abstract

提供一种触控电路、触控面板及显示装置。该触控电路包括：输入模块(1)、复位模块(2)、上拉模块(3)、下拉模块(4)、下拉控制模块(5)和触控信号输出模块(6)，其中输入模块用于将第一参考信号端的信号提供给第一节点，复位模块用于将第二参考信号端的信号提供给第一节点；上拉模块用于将第一时钟信号端的信号提供给控制信号输出端；下拉模块用于将第三参考信号端的信号提供给控制信号输出端；下拉控制模块用于保证第一节点和第二节点在同一时刻只有一个节点的电位为第一电位；触控信号输出模块用于在控制信号输出端的控制下，向触控信号输出端输出高频信号或公共电压信号。上述触控电路、触控面板及显示装置结构简单，且功耗较低。

Description

触控电路、触控面板及显示装置 技术领域
本公开涉及一种触控电路、触控面板及显示装置。
背景技术
随着显示技术的飞速发展，触摸屏(Touch Panel)已经逐渐遍及人们的生活中。目前，触摸屏按照组成结构可以分为：外挂式触摸屏(Add on Mode Touch Panel)、覆盖表面式触摸屏(On Cell Touch Panel)、以及内嵌式触摸屏(In Cell Touch Panel)。其中，外挂式触摸屏是将触摸屏与显示屏分开生产，然后贴合到一起成为具有触摸功能的显示屏。外挂式触摸屏存在制作成本较高、光透过率较低、模组较厚等缺点。而内嵌式触摸屏将触摸屏的触控电极内嵌在显示屏内部，可以减薄模组整体的厚度，又可以大大降低触摸屏的制作成本，受到各大面板厂家青睐。在内嵌式触摸屏技术中，互电容式触摸屏则凭借其较高的灵敏度以及多点触控的优点，成为目前内嵌式触摸屏技术发展的主流。
具体地，内嵌式触摸屏为触摸屏中的触控扫描线和触控感应线集成在显示屏中的装置，如触控扫描线和触控感应线集成在液晶显示屏(Liquid Crystal Display，LCD)或有机电致发光显示屏(Organic Light Emitting Device，OLED)中。
目前，通常将用于向触控扫描线输出触控扫描信号的触控驱动电路集成在阵列基板上，以省去显示边框区域的走线，从而可以实现大尺寸显示屏的窄边框设计。
发明内容
本公开实施例提供了一种触控电路、触控面板及显示装置，用以解决现有技术中存在的触控电路结构较复杂，功耗较大的问题。
本公开实施例提供了一种触控电路，包括：输入模块、复位模块、上拉模块、下拉模块、下拉控制模块和触控信号输出模块，其中：
所述输入模块的控制端与输信号入端相连，输入端与第一参考信号端相连，输出端与第一节点相连，所述输入模块用于在所述输入信号端的控制下，将所述第一参考信号端的信号提供给所述第一节点；
所述复位模块的控制端与复位信号端相连，输入端与第二参考信号端相连，输出端与所述第一节点相连；所述复位模块用于在所述复位信号端的控制将所述第二参考信号端的信号提供给所述第一节点；
所述上拉模块的控制端与所述第一节点相连，输入端与第一时钟信号端相连，输出端与控制信号输出端相连；所述上拉模块用于在所述第一节点的电位为第一电位时，将所述第一时钟信号端的信号提供给所述控制信号输出端；
所述下拉模块的控制端与第二节点相连，输入端与第三参考信号端相连，输出端与所述控制信号输出端相连；所述下拉模块用于在所述第二节点的电位为第一电位时，将所述第三参考信号端的信号提供给所述控制信号输出端；
所述下拉控制模块分别与第二时钟信号端、所述第一节点节点和所述第二节点相连；所述下拉控制模块用于在所述第二时钟信号端的控制下，将所述第二时钟信号端的信号提供给所述第二节点，在所述第一节点的电位为第一电位时，控制所述第二节点的电位为第二电位，在所述第二节点的电位为第一电位时，控制所述第一节点的电位为第二电位；
所述触控信号输出模块的第一输入端与所述控制信号输出端相连，第二输入端与高频信号端相连，第三输入端与公共电压信号端相连；所述触控信号输出模块用于在所述控制信号输出端的控制下，向触控信号输出端输出高频信号或公共电压信号；
当所述输入信号端的有效脉冲信号为高电位信号时，所述第一电位为高电位，所述第二电位为低电位；当所述输入信号端的有效脉冲信号为低电位信号时，所述第一电位为低电位，所述第二电位为高电位；且当所述输入信号端输出有效脉冲信号开始，所述第一时钟信号端和所述第二时钟信号端交替输出第一电位信号。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述下拉控制模块，包括：第一下拉控制单元、第二下拉控制单元和第三下拉控制单元；其中，
所述第一下拉控制单元的控制端和输入端均与第二时钟信号端相连，输出端与所述第二节点相连；所述第一下拉控制单元用于在第二时钟信号端的控制下，将所述第二时钟信号端的信号提供给所述第二节点；
第二下拉控制单元的控制端与所述第一节点相连，输入端与所述第三参考信号端相连，输出端与所述第二节点相连；所述第二下拉控制单元用于在所述 第一节点的电位为第一电位时，将所述第三参考信号端的信号提供给所述第二节点；
所述第三下拉控制单元的控制端与所述第二节点相连，输入端与所述第三参考信号端相连，输出端与所述第一节点相连；所述第三下拉控制单元用于在所述第二节点的电位为第一电位时，将所述第三参考信号端的信号提供给所述第一节点。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述下拉控制模块还包括：第四下拉控制单元；其中，
所述第四下拉控制单元的控制端与所述控制信号输出端相连，输入端与所述第三参考信号端相连，输出端与所述第二节点相连；所述第四下拉控制单元用于在所述控制信号输出端的电位为第一电位时，将所述第三参考信号端的信号提供给所述第二节点。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述第一下拉控制单元，包括：第一开关晶体管；其中，
所述第一开关晶体管，其栅极和源极均与所述第二时钟信号端相连，漏极与所述第一节点相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述第二下拉控制单元，包括：第二开关晶体管；其中，
所述第二开关晶体管，其栅极与所述第一节点相连，源极与所述第三参考信号端相连，漏极与所述第二节点相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述第三下拉控制单元，包括：第三开关晶体管；其中，
所述第三开关晶体管，其栅极与所述第二节点相连，源极与所述第三参考信号端相连，漏极与所述第一节点相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述第四下拉控制单元，包括：第四开关晶体管；其中，
所述第四开关晶体管，其栅极与所述控制信号输出端相连，源极与所述第三参考信号端相连，漏极与所述第二节点相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述触控信号输出模块，包括：高频信号输出单元、公共电压信号输出单元、上拉单元以及下拉单元；其中，
所述上拉单元的控制端为所述触控信号输出模块的第一输入端，输入端与低频信号端相连，输出端与第三节点相连；所述上拉单元用于在所述控制信号输出端的电位为第一电位时，将所述低频信号端的信号提供给所述第三节点；
所述下拉单元的控制端与截止信号端相连，输入端与所述第三节点相连，输出端与所述第三参考信号端相连，所述下拉单元用于在所述截止信号端的控制下，将所述第三参考信号端的信号提供给所述第三节点；
所述高频信号输出单元的控制端与所述第三节点相连，输入端为所述触控信号输出模块的第二输入端，输出端与所述触控信号输出端相连；所述高频信号输出单元用于在所述第三节点的电位为第一电位时，控制所述触控信号输出端输出高频信号；
所述公共电压信号输出单元连接于所述第三节点、所述第三参考信号端、第四参考信号端、所述公共电压信号端、以及所述触控信号输出端之间，所述公共电压信号输出单元用于在所述第三节点的电位为第二电位时，控制所述触控信号输出端输出公共电压信号。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述上拉单元，包括：第五开关晶体管；其中，
所述第五开关晶体管，其栅极与所述控制信号输出端相连，源极与所述低频信号端相连，漏极与所述第三节点相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述下拉单元，包括：第六开关晶体管；其中，
所述第六开关晶体管，其栅极与所述截止信号端相连，源极与所述第三参考信号端相连，漏极与所述第三节点相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述高频信号输出单元，包括：第七开关晶体管和第一电容；其中，
所述第七开关晶体管，其栅极与所述第三节点相连，源极与所述高频信号端相连，漏极与所述触控信号输出端相连；
所述第一电容连接与所述第七开关晶体管的栅极与漏极之间。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述公共电压信号输出单元，包括：第八开关晶体管和第九开关晶体管；其中，
所述第八开关晶体管，其栅极与所述第四参考信号端相连，源极与所述公共电压信号端相连，漏极与所述触控信号输出端相连；
所述第九开关晶体管，其栅极与所述第三节点相连，源极与所述第三参考信号端相连，漏极与所述第四参考信号端相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述输入模块，包括：第十开关晶体管；其中，
所述第十开关晶体管，其栅极与所述输入信号端相连，源极与所述第一参考信号端相连，漏极与所述第一节点相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述复位模块，包括：第十一开关晶体管；其中，
所述第十一开关晶体管，其栅极与所述复位信号端相连，源极与所述第二参考信号端相连，漏极与所述所述第一节点相连。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述上拉模块，包括：第十二开关晶体管和第二电容；其中，
所述第十二开关晶体管，其栅极与所述第一节点相连，源极与所述第一时钟信号端相连，漏极与所述控制信号输出端相连；
所述第二电容连接于所述第十二开关晶体管的栅极与漏极之间。
在一种可能的实施方式中，本公开实施例提供的上述触控电路中，所述下拉模块，包括：第十三开关晶体管；其中，
所述第十三开关晶体管，其栅极与所述第二节点相连，源极与所述第三参考信号端相连，漏极与所述控制信号输出端相连。
相应地，本公开实施例还提供了一种触控面板，包括级联的多个本公开实施例提供的上述触控电路；其中，
除首级触控电路之外，其它各级触控电路的控制信号输出端均与相邻的上一级触控电路的复位信号端相连；
除末级触控电路之外，其它各级触控电路的控制信号输出端均与相邻的下一级触控电路的信号输入端相连。
相应地，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述触控面板。
本公开实施例提供的上述触控电路、触控面板及显示装置，包括：输入模块、复位模块、上拉模块、下拉模块、下拉控制模块和触控信号输出模块；其中，输入模块用于在输入信号端的控制下，将第一参考信号端的信号提供给第一节点；复位模块用于在复位信号端的控制将第二参考信号端的信号提供给第 一节点；上拉模块用于在第一节点的电位为第一电位时，将第一时钟信号端的信号提供给控制信号输出端；下拉模块用于在第二节点的电位为第一电位时，将第三参考信号端的信号提供给控制信号输出端；下拉控制模块用于在第二时钟信号端的控制下，将第二时钟信号端的信号提供给第二节点，在第一节点的电位为第一电位时，控制第二节点的电位为第二电位，在第二节点的电位为第一电位时，控制第一节点的电位为第二电位；触控信号输出模块用于在控制信号输出端的控制下，向触控信号输出端输出高频信号或公共电压信号。这样实现了触控电路输出触控信号的功能，相对于现有技术中需要采用较多的薄膜晶体管搭建传输门、反相器以及三态门电路进而构成的触控电路，本公开实施例提供的触控电路结构简单，功耗较低。
附图说明
图1为一种常用的触控电路的结构示意图；
图2为本公开的一个实施例中提供的触控电路的结构示意图；
图3a为本公开的另一实施例中提供的触控电路的结构示意图；
图3b为本公开的再一个实施例中提供的触控电路的结构示意图；
图4a为本公开实施例提供的触控电路的一种具体电路结构示意图；
图4b为本公开实施例提供的触控电路的另一种具体电路结构示意图；
图5a为本公开实施例提供的触控电路的又一种具体电路结构示意图；
图5b为本公开实施例提供的触控电路的再一种具体电路结构示意图；
图6a为图5a所示的触控电路的工作时序示意图；
图6b为图5b所示的触控电路的工作时序示意图；
图7a和图7b分别为本公开实施例提供的级联的触控电路依次输出触控信号的工作时序示意图。
具体实施方式
下面结合附图，对本公开实施例提供的触控电路、触控面板及显示装置的实施方式进行详细地说明。
图1示出一种常用的触控电路的结构示意图。如图1所示，触控扫描线Txn(n＝1，2，3…)上的触控扫描信号是由外部驱动器(IC)通过位于边框区域的走线传输的。但是随着显示屏的尺寸增大，触控扫描线Txn的数量增 多，则用于向触控扫描线Txn传输触控扫描信号的走线也相应增多，从而导致走线所占用的空间增大，从而限制了内嵌式技术在大尺寸和窄边框显示屏上的应用。
图2示出本公开一个实施例中提供的一种触控电路的结构示意图。如图2所示，该触控电路包括：输入模块1、复位模块2、上拉模块3、下拉模块4、下拉控制模块5和触控信号输出模块6。
在图2所示触控电路中，输入模块1的控制端与输信号入端Input相连，输入端与第一参考信号端Vref1相连，输出端与第一节点P1相连。输入模块1用于在输入信号端Input的控制下，将第一参考信号端Vref1的信号提供给第一节点P1。
复位模块2的控制端与复位信号端Reset相连，输入端与第二参考信号端Vref2相连，输出端与第一节点P1相连。复位模块2用于在复位信号端Reset的控制下，将第二参考信号端Vref2的信号提供给第一节点P1。
上拉模块3的控制端与第一节点P1相连，输入端与第一时钟信号端CK相连，输出端与控制信号输出端OUT相连。上拉模块3用于在第一节点P1的电位为第一电位时，将第一时钟信号端CK的信号提供给控制信号输出端OUT。
下拉模块4的控制端与第二节点P2相连，输入端与第三参考信号端Vref3相连，输出端与控制信号输出端OUT相连。下拉模块4用于在第二节点P2的电位为第一电位时，将第三参考信号端Vref3的信号提供给控制信号输出端OUT。
下拉控制模块5的各端分别与第二时钟信号端CKB、第一节点节点P1和第二节点P2相连。下拉控制模块5用于在第二时钟信号端CKB的控制下，将第二时钟信号端CKB的信号提供给第二节点P2，在第一节点P1的电位为第一电位时，控制第二节点P2的电位为第二电位，在第二节点P2的电位为第一电位时，控制第一节点P1的电位为第二电位。
触控信号输出模块6的第一输入端与控制信号输出端OUT相连，第二输入端与高频信号端TH相连，第三输入端与公共电压信号端Vcom相连。触控信号输出模块6用于在控制信号输出端OUT的控制下，向触控信号输出端TX输出高频信号或公共电压信号；
当输入信号端Input的有效脉冲信号为高电位信号时，第一电位为高电位， 第二电位为低电位；当输入信号端的有效脉冲信号为低电位信号时，第一电位为低电位，第二电位为高电位；且当输入信号端Input开始输出有效脉冲信号时，第一时钟信号端CK和第二时钟信号端CKB交替输出第一电位信号。
本公开实施例提供的上述触控电路包括：输入模块、复位模块、上拉模块、下拉模块、下拉控制模块和触控信号输出模块；其中，输入模块用于在输入信号端的控制下，将第一参考信号端的信号提供给第一节点；复位模块用于在复位信号端的控制将第二参考信号端的信号提供给第一节点；上拉模块用于在第一节点的电位为第一电位时，将第一时钟信号端的信号提供给控制信号输出端；下拉模块用于在第二节点的电位为第一电位时，将第三参考信号端的信号提供给控制信号输出端；下拉控制模块用于在第二时钟信号端的控制下，将第二时钟信号端的信号提供给第二节点，在第一节点的电位为第一电位时，控制第二节点的电位为第二电位，在第二节点的电位为第一电位时，控制第一节点的电位为第二电位；触控信号输出模块用于在控制信号输出端的控制下，向触控信号输出端输出高频信号或公共电压信号。这样实现了触控电路输出触控信号的功能。相对于现有技术中需要采用较多的薄膜晶体管搭建传输门、反相器以及三态门电路进而构成的触控电路，本公开实施例提供的触控电路结构简单，功耗较低。
在具体实施时，在本公开实施例提供的上述触控电路中，当输入信号端Input的有效脉冲信号为高电位信号时，第一参考信号端的信号为高电位，第二参考信号端和第三参考信号端的信号均为低电位；当输入信号端Input的有效脉冲信号为低电位信号时，第一参考信号端的信号为低电位，第二参考信号端和第三参考信号端的信号均为高电位。
下面结合实施例，对本公开进行更详细的说明。需要说明的是，本公开的这些实施例是为了更好的解释本发明，但不限制本发明的保护范围。
图3a示出了本公开的另一实施例中提供的触控电路的结构示意图。在该触控电路中，如图3a所示，下拉控制模块5可以包括：第一下拉控制单元51、第二下拉控制单元52和第三下拉控制单元53。
在图3a中，第一下拉控制单元51的控制端和输入端均与第二时钟信号端CKB相连，输出端与第二节点P2相连。第一下拉控制单元51用于在第二时钟信号端CKB的控制下，将第二时钟信号端CKB的信号提供给第二节点P2。
第二下拉控制单元52的控制端与第一节点P1相连，输入端与第三参考信 号端Vref3相连，输出端与第二节点P2相连。第二下拉控制单元52用于在第一节点P1的电位为第一电位时，将第三参考信号端Vref3的信号提供给第二节点P2。
第三下拉控制单元53的控制端与第二节点P2相连，输入端与第三参考信号端Vref3相连，输出端与第一节点P1相连。第三下拉控制单元53用于在第二节点P2的电位为第一电位时，将第三参考信号端Vref3的信号提供给第一节点P1。
在具体实施时，本公开实施例提供的上述触控电路中，在第一节点的电位为第一电位时，第二下拉控制单元将第三参考信号端的信号提供给第二节点，使第二节点的电位为第二电位；而第一下拉控制单元则在第二时钟信号端的信号为第一电位时，将第二时钟信号端的信号提供给第二节点，使第二节点的电位为第一电位；在第二节点的电位为第一电位时，第三下拉控制单元将第三参考信号端的信号提供给第一节点，使第一节点的电位为第二电位；从而实现第一节点和第二节点在同一时刻只有一个节点的电位为第一电位，进而保证控制信号输出端的正常稳定输出。
图3b示出本公开的再一个实施例中提供的触控电路的结构示意图。如图3b所示，进一步地，在发明实施例提供的上述触控电路中，下拉控制模块5还可以包括：第四下拉控制单元54。
在图3b中，第四下拉控制单元54的控制端与控制信号输出端OUT相连，输入端与第三参考信号端Vref3相连，输出端与第二节点P2相连。第四下拉控制单元54用于在控制信号输出端OUT的电位为第一电位时，将第三参考信号端Vref3的信号提供给第二节点P2，从而进一步保证了控制信号输出端的信号的稳定性。
图4a和图4b分别示出了本公开实施例提供的触控电路的一种具体电路结构的示意图。示例性地，如图4a和图4b所示，在发明实施例提供的上述触控电路中，第一下拉控制单元51可以包括：第一开关晶体管T1。
第一开关晶体管T1的栅极和源极均与第二时钟信号端CKB相连，漏极与第一节点P1相连。
本公开实施例提供的上述触控电路中，当第一开关晶体管在第二时钟信号端的控制下处于导通状态时，将第二时钟信号端的信号提供给第一节点。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a 所示，当输入信号端Input的有效脉冲信号为高电位信号时，第一开关晶体管T1为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第一开关晶体管T1为P型晶体管。
具体地，N型晶体管在其栅极电位为低电位时处于导通状态，在其栅极电位为高电位时处于截止状态；P型晶体管在其栅极电位为低电位时处于导通状态，在其栅极电位为高电位时处于截止状态。
以上仅是举例说明触控电路中第一下拉控制单元的具体结构，在具体实施时，第一下拉控制单元的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，第二下拉控制单元52可以包括：第二开关晶体管T2。
第二开关晶体管T2的栅极与第一节点P1相连，源极与第三参考信号端Vref3相连，漏极与第二节点P2相连。
具体地，本公开实施例提供的上述触控电路中，当第二开关晶体管在第一节点的控制下处于导通状态时，将第三参考信号端的信号提供给第二节点。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第二开关晶体管T2为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第二开关晶体管T2为P型晶体管。
以上仅是举例说明触控电路中第二下拉控制单元的具体结构，在具体实施时，第二下拉控制单元的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，第三下拉控制单元53可以包括：第三开关晶体管T3。
第三开关晶体管T3的栅极与第二节点P2相连，源极与第三参考信号端Vref3相连，漏极与第一节点P1相连。
具体地，本公开实施例提供的上述触控电路中，当第三开关晶体管在第二节点的控制下处于导通状态时，将第三参考信号端的信号提供给第一节点。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第三开关晶体管T3为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号 为低电位信号时，第三开关晶体管T3为P型晶体管。
以上仅是举例说明触控电路中第三下拉控制单元的具体结构，在具体实施时，第三下拉控制单元的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，第四下拉控制单元54可以包括：第四开关晶体管T4。
第四开关晶体管T4的栅极与控制信号输出端OUT相连，源极与第三参考信号端Vref3相连，漏极与第二节点P2相连。
具体地，本公开实施例提供的上述触控电路中，当第四开关晶体管在控制信号输出端的控制下处于导通状态时，将第三参考信号端的信号提供给第二节点。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第四开关晶体管T4为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第四开关晶体管T4为P型晶体管。
以上仅是举例说明触控电路中第四下拉控制单元的具体结构，在具体实施时，第四下拉控制单元的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，在本公开实施例提供的上述触控电路中，如图3a所示，触控信号输出模块6可以包括：高频信号输出单元61、公共电压信号输出单元62、上拉单元63以及下拉单元64。
上拉单元63的控制端为触控信号输出模块6的第一输入端，输入端与低频信号端TL相连，输出端与第三节点P3相连；上拉单元63用于在控制信号输出端OUT的电位为第一电位时，将低频信号端TL的信号提供给第三节点P3。
下拉单元64的控制端与截止信号端END相连，输入端与第三节点P3相连，输出端与第三参考信号端Vref3相连。下拉单元64用于在截止信号端END的控制下，将第三参考信号端Vref3的信号提供给第三节点P3。
高频信号输出单元61的控制端与第三节点P3相连，输入端为触控信号输出模块6的第二输入端，输出端与触控信号输出端TX相连。高频信号输出单元61用于在第三节点P3的电位为第一电位时，控制触控信号输出端TX输出 高频信号。
公共电压信号输出单元62连接于第三节点P3、第三参考信号端Vref3、第四参考信号端Vref4、公共电压信号端Vcom、以及触控信号输出端TX之间。公共电压信号输出单元62用于在第三节点P3的电位为第二电位时，控制触控信号输出端TX输出公共电压信号。
进一步地，在本公开实施例提供的上述触控电路中，当第三参考信号端的信号为高电位时、第四参考信号端的信号为低电位；当第三参考信号端的信号为低电位时、第四参考信号端的信号为高电位。
具体地，本公开实施例提供的上述触控电路中，上拉单元在控制信号输出端的电位为第一电位时，将低频信号端的信号提供给第三节点，下拉单元在截止信号端输入的信号为第一电位时，将第三参考信号端的信号提供给第三节点；高频信号输出单元在第三节点的电位为第一电位时，控制触控信号输出端输出高频信号；公共电压信号输出单元在第三节点的电位为第二电位时，控制触控信号输出端输出公共电压信号，由此实现触控信号输出模块在控制信号输出端的控制下，选择输出高频信号或公共电压信号的功能。
需要说明的是，在本公开实施例提供的上述触控电路中，低频信号端输入的低频信号的脉冲宽度至少为高频信号端输入的高频信号的脉冲宽度的两倍。在触控信号输出端输出高频信号时，低频信号端输入的低频信号的脉冲宽度对触控信号输出端输出高频信号进行采样选择，决定了触控信号输出端每一次输出高频信号时，输出地高频信号有几个。例如，低频信号的脉冲宽度为高频信号的脉冲宽度的两倍，则触控信号输出端TX每次输出高频信号时，输出两个高频信号。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，上拉单元63可以包括：第五开关晶体管T5。
第五开关晶体管T5的栅极与控制信号输出端OUT相连，源极与低频信号端TL相连，漏极与第三节点P3相连。
在本公开实施例提供的上述触控电路中，当第五开关晶体管T5在控制信号输出端的控制下处于导通状态时，将低频信号端的信号提供给第三节点P3。
进一步地，在具体实施时，在本公开实施例提供的上述触控电路中，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第五开关晶体管T5为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信 号为低电位信号时，第五开关晶体管T5为P型晶体管。
以上仅是举例说明触控电路中上拉单元的具体结构，在具体实施时，上拉单元的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，下拉单元64可以包括：第六开关晶体管T6。
第六开关晶体管T6的栅极与截止信号端END相连，源极与第三参考信号端Vref3相连，漏极与第三节点P3相连。
在本公开实施例提供的上述触控电路中，当第六开关晶体管T6在截止信号端END的控制下处于导通状态时，将第三参考信号端Vref3的信号提供给第三节点P3。
进一步地，在具体实施时，在本公开实施例提供的上述触控电路中，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第六开关晶体管T6为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第六开关晶体管T6为P型晶体管。
以上仅是举例说明触控电路中下拉单元的具体结构，在具体实施时，下拉单元的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，高频信号输出单元61可以包括：第七开关晶体管T7和第一电容C1。
第七开关晶体管T7的栅极与第三节点P3相连，源极与高频信号端TH相连，漏极与触控信号输出端TX相连。
第一电容C1连接在第七开关晶体管T7的栅极与漏极之间。
在本公开实施例提供的上述触控电路中，当第七开关晶体管在第三节点P3的控制下处于导通状态时，将高频信号端TH的信号提供给触控信号输出端TX，从而使触控信号输出端TX输出高频信号。
进一步地，在具体实施时，在本公开实施例提供的上述触控电路中，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第六开关晶体管T6为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第六开关晶体管T6为P型晶体管。
以上仅是举例说明触控电路中高频信号输出单元的具体结构，在具体实施 时，高频信号输出单元的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，公共电压信号输出单元62可以包括：第八开关晶体管T8和第九开关晶体管T9。
第八开关晶体管T8的栅极与第四参考信号端Vref4相连，源极与公共电压信号端Vcom相连，漏极与触控信号输出端TX相连；
第九开关晶体管T9的栅极与第三节点P3相连，源极与第三参考信号端Vref3相连，漏极与第四参考信号端Vref4相连。
在本公开实施例提供的上述触控电路中，第三节点的电位为第一电位时，第九开关晶体管T9处于导通状态，导通的第九开关晶体管T9将第八开关晶体管T8的栅极与第三参考信号端导通Vref3，使第八开关晶体管T8截止，且第九开关晶体T9管的尺寸较大，这样可以增大其分压的作用，可以很好地拉低第八开关晶体管T8的栅极电压，保证第八开关晶体管T8处于完全截止状态。第三节点P3的电位为第二电位时，第九开关晶体管T9处于截止状态，由于第八开关晶体管T8的栅极与第四参考信号端相连，因此第八开关晶体管T8处于导通状态，导通的第八开关晶体T8管将公共电压信号端与触控信号输出端导通，从而使触控信号输出端输出公共电压信号。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第八开关晶体管T8和第九开关晶体管T9为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第八开关晶体管T8和第九开关晶体管T9为P型晶体管。
进一步地，在本公开实施例提供的上述触控电路中，如图5a和图5b所示，公共电压信号输出单元62还可以包括：第三电容C3。第三电容C3连接于第八开关晶体管T8的栅极与漏极之间。这里第三电容C3主要起滤波和稳压的作用，以保证触控信号输出端的稳定性。
进一步地，在本公开实施例提供的上述触控电路中，如图5a和图5b所示，公共电压信号输出单元62还可以包括：第十四开关晶体管T14。
第十四开关晶体管T14的栅极与源极均与第四参考信号端Vref4相连，漏极分别与第八开关晶体管T8的栅极和第九开关晶体管T9的漏极相连。
具体地，在本公开实施例提供的上述触控电路中，第十四开关晶体管T14以二极管的的连接方式将第四参考信号端Vref4与第八开关晶体管T8的栅极和第九开关晶体管T9的漏极连接，一直处于常开状态。在第九开关晶体管T9处于截止状态时，将第四参考信号端Vref4输入的信号提供给第八开关晶体管T8的栅极，使第八开关晶体管T8处于导通状态，导通的第八开关晶体管T8将公共电压信号端Vcom与触控信号输出端TX导通，从而使触控信号输出端TX输出公共电压信号。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图5a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第十四开关晶体管T14为N型晶体管。或者，如图5b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第十四开关晶体管T14为P型晶体管。
以上仅是举例说明触控电路中公共电压信号输出单元的具体结构，在具体实施时，公共电压信号输出单元的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，输入模块1可以包括：第十开关晶体管T10。
第十开关晶体管T10的栅极与输入信号端Input相连，源极与第一参考信号端Vref1相连，漏极与第一节点P1相连。
在本公开实施例提供的上述触控电路中，当第十开关晶体管T10在输入信号端的控制下处于导通状态时，将第一参考信号端Vref1的信号提供给第一节点P1。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第十开关晶体管T10为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第十开关晶体管T10为P型晶体管。
以上仅是举例说明触控电路中输入模块的具体结构，在具体实施时，输入模块的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，复位模块2可以包括：第十一开关晶体管T11。
第十一开关晶体管T11的栅极与复位信号端Reset相连，源极与第二参考 信号端Vref2相连，漏极与第一节点P1相连。
在本公开实施例提供的上述触控电路中，当第十一开关晶体管T11在复位信号端的控制下处于导通状态时，将第二参考信号端的信号提供给第一节点。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第十一开关晶体管T11为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第十一开关晶体管T11为P型晶体管。
以上仅是举例说明触控电路中复位模块的具体结构，在具体实施时，复位模块的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，上拉模块3可以包括：第十二开关晶体管T12和第二电容C2。
第十二开关晶体管T12的栅极与第一节点P1相连，源极与第一时钟信号端CK相连，漏极与控制信号输出端OUT相连。
第二电容C2连接于第十二开关晶体管T12的栅极与漏极之间。
在本公开实施例提供的上述触控电路中，当第十二开关晶体管T12在第一节点P1的控制下处于导通状态时，将第一时钟信号端的信号提供给控制信号输出端。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第十二开关晶体管T12为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第十二开关晶体管T12为P型晶体管。
以上仅是举例说明触控电路中上拉模块的具体结构，在具体实施时，上拉模块的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
示例性地，在发明实施例提供的上述触控电路中，如图4a和图4b所示，下拉模块4可以包括：第十三开关晶体管T13。
第十三开关晶体管T13的栅极与第二节点P2相连，源极与第三参考信号端Vref3相连，漏极与控制信号输出端OUT相连。
在本公开实施例提供的上述触控电路中，当第十三开关晶体管T13在第二节点P2的控制下处于导通状态时，将第三参考信号端Vref3的信号提供给 控制信号输出端。
进一步地，在具体实施时，本公开实施例提供的上述触控电路，如图4a所示，当输入信号端Input的有效脉冲信号为高电位信号时，第十三开关晶体管T13为N型晶体管。或者，如图4b所示，当输入信号端Input的有效脉冲信号为低电位信号时，第十三开关晶体管T13为P型晶体管。
进一步地，如图5a和图5b所示，在本公开实施例提供的上述触控电路中，下拉模块4还可以包括：第四电容C4。第四电容C4连接于第十三开关晶体管T13的栅极与漏极之间。这里第四电容C4主要起滤波和稳压的作用，以保证控制信号输出端的稳定性。
以上仅是举例说明触控电路中下拉模块的具体结构，在具体实施时，下拉模块的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
需要说明的是本公开上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。在具体实施中，这些开关晶体管的源极和漏极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做区分。
在本公开实施例提供的上述触控电路，如图4a和图5a所示，当输入信号的有效脉冲信号为高电位信号，所有开关晶体管均为N型晶体管；如图4b和图5b所示，当输入信号的有效脉冲信号为低电位信号，所有开关晶体管均为P型晶体管。从而提供了一种单一晶体管结构的集成触控电路设计，与现有技术中的由N型晶体管和P型晶体管构成的触控电路相比，本公开实施例提供的上述触控电路，开发可靠性高，结构简单，且开关晶体管的数量较少，为设计节省空间，更有利于显示产品的窄边框化。
本公开实施例提供的触控电路中，由于各模块可以全部采用N型薄膜晶体管构成，即总共需要十四个NMOS晶体管和四个电容构成触控电路，因此与显示面板中用于驱动显示面板实现显示功能的N型薄膜晶体管驱动电路有更好的匹配性，相对于现有技术中需要采用较多的薄膜晶体管搭建传输门、反相器以及三态门电路进而构成的触控电路，本公开实施例提供的触控电路采用的N型薄膜晶体管数量较少，因此本公开实施例提供的触控电路结构简单，功耗较低。
基于同一发明构思，本公开实施例提供了一种触控面板，包括级联的多个本公开实施例提供的上述触控电路。
在该触控面板中，除首级触控电路之外，其它各级触控电路的控制信号输出端均与相邻的上一级触控电路的复位信号端相连；
除末级触控电路之外，其它各级触控电路的控制信号输出端均与相邻的下一级触控电路的信号输入端相连。
图6a示出了图5a所示的触控电路的工作时序示意图，图6b示出了图5b所示的触控电路的工作时序示意图。
下面分别以图4a至图5b所示的触控电路为例，结合图6a、6b和图7对其工作过程进行详细的描述。下述描述中以1表示高电位信号，0表示低电位信号。
在图5a所示的触控电路中，输入信号端Input的有效脉冲信号为高电位信号，第一电位为高电位，第二电位为低电位，第一参考信号端Vref1和第四参考信号端Vref4的信号为高电位，第二参考信号端Vref2和第三参考信号端Vref3的信号为低电位，所有开关晶体管均为N型晶体管，对应的输入输出时序图如图6a所示。具体地，选取如图6a所示的输入输出时序图中的T1、和T2两个阶段。
在T1阶段，Input＝1，TL＝1，CK＝1，CKB＝0，Reset＝0，END＝0。由于Input＝1，因此第十开关晶体管T10导通。导通的第十开关晶体管T10将高电位的第一参考信号端Vref1的信号提供给第一节点P1，因此第一节点P1的电位为高电位，从而使第十二开关晶体管T12和第二开关晶体管T2导通。导通的第二开关晶体管T2将低电位的第三参考信号端Vref3的信号提供给第二节点P2，因此第二节点P2的电位为低电位，第三开关晶体管T3和第十三开关晶体管T13截止。导通的第十二开关晶体管T12将第一时钟信号端CK与控制信号输出端OUT连接，由于CK＝1，因此控制信号输出端OUT的电位为高电位，使第五开关晶体管T5和第四开关晶体管T4处于导通状态。导通的第四开关晶体管T4将低电位的第三参考信号端Vref3与第二节点P2连接，进一步保证第二节点P2的电位为低电位，而导通的第五开关晶体管T5将低频信号端TL与第三节点P3连接。由于TL＝1，因此第三节点P3的电位为高电位，使第九开关晶体管T9和第七开关晶体管T7处于导通状态。导通的第九开关晶体管T9将低电位的第三参考信号端Vref3与第八开关晶体管T8的栅极和第 十四开关晶体管T14的漏极连接，因此第八开关晶体管T8截止，而导通的第七开关晶体管T7将高频信号端TH与触控信号输出端TX连接，使触控信号输出端TX根据低频信号端TL输入的低频信号的脉冲宽度输出高频信号。
即，上述T1阶段为触控信号输出端TX输出高频信号的阶段。
在T2阶段，Input＝0，TL＝1，CK＝0，CKB＝1，Reset＝1，END＝1。由于Reset＝1，因此第十一开关晶体管T11导通。导通的第十一开关晶体管T1将低电位的第二参考信号端Vref2与第一节点P1连接，因此第一节点P1的电位为低电位。由于CKB＝1，因此第一开关晶体管T1导通。导通的第一开关晶体管T1将第二时钟信号端CKB与第二节点P2连接，因此第二节点P2的电位变为高电位，使第十三开关晶体管T13和第三开关晶体管T3导通。导通的第三开关晶体管T3将低电位的第三参考信号端Vref3的信号提供给第一节点P1，导通的第十三开关晶体管T13将控制信号输出端OUT与低电位的第三参考信号端Vref3连接，因此，控制信号输出端OUT的电位为低电位，使第五开关晶体管T5截止。由于END＝1，因此第六开关晶体管T6导通。导通的第六开关晶体管T6将低电位的第三参考信号端Vref3的信号提供给第三节点P3，因此，第三节点P3的电位为低电位，第九开关晶体管T9和第七开关晶体管T7截止。由于第十四开关晶体管T14处于常开状态，且此时第九开关晶体管T9处于截止状态，因此第八开关晶体管T8的栅极通过第十四开关晶体管T14与高电位的第四参考信号端Vref4连接，因此第八开关晶体管T8导通。导通的第八开关晶体管T8将公共电压信号端VCOM与触控信号输出端TX导通，使触控信号输出端TX输出公共电压信号。
即，上述T2阶段为触控信号输出端TX输出公共电压信号的阶段。
在后续时间段，触控信号输出端将一直输出公共电压信号，直到信号输入端Input的有效脉冲信号为高电位信号为止。
上述过程为一个触控电路分别输出高频信号和公共电压信号的工作过程，在触控面板整个级联的触控电路中，在各个信号控制端的控制下，每级触控电路按照上述工作过程分别输出高频信号或公共电压信号，如图7a所示，最终实现了触控电路逐级输出高频信号的功能，即实现了触控面板逐行触控扫描的过程。
在图5b所示的触控电路中，输入信号端Input的有效脉冲信号为低电位信号，第一电位为低电位，第二电位为高电位，第一参考信号端Vref1和第四 参考信号端Vref4的信号为低电位，第二参考信号端Vref2和第三参考信号端Vref3的信号为高电位，所有开关晶体管均为N型晶体管，对应的输入输出时序图如图6b所示。具体地，选取如图6b所示的输入输出时序图中的T1、和T2两个阶段。
在T1阶段，Input＝0，TL＝0，CK＝0，CKB＝1，Reset＝1，END＝1。由于Input＝0，因此第十开关晶体管T10导通。导通的第十开关晶体管T10将低电位的第一参考信号端Vref1与第一节点P1连接，因此第一节点P1的电位为低电位，使得第十二开关晶体管T12和第二开关晶体管T2导通。导通的第二开关晶体管T2将高电位的第三参考信号端Vref3与第二节点P2连接，因此第二节点P2的电位为高电位，使第三开关晶体管T3和第十三开关晶体管T13截止。导通的第十二开关晶体管T12将第一时钟信号端CK与控制信号输出端OUT连接，由于CK＝0，因此控制信号输出端OUT的电位为低电位，由此第五开关晶体管T5和第四开关晶体管T4处于导通状态。导通的第四开关晶体管T4将高电位的第三参考信号端Vref3与第二节点P2连接，进一步保证第二节点P2的电位为高电位，而导通的第五开关晶体管T5将低频信号端TL与第三节点P3连接。由于TL＝0，因此第三节点P3的电位为低电位，由此第九开关晶体管T9和第七开关晶体管T7处于导通状态。导通的第九开关晶体管T9将高电位的第三参考信号端Vref3与第八开关晶体管T8的栅极和第十四开关晶体管T14的漏极连通，因此第八开关晶体管T8截止，而导通的第七开关晶体管T7将高频信号端TH与触控信号输出端TX连接，使触控信号输出端TX根据低频信号端TL输入的低频信号的脉冲宽度输出高频信号。
即，上述T1阶段为触控信号输出端TX输出低频信号的阶段。
在T2阶段，Input＝1，TL＝0，CK＝1，CKB＝0，Reset＝0，END＝0。由于Reset＝1，因此第十一开关晶体管T11导通。导通的第十一开关晶体管T1将高电位的第二参考信号端Vref2与第一节点P1连接，因此第一节点P1的电位为高电位。由于CKB＝1，因此第一开关晶体管T1导通。导通的第一开关晶体管T1将第二时钟信号端CKB与第二节点P2连接，因此第二节点P2的电位变为低电位，因此第十三开关晶体管T13和第三开关晶体管T3导通。导通的第三开关晶体管T3将高电位的第三参考信号端Vref3的信号提供给第一节点P1，导通的第十三开关晶体管T13将控制信号输出端OUT与高电位高电位的第三参考信号端Vref3连接，因此，控制信号输出端OUT的电位为高电位，因此 第五开关晶体管T5截止。由于END＝0，因此第六开关晶体管T6导通，导通的第六开关晶体管T6将高电位的第三参考信号端Vref3的信号提供给第三节点P3，因此第三节点P3的电位为高电位，第九开关晶体管T9和第七开关晶体管T7截止。由于第十四开关晶体管T14处于常开状态，且此时第九开关晶体管T9处于截止状态，因此第八开关晶体管T8的栅极通过第十四开关晶体管T14与低电位的第四参考信号端Vref4连接，因此第八开关晶体管T8导通。导通的第八开关晶体管T8将公共电压信号端VCOM与触控信号输出端TX连接，使触控信号输出端TX输出公共电压信号。
即，上述T2阶段为触控信号输出端TX输出公共电压信号的阶段。
在后续时间段，触控信号输出端将一直输出公共电压信号，直到信号输入端Input的有效脉冲信号为低电位信号为止。
上述过程为一个触控电路分别输出高频信号和公共电压信号的工作过程，在触控面板整个级联的触控电路中，在各个信号控制端的控制下，每级触控电路按照上述工作过程分别输出高频信号或公共电压信号，如图7b所示，最终实现了触控电路逐级输出高频信号的功能，即实现了触控面板逐行触控扫描的过程。
基于同一发明构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述触控面板。该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与触控电路相似，因此该显示装置的实施可以参见上述触控电路的实施，重复之处不再赘述。
本公开实施例提供的一种触控电路、触控面板及显示装置，实现了触控电路输出触控信号的功能，相对于现有技术中需要采用较多的薄膜晶体管搭建传输门、反相器以及三态门电路进而构成的触控电路，本公开实施例提供的触控电路结构简单，功耗较低。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求的范围之内，则本公开也意图包含这些改动和变型在内。
本申请要求于2015年5月13日递交的中国专利申请第201510243727.7号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (19)

  1. 一种触控电路，包括：
    输入模块，其控制端与输入信号端相连，输入端与第一参考信号端相连，输出端与第一节点相连，用于在所述输入信号端的控制下，将所述第一参考信号端的信号提供给所述第一节点；
    复位模块，其控制端与复位信号端相连，输入端与第二参考信号端相连，输出端与所述第一节点相连，用于在所述复位信号端的控制下，将所述第二参考信号端的信号提供给所述第一节点；
    上拉模块，其控制端与所述第一节点相连，输入端与第一时钟信号端相连，输出端与控制信号输出端相连，用于在所述第一节点的电位为第一电位时，将所述第一时钟信号端的信号提供给所述控制信号输出端；
    下拉模块，其控制端与第二节点相连，输入端与第三参考信号端相连，输出端与所述控制信号输出端相连，用于在所述第二节点的电位为第一电位时，将所述第三参考信号端的信号提供给所述控制信号输出端；
    下拉控制模块，分别与第二时钟信号端、所述第一节点节点和所述第二节点相连，用于在所述第二时钟信号端的控制下，将所述第二时钟信号端的信号提供给所述第二节点，在所述第一节点的电位为第一电位时，控制所述第二节点的电位为第二电位，在所述第二节点的电位为第一电位时，控制所述第一节点的电位为第二电位；
    触控信号输出模块，其第一输入端与所述控制信号输出端相连，第二输入端与高频信号端相连，第三输入端与公共电压信号端相连，用于在所述控制信号输出端的控制下，向触控信号输出端输出高频信号或公共电压信号。
  2. 如权利要求1所述的触控电路，其中，当所述输入信号端的有效脉冲信号为高电位信号时，所述第一电位为高电位，所述第二电位为低电位；当所述输入信号端的有效脉冲信号为低电位信号时，所述第一电位为低电位，所述第二电位为高电位；且当所述输入信号端输出有效脉冲信号开始，所述第一时钟信号端和所述第二时钟信号端交替输出第一电位信号。
  3. 如权利要求1或2所述的触控电路，其中，所述下拉控制模块包括：
    第一下拉控制单元，其控制端和输入端均与第二时钟信号端相连，输出端与所述第二节点相连，用于在第二时钟信号端的控制下，将所述第二时钟信号 端的信号提供给所述第二节点；
    第二下拉控制单元，其控制端与所述第一节点相连，输入端与所述第三参考信号端相连，输出端与所述第二节点相连，用于在所述第一节点的电位为第一电位时，将所述第三参考信号端的信号提供给所述第二节点；
    第三下拉控制单元，其控制端与所述第二节点相连，输入端与所述第三参考信号端相连，输出端与所述第一节点相连，用于在所述第二节点的电位为第一电位时，将所述第三参考信号端的信号提供给所述第一节点。
  4. 如权利要求3所述的触控电路，其中，所述下拉控制模块还包括：
    第四下拉控制单元，其控制端与所述控制信号输出端相连，输入端与所述第三参考信号端相连，输出端与所述第二节点相连，用于在所述控制信号输出端的电位为第一电位时，将所述第三参考信号端的信号提供给所述第二节点。
  5. 如权利要求3所述的触控电路，其中，所述第一下拉控制单元包括：
    第一开关晶体管，其栅极和源极均与所述第二时钟信号端相连，漏极与所述第一节点相连。
  6. 如权利要求3所述的触控电路，其中，所述第二下拉控制单元包括：
    第二开关晶体管，其栅极与所述第一节点相连，源极与所述第三参考信号端相连，漏极与所述第二节点相连。
  7. 如权利要求3所述的触控电路，其中，所述第三下拉控制单元包括：
    第三开关晶体管，其栅极与所述第二节点相连，源极与所述第三参考信号端相连，漏极与所述第一节点相连。
  8. 如权利要求4所述的触控电路，其中，所述第四下拉控制单元包括：
    第四开关晶体管，其栅极与所述控制信号输出端相连，源极与所述第三参考信号端相连，漏极与所述第二节点相连。
  9. 如权利要求1所述的触控电路，其中，所述触控信号输出模块包括：高频信号输出单元、公共电压信号输出单元、上拉单元以及下拉单元；其中，
    所述上拉单元的控制端为所述触控信号输出模块的第一输入端，输入端与低频信号端相连，输出端与第三节点相连；所述上拉单元用于在所述控制信号输出端的电位为第一电位时，将所述低频信号端的信号提供给所述第三节点；
    所述下拉单元的控制端与截止信号端相连，输入端与所述第三节点相连，输出端与所述第三参考信号端相连，所述下拉单元用于在所述截止信号端的控制下，将所述第三参考信号端的信号提供给所述第三节点；
    所述高频信号输出单元的控制端与所述第三节点相连，输入端为所述触控信号输出模块的第二输入端，输出端与所述触控信号输出端相连；所述高频信号输出单元用于在所述第三节点的电位为第一电位时，控制所述触控信号输出端输出高频信号；
    所述公共电压信号输出单元连接于所述第三节点、所述第三参考信号端、第四参考信号端、所述公共电压信号端、以及所述触控信号输出端之间，所述公共电压信号输出单元用于在所述第三节点的电位为第二电位时，控制所述触控信号输出端输出公共电压信号。
  10. 如权利要求9所述的触控电路，其中，所述上拉单元包括：
    第五开关晶体管，其栅极与所述控制信号输出端相连，源极与所述低频信号端相连，漏极与所述第三节点相连。
  11. 如权利要求9所述的触控电路，其中，所述下拉单元包括：
    第六开关晶体管，其栅极与所述截止信号端相连，源极与所述第三参考信号端相连，漏极与所述第三节点相连。
  12. 如权利要求9所述的触控电路，其中，所述高频信号输出单元包括：
    第七开关晶体管，其栅极与所述第三节点相连，源极与所述高频信号端相连，漏极与所述触控信号输出端相连；
    第一电容，连接在所述第七开关晶体管的栅极与漏极之间。
  13. 如权利要求9所述的触控电路，其中，所述公共电压信号输出单元包括：
    第八开关晶体管，其栅极与所述第四参考信号端相连，源极与所述公共电压信号端相连，漏极与所述触控信号输出端相连；
    第九开关晶体管，其栅极与所述第三节点相连，源极与所述第三参考信号端相连，漏极与所述第四参考信号端相连。
  14. 如权利要求1-13任一项所述的触控电路，其中，所述输入模块包括：
    第十开关晶体管，其栅极与所述输入信号端相连，源极与所述第一参考信号端相连，漏极与所述第一节点相连。
  15. 如权利要求1-13任一项所述的触控电路，其中，所述复位模块包括：
    第十一开关晶体管，其栅极与所述复位信号端相连，源极与所述第二参考信号端相连，漏极与所述所述第一节点相连。
  16. 如权利要求1-13任一项所述的触控电路，其中，所述上拉模块包括：
    第十二开关晶体管，其栅极与所述第一节点相连，源极与所述第一时钟信号端相连，漏极与所述控制信号输出端相连；
    第二电容，连接于所述第十二开关晶体管的栅极与漏极之间。
  17. 如权利要求1-13任一项所述的触控电路，其中，所述下拉模块包括：
    第十三开关晶体管，其栅极与所述第二节点相连，源极与所述第三参考信号端相连，漏极与所述控制信号输出端相连。
  18. 一种触控面板，包括级联的多个如权利要求1-17任一项所述的触控电路；其中，
    除首级触控电路之外，其它各级触控电路的控制信号输出端均与相邻的上一级触控电路的复位信号端相连；
    除末级触控电路之外，其它各级触控电路的控制信号输出端均与相邻的下一级触控电路的信号输入端相连。
  19. 一种显示装置，包括如权利要求18所述的触控面板。
PCT/CN2015/095372 2015-05-13 2015-11-24 触控电路、触控面板及显示装置 Ceased WO2016180003A1 (zh)

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