WO2016179849A1 - 场效应晶体管和其制造方法及显示器 - Google Patents

场效应晶体管和其制造方法及显示器 Download PDF

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WO2016179849A1
WO2016179849A1 PCT/CN2015/079327 CN2015079327W WO2016179849A1 WO 2016179849 A1 WO2016179849 A1 WO 2016179849A1 CN 2015079327 W CN2015079327 W CN 2015079327W WO 2016179849 A1 WO2016179849 A1 WO 2016179849A1
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layer
field effect
effect transistor
semiconductor layer
gate layer
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French (fr)
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徐洪远
萧祥志
苏长义
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/023—Manufacture or treatment of FETs having insulated gates [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H10K10/482—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors the IGFET comprising multiple separately-addressable gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a field effect transistor.
  • Liquid crystal display technology is a highly developed and highly regarded technology today. As the cornerstone of the information industry, it involves a wide range of technologies and a strong driving force in the industry. It is an important embodiment of the country's industrialization capabilities and competitiveness. Field effect transistors are one of the most important structures in displays, so their structure and manufacturing process are among the key research objects in the field of display technology.
  • the structure of a field effect transistor especially a thin film transistor, has a large limit on the threshold voltage of the field effect transistor, so that the threshold voltage is large. Larger threshold voltages cause the field effect transistors to consume more energy during use, which is not conducive to the research and development of field effect transistors.
  • the present invention proposes a field effect transistor which consumes less power.
  • the present invention also proposes a method of fabricating a field effect transistor by which a field effect transistor having low energy consumption can be fabricated.
  • the present invention also proposes a display comprising the above field effect transistor, which has a lower energy consumption.
  • a field effect transistor comprising: a source and a drain spaced apart from each other, a semiconductor layer disposed between the source and the drain, in the semiconductor layer a first gate layer on one side and a second gate layer on the other side of the semiconductor layer.
  • gate layers are respectively provided on both sides of the semiconductor layer. On both sides When the gate layer is energized, carriers can be generated on both sides of the semiconductor layer toward the gate layer, and even carriers can be generated inside the semiconductor layer, thereby increasing the open conductive channel in the semiconductor layer.
  • this structure can increase the on-state current of the field effect transistor, thereby improving the efficiency of the field effect transistor.
  • this structure also reduces the off-state voltage of the field effect transistor, thereby further reducing the power consumption of the field effect transistor.
  • the projection of the first gate layer in the vertical direction covers the source and drain. This structure can prevent the semiconductor layer between the source, the drain, and the source and the drain from being illuminated, thereby effectively reducing the off-state current.
  • the first gate layer is spaced apart from the semiconductor layer by a first isolation layer
  • the second gate layer is spaced apart from the semiconductor layer by a second isolation layer.
  • the projection of the second gate layer in the vertical direction covers the source and drain of the source and drain layers. This structure can prevent the semiconductor layer between the source, the drain, and the source and the drain from being illuminated, thereby effectively reducing the off-state current.
  • the semiconductor layer extends to accommodate the source and drain. This arrangement is simpler and the semiconductor layer protects the source and drain.
  • the projection of the first gate layer in the vertical direction covers the semiconductor layer. This structure can prevent the semiconductor layer from being exposed to light, thereby effectively reducing the off-state current.
  • the projection of the second gate layer in the vertical direction covers the semiconductor layer. This structure can further prevent the semiconductor layer from being exposed to light, thereby further reducing the off-state current.
  • a method of fabricating the above field effect transistor comprising the steps of: disposing a semiconductor integral film on a first gate layer, and setting on another side of the semiconductor complete film a photoresist, the semiconductor integral film is light transmissive, the first gate layer is opaque, and the photoresist is exposed by using the first gate layer as a mask to form a predetermined pattern
  • the semiconductor integral film is formed into the semiconductor layer by the predetermined pattern. In this way, the manufacturing cost of the field effect transistor can be effectively reduced.
  • a second insulating layer intact film is further disposed on the other side of the semiconductor integral film, and a photoresist is disposed on the other side of the second insulating layer intact film, the second insulating layer Layer intact membrane Transmissively exposing the photoresist with the first gate layer as a mask to form a predetermined pattern, wherein the semiconductor complete film is formed into the semiconductor layer by the predetermined pattern, so that the first The second insulating layer complete film forms the second insulating layer.
  • the manufacturing cost of the field effect transistor can be more effectively reduced.
  • a display comprising the above field effect transistor. This type of display consumes less energy.
  • the present invention has the advantages that: (1) when the gates on both sides are energized, the semiconductor layer covering the source/drain layer can be made on the side facing the first gate layer and facing the second Carriers can be generated on one side of the gate layer, thereby increasing the open conductive channel in the semiconductor layer. This lowers the threshold voltage, thereby reducing the electrical energy required to bring the field effect transistor of the present invention to an on state, thereby reducing the power consumption of the field effect transistor of the present invention. (2) This structure can also increase the on-state current of the field effect transistor, thereby improving the efficiency of the field effect transistor. (3) This structure also reduces the off-state voltage of the field effect transistor, thereby further reducing the power consumption of the field effect transistor.
  • Figure 1 shows the first step in the process of the field effect transistor of the present invention.
  • FIG. 2 shows the latter step of the process of the field effect transistor of the present invention in accordance with Figure 1.
  • Figure 3 shows the latter step of the process of the field effect transistor of the present invention in accordance with Figure 2.
  • Figure 4 shows the latter step of the process of the field effect transistor of the present invention in accordance with Figure 3.
  • Figure 5 shows the latter step of the process of the field effect transistor of the present invention in accordance with Figure 4.
  • Figure 6 shows the latter step of the process of the field effect transistor of the present invention in accordance with Figure 5.
  • Fig. 7 shows the general structure of the field effect transistor of the present invention, and shows the latter step of the process of the field effect transistor of the present invention according to Fig. 6.
  • first gate layer 20 is a lower side
  • second gate layer 70 is One side is the upper side.
  • vertical direction is the direction from the first gate layer 20 to the second gate layer 70, or the opposite direction thereof.
  • the “projection in the vertical direction” is projected on the surface in which the first gate layer is located or parallel to the plane in which the first gate layer is located.
  • FIG. 1 to 7 schematically show the manufacturing process of the field effect transistor 100 of the present invention.
  • the manufacturing method of the field effect transistor 100 is as follows.
  • a metal layer is formed on the substrate 10 by a sputtering process, and is formed into a first gate layer 20 as shown in FIG. 1 by a photolithography process.
  • a first insulating layer 30 is applied over the substrate 10 and the first gate layer 20.
  • a metal layer is formed by a sputtering process and formed into a source/drain layer 40 as shown in FIG. 3 by a photolithography process.
  • the source drain layer 40 includes a source and a drain spaced apart from the source.
  • a semiconductor integral film 51 is coated over the source and drain layers 40 and the first insulating layer 30.
  • the second insulating layer intact film 61 is preferably applied over the semiconductor integral film 51.
  • the first insulating layer 30, the semiconductor intact film 51 and the second insulating layer intact film 61 are all light transmissive, and the first gate layer 20 is opaque.
  • the field effect transistor 100 is irradiated from the lower side to expose the photoresist over the semiconductor layer 50 and/or the second insulating layer 60 to form a predetermined pattern of the photoresist. Etching is then performed according to a predetermined pattern to form the semiconductor layer 50 and/or the second insulating layer 60 as shown in FIG.
  • the semiconductor layer 50 and/or the second insulating layer 60 can be formed by directly exposing the first gate layer 20 as a mask, thereby eliminating the need to separately fabricate a mask, thereby saving the manufacturing cost of the field effect transistor 100.
  • a metal layer is formed by a sputtering process and formed into a second gate layer 70 as shown in FIG. 6 by a photolithography process.
  • a protective layer 80 is overlaid on the second gate layer 70.
  • the protective layer 80 preferably covers the entire field effect transistor 100.
  • Fig. 7 also schematically shows the structure of the field effect transistor 100 of the present invention.
  • the field effect transistor 100 of the present invention includes a source and drain layer 40.
  • Source drain layer 40 includes source and drain electrodes that are spaced apart from one another.
  • the field effect transistor 100 further includes a semiconductor layer 50 disposed between the source and the drain. When the field effect transistor 100 is energized, carriers are generated on the semiconductor layer 50, and a conductive channel is formed.
  • the semiconductor layer 50 can be extended to completely accommodate the source and drain and cover one side of the source and drain.
  • the semiconductor layer 50 of such a structure is easy to process and has a better effect of generating carriers.
  • the field effect transistor 100 further includes a first gate layer 20 on the lower side of the source and drain layer 40, and a second gate layer 70 on the upper side of the source and drain layer 40.
  • the first gate layer 20 and the second gate layer 70 are spaced apart from the source and drain layers 40 and the semiconductor layer 50.
  • the first gate layer 20 and the second gate layer 70 on both sides of the semiconductor layer 50 can form a current carrying current on both faces of the semiconductor layer 50 between the source and the drain.
  • the number of conductive channels opened in the semiconductor layer 50 is thereby increased.
  • carriers are generated on both the surface and the inside of the semiconductor layer 50 between the source and the drain, that is, the semiconductor layer 50 between the source and the drain can be filled with carriers, thereby further The number of conductive channels opened within the semiconductor layer 50 is increased. This can reduce the threshold voltage of the field effect transistor 100, thereby reducing the voltage required to bring the field effect transistor 100 in an on state, thereby reducing the power consumption of the field effect transistor 100.
  • this also increases the on-state current of the field effect transistor 100, and thereby speeds up the charging and discharging of the field effect transistor 100, thereby improving the operational efficiency of the field effect transistor 100. In addition, this also reduces the off-state voltage of the field effect transistor 100, thereby further reducing the power consumption of the field effect transistor 100.
  • the first gate layer 20 is disposed on the substrate 10 and overlies the first insulating layer 30 over the first gate layer 20, over the first insulating layer 30, and then covers the source and drain electrodes.
  • Layer 40 and semiconductor layer 50 This arrangement can be relatively stable, providing a corresponding basis for making a low power field effect transistor 100.
  • the first gate layer 20 completely covers the source and drain. This prevents illumination from being irradiated from the side on which the first gate layer 20 is disposed to the source and drain, and the semiconductor layer 50 therebetween, so that the off-state current of the field effect transistor 100 can be effectively reduced.
  • the first gate layer 20 completely covers the semiconductor layer 50, which prevents illumination from being irradiated from the side on which the first gate layer 20 is disposed.
  • the source, drain and semiconductor layers 50 further reduce the off-state current of the field effect transistor 100.
  • the field effect transistor 100 further includes a second insulating layer 60 disposed between the semiconductor layer 50 and the second gate layer 70 . This configuration assures the stability of the field effect transistor 100, thereby providing a corresponding basis for the low power field effect transistor 100.
  • the second gate layer 70 completely covers the source and drain. This prevents illumination from being irradiated from the side on which the second gate layer 70 is disposed to the source and drain, and the semiconductor layer 50 therebetween, so that the off-state current of the field effect transistor 100 can be effectively reduced.
  • the second gate layer 70 completely covers the semiconductor layer 50, which prevents illumination from being irradiated from the side on which the second gate layer 70 is disposed.
  • the source, drain and semiconductor layers 50 further reduce the off-state current of the field effect transistor 100.
  • the first gate layer 20 and the second gate layer 70 are covered with the semiconductor layer 50, and the light on both sides can be effectively prevented from being irradiated to the semiconductor layer 50.
  • the first gate layer 20 can block the backlight
  • the second gate layer 70 can block the front light source (ie, natural light, etc.). The state voltage is reduced to a minimum.
  • a protective layer 80 is disposed over the second gate layer 70.
  • the protective layer 80 preferably covers the entire field effect transistor 100 to protect the stability of the structure of the field effect transistor 100.
  • the field effect transistor 100 of the present invention is a thin film transistor.
  • the field effect transistor 100 of the present invention is particularly suitable for use in a flexible display, in which case the field effect transistor of the present invention is an organic thin film transistor.
  • the material of the substrate 10 is polyethylene naphthalate (PEN), polyethylene terephthalate (PET) or polyimide (PI).
  • the field effect transistor 100 described above has a lower power consumption and can even bring the threshold voltage to be close to zero.
  • the display using the field effect transistor 100 described above has a correspondingly lower power consumption.

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  • Thin Film Transistor (AREA)

Abstract

一种场效应晶体管（100）和其制造方法及显示器。场效应晶体管（100）包括：相互间隔开设置的源极和漏极，设置于所述源极和漏极之间的半导体层（50），处于所述半导体层（50）的一侧的第一栅极层（20），以及处于所述半导体层（50）的另一侧的第二栅极层（70）。这种场效应晶体管（100）的能耗较低。用于制造这种场效应晶体管（100）的方法成本较低。使用这种场效应晶体管（100）的显示器的能耗较低。

Description

场效应晶体管和其制造方法及显示器
相关申请的交叉引用
本申请要求享有于2015年5月8日提交的名称为“场效应晶体管和其制造方法及显示器”的中国专利申请CN201510232927.2的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，特别是涉及一种场效应晶体管。
背景技术
液晶显示技术是在当今高度发展并备受重视的一项技术。其作为信息产业的基石，涉及技术面宽，产业带动力大，是国家工业化能力和竞争力的重要体现。场效应晶体管是显示器中最为重要的结构之一，因此其结构和制造工艺是在显示器技术领域中的重点研究对象之一。
在现有技术中，场效应晶体管，尤其是薄膜晶体管，的结构对场效应晶体管的阈值电压有较大的限制，使得阈值电压较大。阈值电压较大会导致场效应晶体管在使用的过程中耗能较多，十分不利于场效应晶体管的研究和发展。
因此，需要一种耗能低的场效应晶体管。
发明内容
针对上述问题，本发明提出了一种场效应晶体管，使用这种场效应晶体管的耗能较低。本发明还提出了一种场效应晶体管制造方法，使用这种方法能够制造出耗能低的场效应晶体管。本发明还提出了一种包括上述场效应晶体管的显示器，这种显示器的耗能较低。
根据本发明的第一方面，提出了一种场效应晶体管，其包括：相互间隔开设置的源极和漏极，设置于所述源极和漏极之间的半导体层，处于所述半导体层的一侧的第一栅极层，以及处于所述半导体层的另一侧的第二栅极层。
根据本发明的场效应晶体管，在半导体层的两侧分别设置栅极层。在两侧的 栅极层通电时，使得半导体层朝向栅极层的两侧均能产生载流子，甚至令半导体层内部也能产生载流子，从而增加了半导体层中的打开的导电沟道。这减小了阈值电压，从而降低了使本发明的场效应晶体管处于开态所需的电能，进而降低了本发明的场效应晶体管的能耗。另外，这种结构还能增大场效应晶体管的开态电流，从而提高了场效应晶体管的工作效率。此外，这种结构还减小了场效应晶体管的关态电压，从而进一步降低了场效应晶体管的能耗。
在一个实施例中，第一栅极层沿竖直方向上的投影覆盖所述源极和漏极。这种结构能够防止源极、漏极和源极与漏极之间的半导体层受到光照，从而能有效减小关态电流。
在一个实施例中，所述第一栅极层与所述半导体层通过第一隔离层间隔开，所述第二栅极层与所述半导体层通过第二隔离层间隔开。这种结构能稳定地实现本发明的场效应晶体管的结构，从而使得本发明的场效应晶体管能有效减小阈值电压，增大开态电流，并减小关态电流。
在一个实施例中，第二栅极层沿竖直方向上的投影覆盖所述源漏极层的源极和漏极。这种结构能够防止源极、漏极和源极与漏极之间的半导体层受到光照，从而能有效减小关态电流。
在一个实施例中，半导体层延伸以容纳所述源极和漏极。这种设置加工方式较为简便，并且半导体层能对源极和漏极起到保护作用。
在一个实施例中，第一栅极层沿竖直方向上的投影覆盖半导体层。这种结构能够防止半导体层受到光照，从而能有效减小关态电流。
在一个实施例中，第二栅极层沿竖直方向上的投影覆盖半导体层。这种结构能进一步防止半导体层受到光照，从而进一步减小了关态电流。
根据本发明的第二方面，提出了一种制造上述场效应晶体管的方法，所述方法包括以下步骤：在第一栅极层上设置半导体完整膜，在所述半导体完整膜的另一侧设置光刻胶，所述半导体完整膜为透光的，所述第一栅极层为不透光的，以所述第一栅极层作为掩膜对所述光刻胶进行曝光以形成预定图案，借助所述预定图案使所述半导体完整膜形成所述半导体层。通过这种方式，能有效降低场效应晶体管的制造成本。
在一个实施例中，在所述半导体完整膜的另一侧还设置有第二绝缘层完整膜，再在所述第二绝缘层完整膜的另一侧设置光刻胶，所述第二绝缘层完整膜为 透光的，以所述第一栅极层作为掩膜对所述光刻胶进行曝光，以形成预定图案，借助所述预定图案使所述半导体完整膜形成所述半导体层，使所述第二绝缘层完整膜形成所述第二绝缘层。通过这种方式，能更加有效降低场效应晶体管的制造成本。
根据本发明的第三方面，还提出了一种显示器，其包括上述场效应晶体管。这种显示器的耗能较低。
与现有技术相比，本发明的优点在于：(1)在两侧的栅极通电时，能使得覆盖源漏极层的半导体层在其朝向第一栅极层的一侧和朝向第二栅极层的一侧均能产生载流子，从而增加了半导体层中的打开的导电沟道。这降低了阈值电压，从而降低了使本发明的场效应晶体管处于开态所需的电能，进而降低了本发明的场效应晶体管的能耗。(2)这种结构还能增大场效应晶体管的开态电流，从而提高了场效应晶体管的工作效率。(3)这种结构还减小了场效应晶体管的关态电压，从而进一步降低了场效应晶体管的能耗。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1显示了本发明的场效应晶体管的工艺过程中的第一步。
图2显示了根据图1的本发明的场效应晶体管的工艺过程的后一步过程。
图3显示了根据图2的本发明的场效应晶体管的工艺过程的后一步过程。
图4显示了根据图3的本发明的场效应晶体管的工艺过程的后一步过程。
图5显示了根据图4的本发明的场效应晶体管的工艺过程的后一步过程。
图6显示了根据图5的本发明的场效应晶体管的工艺过程的后一步过程。
图7显示了本发明的场效应晶体管的大体结构，并且显示了根据图6的本发明的场效应晶体管的工艺过程的后一步过程。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例绘制。
具体实施方式
下面将结合附图对本发明作进一步说明。
应理解地是，这里所说的“上”、“下”均为相对的方向，相对于半导体层50而言，第一栅极层20的一侧为下侧，第二栅极层70的一侧为上侧。另外，这 里所说的“竖直方向”为从第一栅极层20到第二栅极层70的方向，或其相反方向。“沿竖直方向上的投影”即投影在与第一栅极层所在平面，或与第一栅极层所在平面平行的表面上。
图1到图7示意性显示了本发明的场效应晶体管100的制造过程。场效应晶体管100的制造方法如下。
如图1所示，在基板10上通过溅射工艺形成一层金属层，并通过光刻工艺使其形成为如图1所示的第一栅极层20。
如图2所示，在基板10和第一栅极层20之上涂覆第一绝缘层30。
如图3所示，在第一绝缘层30上，通过溅射工艺形成一层金属层，并通过光刻工艺使其形成为如图3所示的源漏极层40。源漏极层40包括源极和与源极间隔开的漏极。
如图4所示，在源漏极层40和第一绝缘层30之上涂覆半导体完整膜51。优选地再在半导体完整膜51之上涂覆第二绝缘层完整膜61。
这里的第一绝缘层30、半导体完整膜51和第二绝缘层完整膜61均为透光的，而第一栅极层20为不透光的。
如果不设置第二绝缘层完整膜61，就在半导体完整膜51上涂覆光刻胶，如果有第二绝缘层完整膜61，则在第二绝缘层完整膜61上涂覆光刻胶。如图4所示的那样，从下侧朝向场效应晶体管100照射，以对半导体层50和/或第二绝缘层60之上的光刻胶曝光，使光刻胶形成预定图案。然后再根据预定图案进行蚀刻以形成如图5所示的半导体层50和/或第二绝缘层60。这种半导体层50和/或第二绝缘层60的形成方式能直接以第一栅极层20为掩膜进行曝光，从而不必再单独制作掩膜，节省了场效应晶体管100的制造成本。
如图6所示，在第二绝缘层60之上，通过溅射工艺形成一层金属层，并通过光刻工艺使其形成为如图6所示的第二栅极层70。
如图7所示，在第二栅极层70之上再覆盖一层保护层80。保护层80优选为覆盖整个场效应晶体管100。
图7还示意性显示了本发明的场效应晶体管100的结构。
本发明的场效应晶体管100包括源漏极层40。源漏极层40包括相互间隔开的源极和漏极。场效应晶体管100还包括设置于源极和漏极之间的半导体层50。在场效应晶体管100通电时，在半导体层50上产生载流子，并形成导电沟道。
优选地，如图7所示的那样，半导体层50能延伸以完全容纳源极和漏极，并覆盖在源极和漏极的一侧。这种结构的半导体层50易于加工，并且产生载流子的效果更好。
场效应晶体管100还包括处于源漏极层40下侧的第一栅极层20，以及处于源漏极层40上侧的第二栅极层70。第一栅极层20和第二栅极层70与源漏极层40和半导体层50间隔开。
在场效应晶体管100通电时，处于半导体层50两侧的第一栅极层20和第二栅极层70能在在源极和漏极之间的半导体层50的两个面上均形成载流子，由此增加半导体层50内打开的导电沟道的数量。另外还优选地使源极和漏极之间的半导体层50的表面和内部都产生载流子，即是说可令源极和漏极之间的半导体层50充满载流子，由此进一步增加半导体层50内打开的导电沟道的数量。这能减小场效应晶体管100的阈值电压，从而使得令场效应晶体管100处于开态所需的电压减小，进而降低了场效应晶体管100的能耗。另外，这还增大了场效应晶体管100的开态电流，并由此加快了场效应晶体管100充电和放电的速率，从而提高了场效应晶体管100的工作效率。此外，这还减小了场效应晶体管100的关态电压，由此进一步降低了场效应晶体管100的能耗。
在一个实施例中，第一栅极层20设置于基板10上，并在第一栅极层20之上再覆盖第一绝缘层30，在第一绝缘层30之上，再覆盖源漏极层40和半导体层50。这种设置能够较为稳定，从而为制得低能耗的场效应晶体管100提供了相应的基础。
如图7所示，第一栅极层20完全覆盖源极和漏极。这样能防止光照从设置有第一栅极层20的这一侧照射到源极和漏极，及其之间的半导体层50，从而能有效减小场效应晶体管100的关态电流。
优选地，在半导体层50延伸以容纳源极和漏极的情况下，第一栅极层20完全覆盖半导体层50，这样能防止光照从设置有第一栅极层20的这一侧照射到源极、漏极和半导体层50，从而进一步减小了场效应晶体管100的关态电流。
如图7所示，场效应晶体管100还包括第二绝缘层60，第二绝缘层60设置于半导体层50与第二栅极层70之间。这种结构保证了场效应晶体管100的稳定性，从而为低能耗的场效应晶体管100提供了相应的基础。
如图7所示，第二栅极层70完全覆盖源极和漏极。这样能防止光照从设置有第二栅极层70的这一侧照射到源极和漏极，及其之间的半导体层50，从而能有效减小场效应晶体管100的关态电流。
优选地，在半导体层50延伸以容纳源极和漏极的情况下，第二栅极层70完全覆盖半导体层50，这样能防止光照从设置有第二栅极层70的这一侧照射到源极、漏极和半导体层50，从而进一步减小了场效应晶体管100的关态电流。
同时令第一栅极层20和第二栅极层70覆盖半导体层50，能有效防止两侧的光照射到半导体层50。尤其是在使用这种场效应晶体管100的显示器中，第一栅极层20能阻挡背光源，而第二栅极层70能阻挡前光源(即自然光等)，这种遮光的结构能使关态电压降到最小。
在第二栅极层70之上设置保护层80，保护层80优选为覆盖整个场效应晶体管100，以保护场效应晶体管100结构的稳定性。
在使用于显示器中的情况下，本发明的场效应晶体管100为薄膜晶体管。另外，本发明的场效应晶体管100尤其适用于柔性显示器中，此时，本发明的场效应晶体管为有机薄膜晶体管。当场效应晶体管作为有机薄膜晶体管时，基板10的材料为聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)或聚酰亚胺(PI)。
上述场效应晶体管100的能耗较低，甚至可令阈值电压极接近于零。使用上述场效应晶体管100的显示器，相应地具有较低的能耗。这里优选地在第一栅极层20和第二栅极层70上施加相同电位的电压，能以最简便的方式，使场效应晶体管100的耗能降到最低。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (22)

  1. 一种场效应晶体管，其包括：
    相互间隔开设置的源极和漏极，
    设置于所述源极和漏极之间的半导体层，
    处于所述半导体层的一侧的第一栅极层，以及
    处于所述半导体层的另一侧的第二栅极层。
  2. 根据权利要求1所述的场效应晶体管，其中，所述第一栅极层沿竖直方向上的投影覆盖所述源极和漏极。
  3. 根据权利要求1所述的场效应晶体管，其中，所述第一栅极层与所述半导体层通过第一隔离层间隔开，所述第二栅极层与所述半导体层通过第二隔离层间隔开。
  4. 根据权利要求3所述的场效应晶体管，其中，所述第二栅极层沿竖直方向上的投影覆盖所述源极和漏极。
  5. [根据细则91更正 05.06.2015]　

  6. [根据细则91更正 05.06.2015]　
  7. 根据权利要求1所述的场效应晶体管，其中，所述半导体层延伸以容纳所述源极和漏极。
  8. 根据权利要求5所述的场效应晶体管，其中，所述第一栅极层沿竖直方向上的投影覆盖所述半导体层。
  9. 根据权利要求5所述的场效应晶体管，其中，所述第二栅极层沿竖直方向上的投影覆盖所述半导体层。
  10. 根据权利要求2所述的场效应晶体管，其中，所述半导体层延伸以容纳所述源极和漏极。
  11. 根据权利要求8所述的场效应晶体管，其中，所述第一栅极层沿竖直方向上的投影覆盖所述半导体层。
  12. 根据权利要求8所述的场效应晶体管，其中，所述第二栅极层沿竖直方向上的投影覆盖所述半导体层。
  13. 一种制造场效应晶体管的方法，所述方法包括以下步骤：
    在第一栅极层上设置半导体完整膜，在所述半导体完整膜的另一侧设置光刻胶，所述半导体完整膜为透光的，所述第一栅极层为不透光的，
    以所述第一栅极层作为掩膜对所述光刻胶进行曝光，以形成预定图案，
    借助所述预定图案使所述半导体完整膜形成所述半导体层，
    所述场效应晶体管包括：
    相互间隔开设置的源极和漏极，
    设置于所述源极和漏极之间的半导体层，
    处于所述半导体层的一侧的第一栅极层，以及
    处于所述半导体层的另一侧的第二栅极层。
  14. 根据权利要求11所述的方法，其中，在所述半导体完整膜的另一侧还设置有第二绝缘层完整膜，再在所述第二绝缘层完整膜的另一侧设置光刻胶，所述第二绝缘层完整膜为透光的，
    以所述第一栅极层作为掩膜对所述光刻胶进行曝光，以形成预定图案，
    借助所述预定图案使所述半导体完整膜形成所述半导体层，使所述第二绝缘层完整膜形成所述第二绝缘层。
  15. 根据权利要求11所述的方法，其中，所述第一栅极层沿竖直方向上的投影覆盖所述源极和漏极。
  16. 一种显示器，其包括场效应晶体管，所述场效应晶体管包括：
    相互间隔开设置的源极和漏极，
    设置于所述源极和漏极之间的半导体层，
    处于所述半导体层的一侧的第一栅极层，以及
    处于所述半导体层的另一侧的第二栅极层。
  17. 根据权利要求14所述的显示器，其中，所述第一栅极层沿竖直方向上的投影覆盖所述源极和漏极。
  18. 根据权利要求14所述的显示器，其中，所述第一栅极层与所述半导体层通过第一隔离层间隔开，所述第二栅极层与所述半导体层通过第二隔离层间隔开。
  19. 根据权利要求16所述的显示器，其中，所述第二栅极层沿竖直方向上的投影覆盖所述源极和漏极。
  20. 根据权利要求14所述的显示器，其中，所述半导体层延伸以容纳所述源极和漏极。
  21. 根据权利要求18所述的显示器，其中，所述第一栅极层沿竖直方向上的投影覆盖所述半导体层。
  22. 根据权利要求18所述的显示器，其中，所述第二栅极层沿竖直方向上的投影覆盖所述半导体层。
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