WO2016178281A1 - Appareil d'émission de signal électrique - Google Patents

Appareil d'émission de signal électrique Download PDF

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Publication number
WO2016178281A1
WO2016178281A1 PCT/JP2015/063142 JP2015063142W WO2016178281A1 WO 2016178281 A1 WO2016178281 A1 WO 2016178281A1 JP 2015063142 W JP2015063142 W JP 2015063142W WO 2016178281 A1 WO2016178281 A1 WO 2016178281A1
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WIPO (PCT)
Prior art keywords
signal
impedance
signal transmission
transmission line
substrate
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PCT/JP2015/063142
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English (en)
Japanese (ja)
Inventor
文夫 結城
健治 古後
則雄 中島
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株式会社日立製作所
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Priority to PCT/JP2015/063142 priority Critical patent/WO2016178281A1/fr
Publication of WO2016178281A1 publication Critical patent/WO2016178281A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/12—Compensating for variations in line impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to an electric transmission apparatus, and more particularly to a transmission path configuration for reducing reflection caused by impedance mismatching that occurs between a transmission path and solder balls or vias existing at both ends of the transmission path.
  • FIG. 11A shows a configuration diagram of conventional impedance matching
  • FIG. 11B shows a block diagram.
  • This is a transmission path configuration in which a transmission path substrate 1001, a semiconductor package (PKG) 1010, and a semiconductor integrated circuit device 1009 are connected via a BGA (ball grid array) 1006 and solder balls 1008.
  • the impedance Zc of the solder ball 1008 or the like is designed to have a substantially differential impedance of 100 ⁇ , and is composed of the wiring layer 1002 of the transmission line substrate 1001 and the vias 1003 and 1004.
  • the impedances (Zline and Zpkg) of the transmission line 1005 and the PKG wiring 1007 are also designed with a differential impedance of 100 ⁇ . This is for matching with an external interface 1012 (electric cable or measuring instrument) having a differential impedance of 100 ⁇ connected via the input / output 1011.
  • Patent Literature 1 discloses a conventional impedance matching technique.
  • the inventors examined the influence of impedance matching on the transmission line as the signal speed handled by the device increases as follows.
  • FIG. 12 shows an image of the impedance characteristic output using the TDR (Time Domain Reflectometry) method corresponding to the configuration of FIG.
  • the horizontal axis indicates the electrical length of each line appearing in the order of the physical configuration, and the vertical axis indicates the impedance.
  • the board wiring Zline and the PKG wiring Zpkg have a differential impedance of 100 ⁇ , and the BGAZbga and the solder ball Zc also have characteristics of a differential impedance of 100 ⁇ . In other words, reflection caused by impedance mismatching is prevented, and jitter characteristic deterioration caused by reflection noise is prevented.
  • Fig. 13 shows the calculation results of the frequency dependence of the differential impedance of the solder balls.
  • Frequency, resistance, inductance and capacity were calculated as parameters from the above formula.
  • the capacitance value was calculated under the conditions of 50 fF, 100 fF, and 250 fF assuming a large solder ball such as a small solder ball ( ⁇ 0.1 mm) to BGA ( ⁇ 0.7 mm).
  • the resistance value was also set to 2 to 20 ⁇ depending on the size of the solder ball.
  • the inductance was obtained by fitting from a TDR simulation of a transmission line model, and calculated as several tens pH.
  • the impedance is high in the conventional low-speed operation region 1301, and is small in the high-speed operation region 1302 (> 7 GHz) assumed by the present invention.
  • the impedance curve tends to converge to a constant value due to the influence of the inductor as the speed increases.
  • the impedance tends to decrease as the capacity increases. That is, the impedance of BGA, solder balls and vias in a transmission line having a large capacity tends to be small.
  • FIG. 14 shows an impedance characteristic image diagram at high speed operation (> 7 GHz) output using the TDR method.
  • the transmission line impedance (Zline) of the substrate wiring and the impedance (Zpkg) of the PKG wiring are reduced to 100 ⁇ differential impedance, and the BGA impedance (Zbga) and the solder ball impedance (Zc) are both reduced to the differential impedance 60 ⁇ . It can be seen that impedance matching is not achieved.
  • the line loss is large, so the reflection noise generated by the impedance mismatch is also attenuated. Therefore, the increase in jitter due to the influence of multiple reflection is small.
  • the line loss is small, so that the attenuation of reflected noise caused by the impedance mismatch is small. Therefore, the jitter increase due to the influence of multiple reflection is large.
  • the problem of the present invention is that solder balls and vias having capacitance characteristics with GND close to the periphery pay attention to the fact that the impedance at high speed operation is different from the characteristic impedance of the transmission line, etc.
  • solder balls or vias are present at both ends of a short line with a small loss, it is to prevent multiple reflections due to impedance mismatch and deterioration of jitter characteristics.
  • One of the ideas of the present invention is to match the impedance of the transmission line with a connection member such as a solder ball or a via that has a characteristic of reducing the impedance during high-speed operation, thereby reducing the influence of multiple reflection.
  • One aspect of the present invention is mounted on a first substrate including a first signal transmission path, a second substrate mounted on the first substrate and including a second signal transmission path, and the second substrate.
  • This is an electric signal transmission device composed of a semiconductor integrated circuit device having an internal signal path through which an electric signal having a transmission rate of 14 Gbps or more is input / output.
  • the device is disposed between a first substrate and a second substrate, and includes a first connection member that connects the first signal path and the second signal path, a second substrate, and a semiconductor integrated circuit device. And a second connecting member disposed between the second signal path and the internal signal path.
  • the impedance of the second signal transmission line is 20 times higher than the impedance of the first signal transmission line in the frequency band of the signal transmitted to the first and second signal paths.
  • the impedance of the second signal transmission line is in the range of plus or minus 35% with respect to the impedance of the first or second connection member.
  • the semiconductor integrated circuit device performs information processing for information communication
  • the first substrate constitutes a transmission path substrate
  • the second substrate stores the semiconductor integrated circuit device.
  • the semiconductor package is configured, the first connecting member is a ball grid array, the second connecting member is a solder ball, and the frequency band of the transmitted signal is 7 GHz or more.
  • the impedance of the second signal transmission line is smaller than the impedance of the first signal transmission line and larger than the impedances of the first and second connection members.
  • the impedance can be adjusted by controlling the electric capacity. In order to adjust the electric capacity, for example, the interval between the wirings is adjusted, the dielectric constant of the insulator is changed, or the shape of the ground wiring is changed.
  • the impedance of the second signal path is 75 ⁇ in the frequency band of the signal transmitted to the first and second signal paths,
  • the impedance of the first signal path is 100 ⁇ .
  • an error of about plus or minus 10% of the numerical value is allowed.
  • Another aspect of the present invention includes a semiconductor integrated circuit device in which active or passive elements are formed and having an internal signal path, a first substrate having a first signal transmission path, and a second signal transmission path.
  • An electrical signal transmission device comprising a second substrate. The device is disposed between the first substrate and the second substrate, and includes a first connection member that connects the first signal path and the second signal path, a second substrate, and a semiconductor integrated circuit device. And a second connecting member disposed between the second signal path and the internal signal path.
  • the impedance of the second signal transmission path is the same as the impedance of the first signal transmission path in the frequency band of the signal transmitted to the first and second signal paths. It takes a value between the impedances of the first or second connecting member.
  • the impedance of the second signal transmission path is closer to the impedance of the first or second connecting member than the impedance of the first signal transmission path.
  • the impedance of the second signal transmission line is 20% or more lower than the impedance of the first signal transmission line.
  • the impedance of the second signal transmission line is in the range of plus or minus 35% with respect to the impedance of the first or second connecting member.
  • Still another aspect of the present invention is an electrical transmission device including a first substrate, a second substrate, and a connector.
  • the first substrate has a first signal transmission line and a first signal terminal for transmitting a signal from the first signal transmission line.
  • the second substrate has a second signal transmission line and a second signal terminal for transmitting a signal from the second signal transmission line.
  • the connector includes a connector signal transmission line and first and second connector terminals connected to both ends of the connector signal transmission line. The first signal terminal and the first connector terminal are connected, and the second signal terminal and the second connector terminal are connected.
  • the impedance of the connector signal transmission line includes the impedance of the first and second signal transmission lines, the connection portion between the first signal terminal and the first connector terminal, and the second signal terminal and the second connector. Set to an intermediate value of the impedance of the terminal connection.
  • the connecting part can be constituted by, for example, solder or a pin / VIA fitting structure.
  • the size of the electric capacity can be controlled by adding a stub to the VIA.
  • a third board mounted on the second board and having a third signal transmission path, and an electric signal mounted on the third board and having a transmission rate of 14 Gbps or more are input / output.
  • a semiconductor integrated circuit device having an internal signal path.
  • the first connection member disposed between the second substrate and the third substrate and connecting the second signal path and the third signal path, and the third substrate and the semiconductor integrated circuit device And a third signal path and a second connection member connecting the internal signal path.
  • the impedance of the third signal transmission line is 20 times higher than the impedance of the second signal transmission line in the frequency band of the signal transmitted to the first and second signal paths.
  • the impedance of the third signal transmission line is in the range of plus or minus 35% with respect to the impedance of the first or second connection member.
  • Another aspect of the present invention is a transmission line impedance matching method, the gist of which is to electrically couple devices having a transmission path through which an electric signal with a transmission rate of 14 Gbps or more is input / output, for example.
  • the impedance of the device is matched with the impedance of the connection portion (solder, connector, etc.) between the devices.
  • reflection between wirings during high-speed operation can be reduced, and jitter characteristics can be improved.
  • Embodiment 1 of the present invention It is the upper section lineblock diagram and block diagram showing the transmission line substrate by Embodiment 1 of the present invention. It is the upper cross-section block diagram and block diagram of the PKG upper surface which show the transmission line board
  • notations such as “first”, “second”, and “third” are attached to identify the constituent elements, and do not necessarily limit the number or order.
  • a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
  • FIG. 1 is a diagram illustrating a configuration of an electric transmission apparatus according to a first embodiment of the present invention.
  • each transmission path is assumed to operate at a high speed of 7 GHz or higher.
  • Applications include, for example, communication devices and information processing devices.
  • FIG. 1A is a transparent top view of the device configuration
  • FIG. 1B is a cross-sectional view (AB cross section) of the device configuration
  • FIG. 1C is a circuit block diagram.
  • the electrical transmission device has a configuration in which a transmission path substrate 101, a semiconductor package (PKG) 160, and a semiconductor integrated circuit device 111 are connected via a BGA 105 and solder balls 110 from below.
  • the semiconductor integrated circuit device 111 various active or passive elements are formed by semiconductor integrated circuit technology.
  • the semiconductor PKG 160 functions as a signal transmission line that transmits a signal between the semiconductor integrated circuit device 111 and the transmission path substrate 101.
  • the semiconductor PKG 160 is normally used for absorbing a difference in accuracy between terminals formed on the semiconductor integrated circuit device 111 and the transmission path substrate 101, protecting the semiconductor integrated circuit device 111, and the like.
  • the semiconductor PKG 160 is configured to have a semiconductor integrated circuit device mounted therein, and FIG. 1B shows only a partial cross section thereof.
  • a BGA 105 is connected via a first signal transmission line 102 formed on a transmission line substrate 101 and a first VIA 103.
  • the BGA 105 and the second signal transmission line 107 formed in the semiconductor PKG 106 are connected via the second VIA 108.
  • the second signal transmission line 107 and the solder ball 110 are connected via the third VIA 109.
  • the solder ball 110 and the semiconductor integrated circuit device 111 are connected.
  • the first signal line transmission line 102 of the transmission line substrate 101 and the second signal transmission line 107 of the semiconductor PKG 160 are each a pair of differentials. It has a track structure.
  • the first signal line transmission line 102 is sandwiched between first GND solid layers (GROUND PLANE) 112 at the top and bottom.
  • the second signal line transmission line 107 is sandwiched between the upper and lower GND solid layers (GROUND PLANE) 113.
  • a pair of signals BGA 105 corresponding to each of the differential lines are surrounded by a plurality of GND-BGAs 114 having a GND potential arranged in the periphery.
  • a capacitive component is formed between the GND and the BGA 114. Further, a capacitive component is formed between the signal BGA 105 and the first GND solid layer (GROUND PLANE) 112 of the transmission path substrate 101 and the second GND solid layer (GROUND PLANE) 113 of the semiconductor PKG160.
  • a pair of signal solder balls 110 corresponding to each of the differential lines are surrounded by a plurality of GND-solder balls 115 having a GND potential arranged around the periphery.
  • a capacitive component is formed between the GND and the solder ball 115. Further, a capacitive component is formed between the signal solder ball 110 and the second GND solid layer (GROUND PLANE) 113.
  • FIG. 2 is a diagram showing the configuration of the electric transmission apparatus according to the first embodiment of the present invention from another viewpoint.
  • 2A is a transparent top view of the device configuration
  • FIG. 2B is a transparent side view of the device configuration
  • FIG. 2C is a circuit block diagram.
  • a portion where the GND solid layer (GROUND PLANE) 113 included in the semiconductor PKG 160 exists is shown by hatching.
  • the portion where the GND solid layer (GROUND PLANE) 113 overlaps the signal BGA 105 is hollowed out in an elliptical shape so that no extra capacity is added.
  • the first signal transmission line 102 formed on the substrate 101 is a differential line having a length of about 100 mm.
  • the second signal transmission line 107 formed in the semiconductor PKG 106 is a differential wiring having a wiring length of 3 to 7 mm.
  • the relative dielectric constant ⁇ r 3 to 5
  • the wiring width is 0.023 mm
  • the wiring space is 0.70 mm
  • the wiring thickness is 0.015 mm. That is, to reduce the wiring impedance, it is possible to cope with it by widening the wiring width.
  • the BGA105 with a diameter of about ⁇ 0.6 mm is arranged at a pitch of 1 mm, and the capacity is estimated to be 200 to 250 fF from the relationship between the BGA size and the GND 116.
  • the solder balls 110 having a diameter of about 0.1 mm are arranged at a pitch of 0.2 mm, and the capacity is estimated to be 50 to 100 fF from the relationship between the solder ball size and the GND 115.
  • the impedance tends to decrease as the operating frequency increases. It also varies depending on the capacitance value.
  • the differential impedance of the BGA 105 and the solder ball 110 is estimated from FIG. 13, it can be estimated from 14 GHz operation and a capacitance value of 50 to 250 fF to 50 to 70 ⁇ .
  • the receiving end configuration of the semiconductor integrated circuit 111 is such that the receiving end resistor 119 has a differential impedance of 100 ⁇ , and an electrostatic protection capacitance of about 250 fF is added to prevent electrostatic breakdown of the internal circuit 120.
  • the impedance Zpkg of the second signal transmission line 107 is set to a value close to the impedances Zbga and Zc of the BGA 105 and the solder ball 110. Specifically, in order to suppress the influence of the multiple reflection of the short PKG wiring having a large influence of reflection, the impedance of the second signal transmission line 107 with respect to the impedances Zbga and Zc of the BGA 105 and the solder ball 110 is set to 50 to 70 ⁇ . The impedance Zpkg is set to 60 to 80 ⁇ .
  • FIG. 3 is a TDR characteristic simulation result showing the impedance of this example.
  • the horizontal axis indicates the electrical length of each line appearing in the order of the physical configuration, and the vertical axis indicates the impedance.
  • the impedance Zline of the first signal transmission line 102 and the impedance of the receiving end of the semiconductor integrated circuit 111 are about 100 ⁇ differential impedance, the impedance Zbga of the BGA 105 is 60 ⁇ or less, and the impedance Zc of the solder ball 110 is 60 ⁇ differential impedance.
  • the impedance Zpkg of the second signal transmission line (PKG wiring) 107 is reduced to a differential impedance of 75 ⁇ , and it can be confirmed that the characteristics are as intended.
  • the impedance of the second signal transmission line 107 is the first signal transmission line. Instead of matching with 102, it is matched with the impedance of BGA 105 or solder ball 110. As a result, the impedance of the second signal transmission path is closer to the impedance of the first or second connection member than the impedance of the first signal transmission path. In the present embodiment, the impedance of the second signal transmission line 107 is 20% or more lower than the impedance of the first signal transmission line 102.
  • the impedance of the second signal transmission line is adjusted in a range of plus or minus 35% with respect to the impedance of the BGA 105 or the solder ball 110.
  • the impedance of the second signal transmission line 107 is the impedance of the first signal transmission line 102, the BGA 105 and the solder ball 110. Between the impedances.
  • FIG. 4 is a simulation result confirming the jitter reduction effect of this example.
  • the effect when Zpkg is lowered from 100 ⁇ to 85 ⁇ and 75 ⁇ can be confirmed.
  • jitter at 100 ⁇ is small.
  • 75 ⁇ tends to have smaller jitter.
  • the substrate 101 having the pair of first signal transmission lines 102 and the semiconductor integrated circuit device 111 are mounted therein, and on one surface thereof.
  • the pair of solder balls 110 provided on the semiconductor PKG 106 is electrically connected to the internal signal circuit of the semiconductor integrated circuit device 111.
  • the substrate 101 includes one first signal transmission line 102, a pair of first GND solid layers (GROUND PLANE) 112 provided so as to sandwich the first signal transmission line 102, and one And a first dielectric 104 provided so as to surround between the first signal transmission line and the pair of first GND solid layers (GROUND PLANE) 112, A pair of first signals VIA103 for transmitting signals from the pair of first GND solid layers (GROUND PLANE) 112 to the outside of each pair is provided inside, and one end of the pair of first signals VIA103 is A pair of BGAs 105 are electrically connected to each other.
  • the semiconductor PKG includes a pair of second signal transmission lines 107, a pair of second GND solid layers (GROUND PLANE) 113 provided so as to sandwich the second signal transmission lines 107, a second A second dielectric 117 is provided so as to surround between the signal transmission line 107 and the pair of second GND solid layers (GROUND PLANE) 113.
  • a pair of second signals VIA for transmitting a signal from the pair of second signal transmission lines 107 to the outside thereof is provided therein, and one end of the pair of second signals VIA 108 is connected to the pair of BGAs 105.
  • One end of the pair of third signals VIA 109 that is electrically connected and electrically connected to the pair of second signals VIA 108 is electrically connected to the pair of solder balls 110.
  • a plurality of GND-BGAs 114 having a GND potential arranged around the pair of BGAs 105 are composed of the first GND-BGA, and a high-frequency signal is transmitted between the BGA 105 and the first GND-BGA 114.
  • a first capacitive component is formed when flowing through the electrical transmission line, and a second capacitance is generated between the BGA 105 and the first GND solid layer (GROUND PLANE) 112 when a high-frequency signal is passed through the electrical transmission line.
  • a capacitive component is formed, and a third capacitive component is formed between the BGA 105 and the second GND solid layer (GROUND PLANE) 113 when a high-frequency signal is passed through the electrical transmission path.
  • a plurality of GND-solder balls having a GND potential arranged around the first electrode are composed of a first GND-solder ball 115, and between the solder ball 110 and the second GND solid layer (GROUND PLANE) 113.
  • GROUND PLANE GND solid layer
  • the differential impedance Zline of the first signal transmission line 102 is 100 ⁇
  • the differential impedance Zbga of the BGA 105 is 50 to 70 ⁇
  • the differential impedance Zpkg of the second signal transmission line 107 is The differential impedance Zc of the solder ball 110 is 50 to 70 ⁇ , which is 60 to 80 ⁇ .
  • FIGS. 5A and 5B are diagrams showing a transmission path board configuration according to the second embodiment of the present invention
  • FIG. 5A is a transparent top view of the board configuration
  • FIG. (C) is a circuit block diagram.
  • the first substrate 201 is a backplane substrate constituting a part of the apparatus housing
  • the second substrate 209 is an interface substrate arranged perpendicularly to the backplane substrate. Configured.
  • a first signal transmission line 202 and a first VIA 203 electrically connected to the first signal transmission line 202 are formed on the first substrate 201.
  • the second substrate 209 is formed with a second signal transmission line 210 and a second VIA 207 electrically connected thereto.
  • the connector 205 connecting the first substrate 201 and the second substrate 209 includes a first connector connection pin 204, a connector signal transmission line 206, and a second connector connection pin 208, which are electrically connected. It is connected.
  • the first connector connection pin 204 When the first connector connection pin 204 is fitted to the first VIA 203 and the second connector connection pin 208 is fitted to the second VIA 207, the first signal transmission line 202 and the second signal transmission line are connected. 210 is configured to be electrically connected via the connector signal transmission line 206.
  • the first signal transmission line 202 and the second signal transmission line 210 are differential lines, and each has a pair of first GND solid layers (GROUND PLANE) 211 and the second GND solid layer (GROUND PLANE) 212.
  • the pair of signals VIA 203 is surrounded by a plurality of GND-VIA 213 having a GND potential arranged in the periphery, and a capacitive component is formed between the GND-VIA 213.
  • a capacitive component is also formed in the second VIA 207.
  • the stub 214 of the VIA 207 is an extra wiring, which increases the capacity.
  • the connector signal transmission line 206 formed on the connector 205 is a differential wiring having a wiring length of 20 mm, and has a differential impedance of 92.5 ⁇ .
  • the VIA 203 and 207 having a diameter of about 0.4 mm are arranged at a pitch of 1.35 mm, and the capacity can be estimated from the relationship between the length of the VIA stub 214 and the GND 212. Similar to the solder ball example shown in FIG. 11, the impedance tends to decrease as the operating frequency increases. It also varies depending on the capacitance value. However, since the VIA capacitance is slightly smaller than that of the solder ball of Example 1, the differential impedance of VIA seems to be about 90 ⁇ .
  • the impedance Zcon of the connector signal transmission line 206 is set to a value close to the impedance Zvia of the VIA 203 and 207. Specifically, in order to suppress the influence of the multiple reflection of the connector wiring of the short wiring having a large influence of reflection, the impedance Zvia of the first VIA 203 and the second VIA 207 is set to 80 to 90 ⁇ with respect to the connector signal transmission line 206. The impedance Zcon is set to 85-92.5 ⁇ .
  • FIG. 6 is a TDR characteristic simulation result showing the impedance of this example.
  • the horizontal axis indicates the electrical length of each line appearing in the order of the physical configuration, and the vertical axis indicates the impedance.
  • the impedance Zline of the first signal transmission line 202 and the impedance Zline of the second signal transmission line 210 are about 100 ⁇ differential impedance
  • the impedance Zvia1 of the first VIA 203 is 90 ⁇ differential
  • the impedance Zvia2 of the second VIA 207 is With respect to the differential impedance of 90 ⁇
  • the impedance Zcon of the connector signal transmission line 206 is reduced to the differential impedance of 92.5 ⁇ , and it can be confirmed that the characteristics are as intended.
  • FIG. 6 is a TDR characteristic simulation result showing the impedance of this example.
  • the horizontal axis indicates the electrical length of each line appearing in the order of the physical configuration
  • the vertical axis indicates the impedance.
  • the impedance Zcon of the connector signal transmission line 206 is between the impedance Zline of the first and second signal transmission lines 202 and 210 and the impedance Zvia1 and Zvia2 of the first and second VIA 203 and 207.
  • the jitter reduction effect is the same as that of the first embodiment, and it is effective to reduce Zcon so as to approach Zvia at 14 GHz or higher, and an effect of reducing jitter by ⁇ 10% can be expected.
  • the first substrate 201 having the pair of first signal transmission lines 202 therein, the connector 205 having the pair of connector signal transmission lines 206 therein, A second substrate 209 having a pair of second signal transmission lines 210 therein is included.
  • a pair of first signals VIA 203 for transmitting a signal from the first signal transmission line 202 to the outside thereof is provided therein, and a signal for transmitting the signal from the second signal transmission line 210 to the outside thereof.
  • a pair of second signals VIA 207 are provided therein.
  • the first connection pin 204 and the second connection pin 207 provided on the connector 205 are connected to both ends of the connector signal transmission line 206, respectively.
  • the first substrate 201 includes a first signal transmission line 202, a pair of first GND solid layers (GROUND PLANE) 211 provided so as to sandwich the first signal transmission line 202, and a first And a first dielectric 216 provided so as to surround the pair of first GND solid layers (GROUND PLANE) 211.
  • the second substrate 209 includes a second signal transmission line 210, a pair of second GND solid layers (GROUND PLANE) 212 provided to face each other so as to sandwich the second signal transmission line 210, and a second And a second dielectric 217 provided so as to surround between the pair of second GND solid layers (GROUND PLANE) 212.
  • GROUND PLANE GND solid layers
  • the first VIA 203 is composed of a first main VIA and a first stub
  • the second VIA is composed of a second main VIA 215 and a second stub 214, and the first stub and the first stub.
  • the first capacitive component is formed between the second solid layer (GROUND PLANE) 211 and the second capacitive layer (GROUND PLANE) 211 when a high frequency signal is passed through the electric transmission line.
  • GROUND ⁇ ⁇ ⁇ PLANE a second capacitance component is formed when a high-frequency signal is passed through the electrical transmission path.
  • the transmission rate of the device is 14 Gbps or more
  • the differential impedance Zline of the transmission lines 1 and 2 is 100 ⁇
  • the differential impedance Zvia of VIA1 and 2 is 80 to 90 ⁇
  • the differential impedance Zcon of the connector is 85 It is characterized by being 92.5 ⁇ .
  • the arrangement of the connection pins and the VIA may be exchanged in the above configuration.
  • FIG. 7A and 7B are diagrams showing a device configuration according to the third embodiment of the present invention.
  • FIG. 7A is a transparent top view of the device configuration
  • FIG. 7B is a sectional view of the device configuration (cross section AB)
  • FIG. ) Is a circuit block diagram.
  • the operating frequency region is assumed to be the same as in FIG. While FIG. 1 constitutes a differential line, this embodiment is constituted by a single line.
  • the BGA 305 connected to the first signal transmission line 302 formed on the substrate 301 via the first VIA 303, and the second signal transmission formed on the BGA 305 and the semiconductor PKG 306.
  • the line 307 is connected via the second VIA 308, the solder ball 310 is connected via the third VIA 309, and the solder ball 310 is connected to the semiconductor integrated circuit device 311.
  • the first signal transmission line 302 and the second signal transmission line 307 are single lines, each of which is a pair of first GND solid layers (GROUND PLANE). ) 312 and the second GND solid layer (GROUNDLANPLANE) 313 are provided to face each other.
  • the single signal BGA 305 is surrounded by a plurality of GND-BGAs 314 having a GND potential arranged in the periphery, and a capacitance component is formed between the GND-BGAs 314. Further, a capacitive component is formed between the signal BGA 305 and the first GND solid layer (GROUND PLANE) 312 and the second GND solid layer (GROUND PLANE) 313.
  • the single signal solder ball 310 is surrounded by a plurality of GND-solder balls 315 having a GND potential arranged in the periphery, and a capacitance component is formed between the GND-solder balls 315. Further, a capacitance component is formed between the signal solder ball 310 and the second GND solid layer (GROUND PLANE) 313.
  • GROUND PLANE GROUND PLANE
  • FIG. 8 is a diagram showing a cross-sectional configuration of the PKG upper surface of the transmission line substrate according to the first embodiment of the present invention
  • FIG. 8A is a top view of the substrate configuration (PKG cross section)
  • FIG. 8B is a side view of the substrate configuration.
  • C is a block diagram.
  • GND solid layer (GROUND PLANE) 313 in FIG. 5A the portion overlapping the signal BGA 305 on the plan view is hollowed out in a circular shape so that no extra capacity is added.
  • the first signal transmission line 302 formed on the substrate 301 is a single line having a length of about 100 mm.
  • the wiring space is 0.1 mm, and the wiring thickness is 0.013 mm.
  • the second signal transmission line 307 formed in the semiconductor PKG 306 is a single wiring having a wiring length of 3 to 7 mm.
  • the wiring specifications of characteristic impedance 50 ⁇ are shown for reference.
  • the wiring width is 0.023 mm, the wiring space is 0.70 mm, and the wiring thickness is 0.015 mm. That is, to reduce the wiring impedance, it is possible to cope with it by widening the wiring width.
  • BGA305 with a diameter of about 0.6 mm is arranged at a pitch of 1 mm, and it is estimated that the capacity is 200 to 250 fF from the relationship between the BGA size and the distance between GND316.
  • the solder balls 310 having a diameter of about 0.1 mm are arranged at a pitch of 0.2 mm, and the capacity is estimated to be 50 to 100 fF from the relationship between the solder ball size and the GND 315. Similar to the example of the differential impedance of the solder ball of the first embodiment shown in FIG. 11, the impedance tends to decrease as the operating frequency increases. It also varies depending on the capacitance value. By analogizing the characteristic impedance of the BGA 305 and the solder ball 310 from FIG. 11, it can be estimated to be 1/2 of the differential impedance, and the 14 GHz operation and the capacity from 50 to 250 fF to 25 to 35 ⁇ .
  • the receiving end configuration of the semiconductor integrated circuit 311 is a single 50 ⁇ , and an electrostatic protection capacitor of about 250 fF is added to prevent electrostatic breakdown of the internal circuit.
  • the impedance Zpkg of the second signal transmission line 307 is set to a value close to the impedances Zbga and Zc of the BGA 305 and the solder ball 310.
  • the second signal transmission line of the package with respect to the characteristic impedances Zbga and Zc of the BGA 305 and the solder ball 310 of 25 to 35 ⁇ .
  • the characteristic impedance Zpkg of 307 is set to 30 to 40 ⁇ .
  • the ratio of impedance mismatch between the solder balls 310 can be reduced and reflection can be reduced, there is an effect of improving the jitter characteristics.
  • the substrate 301 having the first signal transmission line 302 therein and the semiconductor integrated circuit device 311 are mounted therein, and on one surface thereof.
  • a solder ball 310 provided on the semiconductor PKG 306 is electrically connected to an internal signal circuit of the semiconductor integrated circuit device 311.
  • the substrate 301 includes one first signal transmission line 302, a pair of first GND solid layers (GROUND PLANE) 312 provided to face each other so as to sandwich the first signal transmission line 302, and one The first signal transmission line 302 and a first dielectric 304 provided so as to surround the pair of first GND solid layers (GROUND PLANE) 312 are provided.
  • GROUND PLANE first GND solid layers
  • a first signal VIA 303 for transmitting a signal from one first signal transmission line 302 and a pair of first GND solid layers (GROUND PLANE) 312 to the outside thereof is provided therein.
  • One end of the first signal VIA 303 is electrically connected to the BGA 305, and the semiconductor PKG 306 is paired with a second signal transmission line 307 and a pair of signals provided so as to sandwich the second signal transmission line 307.
  • a second signal VIA 308 is provided in the second signal transmission line 307 for transmitting a signal from the second signal transmission line 307 to the outside thereof.
  • One end of the pair of second signals VIA 308 is electrically connected to the BGA 305, and one end of the third signal VIA 309 electrically connected to the second signal VIA 308 is electrically connected to the solder ball 310.
  • a plurality of GND-BGAs arranged at the periphery of the BGA 305 and having a GND potential are composed of the first GND-BGA 314. Between the BGA 305 and the first GND-BGA 314, a high-frequency signal is used as an electric transmission path. A first capacitive component is formed when flowed.
  • a second capacitive component is formed between the BGA 305 and the first GND solid layer (GROUND PLANE) 312 when a high-frequency signal is passed through the electric transmission line, and the BGA305 and the second GND solid layer (GROUND PLANE) 312. ) 313, a third capacitance component is formed when a high-frequency signal is passed through the electrical transmission line.
  • a plurality of GND-solder balls having the GND potential arranged around the pair of solder balls 310 are composed of the first GND-solder balls 315, and the solder balls 310 and the second GND solid layer (GROUND PLANE).
  • a fourth capacitive component is formed between the solder ball 310 and the first GND solder ball 315 when a high frequency signal is passed through the electrical transmission path.
  • a fifth capacitive component is formed when flowing through
  • the transmission rate of the device is 14 Gbps or more
  • the impedance Zline of the first signal transmission line 302 is 50 ⁇
  • the impedance Zbga of the BGA is 25 to 35 ⁇
  • the impedance Zpkg of the second signal transmission line is 30 to 30 ⁇ .
  • the impedance is 40 ⁇
  • the impedance Zc of the solder ball is 25 to 35 ⁇ .
  • FIG. 9 is a diagram showing a transmission path board configuration according to the third embodiment of the present invention
  • FIG. 9A is a configuration diagram
  • FIG. 9B is a block diagram.
  • the single impedance configuration is different from the third embodiment in that a DC cut capacitor 421 is disposed between the first signal transmission line 402a and the BGA 405. Even if the DC cut capacitor 421 is disposed between them, the impedance Zline remains unchanged at 50 ⁇ , and the same operation and effect as in the third embodiment can be obtained.
  • a GND solid layer (GROUND PLANE) sandwiching the signal line transmission line is omitted in the configuration diagram of FIG. It is formed.
  • a differential impedance configuration may be used, and the same effect can be obtained.
  • FIG. 10 is a diagram showing a transmission path board configuration according to the fifth embodiment of the present invention
  • FIG. 10 (a) is a configuration diagram
  • FIG. 10 (b) is a block diagram.
  • the single impedance configuration is different from the third embodiment in that the first transmission path board 509a and the second transmission path board 509b are connected to both ends of the backplane board 501 via connectors 505a and 505b. .
  • the first signal transmission line 502 formed on the substrate 501 has a first VIA 503a at the first end and a second VIA 503b at the second end.
  • the first connector connection pin 504a of the connector 505a is connected to the first VIA 503a.
  • One end of a second signal transmission line 506a formed on the connector 505a is connected to the first connector connection pin 504a.
  • a second connector connection pin 506a is connected to the other end of the second signal transmission line 506a.
  • the second signal transmission line 506a is connected to the third signal transmission line 510a of the first transmission line substrate 509a via the second connection pin 506a and the second VIA 507a formed on the first substrate 509a.
  • the third signal line 510a is connected to the BGA 512a via a third VIA 511a connected thereto. Further, the BGA 512a is connected to the solder ball 515a via the fourth VIA 513a and the fourth signal transmission line 514a.
  • the solder ball 515a is connected to the semiconductor integrated circuit device 516a, and the second end of the first signal line 502 is connected in the same manner as the first end.
  • the second substrate 509b side has the same configuration.
  • the first substrate 509a in FIG. 10 corresponds to the substrate 301 in FIG. 7
  • the PKG 500a corresponds to the PKG 306
  • the semiconductor integrated circuit device 516a is a semiconductor integrated circuit.
  • this part can have the same configuration.
  • the impedance Zline of the signal transmission lines 502, 510a, and 510b is 50 ⁇ , and the same operation as in the third embodiment and further effects can be obtained. Since there are two effects of reducing Zpkg and Zcon, respectively, a reflection reduction effect of about four times that of Example 3 can be obtained.
  • the GND solid layer (GROUND PLANE) sandwiching the signal line transmission line is omitted in the configuration diagram of FIG. 10A, a capacitive component is formed between the VIA stub and GND as in the second embodiment. .
  • a capacitive component is formed between the BGA or solder ball and GND.
  • the fifth embodiment has a single impedance configuration, a differential impedance configuration as shown in FIG. 1 may be used, and similar effects can be obtained.
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
  • the present invention can be used in various device fields for transmitting electrical signals, such as communication devices and information processing devices.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente invention aborde le problème de réduction de réflexion entre des fils pendant un fonctionnement à grande vitesse. La présente invention porte sur un appareil de transmission de signal électrique comprenant : une première carte de circuits imprimés qui comprend un premier trajet d'émission de signal ; une seconde carte de circuits imprimés qui est montée sur la première carte de circuits imprimés et qui comprend un second trajet d'émission de signal ; et un dispositif de circuit intégré à semi-conducteurs qui est monté sur la seconde carte de circuits imprimés, vers/depuis laquelle un signal électrique ayant une vitesse d'émission de 14 Gbps ou plus est mise en entrée/délivrée en sortie, et qui comprend un trajet de signal interne. Ici, sont comprises un premier élément de connexion qui est disposé entre la première carte de circuits imprimés et la seconde carte de circuits imprimés, et qui connecte le premier trajet de signal et le second trajet de signal ; et un second élément de connexion qui est disposé entre la seconde carte de circuits imprimés et le dispositif de circuit intégré à semi-conducteurs, et qui connecte le second trajet de signal et le trajet de signal interne. Dans cet appareil, lorsque le dispositif de circuit intégré à semi-conducteurs est en fonctionnement, dans une bande de fréquence d'un signal émis à travers les premier et second trajets de signal, l'impédance du second trajet d'émission de signal est inférieure, selon au moins 20 %, à l'impédance du premier trajet d'émission de signal, et l'impédance du second trajet d'émission de signal correspond à l'impédance des premier ou second éléments de connexion à l'intérieur d'une plage de ± 35 %.
PCT/JP2015/063142 2015-05-01 2015-05-01 Appareil d'émission de signal électrique WO2016178281A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI640230B (zh) * 2017-05-16 2018-11-01 中華精測科技股份有限公司 高速傳輸結構的負載板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006128633A (ja) * 2004-09-28 2006-05-18 Canon Inc 多端子素子及びプリント配線板
WO2012133781A1 (fr) * 2011-03-30 2012-10-04 日本電気株式会社 Procédé et système de transmission pour élaborer un système de fond de panier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006128633A (ja) * 2004-09-28 2006-05-18 Canon Inc 多端子素子及びプリント配線板
WO2012133781A1 (fr) * 2011-03-30 2012-10-04 日本電気株式会社 Procédé et système de transmission pour élaborer un système de fond de panier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI640230B (zh) * 2017-05-16 2018-11-01 中華精測科技股份有限公司 高速傳輸結構的負載板

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