WO2016177170A1 - 一种光电传感器和显示面板 - Google Patents

一种光电传感器和显示面板 Download PDF

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Publication number
WO2016177170A1
WO2016177170A1 PCT/CN2016/077261 CN2016077261W WO2016177170A1 WO 2016177170 A1 WO2016177170 A1 WO 2016177170A1 CN 2016077261 W CN2016077261 W CN 2016077261W WO 2016177170 A1 WO2016177170 A1 WO 2016177170A1
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WIPO (PCT)
Prior art keywords
transistor
voltage
pole
control
signal
Prior art date
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PCT/CN2016/077261
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English (en)
French (fr)
Inventor
张盛东
廖聪维
胡治晋
曹世杰
李君梅
李文杰
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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Priority to US15/572,317 priority Critical patent/US10089917B2/en
Publication of WO2016177170A1 publication Critical patent/WO2016177170A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/0102—Constructional details, not otherwise provided for in this subclass
    • G02F1/0105—Illuminating devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/041—Manufacture or treatment of thin-film BJTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/144—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light being ambient light

Definitions

  • the present application relates to the field of electronic circuits, and in particular to a photoelectric sensor.
  • TFT Thin Film Transistor
  • the display panel of the SoP has the following advantages: First, the number of peripheral driving chips of the display panel is small, and thus the number of pins and the number of connecting lines of the chip are correspondingly small; Second, the frame of the display panel is narrow. Therefore, the module of the related display panel is beautiful and compact; third, the module process of the display panel is relatively simple, and the manufacturing cost is reduced; fourth, the resolution of the display panel is high; and the display panel has high reliability, thereby making it easier to manufacture. Flexible display panel; Six, SoP's display panel is easier to integrate touch, temperature and photoelectric sensing devices, so the display panel has higher added value.
  • the present application provides a photoelectric sensor comprising:
  • a signal output port for outputting a pulse signal
  • the pulse transfer unit includes a control end, and after the control end of the pulse transfer unit obtains the driving voltage, the first clock signal is transmitted to the signal output port;
  • a pulse control unit configured to receive an input scan signal from a signal input port, and charge a control end of the pulse transfer unit to provide the drive voltage
  • the photoelectric sensing unit is configured to provide a leakage current in response to external light intensity when receiving external illumination, and the leakage current is discharged to the control end of the pulse transmission unit so that the voltage of the control terminal of the pulse transmission unit is less than the driving voltage after a period of time.
  • a display panel of the present application includes the above-described photosensor.
  • the pulse transmission unit, the pulse control unit and the photoelectric sensing unit utilize the scanning signal and the clock signal which are provided by the conventional display panel, no additional control signal is required, so the circuit structure is simple and the process is realized. Less difficult.
  • FIG. 1 is a schematic structural view of a photoelectric sensor according to Embodiment 1 of the present application.
  • FIG. 3 is a schematic structural view of a photoelectric sensor according to Embodiment 2 of the present application.
  • FIG. 4 is a schematic circuit diagram of a photoelectric sensor according to Embodiment 3 of the present application.
  • FIG. 5 is another schematic circuit diagram of a photoelectric sensor according to Embodiment 3 of the present application.
  • FIG. 6 is a timing chart of operation of a photoelectric sensor according to Embodiment 3 of the present application.
  • FIG. 7 is a schematic structural view of a photoelectric sensor according to Embodiment 4 of the present application.
  • FIG. 9 is a test response curve of a photoelectric sensor in a plurality of line scanning time and one frame time in a bright state according to Embodiment 4 of the present application.
  • the transistor in the present application is a three-terminal transistor, the three terminals of which are the control pole, the first pole and the second pole respectively; when the transistor is a bipolar transistor, the control pole refers to the base of the bipolar transistor, the first The pole refers to the collector or emitter of a bipolar transistor, and the corresponding second pole refers to the emitter or collector of a bipolar transistor; when the transistor is a field effect transistor, the gate refers to the gate of the field effect transistor.
  • the first pole refers to the drain or source of the field effect transistor, and the corresponding second pole refers to the source or drain of the field effect transistor.
  • the transistor in the present application may be a bipolar transistor or a field effect transistor.
  • the inventors use a thin film transistor (TFT: Thin Film Transistor) in a field effect transistor to implement the photovoltaic of the present application.
  • TFT Thin Film Transistor
  • TFT Thin Film Transistor
  • the electrical characteristics of a thin film transistor (TFT: Thin Film Transistor) in a field effect transistor may undergo a significant change under the action of external light. For example, after the thin film transistor is applied with light, the threshold voltage is decreased and the off-state current is increased by an order of magnitude compared to the thin film transistor in the dark state.
  • the inventors used a thin film transistor to fabricate a photosensor, and since the photosensor is made of a thin film transistor, it is very easy to be integrated into a main circuit element which is also made up of a thin film transistor. SoP's display panel.
  • the following may be a transistor as an N-type thin film transistor as an example of the photoelectric sensor of the present application.
  • the display panel will be described.
  • the control electrode of the transistor at this time refers to the gate
  • the first pole refers to the drain
  • the second pole refers to the source.
  • the embodiment discloses a photoelectric sensor including a pulse transfer unit 2, a pulse control unit 1, and a photoelectric sensing unit 3.
  • the pulse transfer unit 2 is connected between the first clock signal V A input terminal and the signal output port, and includes a control terminal Q. After the control terminal Q of the pulse transfer unit 2 obtains the driving voltage, the first clock signal V A is transmitted to the signal output. port.
  • the pulse transfer unit 2 has various implementations.
  • the pulse transfer unit 2 may include a transistor T2, which may be a non-photosensitive transistor. Specifically, the transistor T2 is in a light-shielded state to make the transistor T2 A non-photosensitive transistor.
  • the transistor T2 is controlled to be the control terminal Q of the pulse transfer unit 2, the first pole of the transistor T2 is used to input the first clock signal V A , and the second pole of the transistor T2 is connected to the signal output port for being driven at the transistor T2. when turned on, when the high-level first clock signal V a charging port of arrival output signal, a low level when the first clock signal V a to the signal output port soon discharged.
  • a storage capacitor C1 can be connected between the control electrode and the second electrode of the transistor T2 for storing the charge of the control terminal Q, so that the control electrode of the transistor T2 can obtain a more stable driving. Voltage.
  • the pulse control unit 1 is connected between the signal input port and the control terminal Q of the pulse transfer unit 1 for receiving the input scan signal Vscan from the signal input port, and charging the control terminal Q of the pulse transfer unit 1 to provide the above drive.
  • the voltage refers to the voltage at which transistor T2 can be turned on to turn on the first and second poles of transistor T2.
  • the pulse control unit 1 also has various implementations.
  • the pulse control unit 1 can include a transistor T7, which is a non-photosensitive transistor.
  • the first pole of the transistor T7 is connected to the control electrode; the first pole of the transistor T7 is also connected to the signal input port for inputting the scan signal Vscan , and the second pole of the transistor T7 is connected to the control terminal Q of the pulse transfer unit 2,
  • the control terminal Q of the pulse transfer unit 2 is charged to supply the above-described drive voltage when the high-level power of the scan signal V scan comes.
  • the photoelectric sensing unit 3 is connected between the low potential and the control terminal Q of the pulse transfer unit 2 for providing a leakage current in response to external light intensity when receiving external light, and the leakage current is discharged to the control terminal Q of the pulse transfer unit 2
  • the voltage of the control terminal Q of the pulse transfer unit 2 is less than the drive voltage for turning on the transistor T2 after a period of time.
  • the photoelectric sensing unit 3 can have various implementations.
  • the photoelectric sensing unit 3 can include a transistor T8, which is a photosensitive transistor, and specifically, can be set by setting the transistor T8 to a photosensitive state. Transistor T8 becomes a phototransistor.
  • the first pole of the transistor T8 is connected to the control electrode; the first pole of the transistor T8 is also connected to the low level source V L , and the second pole of the transistor T8 is connected to the control terminal Q of the pulse transfer unit 2; since the transistor T8 is a photosensitive The transistor, so the transistor T8 has a leakage current in response to external illumination, so the transistor T8 is used to provide a leakage current in response to external light intensity when receiving external light; this leakage current flows from the second pole of the transistor T8 to the first pole.
  • the control terminal Q for discharging the pulse transfer unit 2 causes the voltage of the control terminal Q of the pulse transfer unit 2 to be smaller than the above-described drive voltage.
  • FIG. 2 is a timing chart of operation of the above photoelectric sensor, and the working process of the above photoelectric sensor will be described in stages with reference to FIG. 1 and FIG.
  • the above photoelectric sensor operates in two phases: a voltage preset phase and a light sensing phase.
  • Fig. 2(a) is a timing chart of the operation of the photosensor in a limited length of time of one line scan, and one line scan time is a half period of the first clock signal V A in the figure.
  • Fig. 2(b) is a timing chart showing the operation of the output signal terminal of the photosensor and the internal control terminal Q in one frame time.
  • the voltage preset phase refers to uniformly setting the voltage of the circuit node inside the photosensor, that is, the control terminal Q, to a high level before or before the photosensor receives the high level of the scan signal V scan .
  • the voltage of the control terminal Q is set to a high level V H1 before or after the high level of the scan signal V scan arrives to avoid mutual interference of the front and rear frame states, that is, the photoelectric sensor regardless of the previous frame how the voltage state of each node on the circuit during operation, run time in the next frame, the photoelectric sensor is checked before the scan signal V scan (i.e., V scan is high), or when selected, the internal circuit node is pre photosensor i.e.
  • the voltage of the control terminal Q is uniformly set to a high level V H1 , thus effectively preventing mutual interference of the preceding and succeeding frame states.
  • the voltage V Q of the control terminal Q is temporarily set to a high level V H1 in advance of the high voltage of the scan signal V scan of the frame, in a preferred embodiment.
  • the high level V H1 can be set to be sufficient to turn on the transistor T2.
  • the transistor T7 Since the scan signal V scan is at the high level V H in the (1) phase, the transistor T7 is turned on, and the scan signal V scan charges the control terminal Q, so that the voltage V Q of the control terminal Q rises, thereby turning on the transistor T2.
  • the first clock signal V A is at a high level, so the voltage V o of the signal output port is charged to a high level, which in turn causes the voltage V Q of the control terminal Q to further rise to V H2 due to the bootstrap.
  • the first clock signal V A As shown in the stage (2); in the (3) phase, the first clock signal V A is at a low level, so the voltage V o of the signal output port is discharged to a low level.
  • the scan signal V scan input to the scan line connected to one photosensor is at a high level in the (1) phase, and the other time is a low level.
  • transistor T2 When the transistor T2 is turned on, due to the V Scan becomes low level, so transistor T7 is turned off, control terminal Q does not leak through transistor T7, and photosensitive transistor T8, although there is a leakage current in response to light intensity, this current is connected to the charge amount at Q point. It is too small to significantly affect the charge number and voltage value of the Q point during the scan time of several lines. Therefore, during the scan time of the finite line, the transistor T2 remains open, and the first clock signal V A follows. When the high and low levels arrive, the signal output terminal is continuously charged and discharged, that is, the phases (2) and (3) in Fig. 2(a) are repeated.
  • the photo-sensing phase is that the photosensor receives illumination for a relatively long period of time relative to the line scan time, and the photosensor outputs different voltages V o depending on the illumination intensity.
  • the photoelectric sensing unit 3 discharges the charge of the control terminal Q by using a leakage current in response to the external light intensity for a period of time, that is, discharging the control terminal Q so that the voltage V Q of the control terminal Q is smaller than the driving voltage, thereby
  • the pulse transfer unit 2 is turned off, causing a process in which the voltage V o of the output signal terminal changes.
  • the transistor T2 is turned on during the voltage preset phase, so when the first clock signal V A is at a high level, the output port Vo will also be pulled up to a high level, as in 2(a) ( 2)
  • the stage shows; while the first clock signal V A is low, the output port V o will also be pulled low, as shown in stage (3) of 2(a). Therefore, in the following time, as the clock signal V A periodically changes to high and low levels, the voltage on the output port V o also periodically changes to high and low levels.
  • t1 is defined as the time when the pulse waveform appears on the output V o of the light sensing phase, that is, the time when the high level of V o is attenuated to a low level, as the light intensity is larger as described above, the shorter the t1 is, the weaker the light intensity is. The longer t1 is, therefore, through the photoelectric sensor of the present application, we establish the relationship between the illumination intensity and t1, and measure the time at which the pulse waveform appears on the output V o in the light sensing phase, that is, the high level of V o decays to low power. At the flat time t1, the light intensity is calibrated.
  • the photoelectric sensor, the pulse control unit 1 and the photoelectric sensing unit 3 are realized by different units.
  • the pulse control unit 1 and the photoelectric sensing unit 3 are respectively composed of a transistor T7 and a transistor. T8 is realized, and the advantage of this is that the two functions of voltage preset and light intensity induction, that is, supplying the driving voltage to the pulse transmitting unit 2 and discharging the charge of the control terminal Q of the pulse transmitting unit 2, There are different requirements for the size of the transistor, etc.
  • the pulse control unit 1 and the photo-sensing unit 3 are different units, it is convenient to separately optimize the design transistor T7 and the transistor T8 to achieve the best effect of the respective implemented functions.
  • the pulse control unit 1 and the photoelectric sensing unit 3 may be the same unit 13, and the unit 13 may implement the functions of the pulse control unit 1 and the photoelectric sensing unit 3.
  • the unit 13 includes a transistor T78, and the transistor T78 is a phototransistor; the first pole of the transistor T78 is connected to the control electrode; the first pole of the transistor T78 is also connected to the signal input port for inputting the scan signal V.
  • a second transistor T78 is connected to the control terminal of the pulse transmission unit Q 2; and a transistor T78, a control unit for transmitting the pulse to the end of charge Q 2 to provide a drive voltage when the scan signal V scan Kopin electrical arrival; and Providing a leakage current in response to external light intensity when receiving external illumination, the leakage current flowing from the second pole of the transistor T78 to the first pole for discharging the control terminal Q of the pulse transfer unit 2 to the voltage of the control terminal of the pulse transfer unit Less than the above driving voltage.
  • the working principle and the working timing chart of the photoelectric sensor of this embodiment are similar to those of the photoelectric sensor of the first embodiment, and will not be described herein.
  • the photosensor disclosed in the embodiment further includes a low level maintaining unit 4 for the second clock on the basis of the first or second embodiment.
  • the voltage V o of the signal output port is maintained at a low level, wherein the second clock signal V B has the same period and opposite phase as the first clock signal V A .
  • the low level sustaining unit 4 includes a transistor T3, and the transistor T3 is a non-photosensitive transistor; the gate of the transistor T3 is used to input the second clock signal V B The first pole of the transistor T3 is connected to the signal output port V o , and the second pole of the transistor T3 is connected to the low level source V L for outputting the signal to the port when the high level of the second clock signal V B comes The voltage V o is pulled down to the voltage of the low level source V L to maintain the voltage V o of the signal output port at a low level.
  • FIG. 5 is a preferred embodiment based on the second embodiment, and the low level maintaining unit 4 is the same as that in FIG. 4, and details are not described herein again.
  • FIG. 6 is a timing chart of operation of the photoelectric sensor of the third embodiment.
  • the second clock signal V B has the same period and opposite phase as the first clock signal V A , when the pulse transfer unit 2 is turned on, the first clock signal V A is given high.
  • the second clock signal V B is at a low level, the transistor T3 is in a off state, and the low level source V L does not give a signal to the first clock signal V A .
  • the output port is affected by charging; when the first clock signal V A is given a low level to discharge the signal output port to make V o low level, the second clock signal V B is at a high level, and the transistor T3 is in an on state, so the transistor Both T2 and transistor T3 pull the voltage V o at the signal output to a low level.
  • the voltages of the control terminal Q and the signal output terminal on the circuit of the photosensor should be kept at a low level, but due to the voltage feedthrough effect, etc., there is no control terminal Q and signal output terminal. Some noise voltage can be avoided.
  • the pulse transfer unit 2 there is an overlap region between the control electrode of the transistor T2 and the first pole, between the control electrode and the second pole, which inevitably brings about the control pole of the transistor T2.
  • Parasitic capacitances C GD and C GS (not shown), wherein the parasitic capacitance C GD refers to the parasitic capacitance between the control electrode and the first electrode of the transistor T2, and the parasitic capacitance C GS refers to the control electrode of the transistor T2 and the Parasitic capacitance between the two poles.
  • the presence of the parasitic capacitance C GD causes V Q and V o to also jump when the first clock signal V A transitions between high and low levels. This will cause interference in determining the time at which the high level of V o decays to a low level, which in turn affects the calibration of the illumination intensity.
  • the photosensor needs to enter a low level sustaining phase, and the transistor T3 is turned on under the control of the second clock signal V B , thereby causing possible noise of the signal output port. The charge is released. Since the second clock signal V B is also a periodic signal, the transistor T2 can be periodically turned on, which enables the charge of the signal output port to not accumulate, thereby maintaining the voltage of the signal output port at a low level.
  • the low level sustaining unit 4 can reduce the noise voltage on the signal output port, the voltage V Q of the control terminal Q may still be disturbed by the voltage feedthrough effect.
  • the noise voltage value on the control terminal Q may exceed the threshold voltage of the transistor T2, thereby turning on the transistor T2 by mistake.
  • a feedthrough voltage transistor T2 is turned on by mistake, it will give a signal voltage V o output port to bring a large noise amplitude voltage, this time to maintain a low level of 4 V o means the ability to maintain low limited.
  • the present embodiment contemplates introducing a module that suppresses the voltage feedthrough effect.
  • This embodiment can be implemented on the basis of any of the implementations one to three.
  • the following is an example of the basis of the third embodiment.
  • the present embodiment further includes a voltage feedthrough suppression unit 5 for controlling the first clock signal V A according to the photosensor shown in FIG. 5 in the third embodiment.
  • the voltage at the signal output port and the pulsed control terminal is maintained at a low level.
  • the voltage feedthrough suppression unit 5 includes a transistor T4, a transistor T5, a transistor T6, and a coupling capacitor C2, and the transistor T4, the transistor T5, and the transistor T6 are non-photosensitive transistors.
  • the control electrode of the transistor T4, the first pole of the transistor T5, the control electrode of the transistor T6, and one end of the coupling capacitor C2 are all connected to the same node P, and the other end of the coupling capacitor C2 is connected to the port that outputs the first clock signal V A
  • the second pole of the transistor T4, the control pole of the transistor T5, and the first pole of the transistor T6 are all connected to the signal output port; the first pole of the transistor T4 is connected to the control terminal Q of the pulse transfer unit 2; the transistor T5, the transistor T6 The second pole is connected to the low level source V L .
  • the transistor T5 is configured to pull down the voltages of the control electrodes of the transistor T4 and the transistor T6 to the voltage of the low-level source V L when the voltage V o of the signal output port is high level, thereby turning off the transistor T4 and the transistor T6 to prevent The signal output port and the control terminal Q of the pulse transfer unit 2 are leaked; the coupling capacitor C2 is used when the voltage V Q of the control terminal Q of the pulse transfer unit 2 is less than the drive voltage, when the high level of the first clock signal V A comes When this high level is coupled to the control electrode of the transistor T4 and the transistor T6, the transistor T4 and the transistor T6 are turned on to pull the signal output port and the voltage V Q of the control terminal Q of the pulse transfer unit 2 to the low level source V.
  • the voltage of L is configured to pull down the voltages of the control electrodes of the transistor T4 and the transistor T6 to the voltage of the low-level source V L when the voltage V o of the signal output port is high level, thereby turning off the transistor T4
  • the voltage of the node P is raised to a higher level, so the transistor T4 and the transistor T6 When turned on, the voltage V Q of the control terminal Q and the voltage of the signal output port are both pulled down to the level of the low level source V L .
  • the voltage of the node P depends on the ratio of the coupling capacitor C2 and other capacitors on the node P. When the value of the coupling capacitor C2 is designed to be large, the voltage of the node P can be adjusted to be large, thereby turning the transistor. T4 and transistor T6 are turned on.
  • the transistor T5 In the voltage preset phase and the light sensing phase, when the voltage V o of the signal output port is high, since the control electrode of the transistor T5 is connected to the signal output port, the transistor T5 is turned on, thereby pulling down the voltage of the node P to low power. Flat voltage. Since the control electrodes of the transistor T4 and the transistor T6 are both connected to the node P, the transistor T4 and the transistor T6 are turned off, thereby suppressing the voltage preset phase and the light sensing phase, and the photosensor needs to output a high level, the control terminal Q and the signal output port. Leakage of charge.
  • the voltage feedthrough suppression unit 5 can maintain the voltage V Q of the control terminal Q and the voltage of the signal output port at a low level in the low level sustaining phase, and can enable the signal output port in the voltage preset phase and the light sensing phase. It is correctly charged, and at the same time, mutual interference between the light sensing phase and the low level sustaining phase can be avoided, and the reliability of the photoelectric sensor is improved.
  • Figure 8(a) shows the test response curve of the photoelectric sensor in several rows during the dark state
  • Figure 8(b) shows the test response curve of the photosensor in the dark state for the next frame time, where V scan [ N-1] and V scan [n] are two adjacent scan signals, V A is the first clock signal, and V o is the output signal of the photosensor.
  • V scan [ N-1] and V scan [n] are two adjacent scan signals
  • V A is the first clock signal
  • V o is the output signal of the photosensor.
  • V o periodically outputs a pulse signal (i.e., a high level).
  • a pulse signal i.e., a high level.
  • the output pulse amplitude of V o starts to decay after 5 ms. In the dark state, the pulse duration on the signal output port is 6ms or longer.
  • Figure 9(a) shows the test response curve of the photoelectric sensor in several rows of scanning time in the bright state
  • Figure 9(b) shows the next frame time of the photosensor in the bright state.
  • Test response curve inside From the perspective of several times of line scan time, the periodic pulse output signal on the signal output port is not significantly different in the dark state and the bright state. However, from a frame time, in the bright state, the amplitude of the high level begins to decay after the signal output port output pulse signal V o is 1 ms. In the bright state, the pulse duration on the signal output port is approximately 1.5 ms. Therefore, it can be seen that the difference in illumination conditions has a significant effect on the output V o of the photosensor. In further optimizing the structure and size of the design transistor T78, as well as optimizing the dimensions of other components on the circuitry of the photosensor, the sensitivity of the photosensor of the present application to light intensity is further enhanced.
  • the above is a preferred embodiment of the photosensor of the present application.
  • the present application utilizes a transistor, such as a thin film transistor (TFT), to change its electrical characteristics under the action of external light, and designs a photoelectric sensor that utilizes the display panel reasonably.
  • the upper scanning signal and the clock signal are controlled, so that the circuit structure is simple, and it is not necessary to introduce a complicated control signal like a conventional photoelectric sensor.
  • the photosensor of the present application makes reasonable use of the scanning signal and the clock signal on the display panel, it is also particularly suitable for integration in display panels, especially TFT display panels, and some flexible electronic applications. Therefore, the present application also proposes a display panel comprising the photosensors of the above embodiments, which not only has a high added value, but also the complexity of the mechanical structure and circuit of the display panel is hardly increased.
  • this photoelectric sensor can be easily integrated into the display panel, but it can also be integrated into other fields for detecting light intensity or detecting other indicators by detecting light intensity. At this time, there may be no ready-made scanning. Signal, that only needs to use the existing control signals in other fields or add another control signal.

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Abstract

一种光电传感器和显示面板，包括：脉冲传递单元(2)，包括控制端(Q)，所述脉冲传递单元(2)的控制端(Q)获得驱动电压后，将第一时钟信号(V A)传送至信号输出端口；脉冲控制单元(1)，用于从信号输入端口接收输入的扫描信号(V SCAN)，给所述脉冲传递单元(2)的控制端(Q)充电以提供所述驱动电压；光电感应单元(3)，用于接收外界光照时提供一个响应外界光照强度的泄漏电流，所述泄漏电流给脉冲传递单元(2)的控制端(Q)放电使脉冲传递单元(2)的控制端(Q)的电压经过一段时间后小于所述驱动电压。光电传感器电路利用常规显示面板已有的扫描信号(V SCAN)和时钟信号(V A)，而不需要额外引入控制信号，因此电路结构简单，更适合于集成在显示面板上。

Description

一种光电传感器和显示面板 技术领域
本申请涉及电子电路领域，具体为一种光电传感器。
背景技术
基于薄膜晶体管(TFT：Thin Film Transistor)阵列的平板显示技术是当今显示技术的主流，这主要是因为TFT的加工工艺相对简单，工艺成本低廉，适合于大面积生产。随着TFT平板显示技术的发展，越来越多的显示驱动及其它功能模块可能采用TFT集成电路实现。将行列驱动电路、电源电路、光电传感电路等以TFT为主要元件制作从而集成于显示面板上，能够形成屏上系统集成(SoP：System on Panel)。相比于常规面板，SoP的显示面板具有以下一些优势：一、显示面板的周边驱动芯片数量较少，因而芯片的引脚以及连接线数量也相应的较少；二、显示面板的边框窄，从而相关的显示面板的模组显得美观和紧凑；三、显示面板的模组工序较简洁，制作成本降低；四、显示面板的分辨率高；五、显示面板可靠性高，从而更容易制成柔性的显示面板；六、SoP的显示面板上更容易集成触控、温度和光电传感等器件，于是显示面板具有更高的附加价值。
在传统的显示面板上，光电传感器多以分立地放置。这种分立式的光电传感器使得SoP显示面板的边框较宽，使SoP的显示面板的优势发挥不出来。虽然日韩等研究者报道了一些采用TFT技术实现的光电传感器，但是这些方案的实现一般独立于显示面板，需要引入额外的控制信号，于是可行性较低。因此，如何在TFT阵列内部或者边缘实现光电传感功能，并且合理地利用TFT阵列中的资源，而不显著地增加显示面板的复杂度是TFT集成光电传感器实现的关键。
发明内容
根据本申请的第一方面，本申请提供一光电传感器，包括：
信号输入端口，用于输入扫描信号；
信号输出端口，用于输出脉冲信号；
脉冲传递单元，包括控制端，所述脉冲传递单元的控制端获得驱动电压后，将第一时钟信号传送至信号输出端口；
脉冲控制单元，用于从信号输入端口接收输入的扫描信号，给所述脉冲传递单元的控制端充电以提供所述驱动电压；
光电感应单元，用于接收外界光照时提供一个响应外界光照强度的泄漏电流，所述泄漏电流给脉冲传递单元的控制端放电使脉冲传递单元的控制端的电压经过一段时间后小于所述驱动电压。
根据本申请的第二方面，本申请一种显示面板，包括上述的光电传感器。
依上述实施的光电传感器和显示面板，由于脉冲传递单元、脉冲控制单元和光电感应单元利用常规显示面板就有的扫描信号和时钟信号，而不需要额外引入控制信号，因此电路结构简单，工艺实现难度较低。
附图说明
图1为本申请实施例一的光电传感器的一种结构示意图；
图2为本申请实施例一的光电传感器的一种工作时序图；
图3为本申请实施例二的光电传感器的一种结构示意图；
图4为本申请实施例三的光电传感器的一种电路示意图；
图5为本申请实施例三的光电传感器的另一种电路示意图；
图6为本申请实施例三的光电传感器的一种工作时序图；
图7为本申请实施例四的光电传感器的一种结构示意图；
图8为本申请实施例四的一种光电传感器在暗态下数个行扫描时间和一帧时间内的测试响应曲线；
图9为本申请实施例四的一种光电传感器在亮态下数个行扫描时间和一帧时间内的测试响应曲线。
具体实施方式
下面通过具体实施方式结合附图对本申请作进一步详细说明。
首先对本申请中用到的术语进行解释。
本申请中的晶体管为三端子晶体管，其三个端子分别为控制极、第一极和第二极；当晶体管为双极型晶体管时，控制极是指双极型晶体管的基极，第一极是指双极型晶体管的集电极或发射极，对应的第二极就是指双极型晶体管的发射极或集电极；当晶体管为场效应晶体管时，控制极是指场效应晶体管的栅极，第一极是指场效应晶体管的漏极或源极，对应的第二极就是指场效应晶体管的源极或漏极。
本申请中的晶体管可以为双极型晶体管也可以为场效应晶体管，在某些优选的实施例中，发明人使用场效应晶体管中的薄膜晶体管(TFT：Thin Film Transistor)来实现本申请的光电传感器和显示面板，理由如下：
场效应晶体管中的薄膜晶体管(TFT：Thin Film Transistor)的电学特性在外界光作用下会可能发生显著的改变。例如，薄膜晶体管加上光照之后，相比于暗态下的薄膜晶体管，其阈值电压减小、关态电流呈数量级地增加。考虑到薄膜晶体管的这种光电特性，发明人使用薄膜晶体管来制成光电传感器，同时这种光电传感器由于是用薄膜晶体管制成，因此非常容易集成于同样用薄膜晶体管为主要电路元件制成的SoP的显示面板。
下面不妨以晶体管为N型薄膜晶体管为例对本申请的光电传感器和 显示面板进行说明，相应地，此时晶体管的控制极指栅极，第一极指漏极，第二极指源极。
实施例1：
请参照图1，本实施例公开了一种光电传感器，包括脉冲传递单元2、脉冲控制单元1和光电感应单元3。
脉冲传递单元2连接在第一时钟信号VA输入端和信号输出端口之间，包括控制端Q，脉冲传递单元2的控制端Q获得驱动电压后，将第一时钟信号VA传送至信号输出端口。脉冲传递单元2有多种实现方式，在一个优选的实施方式中，脉冲传递单元2可以包括晶体管T2，此晶体管T2可为非感光晶体管，具体地，晶体管T2处于被遮光状态而使晶体管T2成为一个非感光晶体管。晶体管T2的控制极为脉冲传递单元2的控制端Q，晶体管T2的第一极用于输入第一时钟信号VA，晶体管T2的第二极连接到信号输出端口，用于在晶体管T2被驱动电压开启后，当第一时钟信号VA的高电平到来时对信号输出端口充电，当第一时钟信号VA的低电平到来时对信号输出端口放电。在某些优选的实施例中，晶体管T2的控制极和第二极之间还可以连接一个存储电容C1，用于存储控制端Q的电荷，使晶体管T2的控制极能获得一个较稳定的驱动电压。
脉冲控制单元1连接在信号输入端口和脉冲传递单元1的控制端Q之间，用于从信号输入端口接收输入的扫描信号Vscan，给脉冲传递单元1的控制端Q充电以提供上述的驱动电压，如上所述，这个驱动电压指的是能将晶体管T2开启，使晶体管T2的第一极和第二极导通的电压。脉冲控制单元1也有多种实现方式，在一个优选的实施方式中，脉冲控制单元1可以包括晶体管T7，此晶体管T7为非感光晶体管。晶体管T7的第一极与控制极相连；晶体管T7的第一极还连接到信号输入端口，用于输入扫描信号Vscan，晶体管T7的第二极连接到脉冲传递单元2的控制端Q，用于在扫描信号Vscan的高平电到来时给脉冲传递单元2的控制端Q充电以提供上述的驱动电压。
光电感应单元3连接在低电位和脉冲传递单元2的控制端Q之间，用于接收外界光照时提供一个响应外界光照强度的泄漏电流，此泄漏电流给脉冲传递单元2的控制端Q放电使脉冲传递单元2的控制端Q的电压经过一段时间后小于将晶体管T2开启的驱动电压。光电感应单元3可以有多种实现方式，在一个优选的实施方式中，光电感应单元3可以包括晶体管T8，此晶体管T8为感光型晶体管，具体地，可以通过将晶体管T8设置为感光状态而使晶体管T8成为一个感光晶体管。晶体管T8的第一极与控制极相连；晶体管T8的第一极还连接到低电平源VL， 晶体管T8的第二极连接到脉冲传递单元2的控制端Q；由于晶体管T8为一感光型晶体管，因此晶体管T8有一个响应外界光照的泄漏电流，所以晶体管T8用于接收外界光照时提供一个响应外界光照强度的泄漏电流；这个泄漏电流是从晶体管T8的第二极流向第一极，用于给脉冲传递单元2的控制端Q放电使脉冲传递单元2的控制端Q的电压小于上述的驱动电压。
图2为上述光电传感器的一种工作时序图，下面结合图1和图2，分阶段说明上述光电传感器的工作过程。
上述光电传感器工作时包括两个阶段：电压预置阶段和光感应阶段。
图2(a)为有限的数行扫描时间长度内光电传感器的工作时序图，一个行扫描时间为图中第一时钟信号VA的半个周期。
图2(b)为一帧时间内光电传感器的输出信号端和内部的控制端Q的工作时序图。
电压预置阶段：
请参照图2(a)，电压预置阶段是指在光电传感器接收扫描信号Vscan的高电平时或之前，预先将光电传感器内部的电路节点即控制端Q的电压统一设置为一高电平。具体地，控制端Q的电压在扫描信号Vscan的高电平到来之前或到来时，预先被设置为一高电平VH1，以避免前后帧状态的相互干扰，即此光电传感器无论前面帧运行期间电路上各节点的电压状态如何，在下一帧运行时，此光电传感器被扫描信号Vscan选中(即Vscan为高电平)之前或选中时，都预先将光电传感器的内部电路节点即控制端Q的电压统一设置为高电平VH1，这样就有效地防止了前后帧状态的相互干扰。
如图2(a)中的(1)阶段，控制端Q的电压VQ在此帧的扫描信号Vscan的高电来临时被预先设置为高电平VH1，在一个优选的实施例中，高电平VH1可以被设置为足以开启晶体管T2。
由于扫描信号Vscan在(1)阶段为高电平VH，于是晶体管T7被开启，扫描信号Vscan给控制端Q充电，使控制端Q的电压VQ升高，进而将晶体管T2开启，此时第一时钟信号VA为高电平，因此信号输出端口的电压Vo被充电到高电平，这反过来又使得控制端Q的电压VQ因自举而进一步升高到VH2，如图(2)阶段所示；在(3)阶段，第一时钟信号VA为低电平，因此信号输出端口的电压Vo被放电到低电平。需要说明的是，在此帧中，与一个光电传感器相连的扫描线输入的扫描信号Vscan在(1)阶段为高电平，其他时间为低电平，当晶体管T2被开启后，由于Vscan变为低电平，因此晶体管T7被关闭，控制端Q不会通过晶体管T7漏电，而感光型晶体管T8，虽然存在一个响应光强的泄漏电流，但此电流相连于对Q点电荷量来说太小，不足以在数行的扫描时间内明 显的影响Q点的电荷数及电压值，因此在有限行的扫描时间内，晶体管T2仍然保持开启的状态，第一时钟信号VA随着高低电平的到来，不断地给信号输出端充放电，即重复图2(a)中的(2)、(3)阶段。
光感应阶段：
请参照图2(b)，光感应阶段是光电传感器在一段相对行扫描时间来讲较长的时间内接受光照，根据光照强度的不同，光传感器将输出不同的电压Vo。具体地，光电感应单元3用一个响应外界光强的泄漏电流经过一段时间将控制端Q的电荷泄放掉，即对控制端Q进行放电使控制端Q的电压VQ小于驱动电压，从而将脉冲传递单元2关闭，导致输出信号端的电压Vo变化的过程。
如上所述，在电压预置阶段晶体管T2被开启，因此当第一时钟信号VA为高电平时，输出端口Vo也将被充电上拉为高电平，如2(a)中的(2)阶段所示；而第一时钟信号VA为低电平时，输出端口Vo也将被下拉到低电平，如2(a)中的(3)阶段所示。因此在接下来的时间内，随着时钟信号VA周期性地变化为高、低电平，输出端口Vo上的电压也周期性地变化为高、低电平。
光电感应单元3中存在一个响应外界光照的泄漏电流，即使完全黑暗，这个泄漏电流仍然存在，这会带来控制端Q上电荷的泄放。具体地，晶体管T8上存在一个由第二极流向第一极的泄漏电流，泄放控制端Q上的电荷，从而逐渐将控制端Q上的电压VQ的高电平幅度不断拉低，进而导致输出信号端的电压Vo的高电平幅度也逐渐衰减。
如图2(a)，虽然在有限个行扫描时间内无法明显地察觉出VQ和Vo的高电平的衰减，但在一帧时间内就能够看出VQ以及Vo的高电平幅度在逐渐衰减，如图2(b)。
因此，在一帧时间内经过一段时间，当控制端Q的电荷泄漏到一定程度，使控制端的电压VQ不足为开启晶体管T2时，晶体管T2就会转变为关闭状态，这时，即使第一时钟信号VA不断地在高、低电平之间跳变，信号输出端口的电压Vo也将保持着低电平电压，不再受到VA的影响。
如上所述，控制端Q上的电荷的泄漏是由于光电感应单元3的泄漏电流造成，而泄漏电流的大小则与照射在光电感应单元3上的光强密切相关，当光强增加时，泄漏电流呈数量级地增加，由公式：电荷＝电流*时间，可知，随着光强的增加，VQ和Vo的泄漏速度会加快，即在更短的时间内，VQ和Vo就衰减成低电平了。尤其是相比于暗态，在亮态情况下，可以明显观察到VQ和Vo的泄漏速度显著地加速，VQ和Vo更快地变成低电平。
如果定义t1为光感应阶段输出Vo上出现脉冲波形的时间即Vo的高 电平衰减到低电平的时间，如上所述光强越大，t1就越短，而光强越弱，t1就越长，因此，通过本申请的光电传感器，我们建立了光照强度与t1的函数关系，通过测算光感应阶段输出Vo上出现脉冲波形的时间即Vo的高电平衰减到低电平的时间t1，就通过标定出光照强度。
实施例2：
在实施例一中光电传感器，其脉冲控制单元1和光电感应单元3是由不同的单元实现的，在某些优选的实施例中，脉冲控制单元1、光电感应单元3分别由晶体管T7、晶体管T8来实现，这样做的好处是，电压预置以及光强感应这两个功能，即给脉冲传递单元2提供驱动电压和将脉冲传递单元2的控制端Q的电荷泄放这两个功能，对于晶体管的尺寸等具有不同的要求，当脉冲控制单元1和光电感应单元3是不同的单元时，便于分别优化设计晶体管T7和晶体管T8，以达到各自实现的功能的最好效果。
请参照图3，本实施例二，为了节省器件，也可以使脉冲控制单元1和光电感应单元3为同一单元13，此单元13可以实现脉冲控制单元1和光电感应单元3的功能。在一个优选的实施例中，单元13包括晶体管T78，晶体管T78为感光晶体管；晶体管T78的第一极与控制极相连；晶体管T78的第一极还连接到信号输入端口，用于输入扫描信号Vscan；晶体管T78的第二极连接到脉冲传递单元2的控制端Q；晶体管T78，用于在扫描信号Vscan的高平电到来时给脉冲传递单元2的控制端Q充电以提供驱动电压；以及用于接收外界光照时提供一个响应外界光照强度的泄漏电流，泄漏电流从晶体管T78的第二极流向第一极，用于给脉冲传递单元2的控制端Q放电使脉冲传递单元的控制端的电压小于上述驱动电压。
本实施例的光电传感器其工作原理与工作时序图与实施例一的光电传感器类似，在此不再赘述。
实施例3：
为了避免时钟馈通效应等在信号输出端口造成的噪声电压，本实施例所公开的光电传感器，在实施例一或二的基础上，还包括低电平维持单元4，用于在第二时钟信号VB的控制下，维持信号输出端口的电压Vo为低电平，其中第二时钟信号VB与第一时钟信号VA的周期相同、相位相反。
请参照图4，在实施例一基础上的一个优选的实施例中，低电平维持单元4包括晶体管T3，晶体管T3为非感光晶体管；晶体管T3的控制极用于输入第二时钟信号VB，晶体管T3的第一极连接到信号输出端 口Vo，晶体管T3的第二极连接到低电平源VL，用于在第二时钟信号VB的高电平到来时将信号输出端口的电压Vo下拉到低电平源VL的电压以维持信号输出端口的电压Vo为低电平。
图5为在实施例二基础上的一个优选实施例，其低电平维持单元4与图4中的一样，在此不再赘述。
请参照图6，为本实施例三的光电传感器的一种工作时序图。
在电压预置阶段和光感应阶段，由于第二时钟信号VB与第一时钟信号VA的周期相同、相位相反，因此当脉冲传递单元2开启状态下，在第一时钟信号VA给为高电平给信号输出端口充电使Vo为高电平时，第二时钟信号VB为低电平，晶体管T3处于关闭状态，低电平源VL不会对第一时钟信号VA给给信号输出端口充电造成影响；在第一时钟信号VA给为低电平给信号输出端口放电使Vo为低电平时，第二时钟信号VB为高电平，晶体管T3处于开启状态，因此晶体管T2和晶体管T3都将信号输出端的电压Vo拉到低电平。
在光感应阶段之后，如实施例一可知，光电传感器的电路上的控制端Q和信号输出端的电压应该保持低电平状态，但是由于电压馈通效应等，控制端Q和信号输出端上无可避免地存在一些噪声电压。对于脉冲传递单元2而言，由于晶体管T2的控制极和第一极之间、控制极和第二极之间，存在着交叠区域，这不可避免地会带来晶体管T2的控制极相关的寄生电容CGD、CGS(图中未画出)，其中寄生电容CGD是指晶体管T2的控制极与第一极之间的寄生电容，寄生电容CGS是指晶体管T2的控制极与第二极之间的寄生电容。特别是寄生电容CGD的存在，使得当第一时钟信号VA在高低电平之间跳变时，VQ和Vo也会跟着跳变。这会给测定Vo的高电平衰减到低电平的时间带来干扰，进而影响对光照强度的标定。例如，在光感应阶段，经过一段时间t1，信号输出端口的高电平应该消失，但是由于电压馈通效应，信号输出端口的高电平在消失之后又重新出现了脉冲信号(即一个高电平)，这就会引起Vo的高电平衰减到低电平的时间的误判。因此，为了避免电压馈通效应的影响，在光感应阶段之后，光电传感器需要进入低电平维持阶段，晶体管T3在第二时钟信号VB的控制下开启，从而将信号输出端口可能存在的噪声电荷释放掉。由于第二时钟信号VB也是周期信号，故晶体管T2可以被周期性地开启，这能够使信号输出端口的电荷不发生累积，从而维持信号输出端口的电压为低电平。
实施例4：
在实施例三中，虽然低电平维持单元4能够减少信号输出端口上的噪声电压，但是控制端Q的电压VQ仍然可能受到电压馈通效应的扰动。 在寄生电容较大的情况下，控制端Q上的噪声电压值可能超过晶体管T2的阈值电压，从而误将晶体管T2开启。由电压馈通造成的晶体管T2误开启，会给信号输出端口的电压Vo带来幅值较大的噪声电压，这时低电平维持单元4的维持Vo低电平的能力就有限。为了避免这种情况，本实施例考虑引入一抑制电压馈通效应的模块。
可以在实施一到三中任一实施的基础上实施本实施例。下面以在实施例三的基础为例进行说明。
请参照图7，本实施例，在实施例三中的图5所示的光电传感器的基础上，还包括电压馈通抑制单元5，用于在第一时钟信号VA的控制下，下拉所述信号输出端口和脉冲传递的控制端的电压以维持其为低电平。在一种优选的实施例中，电压馈通抑制单元5包括晶体管T4、晶体管T5、晶体管T6和耦合电容C2，晶体管T4、晶体管T5和晶体管T6为非感光晶体管。
晶体管T4的控制极、晶体管T5的第一极、晶体管T6的控制极和耦合电容C2的一端都连接到同一节点P，耦合电容C2的另一端连接到输出所述第一时钟信号VA的端口；晶体管T4的第二极、晶体管T5的控制极、晶体管T6的第一极都连接到信号输出端口；晶体管T4的第一极连接到脉冲传递单元2的控制端Q；晶体管T5、晶体管T6的第二极都连接到低电平源VL。晶体管T5，用于在信号输出端口的电压Vo为高电平时将晶体管T4、晶体管T6的控制极的电压都下拉到低电平源VL的电压，从而将晶体管T4、晶体管T6关闭以防止信号输出端口和脉冲传递单元2的控制端Q漏电；耦合电容C2，用于在脉冲传递单元2的控制端Q的电压VQ小于驱动电压后，当第一时钟信号VA的高电平到来时将此高电平耦合至晶体管T4、晶体管T6的控制极，从而将晶体管T4、晶体管T6开启以将信号输出端口和脉冲传递单元2的控制端Q的电压VQ下拉到低电平源VL的电压。
下面具体说明电压馈通抑制单元5的工作原理。
在光感应阶段之后的低电平维持阶段，由于耦合电容C2的作用，当第一时钟信号VA变成高电平时，节点P的电压被抬升到较高电平，于是晶体管T4和晶体管T6被开启，控制端Q的电压VQ和信号输出端口的电压均被下拉到低电平源VL的电平。需要说明的是，节点P的电压取决于耦合电容C2和节点P上其他的电容之比，当耦合电容C2的值设计得较大时，节点P的电压能够被调节到较大，从而将晶体管T4和晶体管T6开启。
在电压预置阶段和光感应阶段，当信号输出端口的电压Vo为高电平时，由于晶体管T5的控制极连接到信号输出端口，因此晶体管T5被开启，从而将节点P的电压下拉到低电平电压。由于晶体管T4和晶体管 T6的控制极都连接到节点P，因此晶体管T4和晶体管T6被关闭，从而抑制电压预置阶段和光感应阶段，光电传感器需要输出高电平时，控制端Q和信号输出端口的电荷的泄漏。
因此，电压馈通抑制单元5在低电平维持阶段，能够将控制端Q的电压VQ和信号输出端口的电压维持在低电平，在电压预置阶段和光感应阶段，能够使信号输出端口被正确地充电，同时，还能够避免光感应阶段和低电平维持阶段之间的相互的干扰，提高了光电传感器的可靠性。
为了验证本申请提出的光电传感器的功能，发明人采用非晶硅TFT(a-Si TFT)制备了实施例四中的光传感电路，并进行了测试。图8(a)为光电传感器在暗态情况下数个行扫描时间内的测试响应曲线，图8(b)为光电传感器在暗态情况下一帧时间内的测试响应曲线，其中Vscan[n-1]和Vscan[n]是相邻的两个扫描信号，VA是第一时钟信号，Vo是光电传感器的输出信号。从测试图中可以看到，与前面所分析的符合。在数个行扫描时间内，如图8(a)所示，在扫描信号Vscan[n]和第一时钟信号VA作用之后，Vo周期性地输出脉冲信号(即高电平)。如图8(b)所示，从一帧时间来看，在5ms之后Vo的输出脉冲幅度开始衰减。在暗态环境下，信号输出端口上脉冲持续时间长度为6ms以上。
与暗态情况下测试结果相对照，图9(a)为光电传感器在亮态情况下数个行扫描时间内的测试响应曲线，图9(b)为光电传感器在亮态情况下一帧时间内的测试响应曲线。从数倍个行扫描时间来看，信号输出端口上的周期性脉冲输出信号在暗态与亮态情况下并无显著差别。但是从一帧时间来看，在亮态情况下，信号输出端口输出脉冲信号Vo在1ms之后高电平的幅度就开始衰减。亮态情况下，信号输出端口上的脉冲持续时间长度约为1.5ms。因此可以看出，光照情况的不同对于本光电传感器的输出Vo影响非常显著。在进一步地优化设计晶体管T78的结构和尺寸，以及优化光电传感器的电路上其他元件的尺寸，本申请的光电传感器对于光强的灵敏度还会进一步地提升。
以上就是本申请的光电传感器的一些优选实施例，本申请利用晶体管如薄膜晶体管(TFT)在外界光作用下其电学特征发生改变的特性，设计了一种光电传感器，其合理地利用了显示面板上的扫描信号和时钟信号来进行控制，因而电路结构简，不需要像传统的光电传感器一样引入过入复杂的控制信号。由于本申请的光电传感器合理地利用了显示面板上的扫描信号和时钟信号，因此还特别适合集成于显示面板尤其是TFT显示面板以及一些柔性电子的应用场合。因此，本申请还提出一种显示面板，包括上述各实施例的光电传感器，其不仅具有较高的附加价值，而且显示面板机械结构和电路的复杂度也几乎不会增加。
需要注意的是，本光电传感器可以很容易集成于显示面板中，但也可以集成于别的用于检测光强或者通过检测光强来检测其他指标的领域，这时候，有可能没有现成的扫描信号，那只需要利用别的领域中现成的控制信号或再增加一个控制信号即可。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本领域的一般技术人员，依据本发明的思想，可以对上述具体实施方式进行变化。

Claims (10)

  1. 一种光电传感器，其特征在于，包括：
    信号输入端口，用于输入扫描信号；
    信号输出端口，用于输出脉冲信号；
    脉冲传递单元，包括控制端，所述脉冲传递单元的控制端获得驱动电压后，将第一时钟信号传送至信号输出端口；
    脉冲控制单元，用于从信号输入端口接收输入的扫描信号，给所述脉冲传递单元的控制端充电以提供所述驱动电压；
    光电感应单元，用于接收外界光照时提供一个响应外界光照强度的泄漏电流，所述泄漏电流给脉冲传递单元的控制端放电使脉冲传递单元的控制端的电压经过一段时间后小于所述驱动电压。
  2. 如权利要求1所述的光电传感器，其特征在于，所述脉冲控制单元包括晶体管T7，所述晶体管T7为非感光晶体管；所述晶体管T7的第一极与控制极相连；晶体管T7的第一极还连接到信号输入端口，用于输入扫描信号；晶体管T7的第二极连接到脉冲传递单元的控制端，用于在所述扫描信号的高平电到来时给脉冲传递单元的控制端充电以提供所述驱动电压。
  3. 如权利要求1所述的光电传感器，其特征在于，所述光电感应单元包括晶体管T8，所述晶体管T8为感光型晶体管；所述晶体管T8的第一极与控制极相连；所述晶体管T8的第一极还连接到低电平源，第二极连接到脉冲传递单元的控制端；所述晶体管T8用于接收外界光照时提供一个响应外界光照强度的泄漏电流，所述泄漏电流从晶体管T8的第二极流向第一极，用于给脉冲传递单元的控制端放电使脉冲传递单元的控制端的电压小于所述驱动电压。
  4. 如权利要求1所述的光电传感器，其特征在于，所述脉冲控制单元和光电感应单元为同一单元，此单元包括晶体管T78，所述晶体管T78为感光晶体管；所述晶体管T78的第一极与控制极相连；晶体管T78的第一极还连接到所述信号输入端口，用于输入扫描信号；晶体管T78的第二极连接到脉冲传递单元的控制端；所述晶体管T78，用于在所述扫描信号的高平电到来时给脉冲传递单元的控制端充电以提供所述驱动电压；以及用于接收外界光照时提供一个响应外界光照强度的泄漏电流，所述泄漏电流从晶体管T78的第二极流向第一极，用于给脉冲传递单元的控制端放电使脉冲传递单元的控制端的电压小于所述驱动电压。
  5. 如权利要求1所述的光电传感器，其特征在于，所述脉冲传递单元包括晶体管T2，所述晶体管T2为非感光晶体管；所述晶体管T2的控制极为所述脉冲传递单元的控制端；晶体管T2的第一极用于输入第一时钟信号；晶体管T2的第二极连接到信号输出端口，用于在晶体管 T2被所述驱动电压开启后，当所述第一时钟信号的高电平到来时对所述信号输出端口充电，当所述第一时钟信号的低电平到来时对所述信号输出端口放电。
  6. 如权利要求1所述的光电传感器，其特征在于，还包括低电平维持单元，用于在第二时钟信号的控制下，维持所述信号输出端口的电压为低电平，所述第二时钟信号与第一时钟信号的周期相同、相位相反。
  7. 如权利要求6所述的光电传感器，其特征在于，所述低电平维持单元包括晶体管T3，所述晶体管T3为非感光晶体管；所述晶体管T3的控制极用于输入所述第二时钟信号，晶体管T3的第一极连接到所述信号输出端口，晶体管T3的第二极连接到低电平源，用于在所述第二时钟信号的高电平到来时将所述信号输出端口的电压下拉到所述低电平源的电压以维持信号输出端口的电压为低电平。
  8. 如权利要求1所述的光电传感器，其特征在于，还包括电压馈通抑制单元，用于在所述第一时钟信号的控制下，下拉所述信号输出端口和脉冲传递单元的控制端的电压以维持其为低电平。
  9. 如权利要求8所述的光电传感器，其特征在于，所述电压馈通抑制单元包括晶体管T4、晶体管T5、晶体管T6和耦合电容C2，所述晶体管T4、晶体管T5和晶体管T6为非感光晶体管；所述晶体管T4的控制极、晶体管T5的第一极、晶体管T6的控制极和耦合电容C2的一端都连接到同一节点，耦合电容C2的另一端连接到输出所述第一时钟信号的端口；所述晶体管T4的第二极、晶体管T5的控制极、晶体管T6的第一极都连接到所述信号输出端口；所述晶体管T4的第一极连接到所述脉冲传递单元的控制端；所述晶体管T5、晶体管T6的第二极都连接到低电平源；
    所述晶体管T5，用于在所述信号输出端口的电压为高电平时将所述晶体管T4、晶体管T6的控制极的电压都下拉到低电平源的电压，从而将所述晶体管T4、晶体管T6关闭以防止所述信号输出端口和脉冲传递单元的控制端漏电；
    所述耦合电容C2，用于在所述脉冲传递单元的控制端的电压小于所述驱动电压后，当所述第一时钟信号的高电平到来时将此高电平耦合至所述晶体管T4、晶体管T6的控制极，从而将所述晶体管T4、晶体管T6开启以将信号输出端口和脉冲传递单元的控制端的电压下拉到所述低电平源的电压。
  10. 一种显示面板，包括权利要求1到9中任一项所述的光电传感器。
PCT/CN2016/077261 2015-05-07 2016-03-24 一种光电传感器和显示面板 Ceased WO2016177170A1 (zh)

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