WO2016177118A1 - 一种高低边自举驱动控制方法及装置 - Google Patents

一种高低边自举驱动控制方法及装置 Download PDF

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Publication number
WO2016177118A1
WO2016177118A1 PCT/CN2016/076502 CN2016076502W WO2016177118A1 WO 2016177118 A1 WO2016177118 A1 WO 2016177118A1 CN 2016076502 W CN2016076502 W CN 2016076502W WO 2016177118 A1 WO2016177118 A1 WO 2016177118A1
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Prior art keywords
side tube
low side
time
low
switching period
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PCT/CN2016/076502
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English (en)
French (fr)
Inventor
洪小芹
卢至锋
孟燕妮
江洪波
孙浩
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中兴通讯股份有限公司
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Publication of WO2016177118A1 publication Critical patent/WO2016177118A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present application relates to, but is not limited to, the field of power electronics, and in particular, to a high and low side bootstrap driving control method and apparatus.
  • High-low side drive is a common application scenario, and the drive mode often uses optocoupler drive, transformer drive and bootstrap drive.
  • Optocoupler drives are generally used in isolated locations. Additional auxiliary circuits must be added to isolate the power supply. The circuits are relatively complex, costly, difficult to integrate, and occupy a large space, which is not conducive to modular design.
  • Transformer drive is usually used in high-frequency drive isolation. Transformer drive often requires more complicated auxiliary circuits. It is costly and bulky. It is generally used in high-power places and is not suitable for modular design.
  • the bootstrap driver is generally integrated with an integrated circuit (IC), with few peripheral components, easy integration, modular design, relatively simple circuit, low cost, and has wide application in the field of power electronics.
  • the bootstrap driver is generally complementary. Operating mode to maintain high-side bootstrap capacitor voltage.
  • High and low side switching tube drives are widely used in switching power supplies, such as bridge circuits, power factor correction (PFC) circuits, BUCK synchronous rectification circuits, BOOST synchronous rectification circuits, and high and low side switches for the above topology.
  • the tube driving method generally adopts a bootstrap driving method, that is, when the low side tube is turned on, the bootstrap capacitor is charged through the low side tube to maintain the voltage of the bootstrap capacitor, which requires the high side tube and the low side tube to work in the complementary mode.
  • the high side tube and the low side tube should not work in the complementary mode.
  • optocoupler drive or transformer drive cannot be used.
  • FIG. 1 is a schematic diagram of a totem pole bridgeless PFC circuit in the related art.
  • CCM Continuous Conduction Mode
  • DCM Discontinuous Conduction Mode
  • the circuit will work in discontinuous conduction mode (DCM, Discontinuous Conduction Mode), after the inductor current continues to zero, the inductor current will be reversed; the low-frequency arm common rectifier bridge (rectifier diode D1 or D2) will be counter-pressured.
  • the recovery current is normal; the normal slow rectifier bridge operates in the high frequency switching state, which generates large reverse loss and interference.
  • the driving waveform and the inductor current (IL) waveform are shown in Figure 2, which are mainly divided into the following three stages:
  • the first stage S001 the main pipe (low side pipe Q2) is turned on, the auxiliary pipe (high side pipe Q1) is turned off, the inductor stores energy, and the current flow direction increases linearly as shown in FIG. 3;
  • the second stage S002 the main pipe (low side pipe Q2) is turned off, the auxiliary pipe (high side pipe Q1) is turned on, the inductor releases energy, and the current flow direction is linear as shown in FIG. 4;
  • the third stage S003 After the inductor current drops to zero, the rectifier diode is subjected to back pressure, because of its reverse recovery, the inductor current is reversed as shown in FIG. 5.
  • the totem pole bridgeless PFC circuit adopts the single-tube conduction and bootstrap driving mode
  • the high-side tube bootstrap capacitor can not be charged for each switching cycle due to the small inductor current. If the power is sufficient, the bootstrap capacitor voltage will not be maintained, causing the drive to be abnormal. In particular, when the snoring is performed, the bootstrap capacitor is directly discharged. Although the controller sends a drive signal, the driver chip cannot be driven normally.
  • the bootstrap drive of the high side tube and the low side tube adopts a complementary mode with large interference and reverse loss, and severe heat generation; using a single tube conduction bootstrap driving mode, When there is a reverse input, the high-side tube bootstrap capacitor cannot sustain the voltage for normal drive.
  • the industry mostly uses optocoupler isolation drivers or increases the inductor current zero-crossing detection circuit to solve the above problems, however, this approach increases the cost and circuit complexity.
  • Figure 6 is a schematic diagram of a DC-DC (Direct Current to Direct Current) two-stage topology high-side tube and low-side tube drive.
  • DC-DC Direct Current to Direct Current
  • the pre-stage synchronous BUCK circuit when the input voltage is low, the high-side tube Q1 must work in the through state, non-mutual The compensation mode, that is, the low side tube Q2 works in the normally closed state, and the high side tube Q1 works in the normally open state.
  • the high-side bootstrap capacitor cannot be charged when the low-side tube Q2 is normally closed, the high-side tube Q1 cannot be driven.
  • Existing problems can only be driven by optocouplers or transformers for the above problems, but this will undoubtedly increase the cost and complexity of the circuit.
  • the embodiment of the invention provides a high-low-side bootstrap driving control method and device, which can solve the problem that the high-side pipe and the low-side pipe drive cannot normally apply the bootstrap driving in some applications, and avoid the increase of cost and circuit complexity.
  • Embodiments of the present invention provide a high and low side bootstrap driving control method, including: detecting circuit characteristics of a circuit in which a high side tube and a low side tube are located; and when the circuit characteristic satisfies a predetermined condition, controlling the high side tube according to a preset strategy and The low-side tube outputs a specific driving waveform; wherein the preset strategy includes: configuring the high-side tube to operate in a closed-loop state, and the pulse width modulation (PWM) of the high-side tube is driven by a circuit loop It is determined that the low side tube is configured to operate in an open loop state, and the low side tube is turned on at a time shorter than a first predetermined time later than the start time of the switching period in one switching period, and is turned off before the high side tube is turned on.
  • PWM pulse width modulation
  • the side pipe or, in one switching cycle, turns on the low side pipe after the turn-off time of the high side pipe, and turns off the low side pipe at a time longer than the end of the switching cycle for a second predetermined time, wherein the high side
  • the switching period of the tube and the low side tube is the same and synchronized.
  • the preset policy further includes: turning on the low side tube at a time after the first predetermined time later than the start time of the switching period in the N+1th switching period after every N switching periods. Turn off the low side tube before the turn-on time of the high side tube, or turn on the low side tube after the turn-off time of the high side tube during the N+1th switching period, earlier than the end of the switching period The low side tube is turned off at the second predetermined time period, where N is an integer greater than or equal to zero.
  • the preset strategy further includes: the opening period of the low side tube is less than or equal to 10% of the length of the switching period in one switching period.
  • the preset strategy further includes: the maximum opening time of the high side tube and the opening dead time of the high side tube during the switching period The sum of the opening time of the low side tube and the opening dead time of the low side tube is equal to the duration of the switching period.
  • the predetermined condition includes:
  • the input voltage of the circuit where the high side tube and the low side tube are located is lower than the threshold; or,
  • the input polarity of the circuit where the high side tube and the low side tube are located is negative.
  • the embodiment of the invention further provides a high and low side bootstrap driving control device, comprising:
  • the detecting module is configured to: detect circuit characteristics of a circuit in which the high side tube and the low side tube are located;
  • the control module is configured to: when the circuit characteristic meets a predetermined condition, control the high side tube and the low side tube to output a specific driving waveform according to a preset strategy;
  • the preset strategy includes: configuring the high-side tube to work in a closed-loop state, and determining a duty cycle of the PWM driving waveform of the high-side tube is determined by a circuit loop, and configuring the low-side tube to work in an open-loop state, in one switching cycle, Turning on the low side tube at a time shorter than the first predetermined time period of the start of the switching period, turning off the low side tube before the opening time of the high side tube, or turning off the high side tube in one switching period After the time, the low side tube is turned on, and the low side tube is turned off at a time longer than the end of the switching period by a second predetermined time period, wherein the switching period of the high side tube and the low side tube is the same and synchronized.
  • the preset policy further includes: turning on the low side tube at a time after the first predetermined time later than the start time of the switching period in the N+1th switching period after every N switching periods. Turn off the low side tube before the turn-on time of the high side tube, or turn on the low side tube after the turn-off time of the high side tube during the N+1th switching period, earlier than the end of the switching period The low side tube is turned off at the second predetermined time period, where N is an integer greater than or equal to zero.
  • the preset strategy further includes: the opening period of the low side tube is less than or equal to 10% of the length of the switching period in one switching period.
  • the pre- The setting strategy further includes: during the switching cycle, the maximum opening time of the high side tube, the opening dead time of the high side tube, the opening time of the low side tube, and the opening dead time of the low side tube are equal to the switching period duration. .
  • the predetermined condition includes:
  • the input voltage of the circuit where the high side tube and the low side tube are located is lower than the threshold; or,
  • the input polarity of the circuit where the high side tube and the low side tube are located is negative.
  • an embodiment of the present invention further provides a computer readable storage medium storing computer executable instructions, and the high and low side bootstrap driving control method is implemented when the computer executable instructions are executed.
  • the circuit characteristics of the circuit in which the high side tube and the low side tube are located are detected; when the circuit characteristic satisfies a predetermined condition, the high side tube and the low side tube are controlled to output a specific driving waveform according to a preset strategy;
  • the preset strategy includes: configuring the high-side tube to work in a closed-loop state, the duty cycle of the PWM drive waveform of the high-side tube is determined by the circuit loop, and configuring the low-side tube to work in an open-loop state, in one switching cycle, Turning on the low side tube at a time shorter than the first predetermined time period of the start of the switching period, turning off the low side tube before the opening time of the high side tube, or, in one switching period, at the closing time of the high side tube The low-side tube is turned on, and the low-side tube is turned off at a time longer than the end of the switching period by a second predetermined time period, wherein the switching periods of the high-side tube and the low-
  • the embodiment of the invention provides a simple and practical high and low side bootstrap driving control method, which fully utilizes the simplicity of the bootstrap driving circuit and the flexibility of data control.
  • the solution provided by the embodiment of the invention solves the problem that the high side tube and the low side tube drive of some application places cannot normally apply the bootstrap driving. Moreover, it solves the problem of interference and reverse loss in the complementary mode bootstrap driving in some applications, and solves the problem that the bootstrap capacitor cannot be charged by the single-tube conduction bootstrap driving method. Moreover, increased cost and complexity of the circuit are avoided.
  • FIG. 1 is a schematic diagram of a totem pole bridgeless PFC circuit in the related art
  • FIG. 4 is a schematic diagram of current flow in a second stage S002;
  • Figure 5 is a schematic diagram of current flow in the third stage S003;
  • FIG. 6 is a schematic diagram of a DC-DC two-stage topology high side tube and a low side tube drive
  • FIG. 7 is a flowchart of a high and low side bootstrap driving control method according to an embodiment of the present invention.
  • FIG. 9 is a timing diagram 1 of high and low side driving logic according to Embodiment 1 of the present invention.
  • FIG. 10 is a timing diagram 2 of a high and low side driving logic according to Embodiment 1 of the present invention.
  • FIG. 11 is a timing chart 1 of high and low side driving logic according to Embodiment 2 of the present invention.
  • FIG. 12 is a timing diagram 2 of the high and low side driving logic according to the second embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a high and low side bootstrap driving control apparatus according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a high and low side bootstrap driving control method according to an embodiment of the present invention. As shown in FIG. 7, the high and low side bootstrap driving control method provided by this embodiment includes the following steps:
  • Step 701 Detect circuit characteristics of a circuit in which the high side tube and the low side tube are located.
  • the input voltage or input polarity of the circuit in which the high side tube and the low side tube are located is detected.
  • Step 702 When the circuit characteristic satisfies a predetermined condition, the high side tube and the low side tube are controlled to output a specific driving waveform according to a preset strategy.
  • predetermined conditions include:
  • the input voltage of the circuit where the high side tube and the low side tube are located is lower than the threshold; or,
  • the input polarity of the circuit where the high side tube and the low side tube are located is negative.
  • the preset strategy includes: configuring the high-side tube to work in a closed-loop state, and determining a duty cycle of the PWM driving waveform of the high-side tube is determined by a circuit loop, and configuring the low-side tube to work in an open-loop state, in one switching cycle, Turning on the low side tube at a time shorter than the first predetermined time period of the start of the switching period, turning off the low side tube before the opening time of the high side tube, or turning off the high side tube in one switching period After the time, the low side tube is turned on, and the low side tube is turned off at a time longer than the end of the switching period by a second predetermined time period, wherein the switching period of the high side tube and the low side tube is the same and synchronized.
  • the first predetermined duration and the second predetermined duration may be equal or unequal, and the specific values of the two may be Set as needed. This application is not limited thereto.
  • the preset policy further includes: turning on the low side tube at a time after the first predetermined time later than the start time of the switching period in the N+1th switching period after every N switching periods. Turn off the low side tube before the turn-on time of the high side tube, or turn on the low side tube after the turn-off time of the high side tube during the N+1th switching period, earlier than the end of the switching period The low side tube is turned off at the second predetermined time period, where N is an integer greater than or equal to zero.
  • the low side pipe when N is 0, that is, in each switching cycle, the low side pipe is turned on at a time shorter than the start time of the switching cycle, and the low side pipe is turned off before the turn-on time of the high side pipe.
  • the tube, or the low side tube is turned on after the turn-off time of the high side tube, and the low side tube is turned off at a time two second earlier than the end of the switching period.
  • the low side tube is turned on at a time shorter than the start time of the switching period by a first predetermined time, and the low side tube is turned off before the opening time of the high side tube, or, at a high
  • the low side tube is turned on after the turn-off time of the side tube, and the low side tube is turned off at a time two second earlier than the end of the switching period. Thereafter, every two switching cycles are the same as the settings in the first switching cycle and the third switching cycle.
  • the preset strategy further includes: the opening period of the low side tube is less than or equal to 10% of the length of the switching period in one switching period.
  • the pre- The setting strategy further includes: during the switching cycle, the maximum opening time of the high side tube, the opening dead time of the high side tube, the opening time of the low side tube, and the opening dead time of the low side tube are equal to the switching period duration. .
  • high-low-side bootstrap driving control method can be applied to all circuit topology high-low-side bootstrap driving, and the types of high-side and low-side pipes include, for example, metal-oxide-semiconductor (MOS). , Metal-Oxide-Semiconductor) Field-effect transistor, gallium nitride (GaN), insulated gate bipolar transistor (IBGT, Insulated Gate Bipolar Transistor) and other switching tubes.
  • MOS metal-oxide-semiconductor
  • IBGT Insulated Gate Bipolar Transistor
  • FIG. 8 is a flowchart of a high and low side bootstrap driving control method according to Embodiment 1 of the present invention.
  • the present embodiment is applied to the totem pole bridgeless PFC main topology structure as shown in FIG. 1.
  • the high and low side bootstrap driving control method provided in this embodiment includes the following steps:
  • Step 801 Detect the input voltage type and input polarity of the circuit.
  • Step 802 Configure the PWM drive according to the input voltage type and the input polarity.
  • the configuration supervisor (such as the high-side tube) operates in the switch mode
  • the auxiliary pipe (such as the low-side tube) is in the off mode to avoid interference and loss caused by the complementary bootstrap drive
  • the input is positive
  • configure the low side tube in the switch mode the high side tube is always in the off mode to avoid the interference and loss caused by the complementary bootstrap drive
  • when inputting the reverse DC configure the high side tube to work in the main switch mode, low side
  • the tube works in the auxiliary switch mode, and the low-side tube in the auxiliary switch mode has a fixed and short turn-on time to solve the high-side tube driving abnormality caused by the single-tube bootstrap driving and avoid the interference and loss caused by the complementary bootstrap driving.
  • the high side tube Q1 when the input polarity is negative, that is, VL ⁇ VN, the high side tube Q1 operates in a closed loop state, and the driving waveform of the low side tube ( The driving waveform (PWMH) of PWML) and the high side tube is as shown in FIG. 9 or FIG.
  • the high side tube and the low side tube are set to the same switching period and synchronized; the switching period is counted down by the counter (Counter); the high side tube is configured as the filter closed loop driving output mode, that is, the output PWM waveform duty ratio (Duty) is determined by the PFC loop.
  • the low-side tube works in the open-loop state.
  • the turn-on time is determined by Counter#3, and the turn-off time is determined by Counter#4.
  • the high side tube is output at the beginning of each switching cycle, and the duty cycle is controlled by the loop; the opening time of the low side tube is later than the closing time of the high side tube, where the low side tube is near the end of each switching cycle.
  • tl is generally small, and it can be in the nanosecond (ns) level.
  • the opening time of the low side tube is, for example, less than or equal to 10% of the switching period. At this point, the charging of the high side tube bootstrap capacitor is completed.
  • the maximum duty ratio of the high side tube must be limited to ensure the maximum opening time of the high side tube is th_max, and the high side tube is opened.
  • the low side tube and the high side tube are set to the same switching period and synchronized; the switching period is counted down by the counter (Counter); the high side tube is configured as the filter closed loop driving output mode, and the turn-on time is determined by Counter#1.
  • the output PWM waveform duty cycle is determined by the PFC loop; the low side tube operates in the open loop state, its turn-on time is determined by Counter#3, and the turn-off time is determined by Counter#4.
  • tl is generally small, and it can be ns level.
  • the opening time of the low side tube is, for example, less than or equal to 10% of the switching period. At this point, the charging of the high side tube bootstrap capacitor is completed.
  • the high side tube is also turned on at a fixed time of each switching cycle Counter#1.
  • the values of Counter#1, Counter#3, and Counter#4 must be limited to ensure Counter#1>Counter#4>Counter#3.
  • the dead time tdl of the open dead zone is uncertain
  • This embodiment is applied to a pre-stage synchronous rectification Buck circuit of a two-stage DC-DC topology as shown in FIG.
  • a complementary high side tube and a low side tube driving waveform are generated; when the input voltage is lower than a threshold, the driving waveform (PWMH) of the high side tube and The driving waveform (PWML) of the low side tube is as shown in FIG. 11 or FIG.
  • the high side tube and the low side tube are set to the same switching period and synchronized; the switching period is counted down by the counter (Counter); the high side tube continuously generates N cycles of the full duty cycle waveform, at the Nth +1 switching cycle, the low-side tube is first turned on at the beginning of the switching period to fix a small duty time, and the high-side tube bootstrap capacitor is charged to supplement the power lost during the high-side tube driving, at the low side After the turn-off time of the tube, the duty cycle of the high-side tube is turned on for the remaining time.
  • N is an integer greater than or equal to zero.
  • the opening time of the low side tube is, for example, less than or equal to 10% of the switching period.
  • the high side tube and the low side tube are set to the same switching period and synchronized; the switching period is determined by the counter (counter) counting down; the high side tube continuously generates N periods of full duty cycle waveform, after N+1 switching cycles, first turn on the high-side drive with a certain larger duty cycle. After the turn-off time of the high-side pipe, open the low-side pipe with a smaller fixed duty time in the current cycle to complete the high-side Side tube bootstrap capacitor charging.
  • N is an integer greater than or equal to zero.
  • the opening time of the low side tube is, for example, less than or equal to 10% of the switching period.
  • the dead time in order to prevent the high side tube from being connected to the low side tube, the dead time must be set.
  • an embodiment of the present invention further provides a high and low side bootstrap driving control device. As shown in FIG. 13, the device includes:
  • the detecting module is configured to: detect circuit characteristics of a circuit in which the high side tube and the low side tube are located;
  • the control module is configured to: when the circuit characteristic meets a predetermined condition, control the high side tube and the low side tube to output a specific driving waveform according to a preset strategy;
  • the preset strategy includes: configuring the high-side tube to work in a closed-loop state, and determining a duty cycle of the PWM driving waveform of the high-side tube is determined by a circuit loop, and configuring the low-side tube to work in an open-loop state, in one switching cycle, Turning on the low side tube at a time shorter than the first predetermined time period of the start of the switching period, turning off the low side tube before the opening time of the high side tube, or turning off the high side tube in one switching period After the time, the low side tube is turned on, and the low side tube is turned off at a time longer than the end of the switching period by a second predetermined time period, wherein the switching period of the high side tube and the low side tube is the same and synchronized.
  • the preset policy further includes: turning on the low side tube at a time after the first predetermined time later than the start time of the switching period in the N+1th switching period after every N switching periods. Turn off the low side tube before the turn-on time of the high side tube, or turn on the low side tube after the turn-off time of the high side tube during the N+1th switching period, earlier than the end of the switching period The low side tube is turned off at the second predetermined time period, where N is an integer greater than or equal to zero.
  • the preset strategy further includes: the opening period of the low side tube is less than or equal to 10% of the length of the switching period in one switching period.
  • the pre- The setting strategy further includes: during the switching cycle, the maximum opening time of the high side tube, the opening dead time of the high side tube, the opening time of the low side tube, and the opening dead time of the low side tube are equal to the switching period duration. .
  • the detecting module is configured to: detect an input voltage or an input polarity of a circuit where the high side tube and the low side tube are located.
  • the predetermined condition includes:
  • the input voltage of the circuit where the high side tube and the low side tube are located is lower than the threshold; or,
  • the input polarity of the circuit where the high side tube and the low side tube are located is negative.
  • the functions of the above modules are implemented by the processor executing programs/instructions stored in the memory.
  • this application is not limited thereto.
  • the functions of the above modules can also be implemented by firmware/logic circuits/integrated circuits.
  • the hardware of the embodiment of the present invention adopts a common professional integrated circuit (IC) chip, and the driving waveform timing is implemented by a control device (such as a microprocessor), which solves the problem that the complementary mode is adopted in some application places.
  • a control device such as a microprocessor
  • the problem of interference and reverse loss caused by the drive solves the problem that the bootstrap capacitor cannot be charged when the high-side single-tube bootstrap driver is used.
  • increased cost and circuit complexity are avoided.
  • an embodiment of the present invention further provides a computer readable storage medium storing computer executable instructions, and the high and low side bootstrap driving control method is implemented when the computer executable instructions are executed.
  • each module/unit in the above embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, executing a program stored in the memory by a processor. / instruction to achieve its corresponding function.
  • This application is not limited to any specific combination of hardware and software.
  • the embodiment of the invention provides a high and low side bootstrap driving control method and device, which fully utilizes the simplicity of the bootstrap driving circuit and the flexibility of data control, and solves the problem that the high side tube and the low side tube driving of some applications cannot be normal. Apply the issue of bootstrap drivers.

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Abstract

一种高低边自举驱动控制方法，包括：检测高边管及低边管所在电路的电路特性（701）；当电路特性满足预定条件时，根据预设策略控制高边管及低边管输出特定的驱动波形（702）。预设策略包括：配置高边管工作于闭环状态，配置低边管工作于开环状态；在一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，高边管与低边管的开关周期相同且同步。该方法能够解决某些应用场所高边管及低边管驱动无法正常应用自举驱动的问题，并避免增加成本及电路复杂度。

Description

一种高低边自举驱动控制方法及装置 技术领域
本申请涉及但不限于电力电子领域，尤其涉及一种高低边自举驱动控制方法及装置。
背景技术
随着工业发展，绿色节能呼声日渐升高。电力电子应用于工业设备的基础性组件，比如电源、变频器产品，对主设备的能耗至关重要；其转换效率，直接影响了主设备的能耗等级。在设备更新迭代急剧加速、空间要求日益提高的今天，电力电子产品需要顺应时代的要求，朝着高效率、高功率密度、数字化发展；尤其近年来，随着新型半导体开关器件的出现，电力电子将进入下一个全新时代。
在电力电子技术中，高低边驱动为常用的应用场景，驱动方式常采用光耦驱动、变压器驱动以及自举驱动。光耦驱动一般应用在隔离场所，须增加额外辅助电路，隔离供电电源，电路相对复杂，成本高，难以集成，占用空间大，不利于模块化设计。变压器驱动通常应用在高频驱动隔离场所，变压器驱动常常需要较复杂的辅助电路，成本高，体积大，一般应用在大功率场所，也不适用于模块化设计。自举驱动一般采用专用集成电路(IC，Integrated Circuit)集成，外围元器件少，易于集成、模块化设计，电路相对简单，成本低，在电力电子领域有着广泛的应用，自举驱动一般采用互补工作模式，以维持高边自举电容电压。
高低边开关管驱动在开关电源领域应用十分广泛，比如桥式电路、图腾柱功率因素校正(PFC，Power Factor Correction)电路、BUCK同步整流电路、BOOST同步整流电路，针对上述拓扑结构，高低边开关管驱动方式一般采用自举驱动，即当低边管导通时，通过低边管对自举电容充电，以维持自举电容的电压，这要求高边管和低边管工作在互补模式，但是在某些拓扑结构中，高边管及低边管不宜工作在互补模式，另外，由于成本和空间的限制，亦不能采用光耦驱动或变压器驱动。
图1为相关技术中图腾柱无桥PFC电路的示意图。如图1所示，在连续导通模式(CCM，Continuous Conduction Mode)的图腾柱PFC电路中，针对高边管Q1、低边管Q2驱动，如采用互补模式的自举驱动，在轻载时电路将工作在断续导通模式(DCM，Discontinuous Conduction Mode)，电感电流续流到零后，电感电流反灌；低频臂普通整流桥管(整流二极管D1或D2)因承受反压，存在反向恢复电流；普通慢速整流桥工作在高频开关状态，产生很大的反相损耗和干扰。
接下来以正向输入为例说明图腾柱无桥PFC电路的工作过程，驱动波形与电感电流(IL)波形如图2所示，主要分为以下三个阶段：
第一阶段S001：主管(低边管Q2)开通，辅管(高边管Q1)关断，电感储能，电流流向如图3所示，线性增加；
第二阶段S002：主管(低边管Q2)关断，辅管(高边管Q1)开通，电感释放能量，电流流向如图4所示，线性减少；
第三阶段S003：电感电流下降零以后，整流二级管承受反压，因其存在反向恢复，电感电流反向如图5所示。
另外，图腾柱无桥PFC电路若采用单管导通自举驱动方式，在输入电压反向时，在轻载下，由于电感电流较小，每个开关周期无法对高边管自举电容充足够电，将无法维持自举电容电压，导致驱动异常；尤其打嗝时，直接导致自举电容电量泄放，虽然控制器发出了驱动信号，但驱动芯片无法正常驱动。
由上述可知，在图腾柱PFC电路中，高边管及低边管的自举驱动采用互补模式存在较大干扰以及反向损耗、发热严重的问题；采用单管导通自举驱动方式，则当存在反向输入时，高边管自举电容无法维持电压正常驱动。为此，业界多采用光耦隔离驱动或增加电感电流过零检测电路来解决上述问题，然而，该做法增加了成本以及电路的复杂度。
图6为直流至直流(DC-DC，Direct Current to Direct Current)两级拓扑高边管及低边管驱动的示意图。如图6所示，在DC-DC两级拓扑应用中，前级同步BUCK电路，在输入电压低时，高边管Q1须工作在直通状态，非互 补模式，即低边管Q2工作在常闭状态，高边管Q1工作在常开状态。但是，由于低边管Q2常闭时无法对高边的自举电容充电，会导致高边管Q1无法驱动。现有针对上述问题也只能采用光耦或变压器单独驱动，但是，这无疑将增加成本以及电路的复杂度。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本发明实施例提供一种高低边自举驱动控制方法及装置，能够解决某些应用场所高边管及低边管驱动无法正常应用自举驱动的问题，并且避免增加成本以及电路的复杂度。
本发明实施例提供一种高低边自举驱动控制方法，包括：检测高边管及低边管所在电路的电路特性；当所述电路特性满足预定条件时，根据预设策略控制高边管及低边管输出特定的驱动波形；其中，所述预设策略包括：配置高边管工作于闭环状态，高边管的脉冲宽度调制(PWM，Pulse Width Modulation)驱动波形占空比由电路环路确定，配置低边管工作于开环状态，在一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，高边管与低边管的开关周期相同且同步。
可选地，所述预设策略还包括：每间隔N个开关周期之后，在第N+1个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在第N+1个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，N为大于或等于0的整数。
可选地，所述预设策略还包括：在一个开关周期内，低边管的开通时长小于或等于该开关周期时长的10％。
可选地，当在一个开关周期内，在高边管的关断时刻后导通低边管，在 比该开关周期结束时刻早第二预定时长的时刻关断低边管时，所述预设策略还包括：在该开关周期内，高边管的最大开通时长、高边管的开通死区时长、低边管的开通时长以及低边管的开通死区时长之和等于该开关周期时长。
可选地，所述预定条件包括：
高边管及低边管所在电路的输入电压低于阈值；或，
高边管及低边管所在电路的输入极性为负。
本发明实施例还提供一种高低边自举驱动控制装置，包括：
检测模块，设置为：检测高边管及低边管所在电路的电路特性；
控制模块，设置为：当所述电路特性满足预定条件时，根据预设策略控制高边管及低边管输出特定的驱动波形；
其中，所述预设策略包括：配置高边管工作于闭环状态，高边管的PWM驱动波形占空比由电路环路确定，配置低边管工作于开环状态，在一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，高边管与低边管的开关周期相同且同步。
可选地，所述预设策略还包括：每间隔N个开关周期之后，在第N+1个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在第N+1个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，N为大于或等于0的整数。
可选地，所述预设策略还包括：在一个开关周期内，低边管的开通时长小于或等于该开关周期时长的10％。
可选地，当在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管时，所述预设策略还包括：在该开关周期内，高边管的最大开通时长、高边管的开通死区时长、低边管的开通时长以及低边管的开通死区时长之和等于该开关周期时长。
可选地，所述预定条件包括：
高边管及低边管所在电路的输入电压低于阈值；或，
高边管及低边管所在电路的输入极性为负。
此外，本发明实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被执行时实现所述高低边自举驱动控制方法。
在本发明实施例中，检测高边管及低边管所在电路的电路特性；当所述电路特性满足预定条件时，根据预设策略控制高边管及低边管输出特定的驱动波形；其中，所述预设策略包括：配置高边管工作于闭环状态，高边管的PWM驱动波形占空比由电路环路确定，配置低边管工作于开环状态，在一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，高边管与低边管的开关周期相同且同步。本发明实施例提供了简单、实用的高低边自举驱动控制方法，充分应用了自举驱动电路的简单性以及数据控制的灵活性。通过本发明实施例提供的方案，解决了某些应用场所高边管及低边管驱动无法正常应用自举驱动的问题。而且，解决了某些应用场所采用互补模式自举驱动存在的干扰及反向损耗问题，又解决了采用单管导通自举驱动方式无法对自举电容充电的问题。而且，避免了增加成本以及电路的复杂度。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1为相关技术中图腾柱无桥PFC电路的示意图；
图2为互补模式驱动及电感电流波形图；
图3为第一阶段S001的电流流向示意图；
图4为第二阶段S002的电流流向示意图；
图5为第三阶段S003的电流流向示意图；
图6为DC-DC两级拓扑高边管及低边管驱动的示意图；
图7为本发明实施例提供的高低边自举驱动控制方法的流程图；
图8为本发明实施例一提供的高低边自举驱动控制方法的流程图；
图9为本发明实施例一的高低边驱动逻辑时序图一；
图10为本发明实施例一的高低边驱动逻辑时序图二；
图11为本发明实施例二的高低边驱动逻辑时序图一；
图12为本发明实施例二的高低边驱动逻辑时序图二；
图13为本发明实施例提供的高低边自举驱动控制装置的示意图。
本发明的实施方式
以下结合附图对本发明的实施例进行详细说明，应当理解，以下所说明的实施例仅用于说明和解释本申请，并不用于限定本申请。
图7为本发明实施例提供的高低边自举驱动控制方法的流程图。如图7所示，本实施例提供的高低边自举驱动控制方法包括以下步骤：
步骤701：检测高边管及低边管所在电路的电路特性。
具体而言，检测高边管及低边管所在电路的输入电压或输入极性。
步骤702：当电路特性满足预定条件时，根据预设策略控制高边管及低边管输出特定的驱动波形。
其中，所述预定条件包括：
高边管及低边管所在电路的输入电压低于阈值；或，
高边管及低边管所在电路的输入极性为负。
其中，所述预设策略包括：配置高边管工作于闭环状态，高边管的PWM驱动波形占空比由电路环路确定，配置低边管工作于开环状态，在一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，高边管与低边管的开关周期相同且同步。
其中，第一预定时长与第二预定时长可相等或不等，两者的具体取值可 根据需要进行设置。本申请对此并不限定。
可选地，所述预设策略还包括：每间隔N个开关周期之后，在第N+1个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在第N+1个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，N为大于或等于0的整数。
具体而言，当N为0时，即在每个开关周期内，在比开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在高边管的关断时刻后导通低边管，在比开关周期结束时刻早第二预定时长的时刻关断低边管。当N为非0整数时，以N＝2为例，在第一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管；在间隔2个开关周期之后，在第三个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管。之后，每间隔2个开关周期，均与第一开关周期及第三开关周期内的设置相同。
可选地，所述预设策略还包括：在一个开关周期内，低边管的开通时长小于或等于该开关周期时长的10％。
可选地，当在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管时，所述预设策略还包括：在该开关周期内，高边管的最大开通时长、高边管的开通死区时长、低边管的开通时长以及低边管的开通死区时长之和等于该开关周期时长。
需要说明的是，本发明实施例提供的高低边自举驱动控制方法可以应用于所有电路拓扑高低边自举驱动，且高边管及低边管的类型例如包括金属-氧化物-半导体(MOS，Metal-Oxide-Semiconductor)场效应晶体管、氮化镓(GaN)、绝缘栅双极型晶体管(IBGT，Insulated Gate Bipolar Transistor)等开关管。然而，本申请对此并不限定。
接下来通过具体实施例对本申请进行说明。
实施例一
图8为本发明实施例一提供的高低边自举驱动控制方法的流程图。本实施例应用于如图1所示的图腾柱无桥PFC主拓扑结构中，本实施例提供的高低边自举驱动控制方法包括以下步骤：
步骤801：检测电路的输入电压类型及输入极性。
步骤802：根据输入电压类型及输入极性，配置PWM驱动。
具体而言，当输入交流时，配置主管(如高边管)工作于开关模式，辅管(如低边管)处于关闭模式，以避免互补自举驱动产生的干扰和损耗；当输入正向直流时，配置低边管处于开关模式，高边管始终处于关闭模式，以避免互补自举驱动产生的干扰和损耗；当输入反向直流时，配置高边管工作于主开关模式，低边管工作于辅开关模式，处于辅开关模式的低边管的开通时间固定且短，以解决单管自举驱动造成的高边管驱动异常，并避免互补自举驱动产生的干扰和损耗。
举例而言，在如图1所示的图腾柱无桥PFC主拓扑结构中，当输入极性为负时，即VL<VN，高边管Q1工作于闭环状态，低边管的驱动波形(PWML)与高边管的驱动波形(PWMH)如图9或图10所示。
如图9所示，高边管及低边管设置相同开关周期，并同步；开关周期通过计数器(Counter)递减计时；高边管配置为滤波器闭环驱动输出模式，即输出PWM波形占空比(Duty)由PFC环路决定，低边管工作在开环状态，其开通时刻由Counter#3决定，关断时刻由Counter#4决定。高边管在每个开关周期开始时输出，占空比由环路控制；低边管的开通时刻晚于高边管的关断时刻，于此，低边管在每个开关周期靠近末尾的开通时刻Counter#3开通，在关断时刻Counter4#关断，开通时长t1＝Counter#4–Counter#3，于此，关断时刻例如为开关周期的结束时刻，即第二预定时长为0。其中，tl一般较小，为纳秒(ns)级别即可。低边管的开通时长例如小于或等于该开关周期的10％。此时，完成对高边管自举电容的充电。另外，为了防止高边管及低边管互通，须限制高边管的最大占空比，保证高边管最大开通时长th_max、高边管开通 死区时长tdh、低边管开通时长tl以及低边管开通死区时长tdl的和值等于一个开关周期时长，即th_max+tdh+t1+tdl＝一个开关周期时长Period。
如图10所示，低边管以及高边管设置相同开关周期，并同步；开关周期通过计数器(Counter)递减计时；高边管配置为滤波器闭环驱动输出模式，开通时刻由Counter#1决定，输出PWM波形占空比由PFC环路决定；低边管工作在开环状态，其开通时刻由Counter#3决定，关断时刻由Counter#4决定。于此，低边管在每个开关周期开始处的开通时刻Counter#3开通，在关断时刻Counter#4关断，开通时长t1＝Counter#4–Counter#3。其中，tl一般较小，为ns级别即可。低边管的开通时长例如小于或等于该开关周期的10％。此时，完成对高边管自举电容的充电。高边管也在每个开关周期的固定时刻Counter#1开通。另外，为了防止高边管以及低边管互通，须对Counter#1、Counter#3以及Counter#4的取值进行限制，以保证Counter#1>Counter#4>Counter#3。其中，开通死区时长tdl不确定，其最小值tdl_min＝Counter#3-当前开关周期的起始时刻，开通死区时长tdh＝Counter#1–Counter#4。
实施例二
本实施例应用于如图6所示的两级DC-DC拓扑结构的前级同步整流Buck电路。于本实施例中，当检测输入电压高于或等于一阈值时，产生互补的高边管及低边管驱动波形；当输入电压低于一阈值时，高边管的驱动波形(PWMH)及低边管的驱动波形(PWML)如图11或图12所示。
如图11所示，高边管及低边管设置相同开关周期，并同步；开关周期通过计数器(Counter)递减计时；高边管连续产生N个周期的全占空比波形后，在第N+1个开关周期，低边管在该开关周期的起始处先开通固定较小的占空时间，对高边管自举电容充电，以补充高边管驱动时损失的电量，在低边管的关断时刻之后，在剩余时间开通高边管的占空比。其中，N为大于或等于0的整数。其中，低边管的开通时长例如小于或等于该开关周期的10％。
如图12所示，高边管及低边管设置相同开关周期，并同步；开关周期通过计数器(Counter)递减计数确定；高边管连续产生N个周期的全占空比波形后，在第N+1个开关周期，先开通一定较大占空比的高边驱动，在高边管的关断时刻后，在当前周期内再以较小固定占空时间开通低边管，完成对高 边管自举电容的充电。其中，N为大于或等于0的整数。其中，低边管的开通时长例如小于或等于该开关周期的10％。
于本实施例中，为了防止高边管与低边管直通，都须设置死区时间。
此外，本发明实施例还提供一种高低边自举驱动控制装置，如图13所示，所述装置包括：
检测模块，设置为：检测高边管及低边管所在电路的电路特性；
控制模块，设置为：当所述电路特性满足预定条件时，根据预设策略控制高边管及低边管输出特定的驱动波形；
其中，所述预设策略包括：配置高边管工作于闭环状态，高边管的PWM驱动波形占空比由电路环路确定，配置低边管工作于开环状态，在一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，高边管与低边管的开关周期相同且同步。
可选地，所述预设策略还包括：每间隔N个开关周期之后，在第N+1个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在第N+1个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，N为大于或等于0的整数。
可选地，所述预设策略还包括：在一个开关周期内，低边管的开通时长小于或等于该开关周期时长的10％。
可选地，当在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管时，所述预设策略还包括：在该开关周期内，高边管的最大开通时长、高边管的开通死区时长、低边管的开通时长以及低边管的开通死区时长之和等于该开关周期时长。
可选地，所述检测模块，是设置为：检测高边管及低边管所在电路的输入电压或输入极性。
可选地，所述预定条件包括：
高边管及低边管所在电路的输入电压低于阈值；或，
高边管及低边管所在电路的输入极性为负。
于实际应用中，上述模块的功能通过处理器执行存储在存储器中的程序/指令实现。然而，本申请对此并不限定。上述模块的功能还可以通过固件/逻辑电路/集成电路实现。
此外，关于所述装置的具体处理流程同上述方法所述，故于此不再赘述。
综上所述，本发明实施例的硬件采用普通专业驱动集成电路(IC，Integrated Circuit)芯片，驱动波形时序由控制装置(如微处理器)实现，既解决了某些应用场所采用互补模式自举驱动出现的干扰、反向损耗问题，又解决了采用高边单管导通自举驱动时，存在无法对自举电容充电的问题。而且，避免了增加成本及电路复杂度。
此外，本发明实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被执行时实现所述高低边自举驱动控制方法。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本申请不限制于任何特定形式的硬件和软件的结合。
以上显示和描述了本申请的基本原理和主要特征和本申请的优点。本申请不受上述实施例的限制，上述实施例和说明书中描述的只是说明本申请的原理，在不脱离本申请精神和范围的前提下，本申请还会有各种变化和改进，这些变化和改进都落入要求保护的本申请范围内。
工业实用性
本发明实施例提供一种高低边自举驱动控制方法及装置，充分应用了自举驱动电路的简单性以及数据控制的灵活性，解决了某些应用场所高边管及低边管驱动无法正常应用自举驱动的问题。

Claims (11)

  1. 一种高低边自举驱动控制方法，包括：
    检测高边管及低边管所在电路的电路特性；
    当所述电路特性满足预定条件时，根据预设策略控制高边管及低边管输出特定的驱动波形；
    其中，所述预设策略包括：配置高边管工作于闭环状态，高边管的脉冲宽度调制PWM驱动波形占空比由电路环路确定，配置低边管工作于开环状态，在一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，高边管与低边管的开关周期相同且同步。
  2. 如权利要求1所述的方法，其中，所述预设策略还包括：每间隔N个开关周期之后，在第N+1个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在第N+1个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，N为大于或等于0的整数。
  3. 如权利要求1或2所述的方法，其中，所述预设策略还包括：在一个开关周期内，低边管的开通时长小于或等于该开关周期时长的10％。
  4. 如权利要求1或2所述的方法，其中，当在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管时，所述预设策略还包括：在该开关周期内，高边管的最大开通时长、高边管的开通死区时长、低边管的开通时长以及低边管的开通死区时长之和等于该开关周期时长。
  5. 如权利要求1所述的方法，其中，所述预定条件包括：
    高边管及低边管所在电路的输入电压低于阈值；或，
    高边管及低边管所在电路的输入极性为负。
  6. 一种高低边自举驱动控制装置，包括：
    检测模块，设置为：检测高边管及低边管所在电路的电路特性；
    控制模块，设置为：当所述电路特性满足预定条件时，根据预设策略控制高边管及低边管输出特定的驱动波形；
    其中，所述预设策略包括：配置高边管工作于闭环状态，高边管的脉冲宽度调制PWM驱动波形占空比由电路环路确定，配置低边管工作于开环状态，在一个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，高边管与低边管的开关周期相同且同步。
  7. 如权利要求6所述的装置，其中，所述预设策略还包括：每间隔N个开关周期之后，在第N+1个开关周期内，在比该开关周期起始时刻晚第一预定时长的时刻导通低边管，在高边管的开通时刻前关断低边管，或者，在第N+1个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管，其中，N为大于或等于0的整数。
  8. 如权利要求6或7所述的装置，其中，所述预设策略还包括：在一个开关周期内，低边管的开通时长小于或等于该开关周期时长的10％。
  9. 如权利要求6或7所述的装置，其中，当在一个开关周期内，在高边管的关断时刻后导通低边管，在比该开关周期结束时刻早第二预定时长的时刻关断低边管时，所述预设策略还包括：在该开关周期内，高边管的最大开通时长、高边管的开通死区时长、低边管的开通时长以及低边管的开通死区时长之和等于该开关周期时长。
  10. 如权利要求6所述的装置，其中，所述预定条件包括：
    高边管及低边管所在电路的输入电压低于阈值；或，
    高边管及低边管所在电路的输入极性为负。
  11. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被执行时实现权利要求1至5任一项所述的方法。
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