WO2016176923A1 - 一种时钟校准方法、装置及计算机存储介质 - Google Patents

一种时钟校准方法、装置及计算机存储介质 Download PDF

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Publication number
WO2016176923A1
WO2016176923A1 PCT/CN2015/086545 CN2015086545W WO2016176923A1 WO 2016176923 A1 WO2016176923 A1 WO 2016176923A1 CN 2015086545 W CN2015086545 W CN 2015086545W WO 2016176923 A1 WO2016176923 A1 WO 2016176923A1
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Prior art keywords
clock
physical layer
calibration
high frequency
signal
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PCT/CN2015/086545
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English (en)
French (fr)
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马虹霞
卢海涛
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深圳市中兴微电子技术有限公司
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Publication of WO2016176923A1 publication Critical patent/WO2016176923A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements

Definitions

  • the invention relates to a clock management technology in the field of wireless communication, and in particular to a clock calibration method, device and computer storage medium.
  • the clock In the chip design of a mobile terminal such as a mobile phone terminal, the clock is the most important and special signal of the whole circuit, and most of the devices in the terminal work according to the edge of the clock in the chip, so if the clock in the chip and The deviation of the network reference time base will bring about a series of problems such as data loss, network real-time time base synchronization anomaly, system hang, etc., which will eventually lead to the mobile terminal not searching for the serving cell. Therefore, the clock source provided by the mobile terminal is required to have high precision and stability.
  • a mobile terminal chip such as Time Division-Synchronous Code Division Multiple Access (TD-SCDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), Long Term Evolution), or include Global System for Mobile Communication (GSM)/General Packet Radio Service (GPRS)/Enhanced Data Rate for GSM (EDGE, Enhanced Data Rate for GSM)
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • EDGE Enhanced Data Rate for GSM
  • the 32K clock is used as the reference normally open clock; after the physical layer (PHY) completes the paging reception, the physical layer clock is immediately turned off and goes to sleep.
  • the tracking time count of the network real-time time base is realized by the 32K clock, and when the physical layer clock is awakened, the 32K clock sends the real-time time base count value to the physical layer clock, thereby ensuring The physical layer clock can be synchronized to the network reference time base.
  • the 32K clock jitter is large, sleeping The sleep calibration effect is not good.
  • the real-time time base deviation of the reloaded network after the clock is awakened is large, and the mobile terminal often cannot search the service area, and the user experience is extremely poor.
  • Embodiments of the present invention are expected to provide a clock calibration method, apparatus, and computer storage medium, which can improve clock calibration accuracy and stability, and ensure normal operation of the mobile terminal.
  • the embodiment of the invention provides a clock calibration method, including:
  • the physical layer clock is adjusted according to the high frequency clock calibration signal, and the calibration factor is obtained according to the reference clock signal and the high frequency clock calibration signal;
  • the network real-time time base is tracked and counted under the reference clock signal, and the tracking count value is adjusted according to the calibration factor;
  • the tracking count value is loaded to the physical layer clock, and the loaded physical layer clock is counted under the high frequency clock calibration signal.
  • the adjusting the physical layer clock according to the high frequency clock calibration signal includes:
  • the high frequency calibration request is turned on
  • the physical layer clock is controlled to enter a high frequency calibration phase
  • the high frequency clock signal is turned off, and the physical layer clock count value is saved.
  • the reference clock signal is a 32K low frequency clock signal.
  • the tracking count value is loaded to the physical layer clock, and the loaded physical layer clock is counted under the high frequency clock calibration signal, including:
  • Adjusting the new physical layer clock under the high frequency clock calibration signal to make the adjusted The new physical layer clock is consistent with the frequency of the high frequency clock calibration signal
  • the adjusted new physical layer clock is used to count the network real-time time base under the high-frequency clock calibration signal, so that the adjusted physical layer clock is synchronized with the network real-time time base.
  • the embodiment of the invention further provides a clock calibration device, the device comprising: a high frequency calibration unit, a clock control unit and a clock unit;
  • the clock unit is configured to provide a high frequency clock calibration signal and a reference clock signal for a physical layer under the multimode baseband chip;
  • the high frequency calibration unit is configured to adjust the physical layer clock according to the high frequency clock calibration signal provided by the clock unit before the physical layer enters a sleep state, and according to the reference clock signal and the The high frequency clock calibration signal obtains a calibration factor; after the physical layer enters a sleep state, the network real time base is tracked and counted under the reference clock signal, and the tracking count value is adjusted according to the calibration factor; the physical layer is After waking up, the tracking count value is loaded to the physical layer clock, and the loaded physical layer clock is counted under the high frequency clock calibration signal;
  • the clock control unit is configured to control the turning on and off of the clock unit and the frequency of the clock unit output signal.
  • the high frequency calibration unit is configured to enable a high frequency calibration request before the physical layer enters a sleep state; and after the high frequency calibration request is allowed, control the physical layer to enter a high frequency calibration After the high frequency calibration phase is completed, the high frequency clock signal is turned off, and the physical layer clock count value is saved.
  • the high frequency calibration unit is configured to load the tracking count value to the physical layer clock to obtain a new physical layer clock; and the new physical layer clock is in the high frequency clock. Adjusting the calibration signal so that the adjusted new physical layer clock coincides with the high frequency clock calibration signal frequency; and the adjusted new physical layer clock counts the network real-time time base under the high frequency clock calibration signal And adjusting the adjusted physical layer clock to the network in real time Time base synchronization.
  • the device further includes: a main control unit, configured to complete interaction management of software and hardware.
  • the main control unit is an ARM processor.
  • the clock unit includes a phase locked loop circuit, a clock dynamic switching circuit, and a clock gating circuit.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the clock calibration method according to the embodiment of the invention.
  • the clock calibration method and device and the computer storage medium calibrate the mobile terminal by the high frequency clock calibration signal before the mobile terminal enters the sleep state; after the mobile terminal enters the sleep state, the reference clock signal pair
  • the network real-time time base tracking counting method is used to perform cyclic calibration on various stages of the physical layer of the mobile terminal. In this way, by adopting a calibration method for switching between the high-frequency clock calibration signal and the reference clock signal, it is ensured that the physical layer can be synchronized with the network real-time time base before entering the sleep state and after being woken up, overcoming the multi-mode baseband chip.
  • a single 32K clock signal is used as the reference clock signal, the mobile terminal cannot search for the service area due to the poor calibration effect under the temperature drift interference, thereby improving the clock calibration accuracy and stability, and ensuring the normal operation of the mobile terminal. .
  • the mobile terminal main control system can set the physical layer, the high frequency clock and the reference clock, and other resources other than the non-powerable power partition before the physical layer of the mobile terminal enters the sleep state. Turning off, thus, the power consumption control can be made more flexible, and the power consumption is greatly reduced while satisfying the calibration effect.
  • the timing of switching the clock from the reference clock to the high-frequency clock is more flexible, and the lock signal of the phase-locked loop circuit can be simultaneously supported or the switching instruction can be issued according to the software configuration count of the mobile terminal main control system.
  • Conditional switch command Software decision making is simple and flexible.
  • the switching between the high-frequency calibration signal and the main clock signal of the calibration signal is completely completed by hardware, without the intervention of the main control system software, and
  • the clock signal output to the main control system during the entire switching process is stable and glitch free.
  • FIG. 1 is a schematic flowchart of an implementation process of a clock calibration method according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a clock calibration apparatus according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a structure of a clock calibration apparatus according to an embodiment of the present invention when an main control unit is an ARM processor;
  • FIG. 4 is a schematic diagram showing the principle of operation of part of the ARM processor circuit in the clock calibration process
  • FIG. 5 is a schematic flowchart of a high frequency calibration process in a physical layer clock of a mobile terminal
  • FIG. 6 is a schematic diagram showing the specific structure of a phase-locked loop circuit in the case of three external master clocks
  • FIG. 7 is a control timing diagram of the phase locked loop circuit of FIG. 6;
  • FIG. 8 is a schematic diagram showing the relationship between the control timing chart of the phase locked loop circuit of FIG. 7 and the selection of the clock.
  • the physical layer in the mobile phone chip is woken up, and the mobile phone paging function is activated; after the paging ends, the physical layer in the mobile phone chip is turned off to enter a sleep state; When the phone activates other functions again, the physical layer will wake up again. It can be seen that the physical layer of the mobile terminal experiences a loop process of sleeping state, being awakened, and then going to sleep state. When the physical layer is woken up, it may be out of sync with the network real-time time base, and the network real-time time base is not synchronized. Affects the execution of the functions of the mobile terminal, therefore, the physical layer clock needs to be calibrated in the above process.
  • the physical layer clock is adjusted according to the high-frequency clock calibration signal, and a calibration factor is obtained according to the reference clock signal and the high-frequency clock calibration signal; After the layer enters the sleep state, the network real-time time base is tracked and counted under the reference clock signal; and the tracking count value is adjusted according to the calibration factor; after the physical layer is awakened, the tracking count value is loaded. To the physical layer clock, the loaded physical layer clock is counted under the high frequency clock calibration signal.
  • the mobile phone terminal is taken as an example to cooperate with the function and use process of the mobile phone terminal.
  • FIG. 1 is a schematic flowchart of a clock calibration method according to an embodiment of the present invention.
  • a clock calibration method provided by an embodiment of the present invention includes:
  • Step 101 Before the physical layer under the multimode baseband chip enters a sleep state, adjust the physical layer clock according to the high frequency clock calibration signal, and obtain a calibration factor according to the reference clock signal and the high frequency clock calibration signal.
  • the physical layer of the mobile terminal chip will enter a sleep state; correspondingly, before the physical layer enters a sleep state, the following operations may be performed:
  • the high frequency calibration request is started by the physical layer of the mobile terminal chip, and when the high frequency calibration request is allowed by the mobile terminal chip master control system, the physical layer is controlled to enter a high frequency calibration phase;
  • the physical layer sends a high frequency calibration end signal to the main control system, and the main control system turns off the high frequency clock signal to save the physical layer count value.
  • a calibration factor is obtained according to the reference clock signal and the high frequency clock calibration signal; where the calibration factor is a ratio of the high frequency clock to the reference clock, when the reference clock is a 32K clock, The calibration factor is the ratio of the high frequency clock to the 32K clock.
  • Step 102 After the physical layer enters the sleep state, the real-time time base of the network is performed under the reference clock signal. A tracking count is performed and the tracking count value is adjusted according to the calibration factor.
  • the physical layer of the mobile terminal chip enters a sleep state, and the mobile terminal chip master system performs tracking and counting on the network real-time time base under the reference clock signal, and according to the calibration factor obtained in step 101.
  • the tracking count value is calibrated at any time; here, calibrating the tracking count value with the calibration factor may be performed by superimposing a calibration factor on the tracking count value when each rising edge of the reference clock comes, thereby obtaining a new tracking count value.
  • Step 103 After the physical layer is awakened, the tracking count value is loaded to the physical layer clock, and the loaded physical layer clock is counted under the high frequency clock calibration signal.
  • the physical layer of the mobile terminal chip is woken up by the mobile terminal chip master control system, and after the physical layer is woken up, the loading step 102 adjusts the tracking count value according to the calibration factor to the location.
  • the physical layer clock is described, and the loaded physical layer clock continues to be counted under the high frequency clock calibration signal.
  • the loading the tracking count value to the physical layer clock, and the loaded physical layer clock counting under the high frequency clock calibration signal may include the following operations:
  • the tracking count value in step 102 is loaded to the physical layer clock count value saved in step 101 to obtain a new physical layer clock.
  • the mobile terminal chip master control system adjusts the new physical layer clock under the high frequency clock calibration signal, so that the adjusted new physical layer clock is consistent with the high frequency clock calibration signal frequency.
  • the mobile terminal chip master system counts the adjusted new physical layer clock to the network real-time time base under the high-frequency clock calibration signal, so that the adjusted physical layer clock and the network are real-time. Time base synchronization.
  • the main control system will repeatedly perform the process according to the state of the physical layer to achieve timely calibration of the physical layer clock.
  • the reference clock signal It is a 32K low frequency clock signal.
  • the clock calibration method provided by the embodiment of the invention can ensure that the physical layer can synchronize with the real-time time base of the network before entering the sleep state and after being awake by adopting a calibration manner of switching between the high-frequency clock calibration signal and the reference clock signal. It overcomes the problem that the mobile terminal can not search the service area caused by the poor calibration effect caused by the single clock signal as the reference clock signal under the multi-mode baseband chip, thereby improving the clock calibration accuracy and stability and ensuring the clock calibration accuracy and stability. The normal operation of the mobile terminal.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the clock calibration method according to the embodiment of the invention.
  • the embodiment of the invention also provides a clock calibration device.
  • the clock calibration apparatus provided by the embodiment of the present invention includes: a high frequency calibration unit 21, a clock control unit 22, and a clock unit 23;
  • the clock unit 23 is configured to provide a high frequency clock calibration signal and a reference clock signal for a physical layer under the multimode baseband chip;
  • the high frequency calibration unit 21 is configured to adjust the physical layer clock according to the high frequency clock calibration signal provided by the clock unit before the physical layer enters a sleep state, and according to the reference clock signal and high
  • the frequency clock calibration signal obtains a calibration factor; after the physical layer enters a sleep state, the network real-time time base is tracked and counted under the reference clock signal, and the tracking count value is adjusted according to the calibration factor; the physical layer is awakened Afterwards, the tracking count value is loaded to the physical layer clock, and the loaded physical layer clock is counted under the high frequency clock calibration signal;
  • the clock control unit 22 is configured to control the turning on and off of the clock unit and the frequency of the clock unit output signal.
  • the high frequency calibration unit 21 and the clock control unit in the clock calibration apparatus In practical applications, the central processing unit (CPU), the digital signal processor (DSP), or the Field-Programmable Gate Array (FPGA) can be implemented in the device. .
  • CPU central processing unit
  • DSP digital signal processor
  • FPGA Field-Programmable Gate Array
  • the clock unit may include a phase locked loop circuit (PLL), a clock dynamic switching circuit, and a clock gating circuit.
  • PLL phase locked loop circuit
  • the clock calibration device shown in FIG. 2 can be disposed in a mobile terminal (such as a mobile phone or the like). Based on the clock calibration device, after the mobile terminal completes the paging function, the physical layer will enter a sleep state. Before entering the sleep state, the high frequency calibration unit 21 of the mobile terminal adjusts the physical layer clock under the high frequency clock calibration signal provided by the clock unit 23, according to the reference clock signal and the high frequency clock calibration signal provided by the clock unit 23. Obtaining a calibration factor, after which the physical layer enters a sleep state; after the physical layer enters a sleep state, the high frequency calibration unit 21 of the mobile terminal tracks the real-time time base of the network under the reference clock signal provided by the clock unit 23.
  • the high frequency calibration unit 21 loads the tracking count value to the physical layer after the physical layer is woken up. Clock, the loaded physical layer clock is counted under the current high frequency clock calibration signal.
  • the reference clock is typically a 32K clock and can be provided by an off-chip crystal.
  • the clock calibration apparatus of the embodiment of the present invention may further include: a main control unit configured to complete interaction management of software and hardware; and the main control unit may be an ARM processor.
  • the clock calibration apparatus of the embodiment of the present invention may further include: a multi-mode communication processing unit configured to process protocol data of the preset communication mode to complete uplink and downlink reception of data or instructions; the multi-mode communication processing unit may be configured Modem modem.
  • the clock calibration apparatus provided by the embodiment of the invention can ensure that the physical layer can synchronize with the real-time time base of the network before entering the sleep state and after being awake by adopting a calibration manner of switching between the high-frequency clock calibration signal and the reference clock signal. , which improves the accuracy and stability of clock calibration Degree, to ensure the normal operation of the mobile terminal.
  • the clock calibration apparatus in the embodiment of the present invention can turn off the physical layer, the high frequency clock and the reference clock, and other resources other than the non-powerable power partition before the physical layer enters the sleep state. Power consumption control is more flexible, and the power consumption is greatly reduced while satisfying the calibration effect. Moreover, the timing of switching from the reference clock to the high-frequency clock is more flexible, and can simultaneously support the lock signal of the phase-locked loop circuit or issue a switching instruction according to the software configuration count of the mobile terminal main control system, and specifically use which condition to issue the switching command. The decision is made by the main control system software, which is simple and flexible.
  • the high frequency calibration unit 21 is configured to enable a high frequency calibration request before the physical layer enters a sleep state; after the high frequency calibration request is allowed, the physical layer is controlled to enter a high frequency calibration phase; After the high frequency calibration phase is completed, the high frequency clock signal is turned off, and the physical layer clock count value is saved.
  • the physical layer will enter a sleep state, and before entering the sleep state, the high frequency calibration unit 21 of the mobile terminal turns on the high frequency calibration request, and after the high frequency calibration request is allowed,
  • the physical layer clock enters a high frequency calibration phase under the high frequency clock calibration signal provided by the clock unit 23; after the high frequency calibration phase is completed, the high frequency clock signal is turned off, and the physical layer count value is saved. .
  • the physical layer enters a sleep state.
  • the high frequency calibration unit 21 of the mobile terminal after the physical layer enters a sleep state, under the reference clock signal provided by the clock unit 23, Tracking and counting the network real-time time base.
  • the high-frequency calibration unit 21 after the physical layer is woken up, according to the tracking count value and the current high-frequency clock calibration signal. Calibrate the physical layer clock.
  • the high frequency calibration unit 21 is configured to load the tracking count value to the physical layer clock to obtain a new physical layer clock; and the new physical layer clock is at the high frequency Adjusting under the clock calibration signal to make the adjusted new physical layer clock and the high frequency
  • the clock calibration signal has the same frequency; the adjusted new physical layer clock counts the network real-time time base under the high-frequency clock calibration signal, so that the adjusted physical layer clock is synchronized with the network real-time time base.
  • the clock calibration apparatus in this embodiment includes: an ARM processor 31, a clock control circuit 33, a high frequency calibration circuit 35, and a multimode modem. 32 and PLL 34;
  • the clock calibration device shown in FIG. 3 is disposed in a mobile terminal (such as a mobile phone). Based on the clock calibration device, after the mobile terminal completes the paging function, the physical layer will enter a sleep state, and before entering the sleep state, the mobile terminal The high frequency calibration circuit 35 adjusts the physical layer clock under the high frequency clock calibration signal provided by the mobile PLL 34, and the physical layer enters a sleep state after the adjustment is completed;
  • the high frequency calibration circuit 35 of the mobile terminal After the physical layer enters the sleep state, the high frequency calibration circuit 35 of the mobile terminal performs tracking and counting on the network real-time time base under the reference clock signal, and the high frequency calibration is performed when the mobile terminal performs other functions again to make the physical layer wake up.
  • the circuit 35 loads the tracking count value to the physical layer clock after the physical layer is woken up, and the loaded physical layer clock counts under the current high frequency clock calibration signal.
  • the clock calibration apparatus since the clock calibration apparatus is applied to a mobile terminal, the mobile terminal itself has a reference 32K clock, and the reference clock signal can be provided by a 32K reference clock, and therefore, in the present embodiment, the reference clock signal is referenced by the mobile terminal 32K The clock is provided.
  • the physical layer (PHY) layer of the ARM processor 31 is used to run the physical layer software and the physical layer algorithm digital signal processing, and the physical layer protocol.
  • a stack (PS, Protocol Stack) is used to run the multimode protocol stack software.
  • the main control processor in the ARM processor 31 is used to assist the low power in the ARM processor 31.
  • the power consumption control circuit performs low power management, particularly on-site save and recovery when the common resource is powered off;
  • the clock control circuit 33 is configured to control the power-up and power-down timing of the PLL 34, clock circuit selection, gating, and Parameterized configuration, etc.;
  • the PLL 34 is configured to provide a high frequency clock for system operation;
  • the path 35 is configured to complete the control of the calibration process during the physical layer sleep;
  • the multimode modem 32 is configured to process the protocol data of the preset communication mode to complete the uplink and downlink reception of the data/instruction.
  • the system refers to a master control system of the mobile terminal.
  • the physical circuit calibration process is briefly introduced by taking the specific circuit of the ARM processor 31 and the high frequency calibration unit as an example. As shown in FIG. 4, the PCU 42 of the ARM processor 31 controls the power consumption of the chip to reduce the power consumption of the chip; the multimode TPU 44 of the high frequency calibration circuit 35 refers to the event processing circuit under the multimode baseband chip, and is configured.
  • the physical layer is calibrated under the high frequency clock calibration signal;
  • the multimode LPM 43 in the high frequency calibration circuit 35 refers to the sleep circuit, configured to be in the physical layer after entering the sleep state, at 32k
  • the tracking count of the network real-time time base under the reference clock signal reloads the tracking count value to the multi-mode TPU 44 in the high frequency calibration circuit 35 when the physical layer is woken up.
  • the ARM processor 31 When the ARM processor 31 is used as the main control unit, the specific circuit of FIG. 4 is matched. Correspondingly, the high frequency calibration process is as shown in FIG. 5.
  • the PHY core 45 When the PHY core 45 is working normally, the PLL 41 is turned on to provide the high frequency clock, and the PHY core 45 is completed. After the paging is received, all clocks except the physical layer multimode TPU 44 operating clock are turned off, the PHY core 45 is configured to be calibrated, the high frequency calibration request is initiated, the system enters the high frequency calibration phase, and the multimode TPU 44 performs the high frequency calibration operation. The system waits for the calibration end signal.
  • the PCU 42 After receiving the calibration completion flag, it closes the high frequency clock gating used for multimode TPU 44 calibration, then turns off the physical layer PLL 41, and then completes other processes of power management, and the system goes to sleep;
  • the PCU 42 enters the wake-up flow, thereby controlling the power consumption of the mobile terminal chip, after which the physical layer PLL 41 is turned on, wherein the physical layer PLL 41 is determined by the system configuration whether to open in the wake-up process. If not turned on at this time, the subsequent PHY core 45 can also open the physical layer PLL 41 by means of a software configuration register, after which the PHY core 45 is awakened, the mobile terminal Kai paging function.
  • a phase-locked loop circuit in the case of three external master clock signals is provided, which is briefly described in conjunction with a specific clock control circuit.
  • the first stage PLL is configured to output an accurate reference clock as the reference clock of the second stage PLL, and the reasonable parameters are configured.
  • the second stage PLL outputs the physical layer to work high. Frequency clock.
  • the main clock 3 is selected, the first stage PLL is turned off, and the second stage PLL outputs the accurate clock required by the multimode modem; the PLL output high frequency clock is selected and gated to the multimode modem after being gated.
  • the PLL in conjunction with the clock control circuit given in this embodiment, in the process of controlling the phase-locked loop circuit, associated with turning on or off the clock, after the PLL is powered on and the physical layer is woken up, the PLL is powered off before the physical layer sleeps.
  • the PLL power-on and control signal PD is first sent to the clock selection portion of FIG. 6, and is fed back to the direct connection end of the PLL through the PLL PD control logic, thereby completing the entire process.
  • FIG. 7 is a PD control timing diagram of PLL1 and PLL2 in FIG. 6.
  • the PD signal of PLL1 is always high, and after the system issues an instruction to turn off the physical layer PLL, the hardware automatically completes the high frequency first.
  • the clock is dynamically switched to the master clock before the PLL2 is finally turned off.
  • PLL2 immediately turns on. If a two-stage PLL cascade is used and the system issues an instruction to turn off the physical layer PLL, the hardware automatically switches the high-frequency clock to the master clock dynamically, and then turns off both PLL1 and PLL2.
  • PLL1 When the system asks to turn on the physical layer PLL, PLL1 immediately Turn on, wait for PLL1 to lock for a while, then turn on PLL2, the whole power-on and power-down timing hardware is automatically completed.
  • the command signal sent by the system to the PLL is not directly sent to the PD end of the PLL, but is sent to the dynamic selector that provides the clock source for processing, and then fed back to control the PLL operation.
  • the opening of PLL2 depends on the lock signal of PLL1.
  • the switching timing of the clock selection circuit from low frequency to high frequency also depends on the lock of PLL2.
  • the PLL2 on and clock selection are processed according to the lock signal.
  • the initial value of the low level is counted after the T0 time and begins to count down. If the initial value of the count is set to be larger than the actual lock time period of the PLL, then The mobile terminal will also count for a period of time after the lock is locked.
  • the sel is turned on to turn on the PLL 2 or start.
  • the calibration factor that is, the high-frequency clock and the 32k ratio can be closer to the actual situation, so that the temperature drift can be overcome and a better calibration effect can be achieved. Therefore, the mobile terminal can not only find the service area in real time, but also reduce power consumption, the user experience is good, and the product form is relatively competitive.
  • the physical layer working command sent by the mobile terminal is sent to the dynamic clock selection circuit for processing, and then fed back to the mobile terminal for processing to finally control the physical layer.
  • the mobile terminal issues an instruction to turn off the physical layer, that is, pd_in goes high.
  • the system first turns off the high frequency clock, and simultaneously pulls up the pd_out signal that finally controls the physical layer clock to turn off, and then turns on the low frequency main clock to complete the high frequency. Switching from clock to low frequency master clock, the entire clock switching process is done automatically by hardware, the output clock is stable without glitch and no software intervention is required.
  • the clock calibration method and device provided by the embodiments of the present invention can not only improve the clock calibration accuracy and stability, but also ensure the normal operation of the mobile terminal; and can also make the power consumption control more flexible, and make the work while satisfying the calibration effect. The consumption is greatly reduced.
  • the embodiment of the present invention is more flexible in designing the timing of switching the clock from the reference clock to the high-frequency clock, and the implementation is simple; the switching between the clock signals is completed by hardware, without the intervention of the main control system software, and the clock signal during the entire switching process can be guaranteed. Stable without burrs.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the present invention is directed to a method, apparatus (system), and computer program in accordance with an embodiment of the present invention
  • the flow chart and/or block diagram of the product is described. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG.
  • These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the embodiment of the invention can ensure that the physical layer can synchronize with the network real-time time base before entering the sleep state and after being awake, thereby overcoming the multi-mode baseband.
  • the single 32K clock signal is used as the reference clock signal under the chip, the mobile terminal can not search the service area due to the poor calibration effect caused by the temperature drift interference, thereby improving the clock calibration accuracy and stability, and ensuring the mobile terminal. normal work.

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Abstract

本发明实施例公开一种时钟校准方法，包括：多模基带芯片下的物理层进入睡眠状态前，根据高频时钟校准信号调整所述物理层时钟，并根据基准时钟信号和所述高频时钟校准信号获得校准因子；所述物理层进入睡眠状态后，在基准时钟信号下对网络实时时基进行跟踪计数，并根据所述校准因子调整跟踪计数值；所述物理层被唤醒后，将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数。本发明实施例还同时公开一种时钟校准装置及计算机存储介质。

Description

一种时钟校准方法、装置及计算机存储介质 技术领域
本发明涉及无线通讯领域中时钟管理技术，尤其涉及一种时钟校准方法、装置及计算机存储介质。
背景技术
在移动终端如手机终端的芯片设计中，时钟是整个电路最重要、最特殊的信号，终端内大部分器件的工作都要依附于芯片中时钟的跳变沿进行，因此，如果芯片中时钟和网络基准时基产生偏差，就会带来数据丢失、网络实时时基同步异常、系统挂死等一系列问题，最终会导致移动终端搜索不到服务小区。如此，就要求移动终端所提供的时钟源需要有较高的精度和稳定度。
现有技术中，移动终端芯片如时分同步码分多址(TD-SCDMA，Time Division-Synchronous Code Division Multiple Access)、宽带码分多址(WCDMA，Wideband Code Division Multiple Access)、长期演进(LTE，Long Term Evolution)、或者包括全球移动通信系统(GSM，Global System for Mobile Communication)/通用分组无线服务技术(GPRS，General Packet Radio Service)/增强型数据速率GSM演进技术(EDGE，Enhanced Data Rate for GSM Evolution)的GGE(GSM/GPRS/EDGE)多模基带芯片中，均采用32K时钟作为基准常开时钟；物理层(PHY)完成寻呼接收后，物理层时钟会立刻关闭进入睡眠状态。在物理层时钟处于睡眠状态过程中，通过32K时钟实现对网络实时时基的跟踪计数，而当物理层时钟被唤醒时，32K时钟将实时时基计数值发送给物理层时钟，以此来保证物理层时钟能够与网络基准时基同步。但是，由于温漂的存在，使得32K时钟抖动较大，睡 眠校准效果不佳，时钟被唤醒后重新加载的网络实时时基偏差较大，移动终端常会搜索不到服务区，用户体验极差。
发明内容
本发明实施例期望提供一种时钟校准方法、装置及计算机存储介质，能提高时钟校准精度和稳定度，保证移动终端的正常工作。
为实现上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种时钟校准方法，包括：
多模基带芯片下的物理层进入睡眠状态前，根据高频时钟校准信号调整物理层时钟，并根据基准时钟信号和所述高频时钟校准信号获得校准因子；
所述物理层进入睡眠状态后，在所述基准时钟信号下对网络实时时基进行跟踪计数，并根据所述校准因子调整跟踪计数值；
所述物理层被唤醒后，将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数。
作为一种实施方式，所述根据高频时钟校准信号调整所述物理层时钟，包括：
所述物理层进入睡眠状态前，开启高频校准请求；
所述高频校准请求被允许后，控制所述物理层时钟进入高频校准阶段；
所述高频校准阶段完成后，关闭高频时钟信号，保存所述物理层时钟计数值。
作为一种实施方式，所述基准时钟信号为32K低频时钟信号。
作为一种实施方式，所述将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数，包括：
将所述跟踪计数值加载到所述物理层时钟，得到新的物理层时钟；
将所述新的物理层时钟在所述高频时钟校准信号下调整，使调整后的 新的物理层时钟与所述高频时钟校准信号频率一致；
将调整后的新的物理层时钟在所述高频时钟校准信号下对网络实时时基进行计数，使所述调整后的物理层时钟与所述网络实时时基同步。
本发明实施例还提供了一种时钟校准装置，所述装置包括：高频校准单元、时钟控制单元和时钟单元；
所述时钟单元，配置为为多模基带芯片下的物理层提供高频时钟校准信号和基准时钟信号；
所述高频校准单元，配置为在所述物理层进入睡眠状态前，根据所述时钟单元提供的所述高频时钟校准信号调整所述物理层时钟，并根据所述基准时钟信号和所述高频时钟校准信号获得校准因子；所述物理层进入睡眠状态后，在所述基准时钟信号下对网络实时时基进行跟踪计数，并根据所述校准因子调整跟踪计数值；所述物理层被唤醒后，将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数；
所述时钟控制单元，配置为控制所述时钟单元的开启和关闭以及所述时钟单元输出信号的频率。
作为一种实施方式，所述高频校准单元，配置为在所述物理层进入睡眠状态前，开启高频校准请求；所述高频校准请求被允许后，控制所述物理层进入高频校准阶段；所述高频校准阶段完成后，关闭高频时钟信号，保存所述物理层时钟计数值。
作为一种实施方式，所述高频校准单元，配置为将所述跟踪计数值加载到所述物理层时钟，得到新的物理层时钟；将所述新的物理层时钟在所述高频时钟校准信号下调整，使调整后的新的物理层时钟与所述高频时钟校准信号频率一致；将调整后的新的物理层时钟在所述高频时钟校准信号下对网络实时时基进行计数，使所述调整后的物理层时钟与所述网络实时 时基同步。
作为一种实施方式，所述装置还包括：主控单元，配置为完成软硬件的交互管理。
作为一种实施方式，所述主控单元为ARM处理器。
作为一种实施方式，所述时钟单元包括锁相环电路、时钟动态切换电路、时钟门控电路。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的时钟校准方法。
本发明实施例提供的时钟校准方法、装置及计算机存储介质，通过在移动终端进入睡眠状态前，由高频时钟校准信号对移动终端进行校准；在移动终端进入睡眠状态后，以基准时钟信号对网络实时时基跟踪计数方式，来对移动终端物理层的各个阶段进行循环校准。如此，通过采用在高频时钟校准信号以及基准时钟信号之间转换的校准方式，可以保证物理层在进入睡眠状态前和被唤醒后都能够与网络实时时基同步，克服了多模基带芯片下以单一32K时钟信号作为基准时钟信号时在温漂的干扰下校准效果不佳带来的移动终端搜索不到服务区的问题，进而提高了时钟校准精度和稳定度，保证了移动终端的正常工作。
本发明实施例中，在移动终端的物理层进入睡眠状态前的高频校准阶段，移动终端主控系统可以将物理层、高频时钟和基准时钟、以及不可关断电源分区以外的其它资源都关闭，由此，可使功耗控制更加灵活，在满足校准效果的同时，使功耗极大降低。
本发明实施例中，时钟从基准时钟向高频时钟切换的时机设计更加灵活，可以同时支持锁相环电路的锁定信号或者根据移动终端主控系统软件配置计数来发出切换指令，具体使用哪种条件发出切换命令，由主控系统 软件决策，实现简单灵活。
本发明实施例中，移动终端的主控系统在发出打开或者关闭物理层指令后，校准信号在高频校准信号和主时钟信号间的切换纯粹由硬件完成，无须主控系统软件干预，而且在整个切换过程中输出给主控系统的时钟信号稳定无毛刺。
附图说明
图1为本发明实施例提供的时钟校准方法的实现流程示意图；
图2为本发明实施例提供的时钟校准装置的组成结构示意图；
图3为本发明实施例提供的时钟校准装置的主控单元为ARM处理器时的组成结构示意图；
图4为ARM处理器部分电路在时钟校准过程中的作用原理示意图；
图5为手机终端物理层时钟中高频校准过程实现的流程示意图；
图6为锁相环电路在有三个外部主时钟的情况下的具体结构示意图；
图7为图6中的锁相环电路的控制时序图；
图8为图7锁相环电路的控制时序图与时钟的选择的关系示意图。
具体实施方式
通常，移动终端在使用过程中，例如手机在执行寻呼功能时，手机芯片中的物理层被唤醒，手机寻呼功能启动；寻呼结束后，手机芯片中的物理层关闭进入睡眠状态；当手机再次启用其它功能时，物理层会再次被唤醒。可见，移动终端的物理层会经历睡眠状态、被唤醒、再进入睡眠状态这样的循环过程，物理层在被唤醒时可能会与网络实时时基不同步，与网络实时时基不同步就会直接影响移动终端功能的执行，因此，在上述过程中物理层时钟需要校准。
正是为了保证物理层在睡眠被唤醒后能保持与网络实时时基同步，本 发明实施例中，在多模基带芯片下的物理层进入睡眠状态前，根据高频时钟校准信号调整物理层时钟，并根据基准时钟信号和所述高频时钟校准信号获得校准因子；所述物理层进入睡眠状态后，在所述基准时钟信号下对网络实时时基进行跟踪计数；并根据所述校准因子调整所述跟踪计数值；所述物理层被唤醒后，将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数。
下面结合附图和实施例对本发明作进一步的详细说明，本发明实施例中以手机终端为例配合手机终端的功能和使用过程加以说明。
图1为本发明实施例提供的时钟校准方法的实现流程示意图，如图1所示，本发明实施例提供的时钟校准方法包括：
步骤101：多模基带芯片下的物理层进入睡眠状态前，根据高频时钟校准信号调整物理层时钟，并根据基准时钟信号和所述高频时钟校准信号获得校准因子。
这里，移动终端(例如手机)完成寻呼功能后，移动终端芯片物理层将会进入睡眠状态；相应的，在所述物理层进入睡眠状态前，可执行如下操作：
首先，由移动终端芯片物理层开启高频校准请求，当所述高频校准请求被移动终端芯片主控系统允许后，控制所述物理层进入高频校准阶段；
其次，所述高频校准阶段完成后，所述物理层向所述主控系统发出高频校准结束信号，所述主控系统关闭高频时钟信号，保存所述物理层计数值。
同时，根据基准时钟信号和所述高频时钟校准信号获得校准因子；这里，所述校准因子是所述高频时钟与所述基准时钟的比值，当所述基准时钟为32K时钟时，所述校准因子是所述高频时钟与32K时钟的比值。
步骤102：物理层进入睡眠状态后，在基准时钟信号下对网络实时时基 进行跟踪计数，并根据所述校准因子调整跟踪计数值。
这里，移动终端芯片物理层在完成了步骤101后，进入睡眠状态，移动终端芯片主控系统在所述基准时钟信号下，对网络实时时基进行跟踪计数，并根据步骤101中获得的校准因子来随时校准跟踪计数值；这里，用所述校准因子校准跟踪计数值可以采用在每一个基准时钟上升沿到来时，将校准因子叠加到所述跟踪计数值，进而得到新的跟踪计数值。
步骤103：所述物理层被唤醒后，将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数。
这里，移动终端再次执行寻呼功能或者其它功能时，移动终端芯片物理层被移动终端芯片主控系统唤醒，所述物理层被唤醒后，加载步骤102根据校准因子调整后的跟踪计数值到所述物理层时钟，并对加载后的物理层时钟继续在所述高频时钟校准信号下进行计数。
具体地，所述将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数可包括如下操作：
首先，将步骤102中的跟踪计数值加载到步骤101中保存的物理层时钟计数值，得到新的物理层时钟。
其次，移动终端芯片主控系统将所述新的物理层时钟在所述高频时钟校准信号下调整，使调整后的新的物理层时钟与所述高频时钟校准信号频率一致。
最后，移动终端芯片主控系统将所述调整后的新的物理层时钟在所述高频时钟校准信号下对网络实时时基进行计数，使所述调整后的物理层时钟与所述网络实时时基同步。
如此，移动终端在正常运行的过程中，主控系统将会一直根据物理层的状态重复执行所述过程，以达到对物理层时钟的及时校准。
作为一种实施方式，本实施例的时钟校准方法中，所述基准时钟信号 为32K低频时钟信号。
本发明实施例提供的时钟校准方法，通过采用在高频时钟校准信号以及基准时钟信号之间转换的校准方式，可以保证物理层在进入睡眠状态前和被唤醒后都能够与网络实时时基同步，克服了多模基带芯片下以单一时钟信号作为基准时钟信号在温漂的干扰下校准效果不佳带来的移动终端搜索不到服务区的问题，进而提高了时钟校准精度和稳定度，保证了移动终端的正常工作。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的时钟校准方法。
本发明实施例还提供了一种时钟校准装置。如图2所示，本发明实施例提供的时钟校准装置，包括：高频校准单元21、时钟控制单元22和时钟单元23；其中，
所述时钟单元23，配置为为多模基带芯片下的物理层提供高频时钟校准信号和基准时钟信号；
所述高频校准单元21，配置为在所述物理层进入睡眠状态前，根据所述时钟单元提供的所述高频时钟校准信号调整所述物理层时钟，并根据所述基准时钟信号和高频时钟校准信号获得校准因子；所述物理层进入睡眠状态后，在所述基准时钟信号下对网络实时时基进行跟踪计数，并根据所述校准因子调整跟踪计数值；所述物理层被唤醒后，将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数；
所述时钟控制单元22，配置为控制所述时钟单元的开启和关闭以及所述时钟单元输出信号的频率。
本实施例中，所述时钟校准装置中的高频校准单元21和时钟控制单元 22在实际应用中，可通过所述装置中的中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Signal Processor)或可编程门阵列(FPGA，Field－Programmable Gate Array)实现。
这里，所述时钟单元可包括锁相环电路(PLL)、时钟动态切换电路和时钟门控电路。
在实际应用中，图2所示的时钟校准装置可设置于移动终端(例如手机等)中，基于所述时钟校准装置，移动终端在完成寻呼功能后，物理层将会进入睡眠状态，在进入睡眠状态前，移动终端的高频校准单元21在所述时钟单元23提供的高频时钟校准信号下，调整物理层时钟，根据所述时钟单元23提供的基准时钟信号和高频时钟校准信号获得校准因子，之后，所述物理层进入睡眠状态；移动终端的高频校准单元21在物理层进入睡眠状态后，在所述时钟单元23提供的基准时钟信号下，对网络实时时基进行跟踪计数，根据所述校准因子调整所述跟踪计数值，在移动终端再次执行其它功能而物理层被唤醒时高频校准单元21在物理层被唤醒后将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在当前高频时钟校准信号下计数。
这里，所述基准时钟一般是32K时钟，可由片外晶体提供。
本发明实施例的时钟校准装置还可以包括：主控单元，配置为完成软硬件的交互管理；所述主控单元可为ARM处理器。
本发明实施例的时钟校准装置还可以包括：多模通信处理单元，配置为对预设通信模式的协议数据进行处理，完成数据或指令的上下行接收；所述多模通信处理单元可为多模调制解调器(modem)。
本发明实施例提供的时钟校准装置，通过采用在高频时钟校准信号以及基准时钟信号之间转换的校准方式，可以保证物理层在进入睡眠状态前和被唤醒后都能够与网络实时时基同步，从而提高了时钟校准精度和稳定 度，保证了移动终端的正常工作。
本发明实施例中的时钟校准装置，在物理层进入睡眠状态前的高频校准阶段，可将物理层、高频时钟和基准时钟、以及不可关断电源分区以外的其它资源都关闭，以使功耗控制更加灵活，在满足校准效果的同时，使功耗极大降低。并且，从基准时钟向高频时钟切换的时机设计更加灵活，可以同时支持锁相环电路的锁定信号或者根据移动终端主控系统软件配置计数来发出切换指令，具体使用哪种条件发出切换命令，由主控系统软件决策，实现简单灵活。
作为一种实施方式，所述高频校准单元21，配置为在物理层进入睡眠状态前，开启高频校准请求；所述高频校准请求被允许后，控制物理层进入高频校准阶段；所述高频校准阶段完成后，关闭高频时钟信号，保存所述物理层时钟计数值。
具体的，移动终端在完成寻呼功能后，物理层将会进入睡眠状态，在进入睡眠状态前，移动终端的高频校准单元21开启高频校准请求，所述高频校准请求被允许后，在所述时钟单元23提供的高频时钟校准信号下，所述物理层时钟进入高频校准阶段；所述高频校准阶段完成后，关闭所述高频时钟信号，保存所述物理层计数值。高频校准结束后，所述物理层进入睡眠状态，此时，移动终端的所述高频校准单元21在所述物理层进入睡眠状态后，在所述时钟单元23提供的基准时钟信号下，对网络实时时基进行跟踪计数，在移动终端再次执行其它功能而物理层被唤醒时，所述高频校准单元21在所述物理层被唤醒后，根据跟踪计数值与当前高频时钟校准信号校准物理层时钟。
作为一种实施方式，所述高频校准单元21，配置为将所述跟踪计数值加载到所述物理层时钟，得到新的物理层时钟；将所述新的物理层时钟在所述高频时钟校准信号下调整，使调整后的新的物理层时钟与所述高频时 钟校准信号频率一致；将调整后的新的物理层时钟在所述高频时钟校准信号下对网络实时时基进行计数，使所述调整后的物理层时钟与所述网络实时时基同步。
图3为本发明时钟校准装置的一个较佳实施例，如图3所示，本实施例中的时钟校准装置包括：ARM处理器31、时钟控制电路33、高频校准电路35、多模modem 32和PLL 34；
图3所示时钟校准装置设置于移动终端(如手机)中，基于所述时钟校准装置，移动终端在完成寻呼功能后，物理层将会进入睡眠状态，在进入睡眠状态前，移动终端的高频校准电路35在移动PLL 34提供的高频时钟校准信号下，调整物理层时钟，调整结束后物理层进入睡眠状态；
移动终端的高频校准电路35在物理层进入睡眠状态后，在基准时钟信号下，对网络实时时基进行跟踪计数，在移动终端再次执行其它功能使物理层被唤醒时，所述高频校准电路35在物理层被唤醒后将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在当前高频时钟校准信号下计数。这里，因为所述时钟校准装置应用于移动终端，移动终端本身带有基准32K时钟，所述基准时钟信号可以由32K基准时钟提供，因此，在本实施例中基准时钟信号由移动终端的基准32K时钟提供。
由于所述时钟校准装置采用ARM处理器31作为主控单元，所述ARM处理器31中物理层(PHY，Physical Layer)核用来运行物理层软件和物理层算法数字信号处理，物理层的协议栈(PS，Protocol Stack)用来运行多模协议栈软件，除所述PS和所述PHY外，所述ARM处理器31中的主控处理器用来协助所述ARM处理器31中的低功耗控制电路(PCU)完成低功耗管理，特别是公共资源断电时相关的现场保存和恢复；所述时钟控制电路33配置为控制PLL 34的上下电时序、时钟电路的选择、门控和参数化配置等；所述PLL 34配置为提供系统工作的高频时钟；所述高频校准电 路35配置为完成物理层睡眠期间校准流程的控制；所述多模modem 32配置为对预设通信模式的协议数据进行处理，完成数据/指令的上下行接收。这里，所述系统是指移动终端的主控系统。
当采用所述ARM处理器31作为主控单元时，以所述ARM处理器31和高频校准单元的具体电路为例，来简要介绍物理层的校准过程。如图4所示，ARM处理器31的PCU 42控制芯片的功耗，使芯片的功耗降低；高频校准电路35的多模TPU 44指的是多模基带芯片下的事件处理电路，配置为完成物理层进入睡眠状态时，在高频时钟校准信号下对物理层校准；高频校准电路35中的多模LPM 43指的是睡眠电路，配置为物理层在进入睡眠状态后，在32k基准时钟信号下对网络实时时基的跟踪计数，在物理层被唤醒时再将跟踪计数值重新加载到高频校准电路35中的多模TPU 44。
当采用ARM处理器31作为主控单元时配合图4的具体电路，相应的，高频校准流程如图5所示，PHY核45正常工作时，PLL 41打开提供高频时钟，PHY核45完成寻呼接收后，关闭除物理层多模TPU 44工作时钟以外的所有时钟，PHY核45配置校准使能，发起高频校准请求使系统进入高频校准阶段，多模TPU 44进行高频校准工作；系统等待校准结束信号，接收到校准完成标志后，先关闭多模TPU 44校准所用的高频时钟门控，然后关闭物理层PLL 41，再完成功耗管理的其它流程，系统进入睡眠；系统唤醒中断到来时，这里，PCU 42进入唤醒流程，由此，来控制移动终端芯片的功耗，之后，物理层PLL 41打开，其中，物理层PLL 41由系统配置决定是否在唤醒流程中打开，如果此时不打开，后续PHY核45也可以通过软件配置寄存器的方式打开物理层PLL 41，之后，PHY核45被唤醒，移动终端开启寻呼功能。
本实施例中，提供了一种在三个外部主时钟信号情况下的锁相环电路，结合具体的时钟控制电路加以简要说明。如图6所示，在选择主时钟1或 主时钟2时，使用两个PLL进行级联，第一级PLL配置为输出一个准确的基准时钟作为第二级PLL的参考时钟，配置合理的参数，由第二级PLL输出物理层工作的高频时钟。选择主时钟3时，第一级PLL关闭，由第二级PLL输出多模modem所需的准确时钟；PLL输出高频时钟与主时钟1进行选择及门控后送给所述多模modem。
结合本实施例中给出的时钟控制电路，在控制所述锁相环电路的过程中，与打开或者关闭时钟相关联，PLL上电在物理层被唤醒后，PLL下电在物理层睡眠前，PLL上下电控制信号PD是先送入图6中的时钟选择部分，经过PLL PD控制逻辑再反馈到PLL的直接连接端，以此完成整个过程。
图7为图6中PLL1和PLL2的PD控制时序图，如图7所示，若仅使用PLL2，PLL1的PD信号一直为高，系统发出关闭物理层PLL的指令后，硬件先自动完成高频时钟到主时钟的动态切换，然后才最终关闭PLL2，当系统要求打开物理层PLL时，PLL2立刻打开工作。若使用两级PLL级联，系统发出关闭物理层PLL的指令后，硬件先自动完成高频时钟到主时钟的动态切换，然后同时关闭PLL1和PLL2，当系统要求打开物理层PLL时，PLL1立刻打开，等待PLL1锁定一段时间后，再开启PLL2，整个上下电时序硬件自动完成。系统发出PLL的指令信号不是直接送给PLL的PD端，而是先送到提供时钟源的动态选择器中进行处理，之后再反馈回来控制PLL工作。
采用两级PLL级联方法时，PLL2的打开依赖于PLL1的锁定信号，时钟选择电路由低频到高频的切换时机也依赖于PLL2的锁定，PLL2打开和时钟选择都根据锁定信号经过相同处理。如图8所示，移动终端发出打开物理层命令即pd_in变低时，经过T0时间的低电平计数初值并开始递减计数，如果计数初值设置的比PLL实际的锁定时间周期大，则移动终端在锁定之后还会计数一段时间T1待cnt减到0时，拉高sel打开PLL2或者开始 时钟切换，如果计数初值比PLL实际锁定时间短，sel在锁定有效后就立刻拉高，若PLL锁定之后时钟并不是很稳定，设定比锁定时间周期大的计数初值就可以保证装置输出稳定的时钟频率。
本发明实施例通过延长空闲态的高频时钟工作周期，可使校准因子即高频时钟与32k比值更加接近实际情况，这样，就能克服温漂并能取得较好的校准效果。由此，移动终端不仅能实时搜到服务区，而且能降低功耗，用户体验佳，产品形态有较大竞争力。
本发明实施例中，移动终端发出的物理层工作命令会先送到动态时钟选择电路处理，再反馈到移动终端处理后最终控制物理层。当移动终端发出关闭物理层的指令即pd_in变高，如图8所示，系统先关闭高频时钟，同时拉高最终控制物理层时钟关闭的pd_out信号，之后打开低频主时钟，完成从高频时钟到低频主时钟的切换，整个时钟切换过程由硬件自动完成，输出时钟稳定无毛刺且无需软件干预。
通过上述实现过程，本发明实施例提供的时钟校准方法及装置不仅能提高时钟校准精度和稳定度，保证移动终端的正常工作；还能使功耗控制更加灵活，在满足校准效果的同时使功耗极大降低。另外，本发明实施例对时钟从基准时钟向高频时钟切换的时机设计更加灵活，实现简单；时钟信号间的切换由硬件完成，无须主控系统软件干预，且能保证整个切换过程中时钟信号稳定无毛刺。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序 产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例通过采用在高频时钟校准信号以及基准时钟信号之间转换的校准方式，可以保证物理层在进入睡眠状态前和被唤醒后都能够与网络实时时基同步，克服了多模基带芯片下以单一32K时钟信号作为基准时钟信号时在温漂的干扰下校准效果不佳带来的移动终端搜索不到服务区的问题，进而提高了时钟校准精度和稳定度，保证了移动终端的正常工作。

Claims (11)

  1. 一种时钟校准方法，所述方法包括：
    多模基带芯片下的物理层进入睡眠状态前，根据高频时钟校准信号调整物理层时钟，并根据基准时钟信号和所述高频时钟校准信号获得校准因子；
    所述物理层进入睡眠状态后，在所述基准时钟信号下对网络实时时基进行跟踪计数，并根据所述校准因子调整跟踪计数值；
    所述物理层被唤醒后，将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数。
  2. 根据权利要求1所述的时钟校准方法，其中，所述根据高频时钟校准信号调整所述物理层时钟，包括：
    所述物理层进入睡眠状态前，开启高频校准请求；
    所述高频校准请求被允许后，控制所述物理层时钟进入高频校准阶段；
    所述高频校准阶段完成后，关闭高频时钟信号，保存所述物理层时钟计数值。
  3. 根据权利要求1或2所述的时钟校准方法，其中，所述基准时钟信号为32K低频时钟信号。
  4. 根据权利要求1所述的时钟校准方法，其中，所述将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数，包括：
    将所述跟踪计数值加载到所述物理层时钟，得到新的物理层时钟；
    将所述新的物理层时钟在所述高频时钟校准信号下调整，使调整后的新的物理层时钟与所述高频时钟校准信号频率一致；
    将调整后的新的物理层时钟在所述高频时钟校准信号下对网络实时时基进行计数，使所述调整后的物理层时钟与所述网络实时时基同步。
  5. 一种时钟校准装置，所述装置包括：高频校准单元、时钟控制单元和时钟单元；
    所述时钟单元，配置为为多模基带芯片下的物理层提供高频时钟校准信号和基准时钟信号；
    所述高频校准单元，配置为在所述物理层进入睡眠状态前，根据所述时钟单元提供的所述高频时钟校准信号调整所述物理层时钟，并根据所述基准时钟信号和所述高频时钟校准信号获得校准因子；所述物理层进入睡眠状态后，在所述基准时钟信号下对网络实时时基进行跟踪计数，并根据所述校准因子调整跟踪计数值；所述物理层被唤醒后，将所述跟踪计数值加载到所述物理层时钟，加载后的物理层时钟在所述高频时钟校准信号下计数；
    所述时钟控制单元，配置为控制所述时钟单元的开启和关闭以及所述时钟单元输出信号的频率。
  6. 根据权利要求5所述的时钟校准装置，其中，所述高频校准单元，配置为在所述物理层进入睡眠状态前，开启高频校准请求；所述高频校准请求被允许后，控制所述物理层进入高频校准阶段；所述高频校准阶段完成后，关闭高频时钟信号，保存所述物理层时钟计数值。
  7. 根据权利要求5所述的时钟校准装置，其中，所述高频校准单元，配置为将所述跟踪计数值加载到所述物理层时钟，得到新的物理层时钟；将所述新的物理层时钟在所述高频时钟校准信号下调整，使调整后的新的物理层时钟与所述高频时钟校准信号频率一致；将调整后的新的物理层时钟在所述高频时钟校准信号下对网络实时时基进行计数，使所述调整后的物理层时钟与所述网络实时时基同步。
  8. 根据权利要求6所述的时钟校准装置，其中，所述装置还包括：主控单元，配置为完成软硬件的交互管理。
  9. 根据权利要求8所述的时钟校准装置，其中，所述主控单元为ARM处理器。
  10. 根据权利要求5至9任一项所述时钟校准装置，其中，所述时钟单元包括锁相环电路、时钟动态切换电路、时钟门控电路。
  11. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至4任一项所述的时钟校准方法。
PCT/CN2015/086545 2015-05-04 2015-08-10 一种时钟校准方法、装置及计算机存储介质 WO2016176923A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108224498A (zh) * 2018-02-26 2018-06-29 广东美的厨房电器制造有限公司 电控系统及多头电陶炉
CN113453325A (zh) * 2021-06-25 2021-09-28 展讯通信（上海）有限公司 一种晶振时钟校准方法、装置、设备及介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2393610A (en) * 2002-09-26 2004-03-31 Nec Technologies Clock calibration in a mobile communications device
US6725067B1 (en) * 2000-03-24 2004-04-20 International Business Machines Corporation Method and system for restarting a reference clock of a mobile station after a sleep period with a zero mean time error
GB2397465A (en) * 2003-01-15 2004-07-21 Nec Technologies Clock calibration in a mobile radio communications device
CN102187578A (zh) * 2008-10-17 2011-09-14 马维尔国际贸易有限公司 用于确定参考时钟频率和/或锁定环路振荡器的方法、算法、电路和系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101083503B (zh) * 2006-05-30 2011-04-20 上海宣普实业有限公司 一种准确维护接收装置在睡眠状态下系统同步信息的方法
CN101431816B (zh) * 2008-11-19 2010-07-28 华为终端有限公司 一种频率差的获取方法及终端
CN102540868B (zh) * 2010-12-31 2016-05-04 重庆重邮信科通信技术有限公司 一种移动通信终端慢时钟晶体频率补偿方法及装置
US8867421B2 (en) * 2012-04-12 2014-10-21 Gainspan Corporation Correction of clock errors in a wireless station to enable reduction of power consumption

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6725067B1 (en) * 2000-03-24 2004-04-20 International Business Machines Corporation Method and system for restarting a reference clock of a mobile station after a sleep period with a zero mean time error
GB2393610A (en) * 2002-09-26 2004-03-31 Nec Technologies Clock calibration in a mobile communications device
GB2397465A (en) * 2003-01-15 2004-07-21 Nec Technologies Clock calibration in a mobile radio communications device
CN102187578A (zh) * 2008-10-17 2011-09-14 马维尔国际贸易有限公司 用于确定参考时钟频率和/或锁定环路振荡器的方法、算法、电路和系统

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108224498A (zh) * 2018-02-26 2018-06-29 广东美的厨房电器制造有限公司 电控系统及多头电陶炉
CN113453325A (zh) * 2021-06-25 2021-09-28 展讯通信（上海）有限公司 一种晶振时钟校准方法、装置、设备及介质
CN113453325B (zh) * 2021-06-25 2022-11-01 展讯通信（上海）有限公司 一种晶振时钟校准方法、装置、设备及介质

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