WO2016173105A1 - Goa电路修复方法 - Google Patents

Goa电路修复方法 Download PDF

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Publication number
WO2016173105A1
WO2016173105A1 PCT/CN2015/082008 CN2015082008W WO2016173105A1 WO 2016173105 A1 WO2016173105 A1 WO 2016173105A1 CN 2015082008 W CN2015082008 W CN 2015082008W WO 2016173105 A1 WO2016173105 A1 WO 2016173105A1
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WIPO (PCT)
Prior art keywords
electrically connected
thin film
film transistor
signal
goa unit
Prior art date
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PCT/CN2015/082008
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English (en)
French (fr)
Inventor
戴超
Original Assignee
深圳市华星光电技术有限公司
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Priority to US14/761,306 priority Critical patent/US9581873B2/en
Publication of WO2016173105A1 publication Critical patent/WO2016173105A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit repair method.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scanning line, and a drain is connected to a vertical data line, and a source (Source) ) is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by an external integrated circuit (IC), and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • the GOA technology (Gate Driver on Array) is a line scan driving technology integrated on the array substrate, and the gate driving circuit can be fabricated on the TFT array substrate by using an array process of the liquid crystal display panel to realize driving of the gate progressive scanning. the way. GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • the main purpose of GOA technology applied to liquid crystal displays is to reduce costs, but at the same time, there are relatively high requirements for the process.
  • the process of making GOA circuit is prone to damage, and the GOA circuit is difficult to repair after damage, which greatly affects the yield of GOA products, and does not meet the original intention of using GOA technology to reduce production costs.
  • the object of the present invention is to provide a GOA circuit repairing method, which can reduce the repairing difficulty of the GOA circuit, improve the yield of the GOA product, and reduce the production cost.
  • the present invention provides a GOA circuit repair method, which first provides a plurality of cascaded GOA unit circuits, a repair signal, and a repair signal line electrically connected to the repair signal;
  • Each stage of the GOA unit circuit includes a pull-up control module, a pull-up module, a downlink module, a first pull-down module, a bootstrap capacitor, and a pull-down maintenance module;
  • the pull-up control module includes an eleventh thin film transistor, and the gate of the eleventh thin film transistor receives the upper level N-1th GOA unit circuit.
  • a scan control signal the source is electrically connected to the constant voltage high potential, and the drain is electrically connected to the first node;
  • the downlink module outputs a scan control signal of the next N+1th GOA unit circuit;
  • the pull-up The module outputs a scan signal;
  • the gate of the eleventh thin film transistor is electrically connected to a gate lead line, and the scan signal is output via the scan signal output line;
  • the GOA circuit is detected, and the two stages of the GOA unit circuits of the Nth stage and the N+1th stage are used as a group, and when the circuit of the Nth stage GOA unit is detected to be working normally, the first stage of the Nth stage GOA unit circuit is made.
  • the gate lead line of the eleven thin film transistor is insulated from the repair signal line, and the scan signal output line in the Nth stage GOA unit circuit is insulated from the repair signal line;
  • the N+1th stage GOA unit circuit a gate lead line of the eleventh thin film transistor is insulated from the repair signal line, and a scan signal output line in the N+1th GOA unit circuit is insulated from the repair signal line;
  • the connection between the scan signal output line and the pull-up module in the Nth stage GOA unit circuit and the eleventh thin film transistor in the N+1th GOA unit circuit are cut by laser Connecting the gate to the scan control signal of the N+1th GOA unit circuit, and turning on the scan signal output line and the repair signal line in the Nth stage GOA unit circuit by laser welding, and the N+1th stage a gate lead line of the eleventh thin film transistor and the repair signal line in the GOA unit circuit, thereby connecting the repair signal to the Nth stage and the N+1th stage GOA unit circuit as the Nth stage GOA unit respectively The output signal of the circuit and the scan control signal of the N+1th stage GOA unit circuit.
  • the insulation overlap is achieved by interposing an insulating layer between the first and second metal layers.
  • the pull-up module includes: a 21st thin film transistor, a gate of the 21st thin film transistor is electrically connected to the first node, and a source is electrically connected to the Mth a clock signal, the drain is electrically connected to the second node and outputs a scan signal;
  • the downlink module includes: a twenty-second thin film transistor, the second twelve thin film transistor The gate is electrically connected to the first node, the source is electrically connected to the Mth clock signal, and the drain outputs the scan control signal of the next N+1th GOA unit circuit;
  • the first pull-down module includes: a forty-th thin film transistor, the gate and the source of the forty-th thin film transistor are electrically connected to the first node, and the drain electrode is electrically connected to the forty-first thin film transistor
  • the gate of the forty-th thin film transistor is electrically connected to the M+2 clock signal
  • the source is electrically connected to the drain of the fortieth thin film transistor
  • the drain is electrically connected to the second node ;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the second node;
  • the pull-down maintaining module includes: an inverter, an input end of the inverter is electrically connected to the first node, and an output end is electrically connected to the gate of the thirty-second thin film transistor and the forty-second thin film transistor a gate of the thirty-second thin film transistor, the gate of the thirty-second thin film transistor is electrically connected to the output end of the inverter, and the source is electrically connected to the drain of the forty-th thin film transistor The drain is electrically connected to the first negative potential; the forty-second thin film transistor, the gate of the forty-second thin film transistor is electrically connected to the output end of the inverter, and the drain is electrically connected to the first a node, the source is electrically connected to a constant voltage low potential;
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; when the clock signal is a third clock signal, the M+2 clock The signal is a first clock signal, and when the clock signal is a fourth clock signal, the M+2th clock signal is a second clock signal.
  • a second implementation manner of the GOA circuit repair method first provides a plurality of cascaded GOA unit circuits, a repair signal, and a repair signal line electrically connected to the repair signal;
  • Each stage of the GOA unit circuit includes a pull-up control module, a pull-up module, a downlink module, a first pull-down module, a bootstrap capacitor, and a pull-down maintenance module;
  • the pull-up control module includes an eleventh thin film transistor connected in parallel with the twelfth thin film transistor, and the gate of the eleventh thin film transistor receives the previous one.
  • a scan control signal of the N-1th stage GOA unit circuit the source is electrically connected to the constant voltage high potential, the drain is electrically connected to the first node, and the gate of the twelfth thin film transistor is electrically connected to a gate lead a line, the source is electrically connected to the constant voltage high potential, and the drain is electrically connected to the first node;
  • the downlink module outputs a scan control signal of the next stage N+1th GOA unit circuit;
  • the pull-up module output scan a signal; the scan signal is output via a scan signal output line;
  • the GOA circuit is detected, and the two stages of the GOA unit circuits of the Nth stage and the N+1th stage are used as a group, and when the circuit of the Nth stage GOA unit is detected to be working normally, the first stage of the Nth stage GOA unit circuit is made.
  • a gate lead line of the twelve thin film transistor is insulatively overlapped with the repair signal line, and a scan signal output line in the Nth stage GOA unit circuit is insulated from the repair signal line;
  • a gate lead line of the twelfth thin film transistor in the N+1 stage GOA unit circuit is insulated from the repair signal line, and a scan signal output line in the N+1th stage GOA unit circuit is insulated from the repair signal line overlap;
  • the connection between the scan signal output line and the pull-up module in the Nth stage GOA unit circuit and the eleventh thin film transistor in the N+1th GOA unit circuit are cut by laser
  • the drain is connected to the first node, and is electrically connected to the scan signal output line in the Nth stage GOA unit circuit and the repair signal line, and the twelfth thin film transistor in the N+1th GOA unit circuit by laser welding a gate lead line and the repair signal line, thereby connecting the repair signal to the Nth stage and the N+1th stage GOA unit circuit as output signals of the Nth stage GOA unit circuit, and the N+th The scan control signal of the level 1 GOA unit circuit.
  • the Nth-level GOA unit circuit further includes a ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to a constant voltage high potential, and the drain level is electrically connected to the scan signal output. a line, the source is electrically connected to a source lead line;
  • the GOA circuit is detected, and the two stages of the GOA unit circuits of the Nth stage and the N+1th stage are used as a group, and when the circuit of the Nth stage GOA unit is detected to operate normally, the ninth stage of the circuit of the Nth stage GOA unit is also made.
  • a source lead line of the thin film transistor is insulatively overlapped with the repair signal line, and a source lead line of the ninth thin film transistor in the N+1th stage GOA unit circuit is insulated from the repair signal line;
  • the source lead line of the ninth thin film transistor in the Nth stage GOA unit circuit and the repair signal line are laser-welded, thereby turning on the scan signal output line and the repair signal. line.
  • the insulation overlap is achieved by interposing an insulating layer between the first and second metal layers.
  • the pull-up module includes: a 21st thin film transistor, a gate of the 21st thin film transistor is electrically connected to the first node, and a source is electrically connected to the Mth a clock signal, the drain is electrically connected to the second node and outputs a scan signal;
  • the down-transmission module includes: a 22nd thin film transistor, a gate of the 22nd thin film transistor is electrically connected to the first node, a source is electrically connected to the Mth clock signal, and a drain output is next a scan control signal of the stage N+1th GOA unit circuit;
  • the first pull-down module includes: a forty-th thin film transistor, the gate and the source of the forty-th thin film transistor are electrically connected to the first node, and the drain electrode is electrically connected to the forty-first thin film transistor
  • the gate of the forty-th thin film transistor is electrically connected to the M+2 clock signal
  • the source is electrically connected to the drain of the fortieth thin film transistor
  • the drain is electrically connected to the second node ;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the second section. point;
  • the pull-down maintaining module includes: an inverter, an input end of the inverter is electrically connected to the first node, and an output end is electrically connected to the gate of the thirty-second thin film transistor and the forty-second thin film transistor a gate of the thirty-second thin film transistor, the gate of the thirty-second thin film transistor is electrically connected to the output end of the inverter, and the source is electrically connected to the drain of the forty-th thin film transistor The drain is electrically connected to the first negative potential; the forty-second thin film transistor, the gate of the forty-second thin film transistor is electrically connected to the output end of the inverter, and the drain is electrically connected to the first a node, the source is electrically connected to a constant voltage low potential;
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; when the clock signal is a third clock signal, the M+2 clock The signal is a first clock signal, and when the clock signal is a fourth clock signal, the M+2th clock signal is a second clock signal.
  • a third implementation manner of the GOA circuit repair method first provides a plurality of cascaded GOA unit circuits, a repair signal, a repair signal line electrically connected to the repair signal, an enable signal, and the start signal Start signal line for sexual connection;
  • Each stage of the GOA unit circuit includes a pull-up control module, a pull-up module, a downlink module, a first pull-down module, a bootstrap capacitor, and a pull-down maintenance module;
  • the pull-up control module includes an eleventh thin film transistor connected in parallel with the twelfth thin film transistor, and the gate of the eleventh thin film transistor receives the previous one.
  • a scan control signal of the N-1th stage GOA unit circuit the source is electrically connected to the constant voltage high potential, the drain is electrically connected to the first node, and the gate of the twelfth thin film transistor is electrically connected to a gate lead a line, the source is electrically connected to the constant voltage high potential, and the drain is electrically connected to the first node;
  • the downlink module outputs a scan control signal of the next stage N+1th GOA unit circuit;
  • the pull-up module output scan a signal; the scan signal is output via a scan signal output line;
  • the GOA circuit is detected, and the Nth level, the N+1th stage, the N+2th stage, and the N+3th level four-level GOA unit circuit are grouped, and the N+1th level is detected.
  • the N+2 stage GOA unit circuit operates normally, the twelfth thin film transistor of each of the four stages of the GOA unit circuit of the Nth stage, the N+1th stage, the N+2th stage, and the N+3th stage is made.
  • the gate lead lines are respectively insulated from the repair signal line and the start signal line, and the scan signal output lines are respectively insulated from the repair signal line and the start signal line;
  • the connection between the scan signal output line and the pull-up module in the circuit of the N+1th GOA unit is cut off by the laser, and the N+2
  • the connection between the drain of the eleventh thin film transistor and the first node in the stage GOA unit circuit, the connection between the scan signal output line and the pull-up module in the N+2 stage GOA unit circuit, and the a drain of the eleventh thin film transistor of the N+3 stage GOA unit circuit is connected to the first node, and is connected to the scan signal output line and the enable signal line in the circuit of the N+1th GOA unit by laser welding, a gate lead line of the twelfth thin film transistor in the N+2 stage GOA unit circuit and the start signal line, a scan signal output line and a repair signal line of the N+2 stage GOA unit circuit, and an N+3 stage a gate lead line of the twelfth thin film transistor in the GOA unit circuit and the repair signal line,
  • the insulation overlap is achieved by interposing an insulating layer between the first and second metal layers.
  • the pull-up module includes: a 21st thin film transistor, a gate of the 21st thin film transistor is electrically connected to the first node, and a source is electrically connected to the Mth a clock signal, the drain is electrically connected to the second node and outputs a scan signal;
  • the down-transmission module includes: a 22nd thin film transistor, a gate of the 22nd thin film transistor is electrically connected to the first node, a source is electrically connected to the Mth clock signal, and a drain output is next a scan control signal of the stage N+1th GOA unit circuit;
  • the first pull-down module includes: a forty-th thin film transistor, the gate and the source of the forty-th thin film transistor are electrically connected to the first node, and the drain electrode is electrically connected to the forty-first thin film transistor
  • the gate of the forty-th thin film transistor is electrically connected to the M+2 clock signal
  • the source is electrically connected to the drain of the fortieth thin film transistor
  • the drain is electrically connected to the second node ;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the second node;
  • the pull-down maintaining module includes: an inverter, an input end of the inverter is electrically connected to the first node, and an output end is electrically connected to the gate of the thirty-second thin film transistor and the forty-second thin film transistor a gate of the thirty-second thin film transistor, the gate of the thirty-second thin film transistor is electrically connected to the output end of the inverter, and the source is electrically connected to the drain of the forty-th thin film transistor The drain is electrically connected to the first negative potential; the forty-second thin film transistor, the gate of the forty-second thin film transistor is electrically connected to the output end of the inverter, and the drain is electrically connected to the first a node, the source is electrically connected to a constant voltage low potential;
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; when the clock signal is a third clock signal, the M+2 clock The signal is a first clock signal, and when the clock signal is a fourth clock signal, the M+2th clock signal is a second clock signal.
  • the GOA circuit repair method provided by the present invention connects a repair signal to an Nth stage and an N+1th GOA unit circuit by repairing a signal line, respectively, as an output signal of the Nth stage GOA unit circuit, And scanning control signal of the N+1th GOA unit circuit to implement repair of the Nth stage GOA unit circuit; or connecting the start signal to the N+1th stage and the N+2th stage GOA unit circuit by starting the signal line , respectively, as an output signal of the N+1th GOA unit circuit and a scan control signal of the N+2th GOA unit circuit to implement repair of the N+1th GOA unit circuit, and repair the signal by repairing the signal line Accessing the N+2th and N+3th GOA unit circuits as the output signal of the N+2th GOA unit circuit and the scan control signal of the N+3th GOA unit circuit respectively to implement the Nth
  • the repair of the +2 level GOA unit circuit can reduce the repair difficulty of the GOA circuit, improve the yield of the GOA product
  • FIG. 1 is a schematic circuit diagram of a first embodiment of a method for repairing a GOA circuit of the present invention before repairing;
  • FIG. 2 is a schematic view showing a planar structure corresponding to R in FIG. 1;
  • FIG. 3 is a schematic cross-sectional structural view corresponding to R in FIG. 1;
  • FIG. 4 is a schematic circuit diagram of the first embodiment of the GOA circuit repairing method of the present invention after repairing
  • FIG. 5 is a schematic circuit diagram of a second embodiment of the GOA circuit repairing method of the present invention before repairing;
  • FIG. 6 is a schematic circuit diagram of a second embodiment of the GOA circuit repairing method of the present invention after repairing
  • FIG. 7 is a schematic circuit diagram of a third embodiment of the GOA circuit repairing method of the present invention before repairing;
  • FIG. 8 is a schematic diagram of a circuit after repairing a third embodiment of the GOA circuit repairing method of the present invention.
  • FIG. 9 is a first, second, and third embodiment of a GOA circuit repairing method according to the present invention.
  • FIG. 10 is a schematic circuit diagram of a fourth embodiment of the GOA circuit repairing method of the present invention before repairing;
  • FIG. 11 is a schematic diagram of a circuit after repairing a fourth embodiment of the GOA circuit repairing method of the present invention.
  • Fig. 12 is a timing chart showing a fourth embodiment of the GOA circuit repairing method of the present invention.
  • the invention provides a GOA circuit repairing method. Please refer to FIG. 1 to FIG. 4 and FIG. 9 simultaneously to illustrate a first embodiment of the GOA circuit repairing method of the present invention:
  • Each stage of the GOA unit circuit includes a pull-up control module 100, a pull-up module 200, a downlink module 300, a first pull-down module 400, a bootstrap capacitor 500, and a pull-down maintenance module 600;
  • the pull-up control module 100 includes an eleventh thin film transistor T11, and the gate of the eleventh thin film transistor T11 receives the upper level N-1.
  • the scanning control signal ST(N-1) of the GOA unit circuit the source is electrically connected to the constant voltage high potential DCH, and the drain is electrically connected to the first node Q(N); the downstream module 300 outputs the next stage Nth a scanning control signal ST(N) of the +1 level GOA unit circuit; the pull-up module 200 outputs a scan signal G(N); the gate of the eleventh thin film transistor T11 is electrically connected to a gate lead line L11, The scan signal G(N) is output via the scan signal output line L2.
  • the GOA circuit is detected, and the two stages of the GOA unit circuits of the Nth stage and the N+1th stage are used as a group, and when the circuit of the Nth stage GOA unit is detected to be working normally, the first stage of the Nth stage GOA unit circuit is made.
  • the gate lead line L11 of the eleventh thin film transistor T11 is insulatively overlapped with the repair signal line L1, and the scan signal output line L2 in the Nth stage GOA unit circuit is insulated and overlapped with the repair signal line L1;
  • the gate lead line L11 of the eleventh thin film transistor T11 in the stage GOA unit circuit is insulated and overlapped with the repair signal line L1, and the scan signal output line L2 and the repair signal line in the N+1th GOA unit circuit L1 insulation overlaps.
  • the insulation overlap is achieved by interposing an insulating layer S1 between the first and second metal layers M1 and M2, and the insulation at R in FIG. 1 and FIG.
  • the first metal layer M1 may be used to form the repair signal line L1
  • the second metal layer M2 may be used to form the gate lead line L11, which is made of silicon nitride or silicon oxide.
  • the insulating layer S1 is insulated.
  • the connection between the scanning signal output line L2 and the pull-up module 200 in the N-th stage GOA unit circuit by the laser cut (indicated by a cross in FIG. 4), and the N+th
  • the gate of the eleventh thin film transistor T11 in the first-stage GOA unit circuit is connected to the scan control signal ST(N) of the N+1th GOA unit circuit, and is turned on by laser welding (indicated by a solid circle in FIG.
  • the repair signal Repair signal is connected to the Nth stage and the N+1th stage GOA unit circuit, respectively, as an output signal of the Nth stage GOA unit circuit, and a scan control signal of the N+1th GOA unit circuit
  • the repair of the Nth stage GOA unit circuit is completed, so that the Nth and N+1th GOA unit circuits can still work normally.
  • the clock signal CK(M) includes four high frequency clock signals: a first clock signal CK(1) and a second clock signal.
  • CK (2), the third clock signal CK (3), and the fourth clock signal CK (4) when the clock signal CK (M) is the third clock signal (CK (3)), the Mth +2 clock signals CK(M+2) are the first clock signal CK(1), and when the clock signal CK(M) is the fourth clock signal CK(4), the M+2th clock signal CK (M+2) is the second clock signal CK(2);
  • STV is a circuit enable signal and includes only one pulse; and the repair signal Repair signal generates an output signal G(N) of the Nth stage GOA unit circuit.
  • the pull-up module 200 includes: a 21st thin film transistor T21, and a gate of the 21st thin film transistor T21 is electrically connected to the first node Q. (N), the source is electrically connected to the Mth clock signal CK (M), the drain is electrically connected to the second node D (N) and outputs a scan signal G (N);
  • the down-going module 300 includes: a twenty-second thin film transistor T22, the gate of the second twelve-th thin film transistor T22 is electrically connected to the first node Q(N), and the source is electrically connected to the Mth clock.
  • Signal CK (M) the drain outputs the scan control signal ST(N) of the next N+1th GOA unit circuit of the next stage;
  • the first pull-down module 400 includes: a forty-th thin film transistor T40, the gate and the source of the fourth thin film transistor T40 are electrically connected to the first node Q(N), and the drain level is electrically connected to The source of the forty-first thin film transistor T41; the gate of the forty-th thin film transistor T41 is electrically connected to the M+2 clock signal CK(M+2), and the source is electrically connected to the fortieth The drain of the thin film transistor T40, the drain is electrically connected to the second node D (N);
  • One end of the bootstrap capacitor 500 is electrically connected to the first node Q (N), and the other end is electrically connected to the second node D (N);
  • the pull-down maintaining module 600 includes an inverter F1, an input end of the inverter F1 is electrically connected to the first node Q(N), and an output end is electrically connected to the gate of the thirty-second thin film transistor T32. And the gate of the forty-second thin film transistor T42; the thirty-second thin film transistor T32, the gate of the thirty-second thin film transistor T32 is electrically connected to the output end of the inverter F1, and the source is electrically Is electrically connected to the drain of the forty-th thin film transistor T41, the drain is electrically connected to the first negative potential VSS1; the forty-second thin film transistor T42, the gate of the forty-second thin film transistor T42 is electrically connected to The output terminal of the inverter F1 is electrically connected to the first node Q(N), and the source is electrically connected to the constant voltage low potential DCL.
  • a second embodiment of the GOA circuit repairing method of the present invention is illustrated.
  • the difference between the second embodiment and the first embodiment is that, in the Nth stage GOA unit circuit, a twelfth thin film transistor T12 connected in parallel with the eleventh thin film transistor T11 is added to the pull-up control module 100, specifically
  • the gate of the eleventh thin film transistor T11 receives the scan control signal ST(N-1) of the upper N-1th stage GOA unit circuit, the source is electrically connected to the constant voltage high potential DCH, and the drain is electrically Connecting the first node Q(N), the gate of the twelfth thin film transistor T12 is electrically connected to a gate lead line L12, the source is electrically connected to the constant voltage high potential DCH, and the drain is electrically connected to the first node Q. (N).
  • the GOA circuit is detected, and the two stages of the GOA unit circuits of the Nth and N+1th stages are taken as a group, and when the circuit of the Nth stage GOA unit is detected to be working normally, the circuit of the Nth stage GOA unit is
  • the gate lead line L12 of the twelfth thin film transistor T12 is insulated from the repair signal line L1, and the scan signal output line L2 in the Nth stage GOA unit circuit is insulated from the repair signal line L1;
  • the gate lead line L11 of the twelfth thin film transistor T12 in the level-1 GOA unit circuit is insulated and overlapped with the repair signal line L1, and the scan signal output line L2 in the N+1th stage GOA unit circuit and the repair signal Line L1 insulation overlaps.
  • the connection between the scanning signal output line L2 and the pull-up module 200 in the N-th stage GOA unit circuit by the laser cut (indicated by a cross in FIG. 6)
  • the N+th a drain of the eleventh thin film transistor T11 in the first-stage GOA unit circuit is connected to the first node Q(N+1), and is turned on in the Nth-level GOA unit circuit by laser welding (indicated by a solid circle in FIG.
  • repair signal is connected to the Nth stage and the N+1th stage GOA unit circuit, respectively, as an output signal of the Nth stage GOA unit circuit, and a scan control signal of the N+1th GOA unit circuit, completing the Nth level GOA
  • the repair of the unit circuit enables the Nth and N+1th GOA unit circuits to still operate normally.
  • a third embodiment of the GOA circuit repairing method of the present invention is illustrated.
  • a ninth thin film transistor T9 is added to the Nth stage GOA unit circuit, and the gate of the ninth thin film transistor T9 is electrically connected to the constant voltage high potential DCH.
  • the drain level is electrically connected to the scan signal output line L2, and the source is electrically connected to a source lead line L9.
  • the GOA circuit is detected, and the N-th stage and the N+1-th order two-stage GOA unit circuit are grouped.
  • the Nth-level GOA unit circuit is replaced as in the second embodiment.
  • the gate lead line L12 of the twelfth thin film transistor T12 in the circuit is insulated from the repair signal line L1
  • the scan signal output line L2 in the Nth stage GOA unit circuit is insulated from the repair signal line L1.
  • the gate lead line L11 of the twelfth thin film transistor T12 in the N+1th stage GOA unit circuit is insulated and overlapped with the repair signal line L1, and the scan signal output line L2 in the N+1th GOA unit circuit is In addition to the insulation overlap of the repair signal line L1, the source lead line L9 of the ninth thin film transistor T9 in the Nth stage GOA unit circuit is insulated from the repair signal line L1, and the N+1th stage GOA unit circuit The source lead line L9 of the ninth thin film transistor T9 is insulatively overlapped with the repair signal line L1.
  • the second embodiment When detecting that the circuit of the Nth stage GOA unit is damaged, the second embodiment directly splicing the scan signal output line L2 and the repair signal line L1 in the Nth stage GOA unit circuit by laser to make the two conduct, and the third The embodiment is to laser-weld the source lead line L9 of the ninth thin film transistor T9 in the Nth stage GOA unit circuit and the repair signal line L1 such that the scan signal output line L2 passes through the ninth thin film transistor T9 and the repair signal.
  • the line L1 is turned on, and the repair signal Repair signal is output as an output signal of the Nth stage GOA unit circuit via the ninth thin film transistor T9.
  • FIG. 10 a fourth embodiment of the GOA circuit repairing method of the present invention is illustrated.
  • the first, second, and third embodiments all use the repair signal line L1 to repair a single Nth stage GOA unit circuit, and the fourth embodiment can simultaneously repair the two-stage GOA unit circuit:
  • a plurality of cascaded GOA unit circuits a repair signal, a repair signal line L1 electrically connected to the repair signal, a start signal STV, and a start connection electrically connected to the start signal STV are provided.
  • Each stage of the GOA unit circuit includes a pull-up control module 100, a pull-up module 200, a downlink module 300, a first pull-down module 400, a bootstrap capacitor 500, and a pull-down maintenance module 600;
  • the pull-up control module 100 includes the eleventh thin film transistor T11 and the twelfth thin film transistor T12 connected in parallel, and the gate of the eleventh thin film transistor T11
  • the pole receives the scan control signal of the upper N-1th GOA unit circuit ST(N-1), the source is electrically connected to the constant voltage high potential DCH, the drain is electrically connected to the first node Q(N), and the gate of the twelfth thin film transistor T12 is electrically connected to a gate lead line L12, the source is electrically connected to the constant voltage high potential DCH, and the drain is electrically connected to the first node Q(N);
  • the downlink module 300 outputs the scan control signal ST of the next stage N+1th GOA unit circuit ( N); the pull-up module 200 outputs a scan signal G(N); the scan signal G(N) is output via the scan signal output line L2.
  • the GOA circuit is detected, and the Nth level, the N+1th stage, the N+2th stage, and the N+3th level four-level GOA unit circuit are grouped, and the N+1th level is detected.
  • the twelfth thin film transistor T12 of each of the four stages of the GOA unit circuit of the Nth stage, the N+1th stage, the N+2th stage, and the N+3th stage is made.
  • the gate lead lines L12 are insulatively overlapped with the repair signal line L1 and the enable signal line L5, respectively, and the scan signal output lines L2 are insulatively overlapped with the repair signal line L1 and the enable signal line L5, respectively.
  • the scanning signal output line L2 and the pull-up in the N+1th GOA unit circuit are cut by laser (represented by a cross in FIG. 11).
  • the connection between the modules 200, the connection of the drain of the eleventh thin film transistor T11 in the N+2 stage GOA unit circuit to the first node Q(N+2), and the scan signal in the N+2 stage GOA unit circuit a connection between the output line L2 and the pull-up module 200, and a connection between the drain of the eleventh thin film transistor T11 and the first node Q(N+3) in the N+3 stage GOA unit circuit, and guided by laser welding
  • the scan signal output line L2 in the N+1th GOA unit circuit and the start signal line L5 and the gate of the twelfth thin film transistor T12 in the N+2th GOA unit circuit are connected (shown by a solid circle in FIG.
  • the output signal of the element circuit and the scan control signal of the N+2 stage GOA unit circuit, the repair signal Repair signal is connected to the N+2th stage and the N+3th stage GOA unit circuit, respectively as the N+th
  • the output signal of the 2-stage GOA unit circuit and the scan control signal of the N+3-level GOA unit circuit complete the repair of the two-stage GOA unit circuit for the N+1th and N+2th stages, so that the GOA circuit can still normal work.
  • the specific structure and the first structure of the pull-up module 200 , the downlink module 300 , the first pull-down module 400 , the bootstrap capacitor 500 , and the pull-down maintaining module 600 in the N-th stage GOA unit circuit are the same and will not be described again here.
  • the clock signal CK(M) includes four high frequency clock signals: a first clock signal CK(1) and a second clock signal.
  • CK (2), the third clock signal CK (3), and the fourth clock signal CK (4) when When the clock signal CK(M) is the third clock signal (CK(3)), the M+2th clock signal CK(M+2) is the first clock signal CK(1), when the clock When the signal CK(M) is the fourth clock signal CK(4), the M+2th clock signal CK(M+2) is the second clock signal CK(2); the STV is the enable signal, including two pulses.
  • One pulse is used for circuit startup, one pulse is used to generate the output signal G(N+1) of the N+1th GOA unit circuit to repair the N+1th GOA unit circuit; the repair signal Repair signal generates the N+th The output signal G(N+2) of the 2-stage GOA unit circuit is used to repair the N+2 stage GOA unit circuit.
  • the four-stage GOA unit circuits of the Nth, N+1th, N+2, and N+3 stages are respectively pulled up.
  • the source of the 21st thin film transistor T21 in 200 is electrically connected to the first clock signal CK(1), the second clock signal CK(2), the third clock signal CK(3), and the fourth clock signal CK, respectively.
  • the start signal STV repairs the N+1th GOA unit circuit corresponding to the second clock signal CK(2).
  • the GOA circuit repair method connects the repair signal to the Nth stage and the N+1th GOA unit circuit by repairing the signal line, respectively, as the output signal of the Nth stage GOA unit circuit, and
  • the scanning control signal of the N+1th GOA unit circuit is used to implement the repair of the Nth stage GOA unit circuit; or the activation signal is connected to the N+1th stage and the N+2th stage GOA unit circuit by starting the signal line, As the output signal of the N+1th GOA unit circuit and the scan control signal of the N+2th GOA unit circuit, respectively, the repair of the N+1th GOA unit circuit is realized, and the repair signal is connected by repairing the signal line.
  • the N+2th stage and the N+3th stage GOA unit circuit are respectively used as an output signal of the N+2th GOA unit circuit and a scan control signal of the N+3th GOA unit circuit to implement the N+th
  • the repair of the 2-level GOA unit circuit can reduce the repair difficulty of the GOA circuit, improve the yield of the GOA product, and reduce the production cost.

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Abstract

一种GOA电路修复方法，通过修复信号线(L1)将修复信号(Repair signal)接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号来实现对第N级GOA单元电路的修复；或通过启动信号线(L5)将启动信号(STV)接入第N+1级、及第N+2级GOA单元电路，分别作为第N+1级GOA单元电路的输出信号，及第N+2级GOA单元电路的扫描控制信号来实现对第N+1级GOA单元电路的修复，同时通过修复信号线(L1)将修复信号(Repair signal)接入第N+2级、及第N+3级GOA单元电路，分别作为第N+2级GOA单元电路的输出信号，及第N+3级GOA单元电路的扫描控制信号来实现对第N+2级GOA单元电路的修复，能够降低GOA电路的修复难度，提高GOA产品的良率，降低生产成本。

Description

GOA电路修复方法 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路修复方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术(Gate Driver on Array)即集成在阵列基板上的行扫描驱动技术，可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
GOA技术应用于液晶显示器最主要的目的是为了降低成本，但是同时也对制程有比较高的要求。制作GOA电路的工艺过程中容易产生损坏，且GOA电路在损坏后难以修复，大大影响了GOA产品的良率，不符合采用GOA技术降低生产成本的初衷。
发明内容
本发明的目的在于提供一种GOA电路修复方法，能够降低GOA电路的修复难度，提高GOA产品的良率，降低生产成本。
为实现上述目的，本发明提供一种GOA电路修复方法，首先提供级联的多个GOA单元电路、一修复信号、及与所述修复信号电性连接的修复信号线；
其中，每一级GOA单元电路均包括上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、与下拉维持模块；
设N为正整数，在第N级GOA单元电路中，所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的扫描控制信号，源极电性连接恒压高电位，漏极电性连接第一节点；所述下传模块输出下一级第N+1级GOA单元电路的扫描控制信号；所述上拉模块输出扫描信号；所述第十一薄膜晶体管的栅极电性连接一栅极引出线，所述扫描信号经由扫描信号输出线输出；
然后，对GOA电路进行检测，以第N级、第N+1级这两级GOA单元电路为一组，检测到第N级GOA单元电路正常工作时，使第N级GOA单元电路中的第十一薄膜晶体管的栅极引出线与所述修复信号线绝缘交叠，第N级GOA单元电路中的扫描信号输出线与所述修复信号线绝缘交叠；第N+1级GOA单元电路中的第十一薄膜晶体管的栅极引出线与所述修复信号线绝缘交叠，第N+1级GOA单元电路中的扫描信号输出线与所述修复信号线绝缘交叠；
检测到第N级GOA单元电路损坏时，通过激光切断第N级GOA单元电路中的扫描信号输出线与上拉模块之间的连接、及第N+1级GOA单元电路中第十一薄膜晶体管的栅极与第N+1级GOA单元电路的扫描控制信号的连接，并通过激光熔接导通第N级GOA单元电路中的扫描信号输出线与所述修复信号线、及第N+1级GOA单元电路中第十一薄膜晶体管的栅极引出线与所述修复信号线，从而将所述修复信号接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号。
所述绝缘交叠通过在第一、第二金属层之间夹设绝缘层实现。
在第N级GOA单元电路中，所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于第二节点并输出扫描信号；
所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管 的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出下一级第N+1级GOA单元电路的扫描控制信号；
所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一薄膜晶体管的源极；所述第四十一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十薄膜晶体管的漏极，漏极电性连接于第二节点；
所述自举电容的一端电性连接于第一节点，另一端电性连接于第二节点；
所述下拉维持模块包括：反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第三十二薄膜晶体管的栅极、及第四十二薄膜晶体管的栅极；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于所述反相器的输出端，源极电性连接于第四十一薄膜晶体管的漏极，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于所述反相器的输出端，漏极电性连接于第一节点，源极电性连接于恒压低电位；
所述时钟信号包含四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；当所述时钟信号为第三时钟信号时，所述第M+2条时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2条时钟信号为第二时钟信号。
GOA电路修复方法的第二种实施方式，首先提供级联的多个GOA单元电路、一修复信号、及与所述修复信号电性连接的修复信号线；
其中，每一级GOA单元电路均包括上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、与下拉维持模块；
设N为正整数，在第N级GOA单元电路中，所述上拉控制模块包括并联的第十一薄膜晶体管、与第十二薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的扫描控制信号，源极电性连接恒压高电位，漏极电性连接第一节点，所述第十二薄膜晶体管的栅极电性连接一栅极引出线，源极电性连接恒压高电位，漏极电性连接第一节点；所述下传模块输出下一级第N+1级GOA单元电路的扫描控制信号；所述上拉模块输出扫描信号；所述扫描信号经由扫描信号输出线输出；
然后，对GOA电路进行检测，以第N级、第N+1级这两级GOA单元电路为一组，检测到第N级GOA单元电路正常工作时，使第N级GOA单元电路中的第十二薄膜晶体管的栅极引出线与所述修复信号线绝缘交叠，第N级GOA单元电路中的扫描信号输出线与所述修复信号线绝缘交叠；第 N+1级GOA单元电路中的第十二薄膜晶体管的栅极引出线与所述修复信号线绝缘交叠，第N+1级GOA单元电路中的扫描信号输出线与所述修复信号线绝缘交叠；
检测到第N级GOA单元电路损坏时，通过激光切断第N级GOA单元电路中的扫描信号输出线与上拉模块之间的连接、及第N+1级GOA单元电路中第十一薄膜晶体管的漏极与第一节点的连接，并通过激光熔接导通第N级GOA单元电路中的扫描信号输出线与所述修复信号线、及第N+1级GOA单元电路中第十二薄膜晶体管的栅极引出线与所述修复信号线，从而将所述修复信号接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号。
可选的，在所述第N级GOA单元电路中，还包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于恒压高电位，漏级电性连接于扫描信号输出线，源极电性连接一源极引出线；
对GOA电路进行检测，以第N级、第N+1级这两级GOA单元电路为一组，检测到第N级GOA单元电路正常工作时，还使第N级GOA单元电路中的第九薄膜晶体管的源极引出线与所述修复信号线绝缘交叠，第N+1级GOA单元电路中的第九薄膜晶体管的源极引出线与所述修复信号线绝缘交叠；
检测到第N级GOA单元电路损坏时，通过激光熔接第N级GOA单元电路中的第九薄膜晶体管的源极引出线与所述修复信号线，从而导通扫描信号输出线与所述修复信号线。
所述绝缘交叠通过在第一、第二金属层之间夹设绝缘层实现。
在第N级GOA单元电路中，所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于第二节点并输出扫描信号；
所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出下一级第N+1级GOA单元电路的扫描控制信号；
所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一薄膜晶体管的源极；所述第四十一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十薄膜晶体管的漏极，漏极电性连接于第二节点；
所述自举电容的一端电性连接于第一节点，另一端电性连接于第二节 点；
所述下拉维持模块包括：反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第三十二薄膜晶体管的栅极、及第四十二薄膜晶体管的栅极；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于所述反相器的输出端，源极电性连接于第四十一薄膜晶体管的漏极，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于所述反相器的输出端，漏极电性连接于第一节点，源极电性连接于恒压低电位；
所述时钟信号包含四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；当所述时钟信号为第三时钟信号时，所述第M+2条时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2条时钟信号为第二时钟信号。
GOA电路修复方法的第三种实施方式，首先提供级联的多个GOA单元电路、一修复信号、与所述修复信号电性连接的修复信号线、一启动信号、及与所述启动信号电性连接的启动信号线；
其中，每一级GOA单元电路均包括上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、与下拉维持模块；
设N为正整数，在第N级GOA单元电路中，所述上拉控制模块包括并联的第十一薄膜晶体管、与第十二薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的扫描控制信号，源极电性连接恒压高电位，漏极电性连接第一节点，所述第十二薄膜晶体管的栅极电性连接一栅极引出线，源极电性连接恒压高电位，漏极电性连接第一节点；所述下传模块输出下一级第N+1级GOA单元电路的扫描控制信号；所述上拉模块输出扫描信号；所述扫描信号经由扫描信号输出线输出；
然后，对GOA电路进行检测，以第N级、第N+1级、第N+2级、与第N+3级这四级GOA单元电路为一组，检测到第N+1级、与第N+2级GOA单元电路正常工作时，使第N级、第N+1级、第N+2级、及第N+3级这四级GOA单元电路各级的第十二薄膜晶体管的栅极引出线分别与所述修复信号线、启动信号线绝缘交叠，扫描信号输出线分别与所述修复信号线、启动信号线绝缘交叠；
检测到第N+1级、与第N+2级GOA单元电路损坏时，通过激光切断第N+1级GOA单元电路中的扫描信号输出线与上拉模块之间的连接、第N+2级GOA单元电路中第十一薄膜晶体管的漏极与第一节点的连接、第N+2级GOA单元电路中的扫描信号输出线与上拉模块之间的连接、及第 N+3级GOA单元电路中第十一薄膜晶体管的漏极与第一节点的连接，并通过激光熔接导通第N+1级GOA单元电路中的扫描信号输出线与所述启动信号线、第N+2级GOA单元电路中第十二薄膜晶体管的栅极引出线与所述启动信号线、第N+2级GOA单元电路的扫描信号输出线与修复信号线、及第N+3级GOA单元电路中第十二薄膜晶体管的栅极引出线与所述修复信号线，从而将所述启动信号接入第N+1级、及第N+2级GOA单元电路，分别作为第N+1级GOA单元电路的输出信号，及第N+2级GOA单元电路的扫描控制信号，将所述修复信号接入第N+2级、及第N+3级GOA单元电路，分别作为第N+2级GOA单元电路的输出信号，及第N+3级GOA单元电路的扫描控制信号。
所述绝缘交叠通过在第一、第二金属层之间夹设绝缘层实现。
在第N级GOA单元电路中，所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于第二节点并输出扫描信号；
所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出下一级第N+1级GOA单元电路的扫描控制信号；
所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一薄膜晶体管的源极；所述第四十一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十薄膜晶体管的漏极，漏极电性连接于第二节点；
所述自举电容的一端电性连接于第一节点，另一端电性连接于第二节点；
所述下拉维持模块包括：反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第三十二薄膜晶体管的栅极、及第四十二薄膜晶体管的栅极；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于所述反相器的输出端，源极电性连接于第四十一薄膜晶体管的漏极，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于所述反相器的输出端，漏极电性连接于第一节点，源极电性连接于恒压低电位；
所述时钟信号包含四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；当所述时钟信号为第三时钟信号时，所述第M+2条时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2条时钟信号为第二时钟信号。
本发明的有益效果：本发明提供的GOA电路修复方法，通过修复信号线将修复信号接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号来实现对第N级GOA单元电路的修复；或通过启动信号线将启动信号接入第N+1级、及第N+2级GOA单元电路，分别作为第N+1级GOA单元电路的输出信号，及第N+2级GOA单元电路的扫描控制信号来实现对第N+1级GOA单元电路的修复，同时通过修复信号线将修复信号接入第N+2级、及第N+3级GOA单元电路，分别作为第N+2级GOA单元电路的输出信号，及第N+3级GOA单元电路的扫描控制信号来实现对第N+2级GOA单元电路的修复，能够降低GOA电路的修复难度，提高GOA产品的良率，降低生产成本。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的GOA电路修复方法的第一实施例进行修复之前的电路示意图；
图2为对应图1中R处的平面结构示意图；
图3为对应图1中R处的剖面结构示意图；
图4为本发明的GOA电路修复方法的第一实施例进行修复之后的电路示意图；
图5为本发明的GOA电路修复方法的第二实施例进行修复之前的电路示意图；
图6为本发明的GOA电路修复方法的第二实施例进行修复之后的电路示意图；
图7为本发明的GOA电路修复方法的第三实施例进行修复之前的电路示意图；
图8为本发明的GOA电路修复方法的第三实施例进行修复之后的电路示意图；
图9为对应本发明的GOA电路修复方法的第一、第二、及第三实施例 的时序图；
图10为本发明的GOA电路修复方法的第四实施例进行修复之前的电路示意图；
图11为本发明的GOA电路修复方法的第四实施例进行修复之后的电路示意图；
图12为对应本发明的GOA电路修复方法的第四实施例的时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种GOA电路修复方法。请同时参阅图1至图4、及图9，示意出了本发明GOA电路修复方法的第一实施例：
首先提供级联的多个GOA单元电路、一修复信号Repair signal、及与所述修复信号Repair singal电性连接的修复信号线L1；
其中，每一级GOA单元电路均包括上拉控制模块100、上拉模块200、下传模块300、第一下拉模块400、自举电容500、与下拉维持模块600；
设N为正整数，在第N级GOA单元电路中，所述上拉控制模块100包括第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极接收上一级第N-1级GOA单元电路的扫描控制信号ST(N-1)，源极电性连接恒压高电位DCH，漏极电性连接第一节点Q(N)；所述下传模块300输出下一级第N+1级GOA单元电路的扫描控制信号ST(N)；所述上拉模块200输出扫描信号G(N)；所述第十一薄膜晶体管T11的栅极电性连接一栅极引出线L11，所述扫描信号G(N)经由扫描信号输出线L2输出。
然后，对GOA电路进行检测，以第N级、第N+1级这两级GOA单元电路为一组，检测到第N级GOA单元电路正常工作时，使第N级GOA单元电路中的第十一薄膜晶体管T11的栅极引出线L11与所述修复信号线L1绝缘交叠，第N级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1绝缘交叠；第N+1级GOA单元电路中的第十一薄膜晶体管T11的栅极引出线L11与所述修复信号线L1绝缘交叠，第N+1级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1绝缘交叠。具体地，如图2、图3所示，所述绝缘交叠通过在第一、第二金属层M1、M2之间夹设绝缘层S1实现，以图1、图4中R处的绝缘交叠为例，可采用所述第一金属层M1形成所述修复信号线L1，采用所述第二金属层M2形成所述栅极引出线L11，二者通过以氮化硅或氧化硅制作的绝缘层S1进行绝缘。
检测到第N级GOA单元电路损坏时，通过激光切断(图4中用叉号表示)第N级GOA单元电路中的扫描信号输出线L2与上拉模块200之间的连接、及第N+1级GOA单元电路中第十一薄膜晶体管T11的栅极与第N+1级GOA单元电路的扫描控制信号ST(N)的连接，并通过激光熔接导通(图4中以实心圆表示)第N级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1、及第N+1级GOA单元电路中第十一薄膜晶体管T11的栅极引出线L11与所述修复信号线L1，从而将所述修复信号Repair signal接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号，完成对第N级GOA单元电路的修复，使得第N级、第N+1级GOA单元电路仍能正常工作。
图9所示为对应本发明GOA电路修复方法的第一实施例的时序图，其中所述时钟信号CK(M)包含四条高频时钟信号：第一时钟信号CK(1)、第二时钟信号CK(2)、第三时钟信号CK(3)、及第四时钟信号CK(4)，当所述时钟信号CK(M)为第三时钟信号(CK(3))时，所述第M+2条时钟信号CK(M+2)为第一时钟信号CK(1)，当所述时钟信号CK(M)为第四时钟信号CK(4)时，所述第M+2条时钟信号CK(M+2)为第二时钟信号CK(2)；STV是电路启动信号，仅包括一个脉冲；修复信号Repair signal产生第N级GOA单元电路的输出信号G(N)。
进一步地，在所述第N级GOA单元电路中，所述上拉模块200包括：第二十一薄膜晶体管T21，所述第二十一薄膜晶体管T21的栅极电性连接于第一节点Q(N)，源极电性连接于第M条时钟信号CK(M)，漏极电性连接于第二节点D(N)并输出扫描信号G(N)；
所述下传模块300包括：第二十二薄膜晶体管T22，所述第二十二薄膜晶体管T22的栅极电性连接于第一节点Q(N)，源极电性连接于第M条时钟信号CK(M)，漏极输出下一级第N+1级GOA单元电路的扫描控制信号ST(N)；
所述第一下拉模块400包括：第四十薄膜晶体管T40，所述第四十薄膜晶体管T40的栅极与源极均电性连接于第一节点Q(N)，漏级电性连接于第四十一薄膜晶体管T41的源极；所述第四十一薄膜晶体管T41的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于第四十薄膜晶体管T40的漏极，漏极电性连接于第二节点D(N)；
所述自举电容500的一端电性连接于第一节点Q(N)，另一端电性连接于第二节点D(N)；
所述下拉维持模块600包括：反相器F1，所述反相器F1的输入端电性连接于第一节点Q(N)，输出端电性连接于第三十二薄膜晶体管T32的栅极、及第四十二薄膜晶体管T42的栅极；第三十二薄膜晶体管T32，所述第三十二薄膜晶体管T32的栅极电性连接于所述反相器F1的输出端，源极电性连接于第四十一薄膜晶体管T41的漏极，漏极电性连接于第一负电位VSS1；第四十二薄膜晶体管T42，所述第四十二薄膜晶体管T42的栅极电性连接于所述反相器F1的输出端，漏极电性连接于第一节点Q(N)，源极电性连接于恒压低电位DCL。
请参阅图5、图6，结合图2、图3、及图9，示意出了本发明GOA电路修复方法的第二实施例。该第二实施例与第一实施例的区别在于，在第N级GOA单元电路中，对上拉控制模块100增设了一个与第十一薄膜晶体管T11并联的第十二薄膜晶体管T12，具体地，所述第十一薄膜晶体管T11的栅极接收上一级第N-1级GOA单元电路的扫描控制信号ST(N-1)，源极电性连接恒压高电位DCH，漏极电性连接第一节点Q(N)，所述第十二薄膜晶体管T12的栅极电性连接一栅极引出线L12，源极电性连接恒压高电位DCH，漏极电性连接第一节点Q(N)。
相应的，对GOA电路进行检测，以第N级、第N+1级这两级GOA单元电路为一组，检测到第N级GOA单元电路正常工作时，使第N级GOA单元电路中的第十二薄膜晶体管T12的栅极引出线L12与所述修复信号线L1绝缘交叠，第N级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1绝缘交叠；第N+1级GOA单元电路中的第十二薄膜晶体管T12的栅极引出线L11与所述修复信号线L1绝缘交叠，第N+1级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1绝缘交叠。
检测到第N级GOA单元电路损坏时，通过激光切断(图6中用叉号表示)第N级GOA单元电路中的扫描信号输出线L2与上拉模块200之间的连接、及第N+1级GOA单元电路中第十一薄膜晶体管T11的漏极与第一节点Q(N+1)的连接，并通过激光熔接(图6中以实心圆表示)导通第N级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1、及第N+1级GOA单元电路中第十二薄膜晶体管T12的栅极引出线L12与所述修复信号线L1，从而将所述修复信号Repair signal接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号，完成对第N级GOA单元电路的修复，使得第N级、第N+1级GOA单元电路仍能正常工作。
其余与第一实施例相同，此处不再赘述。
请参阅图7、图8，结合图2、图3、及图9，示意出了本发明GOA电路修复方法的第三实施例。该第三实施例相比第二实施例，在所述第N级GOA单元电路中增设了一第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于恒压高电位DCH，漏级电性连接于扫描信号输出线L2，源极电性连接一源极引出线L9。
对GOA电路进行检测，以第N级、第N+1级这两级GOA单元电路为一组，检测到第N级GOA单元电路正常工作时，除了像实施例二那样使第N级GOA单元电路中的第十二薄膜晶体管T12的栅极引出线L12与所述修复信号线L1绝缘交叠，第N级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1绝缘交叠，第N+1级GOA单元电路中的第十二薄膜晶体管T12的栅极引出线L11与所述修复信号线L1绝缘交叠，第N+1级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1绝缘交叠以外，还使第N级GOA单元电路中的第九薄膜晶体管T9的源极引出线L9与所述修复信号线L1绝缘交叠，第N+1级GOA单元电路中的第九薄膜晶体管T9的源极引出线L9与所述修复信号线L1绝缘交叠。
检测到第N级GOA单元电路损坏时，第二实施例是通过激光直接熔接第N级GOA单元电路中的扫描信号输出线L2与所述修复信号线L1使得二者导通，而该第三实施例是通过激光熔接第N级GOA单元电路中的第九薄膜晶体管T9的源极引出线L9与所述修复信号线L1，使得扫描信号输出线L2经由第九薄膜晶体管T9与所述修复信号线L1导通，修复信号Repair signal作为第N级GOA单元电路的输出信号经由第九薄膜晶体管T9输出。
其余均与第二实施例相同，此处不再赘述。
请参阅图10、图11、图12，结合图2、图3，示意出了本发明GOA电路修复方法的第四实施例。上述第一、第二、第三实施例均采用修复信号线L1对单一的第N级GOA单元电路进行修复，而该第四实施例能够同时修复两级GOA单元电路：
首先提供级联的多个GOA单元电路、一修复信号Repair signal、与所述修复信号Repair signal电性连接的修复信号线L1、一启动信号STV、及与所述启动信号STV电性连接的启动信号线L5；
其中，每一级GOA单元电路均包括上拉控制模块100、上拉模块200、下传模块300、第一下拉模块400、自举电容500、与下拉维持模块600；
设N为正整数，在第N级GOA单元电路中，所述上拉控制模块100包括并联的第十一薄膜晶体管T11、与第十二薄膜晶体管T12，所述第十一薄膜晶体管T11的栅极接收上一级第N-1级GOA单元电路的扫描控制信号 ST(N-1)，源极电性连接恒压高电位DCH，漏极电性连接第一节点Q(N)，所述第十二薄膜晶体管T12的栅极电性连接一栅极引出线L12，源极电性连接恒压高电位DCH，漏极电性连接第一节点Q(N)；所述下传模块300输出下一级第N+1级GOA单元电路的扫描控制信号ST(N)；所述上拉模块200输出扫描信号G(N)；所述扫描信号G(N)经由扫描信号输出线L2输出。
然后，对GOA电路进行检测，以第N级、第N+1级、第N+2级、与第N+3级这四级GOA单元电路为一组，检测到第N+1级、与第N+2级GOA单元电路正常工作时，使第N级、第N+1级、第N+2级、及第N+3级这四级GOA单元电路各级的第十二薄膜晶体管T12的栅极引出线L12分别与所述修复信号线L1、启动信号线L5绝缘交叠，扫描信号输出线L2分别与所述修复信号线L1、启动信号线L5绝缘交叠。
检测到第N+1级、与第N+2级GOA单元电路损坏时，通过激光切断(图11中用叉号表示)第N+1级GOA单元电路中的扫描信号输出线L2与上拉模块200之间的连接、第N+2级GOA单元电路中第十一薄膜晶体管T11的漏极与第一节点Q(N+2)的连接、第N+2级GOA单元电路中的扫描信号输出线L2与上拉模块200之间的连接、及第N+3级GOA单元电路中第十一薄膜晶体管T11的漏极与第一节点Q(N+3)的连接，并通过激光熔接导通(图11中用实心圆表示)第N+1级GOA单元电路中的扫描信号输出线L2与所述启动信号线L5、第N+2级GOA单元电路中第十二薄膜晶体管T12的栅极引出线L12与所述启动信号线L5、第N+2级GOA单元电路的扫描信号输出线L2与修复信号线L1、及第N+3级GOA单元电路中第十二薄膜晶体管T12的栅极引出线L12与所述修复信号线L1，从而将所述启动信号STV接入第N+1级、及第N+2级GOA单元电路，分别作为第N+1级GOA单元电路的输出信号，及第N+2级GOA单元电路的扫描控制信号，将所述修复信号Repair signal接入第N+2级、及第N+3级GOA单元电路，分别作为第N+2级GOA单元电路的输出信号，及第N+3级GOA单元电路的扫描控制信号，完成对第N+1与第N+2级则会两级GOA单元电路的修复，使得GOA电路仍能正常工作。
如图10、图11所示，第N级GOA单元电路中的上拉模块200、下传模块300、第一下拉模块400、自举电容500、与下拉维持模块600的具体结构与第一实施例相同，此处不再赘述。
图12所示为对应本发明GOA电路修复方法的第四实施例的时序图，其中所述时钟信号CK(M)包含四条高频时钟信号：第一时钟信号CK(1)、第二时钟信号CK(2)、第三时钟信号CK(3)、及第四时钟信号CK(4)，当 所述时钟信号CK(M)为第三时钟信号(CK(3))时，所述第M+2条时钟信号CK(M+2)为第一时钟信号CK(1)，当所述时钟信号CK(M)为第四时钟信号CK(4)时，所述第M+2条时钟信号CK(M+2)为第二时钟信号CK(2)；STV是启动信号，包括两个脉冲，一个脉冲用于电路启动，一个脉冲用于产生第N+1级GOA单元电路的输出信号G(N+1)，以修复第N+1级GOA单元电路；修复信号Repair signal产生第N+2级GOA单元电路的输出信号G(N+2)，以修复第N+2级GOA单元电路。
值得一提的是，以图10、图11所示为例，设第N级、第N+1级、第N+2级、与第N+3级这四级GOA单元电路各自上拉模块200中第二十一薄膜晶体管T21的源极分别电性连接于第一时钟信号CK(1)、第二时钟信号CK(2)、第三时钟信号CK(3)、及第四时钟信号CK(4)，则所述启动信号STV修复的是第二时钟信号CK(2)对应的第N+1级GOA单元电路。
综上所述，本发明提供的GOA电路修复方法，通过修复信号线将修复信号接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号来实现对第N级GOA单元电路的修复；或通过启动信号线将启动信号接入第N+1级、及第N+2级GOA单元电路，分别作为第N+1级GOA单元电路的输出信号，及第N+2级GOA单元电路的扫描控制信号来实现对第N+1级GOA单元电路的修复，同时通过修复信号线将修复信号接入第N+2级、及第N+3级GOA单元电路，分别作为第N+2级GOA单元电路的输出信号，及第N+3级GOA单元电路的扫描控制信号来实现对第N+2级GOA单元电路的修复，能够降低GOA电路的修复难度，提高GOA产品的良率，降低生产成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种GOA电路修复方法，
    首先提供级联的多个GOA单元电路、一修复信号、及与所述修复信号电性连接的修复信号线；
    其中，每一级GOA单元电路均包括上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、与下拉维持模块；
    设N为正整数，在第N级GOA单元电路中，所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的扫描控制信号，源极电性连接恒压高电位，漏极电性连接第一节点；所述下传模块输出下一级第N+1级GOA单元电路的扫描控制信号；所述上拉模块输出扫描信号；所述第十一薄膜晶体管的栅极电性连接一栅极引出线，所述扫描信号经由扫描信号输出线输出；
    然后，对GOA电路进行检测，以第N级、第N+1级这两级GOA单元电路为一组，检测到第N级GOA单元电路正常工作时，使第N级GOA单元电路中的第十一薄膜晶体管的栅极引出线与所述修复信号线绝缘交叠，第N级GOA单元电路中的扫描信号输出线与所述修复信号线绝缘交叠；第N+1级GOA单元电路中的第十一薄膜晶体管的栅极引出线与所述修复信号线绝缘交叠，第N+1级GOA单元电路中的扫描信号输出线与所述修复信号线绝缘交叠；
    检测到第N级GOA单元电路损坏时，通过激光切断第N级GOA单元电路中的扫描信号输出线与上拉模块之间的连接、及第N+1级GOA单元电路中第十一薄膜晶体管的栅极与第N+1级GOA单元电路的扫描控制信号的连接，并通过激光熔接导通第N级GOA单元电路中的扫描信号输出线与所述修复信号线、及第N+1级GOA单元电路中第十一薄膜晶体管的栅极引出线与所述修复信号线，从而将所述修复信号接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号。
  2. 如权利要求1所述的GOA电路修复方法，其中，所述绝缘交叠通过在第一、第二金属层之间夹设绝缘层实现。
  3. 如权利要求1所述的GOA电路修复方法，其中，在第N级GOA单元电路中，所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号， 漏极电性连接于第二节点并输出扫描信号；
    所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出下一级第N+1级GOA单元电路的扫描控制信号；
    所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一薄膜晶体管的源极；所述第四十一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十薄膜晶体管的漏极，漏极电性连接于第二节点；
    所述自举电容的一端电性连接于第一节点，另一端电性连接于第二节点；
    所述下拉维持模块包括：反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第三十二薄膜晶体管的栅极、及第四十二薄膜晶体管的栅极；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于所述反相器的输出端，源极电性连接于第四十一薄膜晶体管的漏极，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于所述反相器的输出端，漏极电性连接于第一节点，源极电性连接于恒压低电位；
    所述时钟信号包含四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；当所述时钟信号为第三时钟信号时，所述第M+2条时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2条时钟信号为第二时钟信号。
  4. 一种GOA电路修复方法，
    首先提供级联的多个GOA单元电路、一修复信号、及与所述修复信号电性连接的修复信号线；
    其中，每一级GOA单元电路均包括上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、与下拉维持模块；
    设N为正整数，在第N级GOA单元电路中，所述上拉控制模块包括并联的第十一薄膜晶体管、与第十二薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的扫描控制信号，源极电性连接恒压高电位，漏极电性连接第一节点，所述第十二薄膜晶体管的栅极电性连接一栅极引出线，源极电性连接恒压高电位，漏极电性连接第一节点；所述下传模块输出下一级第N+1级GOA单元电路的扫描控制信号；所述上拉模块输出扫描信号；所述扫描信号经由扫描信号输出线输出；
    然后，对GOA电路进行检测，以第N级、第N+1级这两级GOA单元 电路为一组，检测到第N级GOA单元电路正常工作时，使第N级GOA单元电路中的第十二薄膜晶体管的栅极引出线与所述修复信号线绝缘交叠，第N级GOA单元电路中的扫描信号输出线与所述修复信号线绝缘交叠；第N+1级GOA单元电路中的第十二薄膜晶体管的栅极引出线与所述修复信号线绝缘交叠，第N+1级GOA单元电路中的扫描信号输出线与所述修复信号线绝缘交叠；
    检测到第N级GOA单元电路损坏时，通过激光切断第N级GOA单元电路中的扫描信号输出线与上拉模块之间的连接、及第N+1级GOA单元电路中第十一薄膜晶体管的漏极与第一节点的连接，并通过激光熔接导通第N级GOA单元电路中的扫描信号输出线与所述修复信号线、及第N+1级GOA单元电路中第十二薄膜晶体管的栅极引出线与所述修复信号线，从而将所述修复信号接入第N级、及第N+1级GOA单元电路，分别作为第N级GOA单元电路的输出信号，及第N+1级GOA单元电路的扫描控制信号。
  5. 如权利要求4所述的GOA电路修复方法，其中，在所述第N级GOA单元电路中，还包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于恒压高电位，漏级电性连接于扫描信号输出线，源极电性连接一源极引出线；
    对GOA电路进行检测，以第N级、第N+1级这两级GOA单元电路为一组，检测到第N级GOA单元电路正常工作时，还使第N级GOA单元电路中的第九薄膜晶体管的源极引出线与所述修复信号线绝缘交叠，第N+1级GOA单元电路中的第九薄膜晶体管的源极引出线与所述修复信号线绝缘交叠；
    检测到第N级GOA单元电路损坏时，通过激光熔接第N级GOA单元电路中的第九薄膜晶体管的源极引出线与所述修复信号线，从而导通扫描信号输出线与所述修复信号线。
  6. 如权利要求4所述的GOA电路修复方法，其中，所述绝缘交叠通过在第一、第二金属层之间夹设绝缘层实现。
  7. 如权利要求5所述的GOA电路修复方法，其中，所述绝缘交叠通过在第一、第二金属层之间夹设绝缘层实现。
  8. 如权利要求4所述的GOA电路修复方法，其中，在第N级GOA单元电路中，所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于第二节点并输出扫描信号；
    所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出下一级第N+1级GOA单元电路的扫描控制信号；
    所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一薄膜晶体管的源极；所述第四十一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十薄膜晶体管的漏极，漏极电性连接于第二节点；
    所述自举电容的一端电性连接于第一节点，另一端电性连接于第二节点；
    所述下拉维持模块包括：反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第三十二薄膜晶体管的栅极、及第四十二薄膜晶体管的栅极；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于所述反相器的输出端，源极电性连接于第四十一薄膜晶体管的漏极，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于所述反相器的输出端，漏极电性连接于第一节点，源极电性连接于恒压低电位；
    所述时钟信号包含四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；当所述时钟信号为第三时钟信号时，所述第M+2条时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2条时钟信号为第二时钟信号。
  9. 如权利要求5所述的GOA电路修复方法，其中，在第N级GOA单元电路中，所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于第二节点并输出扫描信号；
    所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出下一级第N+1级GOA单元电路的扫描控制信号；
    所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一薄膜晶体管的源极；所述第四十一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十薄膜晶体管的漏极，漏极电性连接于第二节点；
    所述自举电容的一端电性连接于第一节点，另一端电性连接于第二节点；
    所述下拉维持模块包括：反相器，所述反相器的输入端电性连接于第 一节点，输出端电性连接于第三十二薄膜晶体管的栅极、及第四十二薄膜晶体管的栅极；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于所述反相器的输出端，源极电性连接于第四十一薄膜晶体管的漏极，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于所述反相器的输出端，漏极电性连接于第一节点，源极电性连接于恒压低电位；
    所述时钟信号包含四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；当所述时钟信号为第三时钟信号时，所述第M+2条时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2条时钟信号为第二时钟信号。
  10. 一种GOA电路修复方法，
    首先提供级联的多个GOA单元电路、一修复信号、与所述修复信号电性连接的修复信号线、一启动信号、及与所述启动信号电性连接的启动信号线；
    其中，每一级GOA单元电路均包括上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、与下拉维持模块；
    设N为正整数，在第N级GOA单元电路中，所述上拉控制模块包括并联的第十一薄膜晶体管、与第十二薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的扫描控制信号，源极电性连接恒压高电位，漏极电性连接第一节点，所述第十二薄膜晶体管的栅极电性连接一栅极引出线，源极电性连接恒压高电位，漏极电性连接第一节点；所述下传模块输出下一级第N+1级GOA单元电路的扫描控制信号；所述上拉模块输出扫描信号；所述扫描信号经由扫描信号输出线输出；
    然后，对GOA电路进行检测，以第N级、第N+1级、第N+2级、与第N+3级这四级GOA单元电路为一组，检测到第N+1级、与第N+2级GOA单元电路正常工作时，使第N级、第N+1级、第N+2级、及第N+3级这四级GOA单元电路各级的第十二薄膜晶体管的栅极引出线分别与所述修复信号线、启动信号线绝缘交叠，扫描信号输出线分别与所述修复信号线、启动信号线绝缘交叠；
    检测到第N+1级、与第N+2级GOA单元电路损坏时，通过激光切断第N+1级GOA单元电路中的扫描信号输出线与上拉模块之间的连接、第N+2级GOA单元电路中第十一薄膜晶体管的漏极与第一节点的连接、第N+2级GOA单元电路中的扫描信号输出线与上拉模块之间的连接、及第N+3级GOA单元电路中第十一薄膜晶体管的漏极与第一节点的连接，并通 过激光熔接导通第N+1级GOA单元电路中的扫描信号输出线与所述启动信号线、第N+2级GOA单元电路中第十二薄膜晶体管的栅极引出线与所述启动信号线、第N+2级GOA单元电路的扫描信号输出线与修复信号线、及第N+3级GOA单元电路中第十二薄膜晶体管的栅极引出线与所述修复信号线，从而将所述启动信号接入第N+1级、及第N+2级GOA单元电路，分别作为第N+1级GOA单元电路的输出信号，及第N+2级GOA单元电路的扫描控制信号，将所述修复信号接入第N+2级、及第N+3级GOA单元电路，分别作为第N+2级GOA单元电路的输出信号，及第N+3级GOA单元电路的扫描控制信号。
  11. 如权利要求10所述的GOA电路修复方法，其中，所述绝缘交叠通过在第一、第二金属层之间夹设绝缘层实现。
  12. 如权利要求10所述的GOA电路修复方法，其中，在第N级GOA单元电路中，所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于第二节点并输出扫描信号；
    所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出下一级第N+1级GOA单元电路的扫描控制信号；
    所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一薄膜晶体管的源极；所述第四十一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十薄膜晶体管的漏极，漏极电性连接于第二节点；
    所述自举电容的一端电性连接于第一节点，另一端电性连接于第二节点；
    所述下拉维持模块包括：反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第三十二薄膜晶体管的栅极、及第四十二薄膜晶体管的栅极；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于所述反相器的输出端，源极电性连接于第四十一薄膜晶体管的漏极，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于所述反相器的输出端，漏极电性连接于第一节点，源极电性连接于恒压低电位；
    所述时钟信号包含四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；当所述时钟信号为第三时钟信号时，所述第M+2条时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时， 所述第M+2条时钟信号为第二时钟信号。
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