WO2016169366A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2016169366A1
WO2016169366A1 PCT/CN2016/076475 CN2016076475W WO2016169366A1 WO 2016169366 A1 WO2016169366 A1 WO 2016169366A1 CN 2016076475 W CN2016076475 W CN 2016076475W WO 2016169366 A1 WO2016169366 A1 WO 2016169366A1
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common electrode
pattern
insulating layer
array substrate
disposed
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PCT/CN2016/076475
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English (en)
French (fr)
Inventor
冯博
马禹
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/516,130 priority Critical patent/US9958748B2/en
Publication of WO2016169366A1 publication Critical patent/WO2016169366A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • Thin film transistor liquid crystal displays are currently the most mainstream display devices, and most of the electronic products such as mobile phone screens, monitor screens, and televisions use thin film transistor liquid crystal displays.
  • the good display quality of thin film transistor liquid crystal displays enables customers to have a good viewing experience and to make them in a favorable position in the fierce market competition.
  • the double-gate thin film transistor liquid crystal display has a low cost and has certain advantages in competition.
  • the resistance of the common electrode is large, so that the common electrode is susceptible to voltage fluctuations caused by other signals, thereby affecting the quality of the display, for example, the screen display is generated. flicker.
  • the technical solution adopted to solve the above problems is an array substrate, a preparation method thereof, and a display device.
  • An array substrate provided by the present invention includes: a plurality of pixel units arranged in a matrix on a substrate, each of the pixel units being respectively connected with two gate lines and one data line, each of the pixel units including two sub-pixels Each of the sub-pixels is respectively connected with a gate line and the data line, two gate lines are disposed between two adjacent rows of pixel units, and a data line is disposed between adjacent two columns of pixel units, wherein
  • the pixel unit includes a third common electrode disposed on the substrate, a second common electrode disposed in the same layer as the gate line, and a first common electrode disposed in the same layer as the source and drain metal, wherein the first common electrode, The second common electrode and the third common electrode are electrically connected.
  • the first common electrode includes: a bit disposed in parallel with the gate line a first portion between adjacent rows of pixel units in the same column; and a second portion between the two sub-pixels of the pixel unit that is parallel to the data line, wherein the first portion and the second portion of the first common electrode Electrical connection.
  • the pixel unit further includes: a first insulating layer disposed on the source and drain metal layers; and a conductive layer disposed on the first insulating layer, the conductive layer passing through the first common a first portion of the third via corresponding to the second portion of the first insulating layer and a second via located at the first insulating layer corresponding to the first portion of the first common electrode will be the first common
  • the first portion and the second portion of the electrode are electrically connected.
  • the first portion of the third via is located at a position on the first insulating layer corresponding to the end of the second portion of the first common electrode, and the second via is located on the first insulating layer A position corresponding to a position corresponding to a first portion of the first common electrode and an end of the second portion.
  • the first common electrode of the pixel unit adjacent to the column is electrically connected by the first via located at the first insulating layer corresponding to the first portion of the respective first common electrode.
  • the first via hole is located at a position of the first insulating layer corresponding to an end of the first portion of the first common electrode.
  • the pixel unit further includes: a second common electrode disposed in the same layer as the gate line, and a projection of the second common electrode and the second portion of the first common electrode in a direction perpendicular to the substrate Partially coincident,
  • the second common electrode is electrically connected to the first common electrode.
  • a second insulating layer is disposed between the gate line and the source and drain layers; the third via further includes a second portion penetrating the drain metal layer and a second through the second insulating layer
  • the conductive layer electrically connects the first portion, the second portion, and the second common electrode of the first common electrode through the third via.
  • the second common electrode and the second portion of the first common electrode coincide in a projection perpendicular to the direction of the substrate.
  • the second common electrode is disposed on the third common electrode.
  • Another object of the present invention is to provide a method for preparing an array substrate, Includes the following steps:
  • a pattern of a first insulating layer formed by a patterning process on a substrate forming a pattern of source and drain electrodes, a pattern of a first via located at a first portion of the first insulating layer, a pattern of the first via and a second via;
  • the first common electrode and the second common electrode are connected.
  • Another object of the present invention is to provide a display device including the above array substrate.
  • the invention provides an array substrate, a preparation method thereof, and a display device.
  • the first common electrode is formed on the source/drain metal layer, and the first common electrode is connected to the second common electrode and the third common electrode to effectively reduce the resistance of the common electrode.
  • the voltage fluctuation caused by the common electrode is not easily affected by other signals, thereby improving the quality of the display, for example, preventing the screen display from flickering.
  • Embodiment 1 is a schematic structural view of an array substrate in Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of an array substrate after forming a third common electrode in Embodiment 1 of the present invention
  • FIG. 3 is a schematic structural view of an array substrate after forming a gate electrode and a second common electrode in Embodiment 1 of the present invention
  • FIG. 4 is a schematic structural view of an array substrate after forming a pattern of a second insulating layer in Embodiment 1 of the present invention
  • FIG. 5 is a schematic structural diagram of an array substrate after forming a first common electrode in Embodiment 1 of the present invention
  • FIG. 6 is a schematic structural view of an array substrate after forming a pattern of a first insulating layer in Embodiment 1 of the present invention
  • FIG. 7 is a schematic structural view of an array substrate after forming a pattern of a conductive layer in Embodiment 1 of the present invention.
  • the embodiment provides an array substrate and a preparation method thereof.
  • the array substrate in this embodiment includes: a plurality of pixel units 14 arranged in a matrix on the substrate 1, each of the pixel units 14 connecting two gate lines 3 and one data line 5, respectively.
  • the pixel unit 14 includes two sub-pixels 11, each of which is connected to a corresponding gate line 3 and the data line 5, and two gate lines 3 are disposed between two rows of pixel units 14 of adjacent rows.
  • a data line 5 is disposed between two adjacent columns of pixel units 14.
  • the pixel unit 14 includes a third common electrode 2 disposed on the substrate 1, a second common electrode 32 disposed in the same layer as the gate line 3, and a first common electrode 51 disposed in the same layer as the source and drain electrodes; A common electrode 51, the second common electrode 32, and the third common electrode 2 are electrically connected.
  • the first common electrode is formed on the source/drain metal layer, and the first common electrode is connected to the second common electrode and the third common electrode to effectively reduce the resistance of the common electrode, so that the common electrode is not easily subjected to other signals.
  • the effect causes voltage fluctuations, thereby improving the quality of the display, for example, preventing the screen display from flickering.
  • the sub-pixel 11 of the pixel unit 14 may be set as any one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • the adjacent three sub-pixels 11 may be sequentially arranged in a red sub-pixel, a green sub-pixel, and a blue sub-image to form one display pixel.
  • the first common electrode 51 includes: a first portion 511 between the adjacent rows of pixel units 14 arranged in parallel with the gate line 3; and a sum between two sub-pixels 11 of the pixel unit 14
  • the second portion 512 of the data line 5 is parallel; the first portion 511 and the second portion 512 of the first common electrode 51 are electrically connected.
  • the first portion 511 is located at a space between the gate lines 3 of the adjacent column of adjacent pixels, that is, a portion that does not coincide with the gate line 3 in a direction perpendicular to the substrate 1.
  • the pixel unit 14 further includes: a first insulating layer 6 disposed on the source and drain metal layers; and a conductive layer 7 disposed on the first insulating layer 6, the conductive layer 7 passing through a second portion 512 of the first common electrode 51 corresponding to the first portion of the third via 8 of the first insulating layer 6 and a first insulating layer corresponding to the first portion 511 of the first common electrode 51
  • the second via 9 of 6 electrically connects the first portion 511 and the second portion 512 of the first common electrode 51.
  • the first portion of the third via is located at a position on the first insulating layer 6 corresponding to the end of the second portion 512 of the first common electrode 51; the second via 9 is located at the first portion
  • An insulating layer 6 is at a position corresponding to a position corresponding to the end of the first portion 511 of the first common electrode 51 and the second portion 512.
  • the second via 9 is located at a position on the first insulating layer 6 corresponding to the midpoint of the first portion 511 of the first common electrode 51.
  • the first portion and the second via 9 of the third via 8 are arranged such that the two portions of the first common electrode 51 are electrically connected using the shortest connection line, reducing the resistance of the common electrode.
  • the first common electrode 51 of the pixel unit adjacent to the adjacent column is electrically connected through the first via hole 10 located in the first insulating layer 6 corresponding to the first portion 511 of the first common electrode 51.
  • This can electrically connect the common electrodes on the entire array substrate, further reducing the resistance of the common electrode.
  • the first via 10 is located at a position of the first insulating layer corresponding to an end of the first portion 511 of the first common electrode 51. This enables the first common electrode 51 of the adjacent pixel unit 14 to be electrically connected using the shortest connection line.
  • the pixel unit 14 further includes: a second common electrode 32 fabricated in the same layer as the gate line 3, the second common electrode 32 and the second portion 512 of the first common electrode 51 being perpendicular to the substrate The projections in the direction partially overlap.
  • the second common electrode 32 is electrically connected to the first common electrode 51.
  • the second common electrode 32 partially overlaps the second portion 512 of the first common electrode 51, so that the area of the light transmitting region is not excessively reduced. After the second common electrode 32 is electrically connected to the first common electrode 51, the resistance of the common electrode can be further reduced.
  • a second insulating layer 4 is disposed between the gate metal layer forming the gate line and the gate and the source and drain layers;
  • the third via 8 includes a first through the source and drain metal layers a second portion and a third portion penetrating the second insulating layer 4, the conductive layer 7 passing the first common electrode 51 through the first portion, the second portion, the third portion and the second via 9 of the third via 8
  • the first portion 511, the second portion 512, and the second common electrode 32 are electrically connected.
  • the second common electrode 32 coincides with the projection of the second portion 512 of the first common electrode 51 in a direction perpendicular to the substrate 1.
  • the second common electrode 32 and the second portion 512 of the first common electrode 51 are perpendicular to the The directions of the substrates 1 are completely overlapped, and the area of the light-transmitting regions can be increased.
  • the second common electrode 32 is disposed on the third common electrode 2 such that the second common electrode 32 and the third common electrode 2 are directly connected without a via.
  • the third common electrode 2 and the second common electrode 32 are electrically connected to the first common electrode 51, so that the common electrodes of the entire array substrate are connected to form a common electrode distributed in a mesh shape, thereby further reducing the resistance of the common electrode.
  • the third via 8 is a through hole formed by a first portion, a second portion, and a third portion respectively located in the first insulating layer, the source/drain layer, and the second insulating layer.
  • the three-part description is more convenient to describe.
  • a transparent metal layer is coated on the substrate 1, and a pattern of the third common electrode 2 is formed by a patterning process including exposure, development, and etching, and the transparent metal layer is an indium tin oxide layer (ITO layer).
  • ITO layer indium tin oxide layer
  • a pattern of the third common electrode 2 is formed on the substrate 1 by a known patterning process, and it is seen from FIG. 2 that the portion covered by the third common electrode 2 will form one pixel unit 14.
  • a gate metal layer is deposited on the substrate 1 on which the pattern of the third common electrode is formed, and the gate line 3 and the gate electrode 31 and the second common electrode are formed by a patterning process including exposure, development, and etching.
  • a second insulating layer 4 is deposited on the substrate 1 on which the pattern of the gate line 3 and the gate electrode 31 and the second common electrode 32 is formed, and the pattern penetrating through the second insulating layer 4 is formed by a patterning process.
  • the third portion of the third via 8 corresponding to the end of the second common electrode 32 is described.
  • a pattern of the active layer is formed on the substrate 1 on which the pattern of the second insulating layer 4 is formed by a patterning process, and the pattern is concentrated on the thin film transistor 12, and the drawings are not separately.
  • a source drain, a pattern of the data line and the first common electrode 51, and a third pass are formed on the substrate 1 on which the pattern of the active layer is formed by a patterning process.
  • the hole 8 is located in the second portion of the source and drain layers.
  • a pattern of the conductive layer 7 is formed on the substrate 1 on which the pattern of the first insulating layer 6 is formed by a patterning process, and the conductive layer 7 passes through the first via hole 10, the second via hole 9, The first portion, the second portion, and the third portion of the third via 8 electrically connect the first common electrode 51 and the second common electrode 32. It should be understood that the conductive layer 7 is used to fabricate the pixel electrode 13.
  • the third via 8 is a through hole formed by the first portion, the second portion, and the third portion of the first insulating layer, the source and drain layers, and the second insulating layer, respectively. Part of the description can be more convenient to describe.
  • array substrate may further include other necessary functional layers, which will not be further described herein.
  • This embodiment provides a display device including the above array substrate.
  • the array substrate is formed by forming a first common electrode on the source/drain metal layer while forming the second common electrode and the third common electrode, and the first common electrode, the second common electrode and the third common electrode are connected to effectively reduce the common
  • the resistance of the electrodes makes the common electrodes less susceptible to voltage fluctuations caused by other signals, thereby improving the quality of the display, for example, preventing the screen display from flickering.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供了一种阵列基板及其制备方法、显示装置，用于解决现有技术中存在的由于公共电极的布局不合理，造成公共电极的电阻较大，公共电极容易受到其他信号的影响而引起的电压波动，从而影响显示器的品质等问题。提供的阵列基板及其制备方法、显示装置由于在源漏极金属层制作第一公共电极（51），并且还制作有第二公共电极（32）和第三公共电极（2），并且该第一公共电极（51）与第二公共电极（32）、第三公共电极（2）连接，从而能有效的降低公共电极的电阻，使公共电极不容易受到其他信号的影响而引起电压波动，从而改善显示器的品质。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明涉及显示技术领域，具体地，涉及一种阵列基板及其制备方法、显示装置。
背景技术
薄膜晶体管液晶显示器是目前最主流的显示器件，手机屏幕、监视器屏幕、电视等电子产品中绝大多数使用的都是薄膜晶体管液晶显示器。薄膜晶体管液晶显示器的良好显示品质，能够使客户有好的观看体验，并且使其在激烈的市场竞争处于有利地位。其中双栅薄膜晶体管液晶显示器的成本较低，在竞争中有一定优势。但是，双栅薄膜晶体管液晶显示器由于其公共电极的布局不合理，造成公共电极的电阻较大，使得公共电极容易受到其他信号的影响而引起电压波动，从而影响显示器的品质，例如，屏幕显示产生闪烁。
发明内容
解决上述问题所采用的技术方案是一种阵列基板及其制备方法、显示装置。
本发明提供的一种阵列基板，包括：在基板上呈矩阵排列的多个像素单元，每个所述像素单元分别连接两条栅线和一条数据线，每个所述像素单元包括两个子像素，每个所述子像素分别连接一条栅线和所述数据线，相邻两行像素单元之间设有两条栅线，以及相邻两列像素单元之间设有一条数据线，其中，
所述像素单元包括设置在基板上的第三公共电极、与栅线同层设置的第二公共电极、与源漏极金属同层设置的第一公共电极，其中，所述第一公共电极、所述第二公共电极和第三公共电极之间电连接。
优选的，所述第一公共电极包括：与所述栅线平行设置的位 于同列相邻行像素单元之间的第一部分；和位于像素单元的两个子像素之间的与所述数据线平行的第二部分，其中，所述第一公共电极的第一部分和第二部分电连接。
优选的，所述像素单元还包括：设置于所述源漏极金属层上的第一绝缘层以及设置在所述第一绝缘层上的导电层，所述导电层通过与所述第一公共电极的第二部分对应的位于第一绝缘层的第三过孔的第一部分、和与所述第一公共电极的第一部分对应的位于第一绝缘层的第二过孔将所述第一公共电极的第一部分和第二部分电连接。
优选的，所述第三过孔的第一部分位于第一绝缘层上与所述第一公共电极的第二部分的端部对应的位置处，且所述第二过孔位于第一绝缘层上与所述第一公共电极的第一部分与所述第二部分的端部对应的位置相对应位置处。
优选的，同行相邻列的像素单元的第一公共电极通过与各自第一公共电极的第一部分对应的位于第一绝缘层的第一过孔电连接。
优选的，所述的第一过孔位于所述第一绝缘层的与所述第一公共电极的第一部分的端部对应的位置处。
优选的，所述像素单元还包括：与栅线同层设置的第二公共电极，所述第二公共电极与所述第一公共电极的第二部分在垂直于所述基板的方向上的投影部分重合，其中
所述第二公共电极与所述的第一公共电极电连接。
优选的，所述栅线与所述源漏极层之间设有第二绝缘层；所述第三过孔还包括贯穿所述漏极金属层的第二部分和贯穿第二绝缘层的第三部分，所述导电层通过第三过孔将所述第一公共电极的第一部分、第二部分和第二公共电极电连接。
优选的，所述第二公共电极与所述第一公共电极的第二部分在垂直于所述基板方向上的投影重合。
优选的，所述第二公共电极设置在所述第三公共电极上。
本发明的另一个目的还在于提供一种阵列基板的制备方法， 包括以下步骤：
在基板上通过构图工艺形成第三公共电极的图形；
在形成第三公共电极图形的基板上通过构图工艺形成栅极、栅线和第二公共电极的图形，其中，所述第二公共电极设置在所述第三公共电极上；
在形成栅极、栅线和第二公共电极的图形的基板上通过构图工艺形成第二绝缘层的图形、及第三过孔位于第二绝缘层的第三部分的图形；
在形成第二绝缘层的图形的基板上通过构图工艺形成有源层的图形；
在形成有源层的图形的基板上通过构图工艺形成源漏极、数据线和第一公共电极的图形、及第三过孔位于源漏极层的第二部分的图形；
在形成源漏极的图形的基板上通过构图工艺形成的第一绝缘层的图形、第三过孔位于第一绝缘层的第一部分的图形、第一过孔和第二过孔的图形；以及
在形成第一绝缘层的图形的基板上通过构图工艺形成的导电层的图形，其中，所述导电层通过第一过孔、第二过孔、第三过孔将像素单元及相邻像素单元的第一公共电极和第二公共电极连接。
本发明的另一个目的还在于提供一种显示装置，包括上述的阵列基板。
本发明提供阵列基板及其制备方法、显示装置由于在源漏极金属层制作第一公共电极，该第一公共电极与第二公共电极、第三公共电极连接能有效的降低公共电极的电阻，使公共电极不容易受到其他信号的影响而引起的电压波动，从而改善显示器的品质，例如，防止屏幕显示产生闪烁。
附图说明
图1为本发明实施例1中的阵列基板的结构示意图；
图2为本发明实施例1中形成第三公共电极后的阵列基板的结构示意图；
图3为本发明实施例1中形成栅极和第二公共电极后的阵列基板的结构示意图；
图4为本发明实施例1中形成第二绝缘层的图形后的阵列基板的结构示意图；
图5为本发明实施例1中形成第一公共电极后的阵列基板的结构示意图；
图6为本发明实施例1中形成第一绝缘层的图形后的阵列基板的结构示意图；
图7为本发明实施例1中形成导电层的图形后的阵列基板的结构示意图；
其中，1.基板；2.第三公共电极；3.栅线；31.栅极；32.第二公共电极；4.第二绝缘层；5.数据线；51.第一公共电极；511.第一部分；512.第二部分；6.第一绝缘层；7.导电层；8.第三过孔；9.第二过孔；10.第一过孔；11.子像素；12.薄膜晶体管；13.像素电极；14.像素单元。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
如图1-7所示，本实施例提供了一种阵列基板及其制备方法。
具体地，本实施例中的阵列基板包括：在基板1上呈矩阵排列的多个像素单元14，每个所述像素单元14分别连接两条栅线3和一条数据线5，每个所述像素单元14包括两个子像素11，每个所述子像素11分别连接一条相对应的栅线3和所述数据线5，相邻行的两行像素单元14之间设有两条栅线3；相邻的两列像素单元14之间设有一条数据线5。
所述像素单元14包括设置在基板1上的第三公共电极2、与栅线3同层设置的第二公共电极32、与源漏极金属同层设置的第一公共电极51；所述第一公共电极51、所述第二公共电极32和第三公共电极2之间电连接。
本实施例中通过在源漏极金属层制作第一公共电极，该第一公共电极与第二公共电极、第三公共电极连接能有效的降低公共电极的电阻，使公共电极不容易受到其他信号的影响而引起电压波动，从而改善显示器的品质，例如，防止了屏幕显示产生闪烁。
需要指出的是，上述像素单元14的子像素11可以设置为红色亚像素、绿色亚像素、蓝色亚像素中任意一个。为了显示需要，可以将相邻的3个子像素11按红色亚像素、绿色亚像素、蓝色亚像依次设置，以形成一个显示像素。
优选的，所述第一公共电极51包括：与所述栅线3平行设置的位于同列相邻行像素单元14之间的第一部分511；和位于像素单元14的两个子像素11之间的与所述数据线5平行的第二部分512；所述第一公共电极51的第一部分511和第二部分512电连接。其中，第一部分511位于同列相邻像素单元14的栅线3之间空白处，即在垂直于基板1的方向上与栅线3没有重合部分。
优选的，所述像素单元14还包括：设置于所述源漏极金属层上的第一绝缘层6以及设置在所述第一绝缘层6上的导电层7，所述导电层7通过与所述第一公共电极51的第二部分512对应的位于第一绝缘层6的第三过孔8的第一部分，和与所述第一公共电极51的第一部分511对应的位于第一绝缘层6的第二过孔9将所述第一公共电极51的第一部分511和第二部分512电连接。
优选的，所述的第三过孔的第一部分位于第一绝缘层6上与所述第一公共电极51的第二部分512的端部对应的位置处；所述第二过孔9位于第一绝缘层6上与所述第一公共电极51的第一部分511与所述第二部分512的端部对应的位置相对应的位置处。例如，当像素单元14被所述第一公共电极51的第二部分512分成面积相等的两部分时，也就是说，当第一公共电极51的第二部 分512位于像素单元14的横向中心处时，第二过孔9就位于第一绝缘层6上与第一公共电极51的第一部分511的中点相对应的位置处。
这样设置第三过孔8的第一部分和第二过孔9能使用最短的连接线将第一公共电极51的两部分进行电连接，降低公共电极的电阻。
优选的，同行相邻列的像素单元的第一公共电极51通过与所述第一公共电极51的第一部分511对应的位于第一绝缘层6的第一过孔10电连接。这样能将整个阵列基板上的公共电极进行电连接，进一步降低公共电极的电阻。
所述的第一过孔10位于所述第一绝缘层的与所述第一公共电极51的第一部分511的端部对应的位置。这样能使用最短的连接线将相邻像素单元14的第一公共电极51电连接。
优选的，所述像素单元14还包括：与栅线3同层制作的第二公共电极32，所述第二公共电极32与所述第一公共电极51的第二部分512在垂直于基板的方向上的投影部分重合。
所述第二公共电极32与所述第一公共电极51电连接。
这样，第二公共电极32与第一公共电极51的第二部分512部分重合，能保证透光区的面积不被过分缩小。第二公共电极32与所述的第一公共电极51电连接之后能够进一步的降低公共电极的电阻。
具体地，在形成栅线和栅极的栅极金属层与所述源漏极层之间设有第二绝缘层4；所述第三过孔8包括贯穿所述源漏极金属层的第二部分和贯穿第二绝缘层4的第三部分，所述导电层7通过第三过孔8的第一部分、第二部分、第三部分和第二过孔9将所述第一公共电极51的第一部分511、第二部分512和第二公共电极32电连接。
优选的，所述第二公共电极32与所述第一公共电极51的第二部分512在垂直于所述基板1方向上的投影重合。这样第二公共电极32与第一公共电极51的第二部分512的在垂直于所述所 述基板1的方向完全重合，能够增加透光区的面积。
所述的第二公共电极32设置在所述第三公共电极2上，这样第二公共电极32和第三公共电极2直接连接，无需过孔。
这样将第三公共电极2、第二公共电极32与第一公共电极51电连接，从而使整个阵列基板的公共电极进行连接形成网状分布的公共电极，进一步降低公共电极的电阻。
应当理解的是，所述的第三过孔8是由分别位于第一绝缘层、源漏极层和第二绝缘层中的第一部分、第二部分、第三部分构成的贯穿孔，上述分三部分说明能更方便的描述。
下面介绍一下上述的阵列基板的制备方法，包括以下步骤：
S1：在基板1上涂覆一层透明金属层，通过包括曝光、显影及刻蚀的构图工艺形成第三公共电极2的图形，所述透明金属层为氧化铟锡层(ITO层)。
如图2所示，采用已知的构图工艺在基板1上形成第三公共电极2的图形，从图2中可见第三公共电极2覆盖的部分将形成一个像素单元14。
S2：如图3所示，在形成有第三公共电极的图形的基板1上沉积栅金属层，通过包括曝光、显影及刻蚀的构图工艺形成栅线3及栅极31和第二公共电极32的图形，其中，第三公共电极2之间的区域用于设置栅线3和数据线5；这样第三公共电极2与第二公共电极32直接电连接，无需过孔结构。
S3：如图4所示，在形成有栅线3及栅极31和第二公共电极32的图形的基板1上沉积第二绝缘层4，通过构图工艺形成贯穿第二绝缘层4的与所述第二公共电极32的端部对应的第三过孔8的第三部分。
S4：在形成有第二绝缘层4的图形的基板1上通过构图工艺形成有源层的图形，图形集中于薄膜晶体管12上，不再单独附图。
S5：如图5所示，在形成有有源层的图形的基板1上通过构图工艺形成源漏极、数据线和第一公共电极51的图形、及第三过 孔8位于源漏极层的第二部分。
S6：如图6所示，在形成有源漏极的图形的基板1上通过构图工艺形成的第一绝缘层6的图形、第三过孔8位于第一绝缘层6的第一部分的图形、第一过孔10和第二过孔9的图形。
S7：如图7所示，在形成有第一绝缘层6的图形的基板1上通过构图工艺形成导电层7的图形，所述导电层7通过第一过孔10、第二过孔9、第三过孔8的第一部分、第二部分、第三部分，将第一公共电极51和第二公共电极32电连接。应当理解的是，导电层7用于制作像素电极13。
应当理解的是，所述的第三过孔8是由分别位于第一绝缘层、源漏极层和第二绝缘层的第一部分、第二部分、第三部分构成的贯穿孔，上述分三部分说明能更方便的描述。
应当理解的是，阵列基板还可以包括其它必要的功能层，在此不再一一赘述。
实施例2
本实施例提供一种显示装置，包括上述的阵列基板。
上述阵列基板通过在源漏极金属层制作第一公共电极，同时形成有第二公共电极和第三公共电极，并且第一公共电极、第二公共电极和第三公共电极连接能有效的降低公共电极的电阻，使公共电极不容易受到其他信号的影响而引起电压波动，从而改善显示器的品质，例如，防止屏幕显示产生闪烁。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

  1. 一种阵列基板，包括：在基板上呈矩阵排列的多个像素单元，每个所述像素单元分别连接两条栅线和一条数据线，每个所述像素单元包括两个子像素，每个所述子像素分别连接一条栅线和所述数据线，相邻两行的像素单元之间设有两条栅线，以及相邻两列像素单元之间设有一条数据线，其特征在于，
    所述像素单元包括设置在基板上的第三公共电极、与栅线同层设置的第二公共电极、与源漏极金属同层设置的第一公共电极，其中，所述第一公共电极、所述第二公共电极和第三公共电极之间电连接。
  2. 如权利要求1所述的阵列基板，其特征在于，所述第一公共电极包括：与所述栅线平行设置的位于同列相邻行像素单元之间的第一部分；和位于像素单元的两个子像素之间的与所述数据线平行的第二部分，其中，所述第一公共电极的第一部分和第二部分电连接。
  3. 如权利要求2所述的阵列基板，其特征在于，所述像素单元还包括：设置于所述源漏极金属层上的第一绝缘层以及设置在所述第一绝缘层上的导电层，所述导电层通过与所述第一公共电极的第二部分对应的位于第一绝缘层的第三过孔的第一部分、和与所述第一公共电极的第一部分对应的位于第一绝缘层的第二过孔将所述第一公共电极的第一部分和第二部分电连接。
  4. 如权利要求3所述的阵列基板，其特征在于，所述第三过孔的第一部分位于第一绝缘层上与所述第一公共电极的第二部分的端部对应的位置处，且所述第二过孔位于第一绝缘层上与所述第一公共电极的第一部分与所述第二部分的端部对应的位置相对应位置处。
  5. 如权利要求3所述的阵列基板，其特征在于，同行相邻列的像素单元的第一公共电极通过与各自第一公共电极的第一部分对应的位于第一绝缘层的第一过孔电连接。
  6. 如权利要求5所述的阵列基板，其特征在于，所述的第一过孔位于所述第一绝缘层的与所述第一公共电极的第一部分的端部对应的位置处。
  7. 如权利要求2所述的阵列基板，其特征在于，所述像素单元还包括：与栅线同层设置的第二公共电极，所述第二公共电极与所述第一公共电极的第二部分在垂直于所述基板的方向上的投影部分重合，其中
    所述第二公共电极与所述的第一公共电极电连接。
  8. 如权利要求7所述的阵列基板，其特征在于，所述栅线与所述源漏极层之间设有第二绝缘层；所述第三过孔还包括贯穿所述源漏极金属层的第二部分和贯穿所述第二绝缘层的第三部分，所述导电层通过第三过孔将所述第一公共电极的第一部分、第二部分和第二公共电极电连接。
  9. 如权利要求8所述的阵列基板，其特征在于，所述第二公共电极与所述第一公共电极的第二部分在垂直于所述基板方向上的投影重合。
  10. 如权利要求7所述的阵列基板，其特征在于，所述第二公共电极设置在所述第三公共电极上。
  11. 一种阵列基板的制备方法，其特征在于，包括以下步骤：
    在基板上通过构图工艺形成第三公共电极的图形；
    在形成了第三公共电极图形的基板上通过构图工艺形成栅极、栅线和第二公共电极的图形，其中，所述第二公共电极设置在所述第三公共电极上；
    在形成了栅极、栅线和第二公共电极的图形的基板上通过构图工艺形成第二绝缘层的图形、及第三过孔位于第二绝缘层的第三部分的图形；
    在形成了第二绝缘层的图形的基板上通过构图工艺形成有源层的图形；
    在形成了有源层的图形的基板上通过构图工艺形成源漏极、数据线和第一公共电极的图形、及第三过孔位于源漏极层的第二部分的图形；
    在形成了源漏极的图形的基板上通过构图工艺形成第一绝缘层的图形、第三过孔位于第一绝缘层的第一部分的图形、第一过孔和第二过孔的图形；以及
    在形成了第一绝缘层的图形的基板上通过构图工艺形成导电层的图形，其中，所述导电层通过第一过孔、第二过孔、第三过孔将像素单元及相邻像素单元的第一公共电极和第二公共电极连接。
  12. 一种显示装置，其特征在于包括如权1-10任一项所述的阵列基板。
PCT/CN2016/076475 2015-04-23 2016-03-16 阵列基板及其制备方法、显示装置 Ceased WO2016169366A1 (zh)

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