WO2016165430A1 - 数据中转方法、装置、通信系统和计算机存储介质 - Google Patents

数据中转方法、装置、通信系统和计算机存储介质 Download PDF

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Publication number
WO2016165430A1
WO2016165430A1 PCT/CN2016/070871 CN2016070871W WO2016165430A1 WO 2016165430 A1 WO2016165430 A1 WO 2016165430A1 CN 2016070871 W CN2016070871 W CN 2016070871W WO 2016165430 A1 WO2016165430 A1 WO 2016165430A1
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port
clock
data
power
data stream
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PCT/CN2016/070871
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English (en)
French (fr)
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龚翠玲
张涛
钟赛飞
程伟森
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中兴通讯股份有限公司
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Publication of WO2016165430A1 publication Critical patent/WO2016165430A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

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  • the present invention relates to the field of communications, and in particular, to a data relay method, apparatus, communication system, and computer storage medium.
  • the network coverage is generally performed by using a BBU (Building Baseband Unit) and a RRU (Remote Radio Unit).
  • BBU Building Baseband Unit
  • RRU Remote Radio Unit
  • the BBU provides 10G optical ports.
  • the BBUs and RRUs are connected through optical fibers to achieve distributed distribution, The deployment of the base station requires more fiber resources and is costly, and will result in waste of Ethernet twisted pair resources.
  • Embodiments of the present invention are directed to a data transfer method, apparatus, communication system, and computer storage medium, which at least partially solve the problem of high deployment cost of existing distributed base stations.
  • An embodiment of the present invention provides a data transfer method, including:
  • the clock acquisition module obtains a synchronization clock of the data stream, and the synchronization port controls the lower interface to forward the data stream to the downstream device; wherein the clock acquisition module is respectively connected to the uplink port and the lower interface;
  • the data stream is forwarded to the downstream device through the downlink interface connected to the downstream device.
  • the method further includes: de-synchronizing the synchronous clock obtained by the clock acquisition module by the clock de-bounce module, and causing the clock acquisition module to control the downlink port to forward the data stream to the downstream device based on the synchronization clock obtained by the de-bounce re-generation.
  • the clock acquisition module comprises: a dual-port physical layer chip, or two single-port physical layer chips connected according to a serial/deserial interface standard protocol; acquiring a synchronous clock of the data stream, and controlling the lower port based on the synchronous clock
  • Forwarding the data stream to the downstream device includes: obtaining a synchronization clock of the data stream through a connection between the physical layer port and the uplink port, and forwarding the data stream to another physical layer port, through another physical layer port and the The connection of the lower link is based on the synchronization clock to control the downlink port to forward the data stream to the downstream device.
  • the uplink port and the downlink port respectively include: a fiber interface and an Ethernet interface
  • the data transfer method further includes: selecting a corresponding interface according to the connection requirement.
  • the method further includes: controlling, by the control module, powering on the device, and monitoring the operating state.
  • the method further includes: obtaining power through the power module, and supplying power to the data relay device.
  • the power module acquiring the power includes: obtaining power through an external power source, and/or acquiring power from an upstream device configured as a power supply terminal.
  • the method further includes: supplying power to the downstream device as the power receiving device by using the power module.
  • An embodiment of the present invention provides a data relay device, including:
  • the uplink port is connected to the upstream device and configured to receive the data stream of the upstream device.
  • the clock acquisition module is connected to the uplink port and the lower interface, and is configured to acquire a synchronization clock of the data stream, and the synchronization port controls the downlink port to forward the data stream to the downstream device.
  • the lower interface is connected to the downstream device and configured to forward data streams to downstream devices.
  • the method further includes: a clock debounce module configured to de-vibrate the synchronous clock obtained by the clock acquisition module, and enable the clock acquisition module to control the synchronization clock based on the debounced regeneration
  • the downlink port forwards the data stream to the downstream device.
  • the clock debounce module comprises: a digital phase locked loop and a voltage controlled crystal oscillator, or an analog secondary phase locked loop and a voltage controlled crystal oscillator.
  • the clock acquisition module comprises: a dual-port physical layer chip, or two single-port physical layer chips connected according to a serial/deserial interface standard protocol; and one physical layer port is connected to the upper interface for acquiring data
  • the synchronous clock of the stream is forwarded to another physical layer port, and the other physical layer port is connected to the lower interface.
  • the synchronous interface is configured to forward the data stream to the downstream device based on the synchronous clock.
  • the upper interface and the lower interface respectively include: a fiber interface and an Ethernet interface, and are configured to select a corresponding interface according to the connection requirement.
  • the method further includes: a control module configured to control device initialization and power state monitoring.
  • a power module is further configured to obtain power and supply power to the data relay device.
  • the power module is configured to obtain power through an external power source and/or to obtain power from an upstream device disposed as a power supply terminal.
  • the power module is further configured to supply power to the downstream device as the powered device.
  • An embodiment of the present invention provides a communication system, including: a baseband processing unit, a baseband data packet transmission device, a radio remote unit, and a data relay device provided by the present invention, and the baseband processing unit and the radio remote unit pass the data relay device and The baseband data packet transmission device performs data transfer.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute at least one of the foregoing data transfer methods.
  • the embodiment of the present invention provides a data transfer method, a device, a communication system, and a computer storage medium.
  • the transfer device includes an upper and lower joint port to complete data forwarding, and further includes a clock synchronization module.
  • the data stream sent to the downstream device has the same synchronous clock as the data stream sent by the upstream device, which solves the problem that the Ethernet twisted pair cannot be transmitted over long distances and clock synchronization. On this basis, the BBU and the RRU can transit.
  • the device uses the existing Ethernet twisted pair resources to deploy the distributed system, which avoids the waste of the existing Ethernet twisted pair resources and reduces the deployment cost of the distributed system; optionally, the uplink port And the lower port respectively include: a fiber interface and an Ethernet interface, which are used to select a corresponding interface according to the connection requirement, so that the device can realize electro-optical, photoelectric, and electro-electrical conversion; optionally, the power module is used to obtain electric energy through an external power source. And/or, obtaining power from the upstream device set as the power supply terminal can also solve the problem of difficulty in taking power in some scenes.
  • FIG. 1 is a schematic structural diagram of a communication system according to a first embodiment of the present invention
  • FIG. 2 is a flowchart of a data transfer method according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a power module according to a third embodiment of the present invention.
  • the communication system provided by the present invention includes: a baseband processing unit 1, a radio remote unit, and a data relay device. 3 and the baseband data packet transmission device 4, the baseband processing unit 1 and the radio remote unit 2 perform data transfer through the data relay device 3 and the baseband data packet transmission device 4.
  • the data relay device 3 provided by the embodiment of the present invention includes:
  • the uplink port 31 is connected to the upstream device and configured to receive the data stream of the upstream device.
  • the clock acquisition module 32 is connected to the uplink port 31 and the lower interface 33, and is configured to acquire a synchronization clock of the data stream, and control the lower port 33 to forward the data stream to the downstream device based on the synchronous clock.
  • the lower interface 33 is connected to the downstream device and configured to forward the data stream to the downstream device.
  • the data relay device 3 in the above embodiment further includes a clock debounce module 34 configured to de-vibrate the synchronous clock acquired by the clock acquisition module, and based on the clock acquisition module.
  • the synchronous clock obtained by the re-growth is controlled, and the lower joint port is controlled to forward the data stream to the downstream device.
  • the clock debounce module 34 in the above embodiment includes: a digital phase locked loop and a voltage controlled crystal oscillator, or an analog secondary phase locked loop and a voltage controlled crystal oscillator.
  • the clock acquisition module 32 in the above embodiment includes: a dual port physical layer chip, or two single port physical layer chips connected based on a serial/deserial interface standard protocol; and one physical layer port connection
  • the uplink port is configured to obtain a synchronous clock of the data stream, and forward the data stream to another physical layer port, and the other physical layer port is connected to the lower joint port, and is configured to forward the data stream to the downstream device according to the synchronous clock control.
  • the upper port 31 and the lower port 32 in the foregoing embodiments respectively include: a fiber interface and an Ethernet interface, and are configured to select a corresponding interface according to the connection requirement.
  • the data relay device 3 in the above embodiment further includes a control module 35 configured to control device power-on initialization and monitoring of an operational state.
  • the data relay device 3 in the above embodiment further includes a power module 36 configured to obtain power and supply power to the data relay device.
  • the power module 36 of the above embodiment is configured to obtain electrical energy through an external power source, and/or to obtain electrical energy from an upstream device disposed as a power supply terminal.
  • the power module 36 in the above embodiment is further configured to supply power to a downstream device that is a powered device.
  • FIG. 2 is a flowchart of a data transfer method according to a second embodiment of the present invention. As shown in FIG. 2, in the embodiment, the data transfer method provided by the present invention includes the following steps:
  • S201 Connect the upstream device through the uplink port and receive the data flow of the upstream device.
  • the clock acquisition module is connected to the uplink port and the lower interface to obtain a synchronization clock of the data stream.
  • the synchronization port controls the downlink port to forward the data stream to the downstream device.
  • the clock acquisition module is connected to the uplink port and the lower port.
  • the clock acquisition module is further configured to acquire the synchronous clock.
  • S203 Connect the downstream device through the downlink interface to forward the data stream to the downstream device.
  • the upstream device is connected through the uplink port
  • the clock acquisition module is connected to the uplink port and the lower port in step S202
  • the lower port in the step S203 is connected to the downstream device, which may be
  • the preparatory operations that are completed before the corresponding steps are performed may also correspond to the components of the steps.
  • the upstream device connected to the upstream device may be pre-completed before receiving the data stream of the upstream device, or may be connected first when receiving the data stream, and receiving data.
  • the method in the foregoing embodiment further includes: performing, by the clock debounce module, a synchronous clock debounce replay obtained by the clock acquisition module, and causing the clock acquisition module to control the synchronization port based on the synchronized clock obtained by the debounce regeneration.
  • the downstream device forwards the data stream.
  • the clock acquisition module in the above embodiment includes: a dual port physical layer chip, or two single port physical layer chips connected based on a serial/deserial interface standard protocol.
  • the step S202 may include: connecting the uplink port through one physical layer port, acquiring a synchronization clock of the data stream, and forwarding the data stream to another physical layer port, and connecting to the lower interface through another physical layer port, based on synchronization The clocked interface forwards the data stream to the downstream device.
  • the uplink port and the downlink port in the foregoing embodiment respectively include: a fiber interface and an Ethernet interface
  • the data forwarding method further includes: selecting a corresponding interface according to the connection requirement.
  • the method in the above embodiment further includes: controlling, by the control module, power-on initialization, and monitoring of an operational state.
  • the method of the above embodiment further includes acquiring power through the power module and powering the data relay device.
  • obtaining power through the power module in the above embodiment includes: acquiring power through an external power source, and/or acquiring power from an upstream device disposed as a power supply terminal.
  • the method in the foregoing embodiment further includes: supplying power to the downstream device as the powered terminal device by using the power module.
  • the data relay device supports recovering the clock from the service data, and the clock is used as a reference clock for transmitting the service data to the lower stage after the debounce is regenerated, thereby implementing clock synchronization of the upstream and downstream devices.
  • the data transfer device includes: two external optical ports and two RJ45 interfaces (a commonly used Ethernet interface), a dual port PHY chip (physical layer chip) / two single port PHY slices, a clock debounce module, and a control module , power module; where:
  • the optical port/RJ45 interface connected to the upstream device is called the uplink port.
  • the optical port/RJ45 interface connected to the downstream device is called the lower port.
  • Both the upper port and the lower port can be connected to the upstream device or downstream device through the network cable (such as CAT5, CAT6, etc.) or the optical fiber, and support the optical port to electrical port conversion, the electrical port to the optical port conversion, and the electrical port to Electric port conversion;
  • the PHY chip can be a dual-port PHY chip or two single-port PHY chips. Each port supports optical mutual exclusion, and the uplink port sets the Ethernet synchronous clock recovery function and outputs the recovery clock.
  • the serdes between the two PHY chip ports. (Serializer-Deserializer) is connected by SGMII (Serial Gigabit Media Independent Interface, interface between PHY and MAC);
  • the clock debounce module the main device is a digital phase-locked loop/analog second-stage phase-locked loop externally controlled crystal oscillator for de-jittering the Ethernet synchronous clock recovered by the PHY from the uplink receiving data, and Rebirth frequency, sent to the lower joint port as the transmission reference clock;
  • the control module is used for power-on initialization and state monitoring of the PHY chip and the clock debounce module;
  • the power module 36 is divided into four parts, including a PD (Powered Device) module 361 and a PSE (Power Sourcing Equipment) module 362, which are used for external power supply.
  • the PD module 361 obtains power through the POE to supply power to the internal chip.
  • the PSE module 362 connects the downstream device through the network cable to provide POE power for the downstream device.
  • the power interface 363 is used for the uplink port. When the optical port is connected, connect and use an external power supply.
  • the data relay device can flexibly solve the remote problem of long-distance transmission of the network cable, support multi-level cascading, and can also support data synchronization based on the Ethernet clock; when the uplink port uses the RJ45 interface mode, the device can be used. POE power supply; when the lower link uses the RJ45 interface mode, the downstream device can use POE to supply power; support multiple conversion scenarios, including optical port to electrical port conversion, electrical port to electrical port conversion, and electrical port to optical port conversion.
  • the uplink PHY chip After the data transfer device is connected to the optical fiber or the network cable through the uplink port, the uplink PHY chip extracts the Ethernet synchronous clock from the data, and provides a transmission reference to the lower PHY device after the clock debounce regenerative module.
  • the clock, the serdes of the uplink PHY slice transfers the data to the serdes of the lower PHY slice, and the lower link PHY sends the data to the downstream device with reference to the clock, and transmits the data to the downstream device through the lower link optical fiber or the network cable.
  • a typical application scenario of the data relay device provided by the present invention includes: scenario 1 is used when the transmission distance is less than 200 m, and the electrical port is used as the electrical port of the first-level forwarding device; and scenario 2 is when the transmission distance exceeds 200 m but less than 500 m.
  • scenario 1 is used when the transmission distance is less than 200 m, and the electrical port is used as the electrical port of the first-level forwarding device; and scenario 2 is when the transmission distance exceeds 200 m but less than 500 m.
  • scenario 3 is to meet the transmission distance in some scenarios, use two forwarding devices cascade, the first level uses the electrical port to light port, the first The secondary uses the optical port to switch the electrical port, and the two stages are connected by optical fibers.
  • the workflow of the data relay device is basically the same, including the following steps:
  • Step 1 Power on the device.
  • the hardware block diagram of the power module is shown in Figure 3.
  • the power-on mode of the device can be obtained through the external power interface or the PD module of the POE.
  • the uplink port When the uplink port is transmitted by the network cable, it can be powered on by the POE mode.
  • the uplink port is used for fiber transmission, it can only be solved by an external power supply.
  • the downstream device When the lower link is transmitted using the network cable, the downstream device can also be powered by the POE.
  • the local device is connected to the upstream device through a network cable.
  • the PD module of the POE standard in the power module determines and acquires the 48V power supply, and distributes the power to the device through the voltage converter to provide power; and also provides power to the PSE.
  • the power is supplied to the PD of the lower level POE.
  • the second-stage forwarding device uses an external power source, such as an AC-DC power supply.
  • the second step the board chip initialization.
  • the initialization work includes: configuring the working mode of the PHY chip port, such as configuring to Gigabit full duplex, configuring the uplink PHY port to be slave mode, configuring the downlink PHY port as the master mode; configuring the number of the clock debounce unit A phase-locked loop or a two-stage analog phase-locked loop produces the required clock frequency.
  • the third step the uplink PHY chip receives the data signal from the upstream device and extracts the clock.
  • the physical layer code of Ethernet is 4B/5B (FE, Fast Ethernet, Fast Ethernet, refers to 100M Ethernet) and 8B/10B (GE, Gigabit Ethernet, Gigabit Ethernet) for easy clock extraction.
  • the PHY slice extracts the high-precision clock transmitted by the network from the physical layer data stream and outputs the data stream, and the data stream is further transmitted to the lower-link PHY for processing.
  • the fourth step the clock debounce module performs debounce regeneration on the uplink PHY recovery clock.
  • the synchronous recovery clock extracted from the Ethernet data is very jittery and must be debounced to meet the clock requirements in the synchronous Ethernet device (NE) of the G.8262 specification.
  • the main function module of the clock debounce module can be a digital phase-locked loop or a two-stage analog phase-locked loop and an external (voltage control). Crystal oscillator.
  • the first-stage loop of the digital phase-locked loop or the second-stage analog phase-locked loop can achieve below 10hz, or even 0.01hz, and has good debounce performance on the reference clock.
  • the NCO numbererically controlled oscillator
  • the high-frequency VCO voltage controlled oscillator
  • Step 5 The downlink PHY chip uses the clock output from the clock debounce module as the transmission reference clock to send data to the downstream device.
  • the uplink PHY slice transmits data to the lower PHY slice through the serdes interface, and the PHY slice sends the reference clock to send data out.
  • the data relay device provided by the embodiment of the invention provides the Ethernet clock synchronization function and eliminates the dependence on the external power supply through the POE technology, and provides a convenient installation and placement environment for the Ethernet synchronous network relay.
  • the embodiment of the present invention provides a data transfer method and device, where the transfer device includes an upper and lower joint port to complete data forwarding, and further includes a clock synchronization module, so that the data stream sent to the downstream device and the data sent by the upstream device
  • the flow has the same synchronous clock, which solves the problem that the Ethernet twisted pair cannot be transmitted over long distances and clocks.
  • the BBU and the RRU can be distributed through the existing Ethernet twisted pair resources through the relay device. The deployment of the system avoids the waste of existing Ethernet twisted pair resources and reduces the deployment cost of the distributed system;
  • the upper interface and the lower interface respectively include: an optical fiber interface and an Ethernet interface, and are used to select a corresponding interface according to the connection requirement, so that the device can implement electro-optical, photoelectric, and electrical-electrical conversion;
  • the power module is configured to obtain power through an external power source, and/or to obtain power from an upstream device that is configured as a power supply terminal, and the power module can also solve the problem of difficulty in taking power in some scenarios.
  • An embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to implement the data transfer party. At least one of the methods, for example, the method as shown in 2 can be performed.
  • the computer storage medium may be a storage medium such as an optical disk, a hard disk, or a magnetic disk, and may be a non-transitory storage medium.

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Abstract

本发明提供了一种数据中转方法、装置、通信系统和计算机存储介质，该方法包括：通过上联口接收上游设备的数据流；通过时钟获取模块获取数据流的同步时钟，基于同步时钟控制下联口向下游设备转发数据流；通过下联口向下游设备转发数据流。

Description

数据中转方法、装置、通信系统和计算机存储介质 技术领域
本发明涉及通信领域，尤其涉及一种数据中转方法、装置、通信系统和计算机存储介质。
背景技术
在室内部署分布式基站时，一般采用BBU(Building Baseband Unit，基带处理单元)和RRU(Remote Radio Unit，射频拉远单元)的方式进行网络覆盖。在实际应用中，BBU提供的是10G光口，而当前楼宇建筑等室内环境一般都部署了大量的以太网双绞线，而没有部署光纤，因此，如果通过光纤对接BBU和RRU以实现分布式基站的部署，需要较多的光纤资源，成本高，而且将导致以太网双绞线资源的浪费。
因此，如何提供一种降低分布式基站部署成本的数据中转方法，是本领域技术人员亟待解决的技术问题。
发明内容
本发明实施例期望提供了一种数据中转方法、装置、通信系统和计算机存储介质，至少部分解决现有分布式基站部署成本高的问题。
本发明实施例提供了一种数据中转方法，其包括：
通过与上游设备连接的上联口接收上游设备的数据流；
通过时钟获取模块获取数据流的同步时钟，基于同步时钟控制下联口向下游设备转发数据流；其中，所述时钟获取模块分别与所述上联口和所述下联口连接；
通过与下游设备连接的所述下联口向下游设备转发数据流。
可选地，还包括：通过时钟去抖模块对时钟获取模块获取的同步时钟去抖重生，并使得时钟获取模块基于去抖重生得到的同步时钟，控制下联口向下游设备转发数据流。
可选地，时钟获取模块包括：双端口物理层芯片，或者，两个基于串行/解串行接口标准协议连接的单端口物理层芯片；获取数据流的同步时钟，基于同步时钟控制下联口向下游设备转发数据流包括：通过一个物理层端口与所述上联口的连接，获取数据流的同步时钟，并将数据流转发至另一物理层端口，通过另一物理层端口与所述下联口的连接，基于同步时钟控制下联口向下游设备转发数据流。
可选地，上联口及下联口分别包括：光纤接口及以太网接口，数据中转方法还包括：根据连接需要选择对应的接口。
可选地，还包括：通过控制模块控制设备上电初始化、以及运作状态的监控。
可选地，还包括：通过电源模块获取电能，并为数据中转装置供电。
可选地，电源模块获取电能包括：通过外置电源获取电能，和/或，从作为供电端设置的上游设备获取电能。
可选地，还包括：通过电源模块为作为受电端设备的下游设备进行供电。
本发明实施例提供了一种数据中转装置，其包括：
上联口，连接上游设备，配置为接收上游设备的数据流；
时钟获取模块，与上联口及下联口连接，配置为获取数据流的同步时钟，基于同步时钟控制下联口向下游设备转发数据流；
下联口，连接下游设备，配置为向下游设备转发数据流。
可选地，还包括：时钟去抖模块，配置为对时钟获取模块获取的同步时钟去抖重生，并使得时钟获取模块基于去抖重生得到的同步时钟，控制 下联口向下游设备转发数据流。
可选地，时钟去抖模块包括：数字锁相环及压控晶体振荡器，或者，模拟二级锁相环及压控晶体振荡器。
可选地，时钟获取模块包括：双端口物理层芯片，或者，两个基于串行/解串行接口标准协议连接的单端口物理层芯片；一个物理层端口连接上联口，用于获取数据流的同步时钟，并将数据流转发至另一物理层端口，另一物理层端口与下联口连接，配置为基于同步时钟控制下联口向下游设备转发数据流。
可选地，上联口及下联口分别包括：光纤接口及以太网接口，配置为根据连接需要选择对应的接口。
可选地，还包括：控制模块，配置为控制设备上电初始化、以及运作状态的监控。
可选地，还包括电源模块，配置为获取电能，并为数据中转装置供电。
可选地，电源模块配置为通过外置电源获取电能，和/或，从作为供电端设置的上游设备获取电能。
可选地，电源模块还配置为为作为受电端设备的下游设备进行供电。
本发明实施例提供了一种通信系统，其包括：基带处理单元、基带数据分组传输设备、射频拉远单元以及本发明提供的数据中转装置，基带处理单元与射频拉远单元通过数据中转装置及基带数据分组传输设备进行数据中转。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行前述数据中转方法的至少其中之一。
本发明实施例提供了一种数据中转方法、装置、通信系统及计算机存储介质，该中转装置包括上下联口，完成数据转发，还包括时钟同步模块， 使得发送给下流设备的数据流与上流设备发送的数据流具备相同的同步时钟，解决了以太网双绞线无法长距离传输及时钟同步的问题，在此基础上，BBU和RRU就可以通过中转装置采用现有的以太网双绞线资源进行分布式系统的部署，在避免了现有以太网双绞线资源浪费的同时，还降低了分布式系统的部署成本；可选地，上联口及下联口分别包括：光纤接口及以太网接口，用于根据连接需要选择对应的接口，这样设备可以实现电光、光电、电电转换；可选地，电源模块用于通过外置电源获取电能，和/或，从作为供电端设置的上游设备获取电能，也可解决部分场景取电困难问题。
附图说明
图1为本发明第一实施例提供的通信系统的结构示意图；
图2为本发明第二实施例提供的数据中转方法的流程图；
图3为本发明第三实施例提供的电源模块的结构示意图。
具体实施方式
现通过具体实施方式结合附图的方式对本发明做出进一步的诠释说明，应当理解，以下所说明的优选实施例仅用于说明和解释本发明，并不用于限定本发明。
第一实施例：
图1为本发明第一实施例提供的通信系统的结构示意图，由图1可知，在本实施例中，本发明提供的通信系统包括：基带处理单元1、射频拉远单元2、数据中转装置3及基带数据分组传输设备4，基带处理单元1与射频拉远单元2通过数据中转装置3及基带数据分组传输设备4进行数据中转。
如图1所示，在一些实施例中，本发明实施例提供的数据中转装置3包括：
上联口31，连接上游设备，配置为接收上游设备的数据流；
时钟获取模块32，分别与与上联口31及下联口33连接，配置为获取数据流的同步时钟，基于同步时钟控制下联口33向下游设备转发数据流；
下联口33，连接下游设备，配置为向下游设备转发数据流。
如图1所示，在一些实施例中，上述实施例中的数据中转装置3还包括时钟去抖模块34，配置为对时钟获取模块获取的同步时钟去抖重生，并使得时钟获取模块基于去抖重生得到的同步时钟，控制下联口向下游设备转发数据流。
在一些实施例中，上述实施例中的时钟去抖模块34包括：数字锁相环及压控晶体振荡器，或者，模拟二级锁相环及压控晶体振荡器。
在一些实施例中，上述实施例中的时钟获取模块32包括：双端口物理层芯片，或者，两个基于串行/解串行接口标准协议连接的单端口物理层芯片；一个物理层端口连接上联口，配置为获取数据流的同步时钟，并将数据流转发至另一物理层端口，另一物理层端口与下联口连接，配置为基于同步时钟控制下联口向下游设备转发数据流。
在一些实施例中，上述实施例中的上联口31及下联口32分别包括：光纤接口及以太网接口，配置为根据连接需要选择对应的接口。
如图1所示，在一些实施例中，上述实施例中的数据中转装置3还包括控制模块35，配置为控制设备上电初始化、以及运作状态的监控。
如图1所示，在一些实施例中，上述实施例中的数据中转装置3还包括电源模块36，配置为获取电能，并为数据中转装置供电。
在一些实施例中，上述实施例中的电源模块36配置为通过外置电源获取电能，和/或，从作为供电端设置的上游设备获取电能。
在一些实施例中，上述实施例中的电源模块36还配置为为作为受电端设备的下游设备进行供电。
第二实施例：
图2为本发明第二实施例提供的数据中转方法的流程图，由图2可知，在本实施例中，本发明提供的数据中转方法包括以下步骤：
S201：通过上联口连接上游设备并接收上游设备的数据流；
S202：通过时钟获取模块与上联口及下联口连接，获取数据流的同步时钟，基于同步时钟控制下联口向下游设备转发数据流；这里的时钟获取模块与上联口和下联口都连接，该时钟获取模块还用于获取所述同步时钟。
S203：通过下联口连接下游设备，向下游设备转发数据流。
值得注意的是：在步骤S201中所述通过上联口连接上游设备，在步骤S202中时钟获取模块与上联口和下联口都连接，及步骤S203中的下联口连接下游设备，可以是在执行对应步骤之前就完成的预备操作，也可以对应步骤的组成部分。例如，通过上联口连接上游设备可以在接收上游设备的数据流之前就预先完成的预备步骤，也可以是在需要接收数据流时，先进行连接，在接收数据。
在一些实施例中，上述实施例中的方法还包括：通过时钟去抖模块对时钟获取模块获取的同步时钟去抖重生，并使得时钟获取模块基于去抖重生得到的同步时钟，控制下联口向下游设备转发数据流。
在一些实施例中，上述实施例中的时钟获取模块包括：双端口物理层芯片，或者，两个基于串行/解串行接口标准协议连接的单端口物理层芯片。相应地，步骤S202可包括：通过一个物理层端口连接上联口，获取数据流的同步时钟，并将数据流转发至另一物理层端口，通过另一物理层端口与下联口连接，基于同步时钟控制下联口向下游设备转发数据流。
在一些实施例中，上述实施例中的上联口及下联口分别包括：光纤接口及以太网接口，数据中转方法还包括：根据连接需要选择对应的接口。
在一些实施例中，上述实施例中的方法还包括：通过控制模块控制设备上电初始化、以及运作状态的监控。
在一些实施例中，上述实施例中的方法还包括通过电源模块获取电能，并为数据中转装置供电。
在一些实施例中，上述实施例中的通过电源模块获取电能包括：通过外置电源获取电能，和/或，从作为供电端设置的上游设备获取电能。
在一些实施例中，上述实施例中的方法还包括：通过电源模块为作为受电端设备的下游设备进行供电。
现结合具体应用场景对本发明做可选地诠释说明。
第三实施例：
本实施例提供的数据中转装置支持从业务数据中恢复时钟，时钟经过去抖重生后作为向下级发送业务数据的参考时钟，从而实现上下游设备时钟同步。该数据中转装置包括：两个对外光口和两个RJ45接口(一种常用的以太网接口)，双端口PHY片(物理层芯片)/两个单端口PHY片，时钟去抖模块，控制模块，电源模块；其中：
连接上游设备的光口/RJ45接口称为上联口，连接下游设备的光口/RJ45接口称为下联口。上联口和下联口都可以通过网线(如CAT5、CAT6等不同标准的网线)或者光纤分别与上游设备或下游设备相连，支持光口到电口转换、电口到光口转换、电口到电口转换；
PHY片可以为一片双端口PHY片或者两片单端口PHY片，每个端口支持光电互斥，且上联口设置以太网同步时钟恢复功能，并输出恢复时钟；两个PHY片端口间的serdes((Serializer-Deserializer，串行/解串行通信接口)通过SGMII(Serial Gigabit Media Independent Interface，PHY与MAC之间的接口)连接；
时钟去抖模块，主要器件是数字锁相环/模拟二级锁相环外加压控晶体振荡器，用于对PHY从上联口接收数据中恢复的的以太网同步时钟进行去抖动，并且重生频率，送给下联口作为发送参考时钟；
控制模块用于对PHY片、时钟去抖模块进行上电初始化及状态监控；
如图3所示，电源模块36分四部分，包括基于POE协议的PD(Powered Device，受电端设备)模块361、PSE(Power Sourcing Equipment，供电端设备)模块362，用于外接电源的电源接口363，以及用于给本机内芯片工作所需电能的供电模块364。PD模块361在上联口连接网线后，通过POE获取电源，给本机内芯片供电；PSE模块362，若通过网线连接下游设备，为下游设备提供POE电源；电源接口363，若上联口使用光口连接时，连接并使用外置电源供电。
在实际应用中，数据中转装置可以灵活解决网线长距离传输的拉远问题，支持多级级联；还可以支持基于以太网时钟的数据同步；上联口使用RJ45接口方式时，本装置可使用POE供电；下联口使用RJ45接口方式时，下游设备可使用POE供电；支持多种转换场景，包括光口到电口转换，电口到电口转换，电口到光口转换。
本发明实施例提供的数据中转装置，通过上联口连接光纤或者网线后，上联口PHY片从数据中提取出以太网同步时钟，经过时钟去抖重生模块后给下联口PHY片提供发送参考时钟，上联口PHY片的serdes把数据转给下联口PHY片的serdes，下联口PHY以该时钟为参考发送数据给下游设备，通过下联口光纤或者网线把数据传给下游设备。
下面说明本发明所提供装置的数据传输过程以供实施参考。
本发明提供的数据中转装置的典型应用场景包括：场景1在传输距离不超过200m情况下用，使用一级转发装置的电口转电口方式；场景2是传输距离超过200m但低于500m时使用，需要使用多级转发装置转发，使用电口转电口方式；场景3是满足某些场景下传输距离过长，使用两个转发装置级联，第一级使用电口转光口，第二级使用光口转电口方式，两级之间通过光纤连接。
在上述几种场景中，数据中转装置的工作流程基本相同，包括以下步骤：
第一步：设备上电。
电源模块硬件框图见图3。设备取电方式可通过外接电源接口或POE的PD模块获取。上联口使用网线传输时，可通过POE方式上电；上联口使用光纤传输时，只能通过外接电源解决。当下联口使用网线传输时，下游设备也可以通过POE供电。在场景1中，本端设备通过网线连接上游设备，电源模块中符号POE标准的PD模块判断并获取48V电源，分给经过电压转换器转换给本装置芯片工作提供电源；还给PSE提供电源，以供下级POE的PD获取电源。场景3中，第二级转发装置使用外接电源，如AC-DC电源供电。
第二步：单板芯片初始化。
由控制模块负责，初始化工作包括：配置PHY片端口的工作模式，如配置成千兆全双工，上联PHY端口配置成从模式，下联PHY端口配置成主模式；配置时钟去抖单元的数字锁相环或两级模拟锁相环产生所需时钟频率。
第三步：上联口PHY片接收来自上游设备的数据信号并提取时钟。
以太网的物理层编码为4B/5B(FE，Fast Ethernet，快速以太网，指的是百兆以太网)和8B/10B(GE，Gigabit Ethernet，千兆以太网)，方便提取时钟。PHY片从物理层数据码流中提取网络传递的高精度时钟并输出，数据流继续传给下联口PHY处理。
第四步：时钟去抖模块对上联口PHY恢复时钟进行去抖重生。
从以太网数据中提取的同步恢复时钟抖动很大，必须经过去抖处理才能满足G.8262规范的同步以太网设备(网元)中时钟要求。时钟去抖模块的主要功能模块可以是数字锁相环也可以是二级模拟锁相环及外接(压控) 晶体振荡器。数字锁相环或二级模拟锁相环的第一级环路可以做到10hz以下，甚至到0.01hz，具有对参考时钟进行很好的去抖性能。完成去抖功能后，就可以通过数字锁相环内部NCO(numerically controlled oscillator，数字控制振荡器)或模拟锁相环第二级环内置的高频VCO(voltage controlled oscillator，电压控制震荡器)来产生下联口PHY片所需发送工作时钟。
第五步：下联PHY芯片以时钟去抖模块输出的时钟作为发送参考时钟给下游设备发送数据。
上联口PHY片把数据经过serdes接口传给下联口PHY片，PHY片使用发送参考时钟往外发数据。
本发明实施例提供的数据中转装置，提供了以太网时钟同步功能并通过POE技术，取消了对外界电源的依赖，为以太网同步网络中继提供了便利的安装放置环境。
综上可知，本发明实施例提供了一种数据中转方法及装置，该中转装置包括上下联口，完成数据转发，还包括时钟同步模块，使得发送给下流设备的数据流与上流设备发送的数据流具备相同的同步时钟，解决了以太网双绞线无法长距离传输及时钟同步的问题，在此基础上，BBU和RRU就可以通过中转装置采用现有的以太网双绞线资源进行分布式系统的部署，在避免了现有以太网双绞线资源浪费的同时，还降低了分布式系统的部署成本；
可选地，上联口及下联口分别包括：光纤接口及以太网接口，用于根据连接需要选择对应的接口，这样设备可以实现电光、光电、电电转换；
可选地，电源模块配置为通过外置电源获取电能，和/或，从作为供电端设置的上游设备获取电能，也电源模块也可解决部分场景取电困难问题。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于实现所述数据中转方 法的至少其中之一，例如，可执行如2所示的方法。所述计算机存储介质可为光盘、硬盘或磁盘等存储介质，可选为非瞬间存储介质。
以上仅是本发明的具体实施方式而已，并非对本发明做任何形式上的限制，凡按照本发明原理所作的修改，都应当理解为落入本发明的保护范围。

Claims (19)

  1. 一种数据中转方法，包括：
    通过与上游设备连接的上联口接收所述上游设备的数据流；
    通过时钟获取模块获取所述数据流的同步时钟，基于所述同步时钟控制下联口向所述下游设备转发所述数据流；其中，所述时钟获取模块分别与所述上联口和所述下联口连接；
    通过与下游设备连接的所述下连口向所述下游设备转发所述数据流。
  2. 如权利要求1所述的数据中转方法，其中，还包括：通过时钟去抖模块对所述时钟获取模块获取的所述同步时钟去抖重生，并使得所述时钟获取模块基于去抖重生得到的同步时钟，控制所述下联口向所述下游设备转发所述数据流。
  3. 如权利要求1所述的数据中转方法，其中，所述时钟获取模块包括：双端口物理层芯片，或者，两个基于串行/解串行接口标准协议连接的单端口物理层芯片；
    所述获取所述数据流的同步时钟，基于所述同步时钟控制所述下联口向所述下游设备转发所述数据流包括：
    通过一个物理层端口与所述上联口的连接，获取所述数据流的同步时钟，并将所述数据流转发至另一物理层端口，通过所述另一物理层端口与所述下联口的连接，基于所述同步时钟控制所述下联口向所述下游设备转发所述数据流。
  4. 如权利要求1所述的数据中转方法，其中，所述上联口及所述下联口分别包括：光纤接口及以太网接口，所述数据中转方法还包括：根据连接需要选择对应的接口。
  5. 如权利要求1所述的数据中转方法，其中，还包括：通过控制模块控制设备上电初始化、以及运作状态的监控。
  6. 如权利要求1至5任一项所述的数据中转方法，其中，还包括:通过电源模块获取电能，并为所述数据中转装置供电。
  7. 如权利要求6所述的数据中转方法，其中，所述通过电源模块获取电能包括：通过外置电源获取电能，和/或，从作为供电端设置的上游设备获取电能。
  8. 如权利要求6所述的数据中转方法，其中，还包括：通过所述电源模块为作为受电端设备的下游设备进行供电。
  9. 一种数据中转装置，包括：
    上联口，连接上游设备，配置为接收所述上游设备的数据流；
    时钟获取模块，分别与所述上联口及下联口连接，配置为获取所述数据流的同步时钟，基于所述同步时钟控制所述下联口向所述下游设备转发所述数据流；
    所述下联口，连接下游设备，配置为向所述下游设备转发所述数据流。
  10. 如权利要求9所述的数据中转装置，其中，还包括：时钟去抖模块，配置为对所述时钟获取模块获取的所述同步时钟去抖重生，并使得所述时钟获取模块基于去抖重生得到的同步时钟，控制所述下联口向所述下游设备转发所述数据流。
  11. 如权利要求10所述的数据中转装置，其中，所述时钟去抖模块包括：数字锁相环及压控晶体振荡器，或者，模拟二级锁相环及压控晶体振荡器。
  12. 如权利要求9所述的数据中转装置，其中，所述时钟获取模块包括：双端口物理层芯片，或者，两个基于串行/解串行接口标准协议连接的单端口物理层芯片；一个物理层端口连接所述上联口，配置为获取所述数据流的同步时钟，并将所述数据流转发至另一物理层端口，所述另一物理层端口与所述下联口连接，配置为于基于所述同步时钟控制所述下联口向 所述下游设备转发所述数据流。
  13. 如权利要求9所述的数据中转装置，其中，所述上联口及所述下联口分别包括：光纤接口及以太网接口，配置为根据连接需要选择对应的接口。
  14. 如权利要求9所述的数据中转装置，其中，还包括：控制模块，配置为控制设备上电初始化、以及运作状态的监控。
  15. 如权利要求9至14任一项所述的数据中转装置，其中，还包括电源模块，配置为获取电能，并为所述数据中转装置供电。
  16. 如权利要求15所述的数据中转装置，其中，所述电源模块配置为通过外置电源获取电能，和/或，从作为供电端设置的上游设备获取电能。
  17. 如权利要求15所述的数据中转装置，其中，所述电源模块还配置为为作为受电端设备的下游设备进行供电。
  18. 一种通信系统，其中，包括：基带处理单元、基带数据分组传输设备、射频拉远单元以及如权利要求9至17任一项所述的数据中转装置，所述基带处理单元与所述射频拉远单元通过所述数据中转装置及所述基带数据分组传输设备进行数据中转。
  19. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至8所述数据中转方法的至少其中之一。
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