WO2016154826A1 - 基于电阻加固的静态随机访问存储器的存储单元 - Google Patents

基于电阻加固的静态随机访问存储器的存储单元 Download PDF

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WO2016154826A1
WO2016154826A1 PCT/CN2015/075321 CN2015075321W WO2016154826A1 WO 2016154826 A1 WO2016154826 A1 WO 2016154826A1 CN 2015075321 W CN2015075321 W CN 2015075321W WO 2016154826 A1 WO2016154826 A1 WO 2016154826A1
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drain
source
gate
network
grounded
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PCT/CN2015/075321
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French (fr)
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陈亮
刘丽
王静秋
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中国科学院自动化研究所
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Priority to PCT/CN2015/075321 priority Critical patent/WO2016154826A1/zh
Priority to US15/550,898 priority patent/US10192612B2/en
Publication of WO2016154826A1 publication Critical patent/WO2016154826A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Definitions

  • the invention belongs to an integrated circuit design and manufacturing technology, and relates to a static random access memory, in particular to a storage unit based on a resistor-reinforced static random access memory, which can be applied to the military field, the civil field and the commercial space field, and is particularly suitable for high Performance high density radiation resistant applications.
  • Single particle inversion is an important parameter for radiation reinforcement.
  • a single-event flip or soft error is a non-destructive data transition on the data storage location.
  • Charged particles such as cosmic rays or trapped protons
  • the lost energy causes electrons to jump from the valence band to the conduction band.
  • electrons are present in the conduction band, leaving holes in the valence band, forming electron-hole pairs, and introducing unbalanced carriers.
  • the unbalanced carriers When there is no electric field, the unbalanced carriers will diffuse, recombine, and finally disappear.
  • the unbalanced carriers are separated by the electrodes to form a transient current.
  • the transient current causes the node potential to change, causing the device logic state to flip; or propagate along the signal transmission path, thereby interfering with the normal function of the circuit.
  • the space charge region of the drain region of the cut-off tube opposite to the PN junction constitutes a device single-event flip-sensitive region whose electric field is sufficient to separate the electron-hole pairs and be collected by the electrodes.
  • the 6T SRAM cell includes two identical cross-connected inverters that form a latch circuit, i.e., the output of one inverter is coupled to the input of another inverter.
  • the latch circuit is connected between the power supply and the ground potential.
  • Each of the inverters includes an NMOS pull-down transistor N1 or N2 and a PMOS pull-up transistor P1 or P2, respectively.
  • the output of the inverter is two storage nodes Q and QB. When one of the storage nodes is pulled low to a low voltage, the other storage node is pulled to a high voltage to form a complementary pair.
  • Complementary bit line pairs BL and BLB are connected to storage nodes Q and QB via a pair of pass gate transistors N3 and N4, respectively.
  • the gates of the pass gate transistors N3 and N4 are connected to the word line WL.
  • the state of the memory cell is "1", that is, Q is a high voltage, QB is a low voltage, P1 and N2 are turned on, N1 and P2 are turned off, and the reverse biased PN junction space charge region of the N1 and P2 tube drain regions is The single-event flip-flop zone of the device.
  • the transient current lowers the drain (ie Q storage point) voltage, couples to the gates of P2 and N2, turns off the N2 tube, turns the P2 tube on, and the voltage on the drain of the N2 tube (ie QB storage point) rises.
  • the P1 tube is turned off, the N1 tube is turned on, and the state of the memory cell is completely changed from "1" to "0". That is to say, in the radiation environment, the 6T structure storage unit is prone to single-event flipping. The storage content is disturbed and the value of the error will remain until the next time the storage unit is rewritten.
  • the process reinforcement and circuit design reinforcement are usually adopted.
  • the first method is to add a capacitor or a resistor delay element to the storage node of the memory cell, as shown in FIGS. 2 and 3.
  • the potential of the drain of the N1 tube is lowered to a low voltage, but when the P1 tube is still turned on, the state of the memory cell is unstable, and there is competition between the two processes.
  • the power supply charges the gate capacitance of the N2 tube through P1.
  • the second method is to add a coupling capacitor between the two storage nodes, as shown in Figure 4.
  • the principle of this method is that when one of the nodes is hit by the high-energy particle, a transient current is generated to cause the voltage of one of the nodes to jump, and the voltage of the other node is also affected by the coupling capacitance to jump in the same direction. Make the storage unit unable to flip. This method is also limited by the difficulty and area limitations of manufacturing capacitors, as well as the write time.
  • the third method is to use the multi-tube unit to redundantly store the stored information, as shown in Figure 5 of the 12T DICE structure.
  • the storage nodes are respectively connected with the PMOS of the previous stage NMOS and the latter stage, so that the forward and reverse storage data are redundantly saved, and once a storage node has a single event flip, The node voltage to which it is connected will only affect the storage node of the previous or next stage, and the unaffected level will recover the information of the hopping storage node.
  • the disadvantage of this method is that the number of transistors is too large and the area is too large.
  • the object of the present invention is to provide a memory unit for static random access memory based on resistance reinforcement. Without increasing complexity, only a small amount of area can be added to ensure that the memory cell does not undergo state flipping when the particle is bombarded, and the data is correct.
  • Memory unit for static random access memory based on resistance reinforcement proposed by the present invention package Including a latch circuit and a bit selection circuit, the latch circuit is composed of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first RC network and a second RC network; the bit selection circuit is composed of an NMOS transistor N5 and N6 composition; the latch circuit forms four storage points X1, X1B, X2, X2B;
  • the drain of P1 is connected to X1, the source is connected to the power supply, and the gate thereof is connected to X1B; the input end and the output end of the first RC network are respectively connected to X1 and X2; the drain of N1 is connected to X2, and the source thereof is grounded, The gate is connected to X2B;
  • the drain of P2 is connected to X1B, the source is connected to the power supply, and the gate thereof is connected to X1; the input end and the output end of the second RC network are respectively connected to X1B and X2B; the drain of N2 is connected to X2B, and the source thereof is grounded, The gate is connected to X2;
  • the drain of N5 is connected to X2 or X1, the drain of N6 is connected to X2B or X1B; the source of N5 is connected to bit line BL; the source of N6 is connected to complementary bit line BLB; the gates of N5 and N6 are connected together and connected to word On line WL.
  • the first RC network is composed of R1 and C1, and the second RC network is composed of R2 and C2;
  • R1 The two ends of R1 are respectively connected to X1 and X2; one end of C1 is connected to X1, and the other end is grounded;
  • Both ends of R2 are connected to X1B and X2B respectively; one end of C2 is connected to X1B, and the other end is grounded.
  • the RC network can also be configured as follows: the first RC network is composed of a PMOS transistor P3 and an NMOS transistor N3 that are always turned on to serve as a RC isolation point, and the second RC network is always turned on to serve as The PMOS tube P4 and the NMOS tube of the resistance-capacitance isolation point are composed of N4;
  • a storage point X3 is formed between P3 and N3; a storage point X3B is formed between P4 and N4;
  • the source of P3 is connected to X1, its drain is connected to X3, its gate is grounded, and its substrate is connected to a power supply. To keep always on; N3's drain is connected to X3, its source is connected to X2, its gate is connected to the power supply, and its substrate is grounded to keep it always on;
  • the source of P4 is connected to X1B, the drain is connected to X3B, the gate is grounded, the substrate is connected to the power supply to keep it always on; the drain of N3 is connected to X3B, the source is connected to X2B, and the gate is connected to the power supply. Ground the bottom to keep it always on.
  • the invention adds a RC network in the 6T structure storage unit, has small circuit area overhead, is excellent in single-particle reversal performance, and is compatible with a common process.
  • Figure 1 is a conventional 6TSRAM memory unit
  • 2 is a storage unit of a storage node plus a resistor capacitor
  • Figure 3 is a memory unit in which a MOS capacitor is substituted for a resistor and capacitor;
  • 4 is a storage unit of a storage node plus coupling capacitor
  • Figure 5 is a DICE structure memory unit
  • Figure 6 is a circuit diagram of a first embodiment of the present invention.
  • Figure 7 is a circuit diagram of a second embodiment of the present invention.
  • Figure 8 is a circuit diagram of a third embodiment of the present invention.
  • the storage of the static random access memory based on the resistance reinforcement of the present invention a unit comprising a latch circuit and a bit selection circuit, the latch circuit being composed of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first RC network and a second RC network, the first RC The network is composed of R1 and C1, the second RC network is composed of R2 and C2, the bit selection circuit is composed of NMOS transistors N5 and N6, and the latch circuit forms four storage points X1, X1B, X2, and X2B.
  • the drain of P1 is connected to X1, the source is connected to the power supply, and the gate is connected to X1B; the two ends of R1 are respectively connected to X1 and X2; one end of C1 is connected to X1, and the other end is grounded; the drain of N1 is connected to X2, the source thereof The pole is grounded and its gate is connected to X2B.
  • the drain of P2 is connected to X1B, the source is connected to the power supply, and the gate is connected to X1; the two ends of R2 are respectively connected to X1B and X2B; one end of C2 is connected to X1B, and the other end is grounded; the drain of N2 is connected to X2B, the source thereof The pole is grounded and its gate is connected to X2.
  • the drain of N5 is connected to X2, the drain of N6 is connected to X2B; the source of N5 is connected to bit line BL; the source of N6 is connected to complementary bit line BLB; the gates of N5 and N6 are connected together and connected to word line WL.
  • the MOS tube sensitive node collects the charge, and the transient current causes the voltage change, then the change causes the corresponding MOS transistor in the complementary inverter to be turned off on the one hand, and the change is RC extended on the other hand.
  • the gate coupled to the complementary inverter can flip the inverter state.
  • the first RC network is composed of a PMOS transistor P3 and an NMOS transistor N3 that are always turned on to serve as a RC isolation point, and the second RC network is always turned on to serve as a RC isolation point.
  • the PMOS transistor P4 and the NMOS transistor are composed of N4; the always-open P3, P4, N3, and N4 redundantly store the storage node information, and form six storage points of X1, X1B, X2, X2B, X3, and X3B.
  • the source of P3 is connected to X1, the drain is connected to X3, the gate is grounded, the substrate is connected to the power supply to keep it always on, the drain of N3 is connected to X3, the source is connected to X2, and the gate is connected to the power supply. Ground the bottom to keep it always on.
  • the source of P4 is connected to X1B, the drain is connected to X3B, the gate is grounded, the substrate is connected to the power supply to keep it always on; the drain of N3 is connected to X3B, the source is connected to X2B, and the gate is connected to the power supply. Ground the bottom to keep it always on.
  • Bit selection circuits N5 and N6 are connected to the X2 and X2B storage points, respectively.
  • the two transmission tubes that are always on act as resistors and capacitors, and the RC delay is applied to the hopping signal, so that the pull-up PMOS or the pull-down NMOS has time to restore the initial value of the hopping signal. .
  • the source PN junction of P3 is reverse biased, the leakage body PN junction is reverse biased, and the leakage body PN junction of P1 is reverse biased.
  • the MOS tube is used as a RC network in the unit, which is compatible with the general MOS process, and is simple to manufacture and easy to implement.
  • the drain of N5 is connected to X1, the drain of N6 is connected to X1B; the source of N5 is connected to bit line BL; the source of N6 is connected to complementary bit line BLB; the gates of N5 and N6 are connected together, On the word line WL.
  • the three embodiments of the present invention can make the storage unit of the static random access memory do not single-event in a radiation environment without increasing the obvious complexity and increasing the small area, and is compatible with the general-purpose CMOS process, and is easy to implement.

Abstract

本发明提出了一种基于电阻加固的静态随机访问存储器的存储单元，包括锁存电路和位选择电路，锁存电路由两个PMOS管P1和P2、两个NMOS管N1和N2、第一阻容网络和第二阻容网络构成；位选择电路由NMOS管N5和N6组成；锁存电路形成4个存储点X1、X1B、X2、X2B；相对于传统6T结构存储单元，添加了阻容网络，在不改变原读操作通路，在不增加明显复杂性情况下，以增加少量面积为代价，保证存储单元不发生单粒子翻转，保证数据正确。

Description

基于电阻加固的静态随机访问存储器的存储单元 技术领域
本发明属于集成电路设计与制造技术，涉及静态随机访问存储器，特别是涉及一种基于电阻加固的静态随机访问存储器的存储单元，可应用于军事领域、民用领域以及商用太空领域，尤其适用于高性能高密度抗辐射应用。
背景技术
单粒子翻转是辐射加固的重要参数。一次单粒子翻转或称软错误，是指数据存储位上的一次非破坏性的数据转变。带电粒子(如宇宙射线或捕获质子)射入半导体器件，通过与半导体材料相互作用，很快地损失掉能量。损失的能量使电子从价带跳到导带上去。于是，在导带中有了电子，在价带中留下空穴，形成电子空穴对，引入非平衡载流子。无电场时，非平衡载流子将发生扩散、复合，最后消失。有电场时，非平衡载流子(电子空穴对)将分离被电极收集，形成瞬态电流。瞬态电流会使节点电势变化，引起器件逻辑状态翻转；或者沿着信号传输路径传播，从而干扰电路正常功能。对于CMOS SRAM的存储单元，截止管的漏区反偏PN结的空间电荷区构成器件单粒子翻转灵敏区，其电场足以使电子空穴对分离，并被电极收集。
现在典型的存储单元具有6T结构。如图1所示，6T SRAM单元包括两个相同的交叉连接的反相器，形成锁存电路，即一个反相器的输出连接至另一个反相器的输入。锁存电路连接于电源和地电位之间。每个反相器均分别包括NMOS下拉晶体管N1或N2和PMOS上拉晶体管P1或P2。反相器的输出为两个存储节点Q和QB。当存储节点之一被拉低到低电压时，另一个存储节点被拉到高电压，形成互补对。互补位线对BL和BLB分别经由一对传输门晶体管N3和N4连接至存储节点Q和QB。传输门晶体管N3和N4的栅极连接至字线WL。
假设该存储单元的状态为“1”，即Q为高电压，QB为低电压，P1和N2管导通，N1和P2管截止，N1和P2管漏区的反偏PN结空间电荷区就是器件的单粒子翻转灵敏区。对于N1管，瞬态电流使漏极(即Q存储点)电压降低，耦合到P2和N2的栅极，使N2管截止、P2管导通，N2管漏极(即QB存储点)电压升高，反馈到P1、N1管的栅极，使P1管截止，N1管导通，存储单元状态彻底由“1”变为“0”。也就是说在辐射环境下，6T结构存储单元易发生单粒子翻转。使存储内容受到干扰，该错误的值将保持到该存储单元下一次被改写。
为了解决高能粒子(高能质子、重离子)击中存储节点后，引起存储单元发生的单粒子翻转现象，通常采用工艺加固和电路设计加固两种手段。电路设计加固通常有三种解决方法。方法一是在存储单元的存储节点加电容或电阻延时元件，如图2和图3所示。在带电粒子入射，使N1管漏极电位降到低电压，但P1管仍然导通时，存储单元状态时不稳定的，存在两个过程的竞争。一方面，电源通过P1对N2管的栅电容充 电，使N1管漏极电压上升，恢复到初始状态；另一方面，N1管漏极电压降低，耦合到另一个反相器栅极，再反馈回来，使得N1管导通，P1管截止，存储单元状态翻转。通过增加RC延时，瞬态电流使逻辑电路翻转的时间被延迟，进而使得有时间令这个尖峰瞬态电流造成节点电压变化恢复到初始值。这种方法的缺点是芯片上所需的电阻电容值较大，电阻电容面积过大，且写入时间大大增加。方法二是在两个存储节点之间加耦合电容，如图4所示。这种方法的原理是当其中一个节点被高能粒子击中后，产生瞬态电流使得其中一个节点的电压发生跳变，另一个节点的电压受耦合电容的影响也发生同一方向的跳变，从而使存储单元无法发生翻转。这种方法同样受到制造电容的难度和面积限制，以及写入时间的限制。方法三是采用多管单元对存储信息进行冗余保存，如图5所示的12T DICE结构。通过将4个反相器首尾相接，其中存储节点分别与前一级NMOS和后一级的PMOS相连接，使得正反存储数据都被冗余保存，一旦某个存储节点发生单粒子翻转，其连接的节点电压只会影响前一级或者后一级的存储节点，未被影响的那一级对跳变的存储节点的信息进行恢复。该方法的缺点是晶体管个数太多，面积过大。
发明内容
本发明的目的是提出一种基于电阻加固的静态随机访问存储器的存储单元，不增加复杂性，仅增加少量的面积即可保证存储单元受到粒子轰击时不发生状态翻转，保证数据正确。
本发明提出的基于电阻加固的静态随机访问存储器的存储单元，包 括锁存电路和位选择电路，锁存电路由两个PMOS管P1和P2、两个NMOS管N1和N2、第一阻容网络和第二阻容网络构成；位选择电路由NMOS管N5和N6组成；锁存电路形成4个存储点X1、X1B、X2、X2B；
P1的漏极连接X1，其源极连接电源，其栅极连接X1B；第一阻容网络的输入端和输出端分别与X1和X2连接；N1的漏极连接X2，其源极接地，其栅极连接X2B；
P2的漏极连接X1B，其源极连接电源，其栅极连接X1；第二阻容网络的输入端和输出端分别与X1B和X2B连接；N2的漏极连接X2B，其源极接地，其栅极接X2；
N5的漏极接X2或X1，N6漏极对应接X2B或X1B；N5的源极接位线BL；N6的源极接互补位线BLB；N5和N6的栅极连接在一起，接在字线WL上。
所述第一阻容网络由R1和C1构成，所述第二阻容网络由R2和C2构成；
R1的两端分别与X1、X2连接；C1的一端与X1连接，另一端接地；
R2的两端分别与X1B、X2B连接；C2的一端与X1B连接，另一端接地。
阻容网络的构成还可以采用如下方案：所述第一阻容网络由始终开启以充当阻容隔离点的PMOS管P3和NMOS管组成N3组成，所述第二阻容网络由始终开启以充当阻容隔离点的PMOS管P4和NMOS管组成N4组成；
P3和N3之间形成存储点X3；P4和N4之间形成存储点X3B；
P3的源极连接X1，其漏极连接X3，其栅极接地，其衬底接电源， 以保持始终开启；N3的漏极连接X3，其源极连接X2，其栅极接电源，其衬底接地，以保持始终开启；
P4的源极连接X1B，其漏极连接X3B，其栅极接地，其衬底接电源，以保持始终开启；N3的漏极连接X3B，其源极连接X2B，其栅极接电源，其衬底接地，以保持始终开启。
本发明在6T结构存储单元中添加了阻容网络，电路面积开销小，抗单粒子翻转性能优良，且可兼容通用工艺。
附图说明
图1是传统6TSRAM存储单元；
图2是存储节点加电阻电容的存储单元；
图3是以mos电容代替电阻电容的存储单元；
图4是存储节点加耦合电容的存储单元；
图5是DICE结构存储单元；
图6是本发明第一实施例的电路图；
图7是本发明第二实施例的电路图；
图8是本发明第三实施例的电路图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
实施例一
如图6所示，本发明的基于电阻加固的静态随机访问存储器的存储 单元，包括锁存电路和位选择电路，锁存电路由两个PMOS管P1和P2、两个NMOS管N1和N2、第一阻容网络和第二阻容网络构成，所述第一阻容网络由R1和C1构成，所述第二阻容网络由R2和C2构成；位选择电路由NMOS管N5和N6组成；锁存电路形成4个存储点X1、X1B、X2、X2B。
P1的漏极连接X1，其源极连接电源，其栅极连接X1B；R1的两端分别与X1、X2连接；C1的一端与X1连接，另一端接地；N1的漏极连接X2，其源极接地，其栅极连接X2B。
P2的漏极连接X1B，其源极连接电源，其栅极连接X1；R2的两端分别与X1B、X2B连接；C2的一端与X1B连接，另一端接地；N2的漏极连接X2B，其源极接地，其栅极接X2。
N5的漏极接X2，N6漏极对应接X2B；N5的源极接位线BL；N6的源极接互补位线BLB；N5和N6的栅极连接在一起，接在字线WL上。
若高能粒子通过该存储单元，MOS管敏感节点收集电荷，形成瞬态电流引起电压变化，那么该变化一方面使得互补反相器中的相应MOS管关断，另一方面，该变化经过RC延时后，耦合到互补反相器的栅极才能使反相器状态翻转。假设图6中存储器存储高电平，即X1＝“1”，X2＝“1”，而X1B＝“0”，X2B＝“0”，则该单元的敏感节点为N1管漏极，即X2处，以及P1管漏极，即X1B处。粒子只有轰击X2处或者X1B处时会产生瞬态电流引起电压的变化。若粒子通过X2处，则X2由“1”变为“0”，关断原本开启的N2管，使得X2B的“0”浮空；另一方面，X2处的电压变化，需经过RC延时，打开原本关闭的P2管，使得X1B由“0”变“1”，完全关断P1管，使得存储单元翻转。若该RC延时够长，在打开P2管之前， P1管有时间维持X1为“1”，阻止单元翻转。同时由于位选择信号连接在X2和X2B，单元的读操作延时不受影响。
实施例二
该实施例与实施例一的区别在于第一阻容网络和第二阻容网络的电路设计不同，其它部分均与实施例一相同。
如图7所示，所述第一阻容网络由始终开启以充当阻容隔离点的PMOS管P3和NMOS管组成N3组成，所述第二阻容网络由始终开启以充当阻容隔离点的PMOS管P4和NMOS管组成N4组成；始终开启的P3、P4、N3、N4对存储节点信息冗余保存，形成X1、X1B、X2、X2B、X3、X3B六个存储点。
P3的源极连接X1，其漏极连接X3，其栅极接地，其衬底接电源，以保持始终开启；N3的漏极连接X3，其源极连接X2，其栅极接电源，其衬底接地，以保持始终开启。
P4的源极连接X1B，其漏极连接X3B，其栅极接地，其衬底接电源，以保持始终开启；N3的漏极连接X3B，其源极连接X2B，其栅极接电源，其衬底接地，以保持始终开启。
位选择电路N5和N6分别连接X2和X2B存储点。
如果一个存储节点的电压发生跳变，始终开启的两个传输管充当了电阻和电容作用，对跳变信号进行RC延时，使得上拉PMOS或者下拉NMOS有时间令这个跳变信号恢复初始值。
电荷收集敏感区是MOS管中PN结反偏导致有强电场的区域，当粒子轰击这些区域时，电离出的电子空穴对在电场作用下被分离，被电极 收集，形成瞬时电流。如图7结构，若存储单元存储低电平，即X1＝“0”，X3＝“0”，X2＝“0”，X1B＝“1”，X3B＝“1”，X2B＝“1”。P3的源体PN结反偏，漏体PN结反偏，P1的漏体PN结反偏。因此粒子轰击器件时，只有打在P3的源极X1、P3的漏极X3或者P1的漏极X1时会产生瞬时电流。同理，只有打在X3和X2B会产生瞬态电流。即该结构的敏感节点是X1(由“0”翻转为“1”)、X3(由“0”翻转为“1”)、X3B(由“1”翻转为“0”)、X2B点(由“1”翻转为“0”)。
上述分析中，敏感点有4个，X1(由“0”翻转为“1”)、X3(由“0”翻转为“1”)、X3B(由“1”翻转为“0”)、X2B点(由“1”翻转为“0”)。其中X1点由“0”翻转为“1”的变化需要经过两个电阻的RC延时才能使得N2开启，而X3由“0”翻转为“1”的变化只需要经过一个RC延时就开启N1；其中X2B点由“1”翻转为“0”的变化需要经过两个电阻的RC延时才能使得P1开启，而X3B由“1”翻转为“0”的变化只需要经过一个RC延时就开启P1；因此X3由“0”翻转为“1”的变化或X3B由“1”翻转为“0”的变化更“危险”。当X3由“0”翻转为“1”，由于N3带来的RC延时，该单元可利用这个时间通过一直开启的N1将X3处由“0”到“1”的跳变信号恢复为初始值；或者当X3B由“1”翻转为“0”，由于P4带来的RC延时，该单元可利用这个时间通过一直开启的P2将X3B处由“1”到“0”的跳变信号恢复为初始值。
单元中使用MOS管充当阻容网络，兼容通用MOS工艺，制造简单易于实现。
实施例三
该实施例与实施例二的区别在于位选择电路所连接的存储点不同， 其它部分均与实施例二相同。
如图8所示，N5的漏极接X1，N6漏极对应接X1B；N5的源极接位线BL；N6的源极接互补位线BLB；N5和N6的栅极连接在一起，接在字线WL上。
本发明的三个实施例均可以在不增加明显复杂性、增大少量面积的情况下，使静态随机存储器的存储单元在辐射环境下不发生单粒子翻转，兼容通用CMOS工艺，容易实现。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

  1. 基于电阻加固的静态随机访问存储器的存储单元，包括锁存电路和位选择电路，其特征在于，锁存电路由两个PMOS管P1和P2、两个NMOS管N1和N2、第一阻容网络和第二阻容网络构成；位选择电路由NMOS管N5和N6组成；锁存电路形成4个存储点X1、X1B、X2、X2B；
    P1的漏极连接X1，其源极连接电源，其栅极连接X1B；第一阻容网络的输入端和输出端分别与X1和X2连接；N1的漏极连接X2，其源极接地，其栅极连接X2B；
    P2的漏极连接X1B，其源极连接电源，其栅极连接X1；第二阻容网络的输入端和输出端分别与X1B和X2B连接；N2的漏极连接X2B，其源极接地，其栅极接X2；
    N5的漏极接X2或X1，N6漏极对应接X2B或X1B；N5的源极接位线BL；N6的源极接互补位线BLB；N5和N6的栅极连接在一起，接在字线WL上。
  2. 如权利要求1所述的基于电阻加固的静态随机访问存储器的存储单元，其特征在于，所述第一阻容网络由R1和C1构成，所述第二阻容网络由R2和C2构成；
    R1的两端分别与X1、X2连接；C1的一端与X1连接，另一端接地；
    R2的两端分别与X1B、X2B连接；C2的一端与X1B连接，另一端接地。
  3. 如权利要求1所述的基于电阻加固的静态随机访问存储器的存储 单元，其特征在于，所述第一阻容网络由始终开启以充当阻容隔离点的PMOS管P3和NMOS管组成N3组成，所述第二阻容网络由始终开启以充当阻容隔离点的PMOS管P4和NMOS管组成N4组成；
    P3和N3之间形成存储点X3；P4和N4之间形成存储点X3B；
    P3的源极连接X1，其漏极连接X3，其栅极接地，其衬底接电源，以保持始终开启；N3的漏极连接X3，其源极连接X2，其栅极接电源，其衬底接地，以保持始终开启；
    P4的源极连接X1B，其漏极连接X3B，其栅极接地，其衬底接电源，以保持始终开启；N3的漏极连接X3B，其源极连接X2B，其栅极接电源，其衬底接地，以保持始终开启。
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