WO2016150372A1 - Circuit de pixel et son procédé de pilotage, et dispositif d'affichage - Google Patents

Circuit de pixel et son procédé de pilotage, et dispositif d'affichage Download PDF

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Publication number
WO2016150372A1
WO2016150372A1 PCT/CN2016/076962 CN2016076962W WO2016150372A1 WO 2016150372 A1 WO2016150372 A1 WO 2016150372A1 CN 2016076962 W CN2016076962 W CN 2016076962W WO 2016150372 A1 WO2016150372 A1 WO 2016150372A1
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Prior art keywords
transistor
control signal
scan
pixel circuit
data
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PCT/CN2016/076962
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English (en)
Chinese (zh)
Inventor
张盛东
王翠翠
冷传利
孟雪
鲁文高
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北京大学深圳研究生院
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Publication of WO2016150372A1 publication Critical patent/WO2016150372A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present application relates to the field of display devices, and in particular, to a display device, a pixel circuit thereof, and a driving method.
  • OLED Organic Light-Emitting Diode
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the passive matrix drive is low in cost, the crosstalk phenomenon cannot achieve high-resolution display, and the passive matrix drive current is large, which reduces the service life of the OLED.
  • the active matrix driving method sets a different number of transistors as current sources on each pixel, avoiding crosstalk, requiring less driving current, lower power consumption, and increasing the lifetime of the OLED, which can be realized.
  • High resolution display, while active matrix drive is easier to meet the needs of large area and high gray level display.
  • a conventional AMOLED pixel circuit is composed of two thin film transistors (TFTs) and a storage capacitor.
  • the pixel circuit includes a driving transistor 11, a switching transistor 12, a storage capacitor 13, and a light emitting device OLED 14.
  • the signal on the scan control signal line 15 controls the switching transistor 12, and the data signal on the sampled data signal line 16 is supplied to the gate of the drive transistor 11, so that the drive transistor 11 generates the current required by the OLED 14, thereby generating the desired ash.
  • the degree is stored in the storage capacitor 13, and the storage capacitor 13 holds the sampled data information until the next frame.
  • the current flowing through the OLED 14 in the pixel circuit can be expressed as:
  • V G is the gate potential of the driving transistor 11
  • V OLED is the potential of the anode of the OLED 14 during light emission
  • V TH is the threshold voltage of the driving transistor 11.
  • the peripheral circuit compensation method requires a complicated peripheral circuit structure, and the compatibility with the existing AMLCD drive circuit is poor, and special research is required.
  • the currently proposed methods of performing compensation in pixels are mainly divided into current type and voltage type.
  • Current-type pixel circuits have higher compensation accuracy, but require a longer settling time, especially in the case of small currents and large parasitic capacitance on the data lines. This severely limits the use of current-type pixel circuits in large-area, high-resolution displays.
  • the voltage type pixel circuit has a fast driving speed, but the compensation accuracy is not as high as that of the current type pixel circuit, and the circuit structure or/and the driving signal are generally relatively complicated.
  • the present application provides a display device and a pixel circuit and a driving method thereof to compensate for a threshold voltage variation of a driving transistor, thereby alleviating display unevenness caused by a threshold voltage variation.
  • an embodiment provides a pixel circuit, including:
  • a driving transistor, a fourth transistor, and a light emitting element and a second transistor, a third transistor, a fifth transistor, and a storage capacitor connected in series between the first level terminal and the second level terminal;
  • the first pole of the driving transistor is used for Connected to the first level terminal, the second electrode of the driving transistor is connected to the first electrode of the fourth transistor, the second electrode of the fourth transistor is connected to the first end of the light emitting element, and the second end of the light emitting element is used for connecting to the first a two-level terminal, a control electrode of the fourth transistor is configured to input a second scan control signal;
  • a first electrode of the third transistor is used for inputting a data signal, a control electrode of the third transistor is used for inputting a first scan control signal;
  • a storage capacitor is The two ends are respectively connected to the control electrode of the driving transistor and the second electrode of the third transistor, respectively forming a first node and a second node; the second electrode of the fifth transistor is connected to the control electrode of the
  • an embodiment provides a display device, including:
  • a pixel circuit matrix comprising the above pixel circuit arranged in a matrix of n rows and m columns, wherein n and m are integers greater than 0; a gate driving circuit for generating a scan pulse signal and passing the Each row of scan lines formed in one direction supplies a desired scan control signal to the pixel circuit; a data drive circuit for generating a data voltage signal representative of gray scale information, and providing data to the pixel circuit through each data line formed along the second direction a signal controller for providing control timing to the gate drive circuit and the data drive circuit.
  • an embodiment provides a pixel circuit driving method.
  • Each driving cycle of the pixel circuit includes an initialization phase, a threshold extraction and a data writing phase, and an illumination phase.
  • the driving method includes:
  • the fifth transistor and the fourth transistor respectively turn on the active level of the third scan control signal and the first active level of the second scan control signal to initialize the potentials of the first node and the second node;
  • the fourth transistor is controlled to be in an off state by a second scan control signal; the second transistor is turned on in response to an active level of the first scan control signal to extract a threshold voltage of the driving transistor, by storing The capacitor is stored in the first node; the third transistor is responsive to the active level of the first scan control signal to conduct a data signal to the second node; in the illuminating phase, the fourth transistor is responsive to the second effective power of the second scan control signal When turned on, the driving transistor drives the light emitting element to emit light in response to the potential conduction of the first node.
  • a diode-connected topology is formed by connecting a second transistor between the control electrode of the driving transistor and a conducting electrode, and the circuit structure is used in conjunction with the storage capacitor.
  • the strobe voltage signal information related to the threshold voltage and the gradation of the driving transistor is extracted and stored on the storage capacitor, thereby compensating the threshold voltage of the driving transistor, increasing the contrast of the display.
  • 1 is a schematic structural view of a conventional 2T1C pixel circuit
  • FIG. 2a is a structural diagram of a pixel circuit according to Embodiment 1;
  • FIG. 2b is a structural diagram of another pixel circuit provided in Embodiment 1;
  • FIG. 3a is a schematic diagram showing the operation timing of a pixel circuit according to Embodiment 1;
  • FIG. 3a is a schematic diagram showing the operation timing of a pixel circuit according to Embodiment 1;
  • FIG. 3b is a schematic diagram showing the operation timing of another pixel circuit of the first embodiment
  • FIG. 4 is a structural diagram of a pixel circuit provided in Embodiment 2;
  • FIG. 5 is a structural diagram of a pixel circuit according to Embodiment 3.
  • FIG. 6 is a schematic diagram showing the operation timing of a pixel circuit according to Embodiment 3.
  • FIG. 7 is a schematic structural diagram of a display device according to an embodiment
  • FIG. 9 is a schematic diagram of a pixel circuit driving process of Embodiment 5.
  • the transistor in the present application may be a transistor of any structure, such as a bipolar transistor (BJT) or a field effect transistor (FET).
  • BJT bipolar transistor
  • FET field effect transistor
  • the gate of the transistor is the base of the bipolar transistor
  • the first pole can be the collector or emitter of the bipolar transistor
  • the corresponding second pole can be a bipolar transistor.
  • Emitter or collector in the actual application process, “emitter” and “collector” can be interchanged according to signal flow direction;
  • the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor,
  • One pole can be the drain or source of the field effect transistor, and the corresponding second pole can be the source or drain of the field effect transistor.
  • the transistor in the display is typically a field effect transistor: a thin film transistor (TFT).
  • TFT thin film transistor
  • the present application will be described in detail by taking a transistor as a field effect transistor.
  • the transistor may also be a bipolar transistor.
  • the light-emitting element is an Organic Light-Emitting Diode (OLED). In other embodiments, other light-emitting elements may also be used.
  • the first end of the illuminating element can be a cathode or an anode, and correspondingly, the second end of the illuminating element is an anode or a cathode. It will be understood by those skilled in the art that the current should flow from the anode of the light-emitting element to the cathode, and therefore, based on the flow direction of the current, the anode and cathode of the light-emitting element can be determined.
  • the effective level can be either a high level or a low level, which can be adaptively replaced according to the function of the specific component.
  • the first level terminal VDD and the second level terminal VSS are the power provided for the operation of the pixel circuit Both ends of the source.
  • the first level terminal VDD can be a high level terminal
  • the second level terminal terminal is a low level terminal or a ground line. In other embodiments, it can also be adaptively replaced. It is to be noted that, for the pixel circuit, the first level terminal and the second level terminal are not part of the pixel circuit of the present application, and the first device is specifically introduced in order to enable a person skilled in the art to better understand the technical solution of the present application. The flat end and the second level end are described.
  • the first node A, the second node B, and the third node C are introduced in the present application. Identification is not recognized as an additional terminal introduced in the circuit.
  • V H the high level
  • V L the low level
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • a structure diagram of a pixel circuit disclosed in the embodiment includes: a driving transistor T1 and a fourth transistor T4 connected in series between a first level terminal VDD and a second level terminal VSS.
  • each transistor is an N-type thin film transistor, and the effective level of each transistor is turned on.
  • the first pole of the driving transistor T1 is connected to the first level terminal VDD
  • the second pole of the driving transistor T1 is connected to the first pole of the fourth transistor T4
  • the second pole of the fourth transistor T4 is connected to the first layer of the light emitting element OLED
  • the second end of the light emitting element OLED is used to connect to the second level terminal VSS
  • the gate of the fourth transistor T4 is used to input the second scan control signal V EM .
  • the first pole of the third transistor T3 is used to input the data signal V DATA
  • the gate of the third transistor T3 is used to input the first scan control signal V SCAN .
  • Both ends of the storage capacitor Cs are respectively connected to the control electrode of the driving transistor T1 and the second electrode of the third transistor T3 to form a first node A and a second node B, respectively.
  • the fifth transistor T5 is connected to the second electrode to the control electrode of the drive transistor T1, a control electrode of the fifth transistor T5 to the control input of the third scan signal V 3, when there are a plurality of rows of pixel circuits, in a preferred embodiment,
  • the third scan control signal V 3 of the pixel circuit of the row is provided by the first scan control signal V SCAN of the pixel circuit of the previous row; in a specific embodiment, the first pole of the fifth transistor T5 is used for inputting the reference potential V REF , please Referring to FIG. 2b, in another embodiment, referring to FIG. 2a, the first pole of the fifth transistor T5 is connected to the gate of the fifth transistor T5, and the reference potential V REF of the first pole input of the fifth transistor T5 is three scan control signal V 3 provided.
  • the first electrode of the second transistor T2 is connected to the control electrode of the driving transistor T1
  • the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T1
  • the gate of the second transistor T2 is used for inputting the first scanning control signal V SCAN .
  • the pixel circuit operates in an initialization phase, a threshold extraction and data writing phase, and an illumination phase.
  • the fifth transistor T5 and the fourth transistor T4 are active in response to a first level scan control signal turning on the third level V 3 of the second active scan control signal V of the EM, and the first node A initializes a second The potential of node B.
  • the second control transistor T2 in response to a first scan signal V SCAN is turned on to extract the active level the threshold voltage of the transistor T1, the third transistor T3 is electrically active in response to a first scan of the control signal V SCAN
  • the flat conduction transmits a data signal V DATA to the second node B.
  • the fourth transistor T4 is turned on in response to the second active level of the second scan control signal V EM , and the driving transistor T1 is driven to emit light in response to the potential of the first node A to drive the light emitting element OLED.
  • the active level of the third scan control signal V 3 and the first active level of the second scan control signal V EM , the active level of the first scan control signal V SCAN , and the second scan control signal V EM comes in order.
  • FIG. 3a and FIG. 3b are operation timing diagrams of the pixel circuit of the embodiment, wherein FIG. 3a is an operation timing of the pixel circuit corresponding to FIG. 2a, and FIG. 3b is an operation timing of the pixel circuit corresponding to FIG. 2b, which is illustrated by FIG. 2a.
  • FIG. 3a is an operation timing of the pixel circuit corresponding to FIG. 2a
  • FIG. 3b is an operation timing of the pixel circuit corresponding to FIG. 2b, which is illustrated by FIG. 2a.
  • the effective level at which each transistor is turned on is a high level.
  • the third scan control signal V 3 is at a high level
  • the first level terminal VDD provides a low level V DDL
  • the second scan control signal V EM is at a high level.
  • the third scan control signal V 3 of the row of pixel circuits is provided by the first scan control signal V SCAN of the previous row of pixel circuits
  • the previous row of pixel circuits is gated.
  • the fifth transistor T5 and the fourth transistor T4 are respectively turned on in response to the active level of the third scan control signal V 3 and the first active level of the second scan control signal V EM , so that the first node A passes the fifth The transistor T5 is charged to a high level.
  • V DDL should satisfy V DDL ⁇ V OLED0 , where V OLED0 is the threshold voltage of the OLED.
  • the first scan control signal V SCAN of the current row is converted from a low level to a high level, so that the pixel row of the current row is gated, and the third scan control signal V 3
  • the second scan control signal V EM of the current line is converted from the high level to the low level, and the first level terminal VDD is still supplied with the low level V DDL .
  • the fifth transistor T5 and the fourth transistor T4 are third scanning control signal V 3 and the second scanning control signal V control in the EM OFF state; a second transistor T2 and the third transistor T3, respectively, in response to a first control signal V scan
  • the effective level of SCAN is turned on.
  • the first level terminal VDD provides a low level V DDL at this time, the first node A is at a high level, so that the turned-on second transistor T2 causes the driving transistor T1 to form a diode connection to start discharging through the first level terminal VDD to V DDL +V TH_T1 ; at the same time, the turned-on third transistor T3 transmits the gray-scale related data voltage information V DATA to the second node B (ie, one end of the storage capacitor C S ), thus the two storage capacitors C S The terminal forms a reference voltage that can maintain the entire frame time. At this time, the voltage difference between the first node A and the second node B is:
  • V A -V B V DDL +V TH_T1 -V DATA (1)
  • V A is the potential of the first node A
  • V B is the potential of the second node B
  • V TH_T1 represents the threshold voltage of the first transistor T1
  • V DDL represents the low level provided by the first level terminal VDD
  • V DATA represents The pixel signal corresponds to the data signal voltage corresponding to the gray scale information required at this time.
  • the programming process of the line is ended, and the first level terminal VDD is converted from a low level V DDL to a high level V DDH , the current line The second scan signal V EM is converted from a low level to a high level, and the current line enters a light emitting phase.
  • the third scan control signal V 3 and the first scan control signal V SCAN are both low, and then the second transistor T2, the third transistor T3 and the fifth transistor T5 are both controlled to be in an off state;
  • the second scan control signal V EM is converted from a low level to a high level (ie, a second active level), and then the fourth transistor T4 is turned on in response to the second active level of the second scan control signal V EM .
  • the anode potential V OLED of the light-emitting element OLED bootstraps the gate of the driving transistor T1 through the storage capacitor C S , and the reference voltage formed by the storage capacitor C S during the programming process remains unchanged, therefore, At this time, the voltage of the first node A is:
  • V A V TH_T1 +V DDL -V DATA +V B (2)
  • V A V TH_T1 +V DDL -V DATA +V OLED (3)
  • the current generated by the driving transistor T1 that is, the illuminating current flowing through the OLED OLED can be expressed as:
  • the I OLED is an illuminating current flowing through the OLED of the OLED;
  • ⁇ n , C OX and W/L are the field effect mobility of the driving transistor T1, the capacitance of the gate insulating layer per unit area, and the aspect ratio of the tube, respectively.
  • V OLED represents the pressure element OLED across the lighting during light emission can be seen from equation (4): flowing through the threshold voltage V OLED0 the light emitting element OLED current I OLED of the driving transistor T1, the threshold voltage V TH_T1 and the light emitting element OLED Irrelevant, only the data signals V DATA and V DDL related to the current pixel point gradation are related.
  • the first pole of the fifth transistor T5 is used to be connected to a fixed power terminal, and the input reference potential V REF is provided by a certain fixed level V REF . .
  • the working timing diagram is shown in FIG. 3b. It should be noted that since the first electrode of the fifth transistor T5 is coupled to a certain fixed level V REF , the point A is precharged to V REF at point B in the initialization phase. It is discharged to V DDL , and other working processes are the same as those in the above embodiment, and will not be described again here.
  • the pixel circuit in this embodiment can compensate for threshold voltage variation or degradation of the driving transistor and the light emitting element, and can also compensate for display unevenness caused by uneven driving voltage threshold of the pixel circuit of the display panel, and the pixel circuit adopts
  • the second electrode of the driving transistor is connected to the switching transistor to form a diode topology to realize voltage-type threshold voltage extraction.
  • the row is initialized by the gate time of the previous row, and programming of each row is performed. The time is only the time for threshold extraction and data writing, and the driving speed is faster.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG. 4 is a structural diagram of a pixel circuit disclosed in the embodiment, which is different from the above embodiment in that the pixel circuit disclosed in the present embodiment further includes a sixth transistor T6 and a sixth crystal.
  • the first pole of the body tube T6 is connected to the second node B
  • the second pole of the sixth transistor T6 is connected to the first pole of the fourth transistor T4
  • the control pole of the sixth transistor T6 is connected to the gate of the fourth transistor T4.
  • the sixth transistor T6 Since the sixth transistor T6 is responsive to the second scan control signal V EM of the current row, the sixth transistor and the fourth transistor T4 are simultaneously turned on or off; in the initialization phase and the light-emitting phase, the sixth transistor T6 is turned on, The sixth transistor T6 is turned off in the threshold extraction and data writing phase. Since the fourth transistor T4 is not an ideal transistor, there is a voltage drop when a current flows therethrough. The advantage of the embodiment in relation to the first embodiment is that the voltage drop of the fourth transistor T4 is shielded from the current of the driving transistor T1. .
  • FIG. 3a For the working sequence of the pixel circuit in this embodiment, please refer to FIG. 3a.
  • the working process is also divided into three phases, namely, an initialization phase, a threshold extraction and a data writing phase, and an illumination phase. For details, refer to the first embodiment, and details are not described herein again.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 5 is a structural diagram of a pixel circuit disclosed in the embodiment.
  • the fourth transistor T4 and the sixth transistor T6 are P-type transistors, The active level of the four transistors T4 and the sixth transistor T6 is low, and the effective level of other transistors is still high.
  • the control electrode of the fourth transistor T4 and the control electrode of the sixth transistor T6 are also connected to the control electrode of the second transistor T2 or the control electrode of the third transistor T3, and the second scan control signal V EM of the pixel circuit of the row is from the row of pixels
  • the circuit first scan control signal V SCAN is provided.
  • the fourth transistor T4 and the sixth transistor T6 are P-type transistors, the effective level of their conduction becomes a low level, so that the pixel circuit can reduce one scanning signal line (providing the supply of V is omitted). EM[n] scan signal line).
  • the present embodiment will be described by including the fourth transistor T4 and the sixth transistor T6 in the embodiment.
  • FIG. 6 is an operation timing diagram of the pixel circuit of the embodiment. It should be noted that the working process of the circuit structure shown in this embodiment is also divided into three phases, namely, an initialization phase, a threshold extraction, and a data writing phase. Luminous stage.
  • the third scan control signal V 3 is at a high level, and the first level terminal VDD provides a low level V DDL .
  • the third scan control signal V 3 of the row of pixel circuits is provided by the first scan control signal V SCAN of the previous row of pixel circuits, then the previous row of pixel circuits is gated.
  • the first scan control signal V SCAN of the current line is at a low level. Therefore, the fifth transistor T5 and the fourth transistor T4 and the sixth transistor T6 are respectively turned on in response to the third scan control signal V 3 and the active level of the first scan control signal V SCAN of the current line.
  • V DDL should satisfy V DDL ⁇ V OLED0 , where V OLED0 is the threshold voltage of the OLED.
  • Threshold extraction and data writing phase the pixel row of the current row is gated, the first scan signal V SCAN of the current row is converted from a low level to a high level, and the third scan control signal V 3 is driven from a high level. Converted to a low level, then the fifth transistor T5 and the fourth transistor T4 and the sixth transistor T6 are respectively controlled by the third scan control signal V 3 and the first scan control signal V SCAN of the current row in an off state; the second transistor T2 And the third transistor T3 is turned on in response to the first scan signal V SCAN of the current line.
  • the first node A is at a high level, so that the turned-on second transistor T2 causes the driving transistor T1 to form a diode connection to start discharging to V DDL +V TH_T1 ; at the same time, conducting The third transistor T3 transmits the gray-scale related data voltage information V DATA to the second node B (one end of the storage capacitor C S ), so that a reference voltage that can maintain the entire one frame time is formed across the first capacitor C S .
  • the voltage difference between the first node A and the second node B is:
  • V A -V B V DDL +V TH_T1 -V DATA (5)
  • V A is the potential of the first node A
  • V B is the potential of the second node B
  • V TH_T1 represents the threshold voltage of the first transistor T1
  • V DDL represents the low level of the first level terminal V DD
  • V DATA represents The pixel signal corresponds to the data signal voltage corresponding to the gray scale information required at this time.
  • the programming process of the line is ended, and the voltage of the first level terminal V DD is converted from a low level V DDL to a high level V DDH .
  • the current line is ready to enter the lighting phase.
  • the third scan control signal V 3 and the first scan control signal V SCAN are both low level, and the second transistor T2, the third transistor T3 and the fifth transistor T5 are both controlled to be in an off state;
  • the transistor T4 and the sixth transistor T6 are turned on.
  • the anode voltage V OLED of the light-emitting element OLED is bootstrapped by the storage capacitor C S through the conduction of the fourth transistor T4 and the sixth transistor T6, and the reference voltage formed by the storage capacitor C S during the programming process remains unchanged. Change, so, at this time, the voltage of the first node A is:
  • V A V TH_T1 +V DDL -V DATA +V B (6)
  • V A V TH_T1 +V DDL -V DATA +V OLED (7)
  • the current generated by the driving transistor T1 that is, the illuminating current flowing through the OLED OLED can be expressed as:
  • the I OLED is an illuminating current flowing through the OLED of the OLED; ⁇ n , C OX and W/L are the field effect mobility of the driving transistor T1, the capacitance of the gate insulating layer per unit area, and the aspect ratio of the tube, respectively.
  • V OLED represents the voltage across the OLED during the illuminating process. It can be seen from equation (8) that the current I OLED flowing through the OLED of the OLED has nothing to do with the threshold voltage V TH_T1 of the driving transistor T1 and the threshold voltage V OLED of the OLED .
  • the data signals V DATA and V DDL related to the current pixel dot gradation are related.
  • the pixel circuit in this embodiment can compensate for the threshold voltage drift of the driving transistor and the light emitting element, and can also compensate for display unevenness caused by different threshold voltages of the driving transistors of the pixel circuits in the display panel, and the pixel circuit is driven.
  • the second electrode of the tube is connected to the switch tube to form a diode topology to implement voltage-type threshold voltage extraction.
  • the row is initialized by the gate time of the previous row, and the programming time of each row is only Threshold extraction and data writing time, driving speed is fast.
  • the circuit has the advantage of reducing one control signal line, thereby increasing the aperture ratio and reducing the complexity of the peripheral circuit.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the embodiment also discloses a display device.
  • a schematic structural diagram of a display device is also disclosed.
  • the display device includes:
  • the display panel 100 includes the pixel circuits Pixel[1][1]...Pixel[n][m] provided by the above embodiments arranged in a matrix of n rows and m columns, where n and m are integers greater than 0.
  • Pixel[n][m] represents a pixel circuit of the nth row and m columns; a plurality of scan lines Gate[1]...Gate[n] in a first direction (for example, a lateral direction) connected to each pixel, wherein, Gate [n] represents a scan line corresponding to the pixel circuit of the nth row, for providing a scan control signal, such as a first scan control signal V SCAN , a second scan control signal V EM , and a third scan control signal, to the pixel circuit of the line.
  • a scan control signal such as a first scan control signal V SCAN , a second scan control signal V EM , and a third scan control signal
  • the display panel may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, or the like, and the corresponding display device may be a liquid crystal display, an organic light emitting display, an electronic paper display, or the like.
  • some scan control signals required by the pixel circuit may also be provided by a global line, such as a power line required at the first level end and a power line required at the second level end. Etc., those skilled in the art can adjust according to the requirements of a specific pixel circuit.
  • the gate driving circuit 200 is configured to generate a scan pulse signal and provide a desired scan control signal to the pixel circuit through the respective scan lines Gate[1]...Gate[n] formed along the first direction.
  • the data driving circuit 300, the signal output end of the data driving circuit 300 is coupled to the corresponding data lines Data[1]...Data[m] in the display panel 100, and the data voltage signal V DATA generated by the data driving circuit 300 passes through the data line. Data[1]...Data[m] is transferred to the corresponding pixel unit to achieve image gray scale.
  • the controller 400 is configured to provide control timing to the gate driving circuit and the data driving circuit.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • This embodiment also discloses an AC type (Alternating Current) driving method.
  • the pixel circuit described in each of the above embodiments is described by taking each transistor as an N-type transistor as an example. Please refer to FIG. 8 and FIG. 9 respectively, which are respectively a pixel circuit structure diagram and a working timing schematic diagram, and the effective power of each transistor is turned on. Flat is high.
  • Each driving cycle of the pixel circuit includes an initialization phase, a threshold extraction and a data writing phase, and an illumination phase, and the driving method includes:
  • the third scan control signal V 3 is an active level (for example, a high level).
  • the third scan control signal V 3 of the pixel circuit of the row is controlled by the first scan of the previous row.
  • the signal V SCAN is provided.
  • the first scan control signal V SCAN of the previous row is an active level (for example, a high level), so that the previous row of pixel rows is gated; the first level of the current row is VDD low.
  • the second scan signal V EM of the current line is at a first active level (eg, a high level).
  • the fifth transistor T5 and the fourth transistor T4 are respectively turned on in response to the third scan control signal V 3 and the active level of the second scan signal V EM of the current row, and thus the first node A is charged through the fifth transistor T5.
  • the second node B is discharged to V DDL through the turned-on fourth transistor T4 and the driving transistor T1, completing the initialization process.
  • V DDL should satisfy V DDL ⁇ V OLED0 , where V OLED0 is the threshold voltage of the light-emitting element OLED.
  • the pixel row of the current row is gated, the first scan signal V SCAN of the current row is converted from a low level to a high level, and the third scan control signal V 3 is from a high voltage.
  • the level is converted to a low level, and the second scan control signal V EM of the current line is converted from a high level to a low level, and the first level terminal VDD is a low level V DDL .
  • the fifth transistor T5 and the fourth transistor T4 are respectively controlled to be in an off state; the second transistor T2 and the third transistor T3 are turned on in response to an active level of the first scan signal V SCAN of the current line.
  • the first level terminal VDD is at a low level V DDL at this time, the first node A is at a high level, so that the second transistor T2 that is turned on causes the driving transistor to form a diode connection at the second electrode to start discharging to V DDL +V. TH_T1 ; at the same time, the turned-on third transistor T3 transmits the gray-scale related data voltage information V DATA to the second node B (ie, one end of the storage capacitor C S ), so that the storage capacitor C S is formed at both ends to be maintained The reference voltage for the entire frame time. At this time, the voltage difference between the first node A and the second node B is:
  • V A -V B V DDL +V TH_T1 -V DATA (9)
  • V A is the potential of the first node A
  • V B is the potential of the second node B
  • V TH_T1 represents the threshold voltage of the first transistor T1
  • V DDL represents the low level of the first level terminal VDD voltage
  • V DATA represents The pixel signal corresponds to the data signal voltage corresponding to the gray scale information required at this time.
  • the data voltage V DATA will remain on the C OLED until V EM is at a high level to conduct light.
  • the light-emitting element OLED can be effectively driven AC, thereby reducing or suppressing degradation of the light-emitting element OLED.
  • the time when V EM is low level given in this embodiment is 0.3T, wherein T is a cycle time of the pixel circuit driving process of the line. It should be noted that the relevant technician can reasonably set the time of the OLED negative bias according to the condition of the light emitting element OLED.
  • the third scan control signal V 3 is at a low level with the first scan control signal V SCAN of the current row, and the second transistor T2, the third transistor T3 and the fifth transistor T5 are both turned off;
  • the second scan control signal V EM of the row begins to change to a second active level (eg, from a low level to a high level), and then the fourth transistor T4 is turned on in response to the second scan control signal V EM .
  • the anode voltage V OLED of the light-emitting element OLED bootstraps the gate of the driving transistor T1 through the storage capacitor C S , and the reference voltage formed by the driving capacitor C S during the programming process remains unchanged, therefore, At this time, the voltage of the first node A is:
  • V A V TH_T1 +V DDL -V DATA +V B (10)
  • V A V TH_T1 +V DDL -V DATA +V OLED (11)
  • the current generated by the driving transistor T1 that is, the illuminating current flowing through the OLED OLED can be expressed as:
  • the I OLED is an illuminating current flowing through the OLED of the OLED;
  • ⁇ n , C OX and W/L are the field effect mobility of the driving transistor T1, the capacitance of the gate insulating layer per unit area, and the aspect ratio of the tube, respectively.
  • V OLED represents the voltage of the OLED across the lighting process can be seen from equation (12): flowing through the current I OLED of the driving transistor T1 of the light emitting element OLED threshold voltage V TH_T1 and the threshold voltage V OLED0 the light emitting element OLED irrespective only The data signals V DATA and V DDL related to the current pixel dot gradation are related.
  • the pixel circuit in this embodiment can compensate for the threshold voltage drift of the driving transistor and the light emitting element, and can also compensate for display unevenness caused by different threshold voltages of the driving transistors of the pixel circuits in the display panel, and the pixel circuit is driven.
  • the second electrode of the transistor is connected to the switching tube to form a diode topology to implement voltage-type threshold voltage extraction.
  • the row is initialized by the gate time of the previous row, and the programming time of each row is only the threshold extraction and data writing time. The drive speed is fast.
  • the pixel circuit of the present application does not emit light during the programming process, and a contrast pair is added, and the pixel circuit can make the OLED in the AC driving mode, which can reduce or suppress degradation of the OLED.

Abstract

L'invention concerne un circuit de pixel, un procédé de pilotage pour un circuit de pixel et un dispositif d'affichage. Un second transistor (T2) est connecté entre une électrode de commande d'un transistor de pilotage (T1) et une électrode d'activation pour former une structure topologique connectée en diode. En vertu de la structure de circuit et de la coopération avec un condensateur de stockage (Cs), durant une synchronisation de rangée courante, une tension de seuil (VTH_T1) du transistor de pilotage (T1) et des informations de tension de données associées à l'échelle de gris (VDONNÉES) sont extraites et stockées sur le condensateur de stockage (Cs), permettant ainsi de compenser la tension de seuil (VTH_T1) du transistor de pilotage (T1) et d'augmenter le contraste d'un dispositif d'affichage.
PCT/CN2016/076962 2015-03-25 2016-03-22 Circuit de pixel et son procédé de pilotage, et dispositif d'affichage WO2016150372A1 (fr)

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