WO2016149907A1 - 一种接收机及信号处理的方法 - Google Patents

一种接收机及信号处理的方法 Download PDF

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Publication number
WO2016149907A1
WO2016149907A1 PCT/CN2015/074947 CN2015074947W WO2016149907A1 WO 2016149907 A1 WO2016149907 A1 WO 2016149907A1 CN 2015074947 W CN2015074947 W CN 2015074947W WO 2016149907 A1 WO2016149907 A1 WO 2016149907A1
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Prior art keywords
module
signal
sampling
analog
afft
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PCT/CN2015/074947
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English (en)
French (fr)
Inventor
韩冬
刘智涌
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP15885846.4A priority Critical patent/EP3264700B1/en
Priority to CN201580075886.9A priority patent/CN107210985B/zh
Priority to PCT/CN2015/074947 priority patent/WO2016149907A1/zh
Publication of WO2016149907A1 publication Critical patent/WO2016149907A1/zh
Priority to US15/709,999 priority patent/US10333691B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24—Supports; Mounting means by structural association with other equipment or articles with receiving set
    • H01Q1/247—Supports; Mounting means by structural association with other equipment or articles with receiving set with frequency mixer, e.g. for direct satellite reception or Doppler radar
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a receiver and a method for signal processing.
  • a receiver is a device for converting a radio frequency signal into a digital baseband signal.
  • the conventional receiver includes a superheterodyne receiver and an I/Q (In-phase/Quadrature) demodulator receiver.
  • the structure of the superheterodyne receiver is shown in Fig. 5(A).
  • the RF signal is outputted by the filter, the amplifier, the mixer and the detector, and the digital baseband signal is output.
  • the mixer is used to generate the signal and the oscillator.
  • the signal is mixed to obtain an intermediate frequency signal.
  • the receiver Since the channel bandwidth of the mixer in the receiver generally does not exceed twice the center frequency of the intermediate frequency signal, and the center frequency of the intermediate frequency signal generally does not exceed 500 MHz, the receiver The operating bandwidth is limited by the mixer's channel bandwidth not reaching the GHz level; the structure of the I/Q demodulator receiver is shown in Figure 5(B), and the RF signal is filtered, amplified, and I/Q demodulated.
  • the digital baseband signal is output after the detector and the detector, wherein the I/Q demodulator is used to frequency-convert the received signal. Since the channel bandwidth of the I/Q demodulator does not exceed 500 MHz, the working bandwidth of the receiver is limited by I.
  • the channel bandwidth of the /Q demodulator cannot be on the order of GHz.
  • the direct RF receiver is a new generation of receivers.
  • the structure of the direct RF receiver is shown in Figure 5(C).
  • the RF signal is output to the digital baseband via filters, amplifiers, analog-to-digital converters and converters.
  • the signal does not need to mix or convert the RF signal, but directly performs high-speed analog-to-digital conversion. Therefore, the working bandwidth of the direct RF receiver depends only on the sampling bandwidth of the analog-to-digital conversion, thereby increasing the sampling bandwidth.
  • the operating bandwidth of the entire receiver is on the order of GHz.
  • the analog-to-digital converter of the direct RF receiver uses a high-speed ADC (Analog to Digital Converter) and requires a high-speed ADC with a sampling bandwidth much higher than that of a direct RF receiver.
  • ADC Analog to Digital Converter
  • the operating bandwidth requirement of 1 GHz must be Higher than 2GHz sampling bandwidth, but the high complexity of the high sampling ADC with high sampling bandwidth is very complicated and costly, which restricts the development of direct RF receiver.
  • the embodiment of the invention provides a receiver and a signal processing method, which can make the working bandwidth of the receiver reach the GHz level, and has the advantages of low cost and low complexity.
  • a first aspect of the embodiments of the present invention provides a receiver, including a high speed sampling module, an analog fast Fourier transform AFFT module, a selection switch module, a low speed analog to digital conversion ADC module, and a control module, wherein:
  • the high-speed sampling module is connected to the AFFT module, the AFFT module is connected to the selection switch module, the selection switch module is connected to the low-speed ADC module, and the control module is respectively connected to the high-speed sampling module and the Connecting the AFFT module, the selection switch module, and the low speed ADC module;
  • the high-speed sampling module is configured to sample a received signal, and output a sampling signal to the AFFT module, where the AFFT module is configured to perform time-frequency conversion on the sampling signal, and output an analog frequency domain signal to the selection switch.
  • the selection switch module is configured to transmit the analog frequency domain signal to the low speed ADC module
  • the low speed ADC module is configured to convert the analog frequency domain signal into a digital baseband signal
  • the control module is used to The sampling rate of the high speed sampling module, the number of points of the fast Fourier transform used by the AFFT module for time-frequency conversion, and the target input port of the selection switch module are configured.
  • the high-speed sampling module includes an input port and M output ports, where the M is an integer greater than 2.
  • the high-speed sampling module is specifically configured to sequentially switch the input port to each of the output ports according to the configured sampling rate, to sample the received signal, and output the obtained sampling signal to The AFFT module.
  • the receiver further includes a clock module, where the control module is connected to the high-speed sampling module by using the clock module ,
  • the clock module is configured to send a clock signal of a specified period to the high speed sampling module, where the specified period is equal to a reciprocal of the sampling rate;
  • the high-speed sampling module is specifically configured to sequentially switch the input ports to each of the output ports according to the clock signal.
  • the sampling rate is greater than twice the bandwidth of the received signal.
  • the sampling rate is on the order of GHz.
  • the AFFT module includes M input ports and M output ports, the AFFT The M input ports of the module are respectively connected to the M output ports of the high speed sampling module.
  • the AFFT module is configured to perform time-frequency conversion on the sampling signal input by the input port by using the fast Fourier transform, and output the analog frequency domain signal obtained by time-frequency conversion through the output port. To the selection switch module.
  • the selection switch module includes M input ports and one output port, and the target input port of the selection switch module For one of the M input ports, the M input ports of the selection switch module are respectively connected to the M output ports of the AFFT module,
  • the selection switch module is configured to receive the analog frequency domain signal through the configured target input port, and transmit the analog frequency domain signal to the low speed ADC module through the output port.
  • the sampling bandwidth of the low-speed ADC module is not higher than 2 GHz.
  • control module is specifically used according to a formula
  • control module is also specifically used according to a formula
  • the receiver further includes a receiving antenna, a filtering module, and a gain low noise amplifier LNA module, where:
  • the receiving antenna is connected to the filtering module, the filtering module is connected to the gain LNA module, the gain LNA module is connected to the high speed sampling module, and the receiving antenna is configured to receive a radio frequency signal, the filtering module
  • the method is configured to filter the radio frequency signal, and the gain LNA module is configured to amplify the filtered radio frequency signal to obtain the received signal.
  • a second aspect of the embodiments of the present invention provides a signal processing method, including:
  • the analog baseband signal is analog-to-digital converted to obtain a digital baseband signal.
  • the sampling the received signal to obtain the sampling signal includes:
  • the received signal is sampled according to a specified sampling rate to obtain a sampled signal.
  • the sampling the received signal according to the specified sampling rate includes:
  • the received signal is sampled according to the clock signal.
  • the sampling rate is greater than twice the bandwidth of the received signal.
  • the sampling rate is on the order of GHz.
  • the sampling signal is time-frequency converted to obtain an analog frequency domain signal.
  • the sampling rate and the number of points of the fast Fourier transform are according to a formula
  • the fs represents the sampling rate
  • the N represents the number of points of the fast Fourier transform
  • the N is 2 n
  • the n is an integer greater than 1
  • the f0 represents the receiving The center frequency of the signal
  • the x representing an arbitrary natural number
  • B representing the bandwidth of the received signal.
  • the filtering the analog frequency domain signal to obtain an analog baseband signal includes:
  • An analog frequency domain signal with the smallest center frequency is selected as the analog baseband signal.
  • the method before the sampling the received signal to obtain the sampling signal, the method further includes:
  • a third aspect of the embodiments of the present invention provides a computer storage medium storing a program, the program including some or all of the steps of a signal processing method provided by the first aspect.
  • a fourth aspect of the embodiments of the present invention provides a receiver, including: an antenna interface, a memory, and a processor, wherein the memory stores a set of programs, and the processor is configured to call a program stored in the memory, and perform the following operations:
  • the analog baseband signal is analog-to-digital converted to obtain a digital baseband signal.
  • the receiver provided by the embodiment of the present invention samples the received signal by the high-speed sampling module to obtain the sampling signal, and then performs time-frequency conversion on the sampled signal through the AFFT module to obtain the mode.
  • the frequency domain domain signal is finally converted into a digital baseband signal by a low speed ADC module, thereby realizing the function of the receiver.
  • the receiver provided by the embodiment of the present invention does not use the mixer in the conventional receiver. Or I/Q demodulator, so the operating bandwidth is not limited by the channel bandwidth of the mixer or I/Q demodulator.
  • the channel bandwidth of the high-speed sampling module and the AFFT module can reach GHz, and thus the receiver
  • the working bandwidth can reach the GHz level; since the center frequency of the analog frequency domain signal obtained by the fast Fourier transform is not high, the sampling bandwidth of the analog-to-digital conversion is not high (understandably, the sampling bandwidth is equal to the center frequency That is, the high speed ADC can be avoided, and thus the receiver of the embodiment of the present invention has the advantages of low cost and low complexity.
  • FIG. 1 is a schematic structural diagram of a receiver according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another receiver according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method for signal processing according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another receiver according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a conventional receiver according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of simulation of a sampling signal according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of simulation of an analog frequency domain signal according to an embodiment of the present invention.
  • the receiver provided by the embodiment of the present invention can be applied to various communication systems, for example, a Global System of Mobile communication (“GSM”) system, and multiple code points.
  • Code Division Multiple Access (“CDMA”) system Code Division Multiple Access (“WCDMA) system, Wideband Code Division Multiple Access (WCDMA) system, General Packet Radio Service (“GPRS”) ), Long Term Evolution (LTE) system, LTE Frequency Division Duplex (FDD) system, LTE Time Division Duplex (TDD) , Universal Mobile Telecommunication System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX) communication system or PLMN (Public Land Mobile Network) Land mobile network) communication system (referred to as "5G network”).
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • WiMAX Public Land Mobile Network Land mobile network
  • the receiver may be built in various receiving devices, including but not limited to user equipment (User Equipment, referred to as "UE"), and mobile station (Mobile Station, referred to as "MS” for short.
  • UE User Equipment
  • MS Mobile Station
  • Base station Base Transceiver Station, abbreviated as "BTS” in GSM or CDMA
  • NodeB base station
  • eNB evolved Node B
  • LTE evolved Node B
  • the receiver in the embodiment of the present invention may include at least a high speed sampling module 110, an analog fast Fourier transform AFFT (AFFT) module 120, a selection switch module 130, and a low speed analog to digital conversion ADC (Analog to Digital Converter). a module 140 and a control module 150, wherein:
  • the high-speed sampling module 110 is connected to the AFFT module 120, the AFFT module 120 is connected to the selection switch module 130, and the selection switch module 130 is connected to the low-speed ADC module 140.
  • the control module 150 is respectively connected to the high-speed sampling module 110, the AFFT module 120, the selection switch module 130, and The low speed ADC module 140 is connected.
  • the high speed sampling module 110 is configured to sample the received signal and output the sampling signal to the AFFT module 120.
  • the received signal may be a radio frequency signal received by the antenna, or may be a further filtered or amplified radio frequency signal.
  • the high-speed sampling module 110 includes one input port and M output ports, and M is an integer greater than 2.
  • the high-speed sampling module 110 sequentially switches the input ports to the respective output ports according to the configured sampling rate to receive the data.
  • the signal is sampled and the resulting sampled signal is output to the AFFT module 120.
  • the M output ports can only acquire the received signals periodically, which is equivalent to sampling the received signals, and the faster the switching connection rate, the sampling rate thereof. The sooner.
  • the signals output by the M output ports are collectively referred to as sampling signals.
  • the above sampling rate is configured and delivered by the control module 150.
  • the output port to which the input port is sequentially switched may be all output ports, or may be part of M output ports.
  • the number of output ports to which the input port is sequentially switched is also configured by the control module 150. Issued.
  • the receiver shown in FIG. 1 further includes a clock module 160.
  • the control module 150 is connected to the high-speed sampling module 110 through the clock module 160.
  • the clock module 160 sends the specified period to the high-speed sampling module 110.
  • the clock signal, wherein the specified period is equal to the reciprocal of the sampling rate, the sampling rate is configured by the control module 150 and sent to the clock module 160; the high-speed sampling module 110 sequentially switches the input ports to the respective output ports according to the clock signal.
  • the sampling rate mentioned above should be greater than twice the bandwidth of the received signal to satisfy the bandpass sampling law.
  • the upper limit of the sampling rate is not lower than 6 GHz, that is, the bandwidth of at least 6 GHz can be supported, wherein 6 GHz is the core frequency of the 5G network.
  • the high-speed sampling module 110 is only used for sampling, and thus the hardware structure is simple, so even if its sampling rate is increased to the order of GHz ("the magnitude of GHz" in the embodiment of the present invention means "frequency greater than 1 GHz".
  • the embodiment of the present invention selects the high-speed sampling module 110 to sample the received signal, which has the advantages of low cost and low complexity.
  • the AFFT module 120 is configured to perform time-frequency conversion on the sampled signal and output the analog frequency domain signal to the selection switch module 130.
  • the AFFT module 120 includes M input ports and M output ports.
  • the M input ports of the AFFT module 120 are respectively connected to the M output ports of the high-speed sampling module 110, and the AFFT module 120 passes the configured fast Fourier transform.
  • the number of points is time-frequency converted by the sampling signal input to the input port thereof, and the analog frequency domain signal obtained by the time-frequency conversion is output to the selection switch module through the output port thereof, wherein the analog frequency domain signal refers to the frequency domain (Frequency) Analog signal.
  • the respective input ports of the AFFT module 120 also periodically receive the sampling signals, and respectively Time-frequency conversion is performed on the sampling signals received by multiple input ports in each cycle.
  • FFT Fast Fourier Transform
  • y N (n) is the frequency domain signal output by the input port N of the AFFT module 120. Since the above process is all linear transformation, it does not cause loss to the dynamic range of the receiver.
  • the dynamic range refers to the range of the input signal size that the receiver detects the received signal and makes the received signal undistorted, and the dynamic range is too large to generate noise. If it is too small, it cannot be detected.
  • the AFFT module 120 in the embodiment of the present invention is used to implement fast Fourier transform, and has the characteristics of simple structure and low cost.
  • the channel bandwidth of the AFFT module 120 can be on the order of GHz.
  • the receiver in the embodiment of the present invention does not use a mixer or an I/Q demodulator in a conventional receiver, and overcomes the problem that the working bandwidth is limited by the mixer or the I/Q demodulator.
  • the channel bandwidth of the high-speed sampling module 110 and the AFFT module 120 can reach the order of GHz, and the working bandwidth of the receiver can reach the order of GHz.
  • the quality of the received signal is degraded. It is necessary to increase the noise reduction circuit for noise reduction, which makes the architecture complex and the hardware area large. Due to the inherent carrier leakage and DC imbalance leakage of the I/Q demodulator, the dynamic range is lost, and the anti-leakage circuit needs to be added to prevent leakage.
  • the processing also makes the architecture complex and the hardware area large; and the high-speed sampling module 110 and the AFFT module 120 do not need to perform noise reduction processing and anti-leak processing, which can simplify the architecture of the receiver and reduce the hardware area.
  • the selection switch module 130 is configured to transmit the analog frequency domain signal to the low speed ADC module 140.
  • the selection switch module 130 includes M input ports and one output port, and the M input ports of the selection switch module are respectively connected to the M output ports of the AFFT module 120, and the selection switch module 130 passes the configured target input port.
  • the analog frequency domain signal is received and the analog frequency domain signal is transmitted to the low speed ADC module through the output port, wherein the target input port is one of the M input ports of the selection switch module 130.
  • the port number of the target input port is configured and sent by the control module 150 to ensure that the low-speed ADC module 140 obtains the best analog frequency domain signal.
  • the optimal analog frequency domain signal is an analog frequency domain signal with the smallest center frequency point.
  • the AFFT module 120 performs fast Fourier transform on the sampled signal to obtain N analog frequency domain signal outputs with different center frequency points.
  • the smaller the center frequency of the analog frequency domain signal the smaller the sampling bandwidth of the low speed ADC module 140 (the sampling bandwidth of the analog to digital converter is the operating bandwidth for completing the analog to digital conversion), and the lower the cost and complexity of the low speed ADC module 140.
  • the switch module 130 needs to receive the analog frequency domain signal with the smallest center frequency point according to the configured target input port.
  • one of the N analog frequency domain signals output by the AFFT module 120 one of which simulates the center frequency of the frequency domain signal.
  • Zero ie, zero IF signal, the center frequency of the zero IF signal is the smallest
  • the configured target input port is the second input port of the selection switch module 130, and the selection switch module 130 receives the analog frequency domain signal through the target input port and transmits the signal to the low speed ADC. Block 140.
  • the N analog frequency domain signals output by the AFFT module 120 all carry complete useful information (data information or voice information), so only one optimal analog frequency domain signal needs to be selected and transmitted to the low speed ADC module 140. Just discard other analog frequency domain signals.
  • the analog frequency domain signal outputted by the nth output port of the AFFT module 120 is Y(n), and obviously Y(n) includes x(1) to x(N), that is, Y(n) includes a(1)+j. *b(1) to a(N)+j*b(N), that is, the analog frequency domain signals output by any one of the output ports of the AFFT module 120 carry the first to Nth inputs of the AFFT module 120.
  • the embodiment of the present invention simulates the input and output of the AFFT module 120. Referring to FIG. 6, the pulse signal in FIG. 6 is the sampling pulse received by the input port of the AFFT module 120.
  • the sampling pulse is composed of a fundamental wave and a harmonic.
  • the signal in FIG. 7 is an analog frequency domain signal outputted by the first output port of the AFFT module 120. It can be seen that the analog signal carries all input ports and receives Sampling pulse information.
  • the AFFT module 120 performs fast Fourier transform on the sampled signal to obtain N analog frequency domain signals with different center frequency points, wherein at least one analog frequency domain signal has a lower center frequency than the original received signal.
  • the central frequency point since the selection switch module 130 selects the analog frequency domain signal in which the minimum center frequency is received, the center frequency of the analog frequency domain signal must be lower than the center frequency of the original received signal, and the AFFT module 120 and The selection switch module 130 implements spectrum shifting on the original received signal, which is an analog baseband signal.
  • the mixer and the I/Q demodulator in the conventional receiver are respectively used for mixing and frequency conversion, and the purpose is also to achieve spectrum shifting. Therefore, the high-speed sampling module 110 in the embodiment of the present invention.
  • the AFFT module 120 and the selection switch module 130 can replace the mixer or I/Q demodulator in the conventional receiver, which is why the receiver does not use a mixer or an I/Q demodulator.
  • the implementation of the frequency conversion or spectrum shift based on the AFFT provided by the embodiment of the present invention can greatly simplify the complexity of the receiver and reduce the cost.
  • the low speed ADC module 140 is used to convert analog frequency domain signals into digital baseband signals.
  • the converted digital signal is divided into a real part I(t) and an imaginary part Q(t) output, which are sent to a subsequent processing device, and the processing device demodulates the useful signal, such as data information, from the digital baseband signal. Voice information, etc.
  • the sampled signal can be converted from the time domain to the frequency domain. Since the signal processing speed in the frequency domain is faster than that in the time domain, the receiver is improved.
  • the time-frequency conversion process also performs spectral shifting on the sampled signal to obtain a plurality of analog frequency domain signals having different center frequency points, and selects a center frequency from the plurality of analog frequency domain signals through the selection switch module 130.
  • the lowest analog frequency domain signal is used, and the analog frequency domain signal with low center frequency point has low sampling bandwidth requirement for analog-to-digital conversion (it should be understood that the sampling bandwidth is equal to the center frequency point), and high-speed ADC can be avoided.
  • the sampling bandwidth of the low-speed ADC module 140 in the embodiment of the present invention is lower than 2 GHz, and 2 GHz can be considered as a critical value. Above 2 GHz, the cost and complexity of the ADC are high.
  • the control module 150 is configured to configure the sampling rate of the high speed sampling module 110, the number of points of the fast Fourier transform used by the AFFT module 120 for time-frequency conversion, and the target input port of the selection switch module 130.
  • control module 150 according to formula (1)
  • a sampling rate of the high speed sampling module 110 and a number of points of the fast Fourier transform used by the AFFT module 120 for time-frequency conversion wherein the fs represents the sampling rate, and the N represents the number of points of the fast Fourier transform.
  • N 2 n , the n is an integer greater than 1, and the N is not greater than the M, the f0 represents a center frequency of the received signal, the x represents an arbitrary natural number, and the B represents the The bandwidth of the received signal.
  • f0 and B are system pre-configured parameters, which are known by the control module 150 by default, and fs, N and x are unknown.
  • the control module 150 finds the unknown fs, N, and x by an equation and an inequality in the formula (1). Further, if the obtained fs, N, and x have multiple sets of results, the set of results with the smallest fs is taken because the fs is smaller and the speed is high under the condition of fs>B.
  • Control module 150 is further according to formula (2)
  • the target input port of the selection switch module 130 is configured, wherein the Bin represents the port number of the target input port. It should be noted that the embodiment of the present invention pre-identifies the port number of the input port of the selection switch module 130, for example, pre-identifying the first to Nth input ports of the selection switch module 130 by using the first to Nth port numbers, respectively. It should also be noted that the port number obtained according to formula (2) corresponds to the center frequency of the received analog frequency domain signal being the smallest relative to other ports.
  • f0 1.9 GHz
  • B 40 MHz
  • the obtained fs 0.034 GHz
  • the obtained fs 1.5 GHz
  • control module 150 then configures fs to the high speed sampling module 110, or the clock module 160; configures the N point fast Fourier transform to the AFFT module 120; and configures the Bin to the selection switch module 130.
  • the receiver provided by the embodiment of the present invention samples the received signal by the high-speed sampling module to obtain the sampling signal, and then performs time-frequency conversion on the sampled signal through the AFFT module to obtain the analog frequency domain signal, and finally passes the low-speed ADC module.
  • the function of the receiver is implemented by converting the analog frequency domain signal into a digital baseband signal, wherein the receiver provided by the embodiment of the present invention does not use a mixer or an I/Q demodulator in the conventional receiver, and thus works.
  • the bandwidth is not limited by the channel bandwidth of the mixer or I/Q demodulator.
  • the channel bandwidth of the high-speed sampling module and the AFFT module can reach GHz, and the working bandwidth of the receiver can reach the GHz level.
  • the center frequency of the analog frequency domain signal obtained after fast Fourier transform is not high, so the sampling bandwidth of the analog-to-digital conversion is not high (understandably, the sampling bandwidth is equal to the center frequency point), and high-speed ADC can be avoided.
  • the receiver of the embodiment of the present invention also has the advantages of low cost and low complexity.
  • the receiver in the embodiment of the present invention includes at least a high-speed sampling module 110, an analog fast Fourier transform AFFT module 120, a selection switch module 130, a low-speed analog-to-digital conversion ADC module 140, a control module 150, and a clock module 160 receiving antenna. 170, filter module 180 and low noise amplifier LNA (Low Noise Amplifier) Module 190, wherein:
  • the receiving antenna 170 is connected to the filtering module 180, the filtering module 180 is connected to the LNA module 190, the LNA module 190 is connected to the high-speed sampling module 110, the high-speed sampling module 110 is connected to the AFFT module 120, and the AFFT module 120 is connected to the selection switch module 130.
  • the module 130 is connected to the low speed ADC module 140.
  • the control module 150 is respectively connected to the high speed sampling module 110, the AFFT module 120, the selection switch module 130 and the low speed ADC module 140. Further, the control module 150 is connected to the high speed sampling module 110 through the clock module 160. .
  • Receive antenna 170 is used to receive radio frequency signals over land, ocean or air.
  • the filtering module 180 is configured to filter the radio frequency signal. The purpose is to filter out unwanted signals such as clutter or interference signals.
  • the filtering module 180 is a band pass filter.
  • the LNA module 190 is configured to amplify the filtered RF signal to obtain a received signal, that is, to amplify the RF signal to a detectable level.
  • the LNA module 190 may specifically be a gain LNA circuit.
  • the filtering module 180 maintains the bandwidth of the filtered radio frequency signal as B, and the channel bandwidth of the LNA module 190 is greater than B, and the LNA module 190 filters the filtered
  • the level of the radio frequency signal is amplified to a level detectable by the high speed sampling module 110, and the amplified signal is a received signal.
  • the high speed sampling module 110 is configured to sample the received signal and output the sampling signal to the AFFT module 120.
  • the clock module 160 is configured to send a clock signal of a specified period to the high-speed sampling module 110, wherein the specified period is equal to the reciprocal of the sampling rate, and the sampling rate is configured by the control module 150 and sent to the clock module 160.
  • the high speed sampling module 110 sequentially switches the input ports to the respective output ports according to the clock signal.
  • the AFFT module 120 is configured to perform time-frequency conversion on the sampled signal and output the analog frequency domain signal to the selection switch module 130.
  • the selection switch module 130 is configured to transmit the analog frequency domain signal to the low speed ADC module 140.
  • the low speed ADC module 140 is used to convert analog frequency domain signals into digital baseband signals.
  • the control module 150 is configured to configure the sampling rate of the high speed sampling module 110, the number of points of the fast Fourier transform used by the AFFT module 120 for time-frequency conversion, and the target input port of the selection switch module 130.
  • the signal flow direction of the receiver provided by the embodiment of the present invention can be summarized as: 1 analog radio frequency signal ⁇ 2 analog sampling signal ⁇ 3 analog frequency domain signal ⁇ 4 analog baseband signal ⁇ 5 digital baseband signal. It can be seen that the signal processing of the present receiver is concentrated in the analog domain (ie, 1 to 4 are analog domains), and the receiver shown in the embodiment of the present invention can mainly work in the analog domain to convert the radio frequency signal into a digital baseband signal.
  • the receiver provided by the embodiment of the invention samples the received signal by the high-speed sampling module to obtain the sampling signal, and then performs time-frequency conversion on the sampled signal through the AFFT module to obtain the analog frequency domain signal, and finally simulates the frequency domain through the low-speed ADC module.
  • the signal is converted into a digital baseband signal to implement the function of the receiver. Since the receiver provided by the embodiment of the present invention does not use a mixer or an I/Q demodulator in the conventional receiver, the working bandwidth is not affected.
  • the channel bandwidth of the high-speed sampling module and the AFFT module can reach the order of GHz, and the working bandwidth of the receiver can reach the GHz order; due to the fast Fourier transform
  • the center frequency of the obtained analog frequency domain signal is not high, so the sampling bandwidth of the analog-to-digital conversion is not high (it should be understood that the sampling bandwidth is equal to the center frequency point), and the high-speed ADC can be avoided, so the present invention is implemented.
  • the receiver of the example also has the advantages of low cost and low complexity.
  • FIG. 3 is a schematic flowchart diagram of a method for signal processing according to an embodiment of the present invention, which may include:
  • the receiver samples the received signal according to the specified sampling rate to obtain the sampled signal, where the received signal may be a radio frequency signal received by the antenna, or may be a further filtered or amplified radio frequency signal.
  • the receiver is a clock signal of a specified period, the specified period is equal to the reciprocal of the sampling rate; and the received signal is sampled according to the clock signal.
  • the sampling rate mentioned above should be greater than twice the bandwidth of the received signal to satisfy the bandpass sampling law.
  • the upper limit of the sampling rate is not lower than 6 GHz, that is, at least 6 GHz bandwidth can be supported.
  • the receiver before receiving the received signal, receives the radio frequency signal; filters the radio frequency signal; and amplifies the filtered radio frequency signal to obtain the received signal.
  • the receiver performs time-frequency conversion on the sampled signal by fast Fourier transform to obtain multiple analog frequency domain signals with different center frequency points.
  • the time-frequency conversion in the embodiment of the present invention is a fast Fourier transform. Since the process is a linear transformation, the dynamic range of the receiver is not lost.
  • the dynamic range refers to the receiver detecting the received signal.
  • the range of the input signal that does not distort the received signal is too large, and the dynamic range is too large to generate distortion and noise. If it is too small, it cannot be detected.
  • the number of points of the fast Fourier transform is also determined according to the formula (1).
  • the receiver filters out an analog frequency domain signal having the smallest center frequency point as the analog baseband signal.
  • the multiple analog frequency domain signals obtained in step S102 all carry complete useful information (data information or voice information), so it is only necessary to select an optimal analog frequency domain signal as the analog baseband signal. Discard other analog frequency domain signals. The reason why multiple analog frequency domain signals carry complete useful information has been introduced above, and will not be described here.
  • the center frequency of the analog baseband signal selected from the plurality of analog frequency domain signals is lower than the center frequency of the original received signal. Further, the center frequency of the selected analog baseband signal may be At the zero frequency point, it can be seen that the receiver realizes the spectrum shifting of the original received signal.
  • the converted digital signal is divided into a real part I(t) and an imaginary part Q(t) output, which are sent to a subsequent processing device, and the processing device demodulates the useful signal, such as data information, from the digital baseband signal. Voice information, etc.
  • the receiver may include: at least one processor 401, such as a CPU, at least one antenna interface 403, and a memory 404, at least one.
  • Communication bus 402. the communication bus 402 is used to implement the connection between these components Connected to the communication.
  • the antenna interface 403 in the embodiment of the present invention is configured to receive a radio frequency signal.
  • the memory 404 may be a high speed RAM memory or a non-volatile memory such as at least one disk memory.
  • the memory 404 may also be at least one storage device located away from the foregoing processor 401.
  • a set of program codes is stored in the memory 404, and the processor 401 is configured to call the program code stored in the memory 404 to perform the following operations:
  • the analog baseband signal is analog-to-digital converted to obtain a digital baseband signal.
  • the specific operation of the processor 401 to sample the received signal to obtain the sampling signal is:
  • the received signal is sampled according to a specified sampling rate to obtain a sampled signal.
  • the received signal is sampled according to the clock signal.
  • the sampling rate is greater than twice the bandwidth of the received signal.
  • sampling rate is on the order of GHz.
  • the specific operation of the processor 401 to perform time-frequency conversion on the sampling signal to obtain an analog frequency domain signal may also be:
  • the sampled signal is time-frequency converted by fast Fourier transform to obtain multiple analog frequency domain signals with different center frequency points.
  • sampling rate and the number of points of the fast Fourier transform are according to a formula
  • the fs represents the sampling rate
  • the N represents the number of points of the fast Fourier transform
  • the N is 2 n
  • the n is an integer greater than 1
  • the f0 represents the receiving The center frequency of the signal
  • the x representing an arbitrary natural number
  • B representing the bandwidth of the received signal.
  • the specific operation of the processor 401 to filter the analog frequency domain signal to obtain an analog baseband signal is:
  • the processor 401 samples the received signal to obtain the sampling signal, and further performs:
  • the embodiment of the present invention further provides a computer storage medium, wherein the computer storage medium stores a program, and the program includes a plurality of instructions for performing a signal processing method described in the embodiments of the present invention. Part or all of the steps.
  • the receiver provided by the embodiment of the present invention samples the received signal by the high-speed sampling module to obtain the sampling signal, and then performs time-frequency conversion on the sampled signal through the AFFT module to obtain the analog frequency domain signal, and finally passes the low-speed ADC module.
  • the function of the receiver is implemented by converting the analog frequency domain signal into a digital baseband signal, wherein the receiver provided by the embodiment of the present invention does not use a mixer or an I/Q demodulator in the conventional receiver, and thus works.
  • the bandwidth is not limited by the channel bandwidth of the mixer or I/Q demodulator.
  • the channel bandwidth of the high-speed sampling module and the AFFT module can reach GHz, and the working bandwidth of the receiver can reach the GHz level.
  • the center frequency of the analog frequency domain signal obtained after fast Fourier transform is not high, so the sampling bandwidth of the analog-to-digital conversion is not high (understandably, the sampling bandwidth is equal to the center frequency point), and high-speed ADC can be avoided.
  • the receiver of the embodiment of the present invention also has the advantages of low cost and low complexity.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

本发明实施例公开了一种接收机，包括高速采样模块（110）、模拟快速傅氏变换（AFFT）模块（120）、选择开关模块（130）、低速模数转换（ADC）模块（140）以及控制模块（150），所述高速采样模块（110）用于对接收信号进行采样，并输出采样信号至所述AFFT模块（120），所述AFFT模块（120）用于对所述采样信号进行时频转换，并输出模拟频域信号至所述选择开关模块（130），所述选择开关模块（130）用于将模拟频域信号传送至所述低速ADC模块（140），所述低速ADC模块（140）用于将模拟频域信号转换为数字基带信号，所述控制模块（150）用于配置高速采样模块（110）的采样速率、AFFT模块（120）进行时频转换所用的快速傅氏变换的点数和选择开关模块（130）的目标输入端口。相应地，本发明实施例还公开了一种信号处理的方法。本发明可以使接收机的工作带宽达到GHz量级，并具有成本低和复杂度低的优点。

Description

一种接收机及信号处理的方法 技术领域
本发明涉及通信技术领域，尤其涉及一种接收机及信号处理的方法。
背景技术
随着移动通信技术的不断发展，数据传输所需的带宽越来越大，这对接收机的工作带宽提出了更高的要求。接收机是一种用于将射频信号转换为数字基带信号的设备，传统的接收机包括超外差接收机和I/Q(In-phase/Quadrature，同相正交)解调器接收机。超外差接收机的结构如图5(A)所示，射频信号经滤波器、放大器、混频器和检波器后输出数字基带信号，其中，混频器用于将接收信号和振荡器产生的信号进行混频以得到中频信号，由于在接收机中混频器的通道带宽一般不会超过中频信号的中心频点的两倍，且中频信号的中心频点一般不会超过500MHz，故接收机的工作带宽受限于混频器的通道带宽无法达到GHz量级；I/Q解调器接收机的结构如图5(B)所示，射频信号经滤波器、放大器、I/Q解调器和检波器后输出数字基带信号，其中，I/Q解调器用于对接收信号进行变频，由于I/Q解调器的通道带宽不会超过500MHz，故接收机的工作带宽受限于I/Q解调器的通道带宽无法达到GHz量级。
直接射频(Direct RF)接收机是较新一代的接收机，直接射频接收机的结构如图5(C)所示，射频信号经滤波器、放大器、模数转换器和变换器后输出数字基带信号，其无需对射频信号进行混频或变频，而是直接进行高速模数转换，故直接射频接收机的工作带宽仅取决于模数转换的采样带宽，从而通过增大采样带宽便可增大整个接收机的工作带宽，以达到GHz量级。直接射频接收机的模数转换器采用了高速ADC(Analog to digital converter，模数转换器)，并要求高速ADC的采样带宽远高于直接射频接收机的工作带宽，例如1GHz的工作带宽要求必须高于2GHz的采样带宽，但是过高采样带宽的高速ADC的生产复杂度和成本极高，制约了直接射频接收机的发展。
因此，如何使接收机的工作带宽达到GHz量级，又不会增加其成本和生产复杂度，是目前亟需解决的问题。
发明内容
本发明实施例提供了一种接收机及信号处理的方法，可以使接收机的工作带宽达到GHz量级，并具有成本低和复杂度低的优点。
本发明实施例第一方面提供了一种接收机，包括高速采样模块、模拟快速傅氏变换AFFT模块、选择开关模块、低速模数转换ADC模块以及控制模块，其中：
所述高速采样模块与所述AFFT模块连接，所述AFFT模块与所述选择开关模块连接，所述选择开关模块与所述低速ADC模块连接，所述控制模块分别与所述高速采样模块、所述AFFT模块、所述选择开关模块和所述低速ADC模块连接；
所述高速采样模块用于对接收信号进行采样，并输出采样信号至所述AFFT模块，所述AFFT模块用于对所述采样信号进行时频转换，并输出模拟频域信号至所述选择开关模块，所述选择开关模块用于将所述模拟频域信号传送至所述低速ADC模块，所述低速ADC模块用于将所述模拟频域信号转换为数字基带信号，所述控制模块用于配置所述高速采样模块的采样速率、所述AFFT模块进行时频转换所用的快速傅氏变换的点数和所述选择开关模块的目标输入端口。
在第一方面的第一种可能实现方式中，所述高速采样模块包括1个输入端口和M个输出端口，所述M为大于2的整数，
所述高速采样模块，具体用于根据配置的所述采样速率将所述输入端口依次切换连接到各个所述输出端口，以对所述接收信号进行采样，并将得到的所述采样信号输出至所述AFFT模块。
结合第一方面以及第一方面的第一种可能实现方式，在第二种可能实现方式中，所述接收机还包括时钟模块，所述控制模块通过所述时钟模块与所述高速采样模块连接，
所述时钟模块，用于向所述高速采样模块发送指定周期的时钟信号，所述指定周期等于所述采样速率的倒数；
所述高速采样模块，具体用于根据所述时钟信号将所述输入端口依次切换连接到各个所述输出端口。
结合第一方面以及第一方面的第一种可能实现方式，在第三种可能实现方式中，所述采样速率大于两倍的所述接收信号的带宽。
结合第一方面以及第一方面的第三种可能实现方式，在第四种可能实现方式中，所述采样速率达到GHz量级。
结合第一方面以及第一方面的第一至第四种中任意一种可能实现方式，在第五种可能实现方式中，所述AFFT模块包括M个输入端口和M个输出端口，所述AFFT模块的M个输入端口分别与所述高速采样模块的M个输出端口连接，
所述AFFT模块，具体用于通过所述快速傅氏变换对所述输入端口输入的所述采样信号进行时频转换，并将时频转换得到的所述模拟频域信号通过所述输出端口输出至所述选择开关模块。
结合第一方面以及第一方面的第五种可能实现方式，在第六种可能实现方式中，所述选择开关模块包括M个输入端口和1个输出端口，所述选择开关模块的目标输入端口为所述M个输入端口的其中一个，所述选择开关模块的M个输入端口分别与所述AFFT模块的M个输出端口连接，
所述选择开关模块，具体用于通过配置的所述目标输入端口接收所述模拟频域信号，并通过所述输出端口将所述模拟频域信号传送至所述低速ADC模块。
结合第一方面的可能实现方式，在第七种可能实现方式中，所述低速ADC模块的采样带宽不高于2GHz。
结合第一方面以及第一方面的第六种可能实现方式，在第八种可能实现方式中，所述控制模块，具体用于根据公式
Figure PCTCN2015074947-appb-000001
配置所述高速采样模块的采样速率和所述AFFT模块进行时频转换所用的快速傅氏变换的点数，其中，所述fs表示所述采样速率，所述N表示所述快速傅氏变换的点数，所述N＝2n，所述n为大于1的整数，且所述N不大于所述M，所述f0表示所述接收信号的中心频率，所述x表示任意自然数，所述B表示所述接收信号的带宽；
所述控制模块，还具体用于根据公式
Bin＝(f0-fs*x)/(fs/N)
配置所述选择开关模块的所述目标输入端口，其中，所述Bin表示所述目标输入端口的端口号。
结合第一方面的可能实现方式，在第九种可能实现方式中，所述接收机还包括接收天线、滤波模块和增益低噪声放大器LNA模块，其中：
所述接收天线与所述滤波模块连接，所述滤波模块与所述增益LNA模块连接，所述增益LNA模块与所述高速采样模块连接，所述接收天线用于接收射频信号，所述滤波模块用于对所述射频信号进行滤波，所述增益LNA模块用于对滤波后的射频信号进行放大以得到所述接收信号。
本发明实施例第二方面提供了一种信号处理的方法，包括：
对接收信号进行采样，以获取采样信号；
对所述采样信号进行时频转换，以获取模拟频域信号；
对所述模拟频域信号进行筛选，以获取模拟基带信号；
对所述模拟基带信号进行模数转换，以获取数字基带信号。
在第二方面的第一种可能实现方式中，所述对接收信号进行采样，以获取采样信号，包括：
根据指定的采样速率对接收信号进行采样，以获取采样信号。
结合第二方面以及第二方面的第一种可能实现方式，在第二种可能实现方式中，所述根据指定的采样速率对接收信号进行采样，包括：
生成指定周期的时钟信号，所述指定周期等于采样速率的倒数；
根据所述时钟信号对接收信号进行采样。
结合第二方面以及第二方面的第一种可能实现方式，在第三种可能实现方式中，所述采样速率大于两倍的所述接收信号的带宽。
结合第二方面以及第三种可能实现方式，在第四种可能实现方式中，所述采样速率达到GHz量级。
结合第二方面以及第二方面的第一至第四种中任意一种可能实现方式，在第五种可能实现方式中，所述对所述采样信号进行时频转换，以获取模拟频域信号，包括：
通过快速傅氏变换对所述采样信号进行时频转换，以获取多个中心频点不 同的模拟频域信号。
结合第二方面以及第二方面的第五种可能实现方式，在第六种可能实现方式中，所述采样速率和所述快速傅氏变换的点数是根据公式
Figure PCTCN2015074947-appb-000002
确定的，其中，所述fs表示所述采样速率，所述N表示所述快速傅氏变换的点数，所述N＝2n，所述n为大于1的整数，所述f0表示所述接收信号的中心频率，所述x表示任意自然数，所述B表示所述接收信号的带宽。
结合第二方面以及第二方面的第五种可能实现方式，在第七种可能实现方式中，所述对所述模拟频域信号进行筛选，以获取模拟基带信号，包括：
筛选出中心频点最小的一个模拟频域信号作为所述模拟基带信号。
结合第二方面的可能实现方式，在第八种可能实现方式中，所述对接收信号进行采样，以获取采样信号之前，还包括：
接收射频信号；对所述射频信号进行滤波；对滤波后的射频信号进行放大以获取所述接收信号。
本发明实施例第三方面提供了一种计算机存储介质，所述计算机存储介质存储有程序，该程序执行时包括第一方面提供的一种信号处理的方法的部分或全部步骤。
本发明实施例第四方面提供了一种接收机，包括：天线接口、存储器以及处理器，其中，存储器中存储一组程序，且处理器用于调用存储器中存储的程序，执行以下操作：
对接收信号进行采样，以获取采样信号；
对所述采样信号进行时频转换，以获取模拟频域信号；
对所述模拟频域信号进行筛选，以获取模拟基带信号；
对所述模拟基带信号进行模数转换，以获取数字基带信号。
由上可见，本发明实施例提供的接收机，通过高速采样模块对接收信号进行采样以获取采样信号，再通过AFFT模块对采样信号进行时频转换以获取模 拟频域信号，最后通过低速ADC模块将模拟频域信号转换为数字基带信号，从而实现接收机的功能，其中，由于本发明实施例提供的接收机未使用传统的接收机中的混频器或I/Q解调器，故工作带宽不会受限于混频器或I/Q解调器的通道带宽，高速采样模块和AFFT模块的通道带宽均可达到GHz量级，进而接收机的工作带宽可达到GHz量级；由于经快速傅氏变换后得到的模拟频域信号的中心频点不高，故对模数变换的采样带宽要求不高(应理解地，采样带宽等于中心频点即可)，可以避免使用高速ADC，因而本发明实施例的接收机还具有成本低和复杂度低的优点。
附图说明
为了更清楚地说明本发明实施例，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种接收机的结构示意图；
图2是本发明实施例提供的另一种接收机的结构示意图；
图3是本发明实施例提供的一种信号处理的方法的流程示意图；
图4是本发明实施例提供的又一种接收机的结构示意图；
图5是本发明实施例提供的一种现有的接收机的结构示意图；
图6是本发明实施例提供的一种采样信号的仿真示意图；
图7是本发明实施例提供的一种模拟频域信号的仿真示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供的接收机可以应用于各种通信系统，例如：全球移动通讯(Global System of Mobile communication，简称为“GSM”)系统、码分多 址(Code Division Multiple Access，简称为“CDMA”)系统、宽带码分多址(Wideband Code Division Multiple Access，简称为“WCDMA”)系统、通用分组无线业务(General Packet Radio Service，简称为“GPRS”)、长期演进(Long Term Evolution，简称为“LTE”)系统、LTE频分双工(Frequency Division Duplex，简称为“FDD”)系统、LTE时分双工(Time Division Duplex，简称为“TDD”)、通用移动通信系统(Universal Mobile Telecommunication System，简称为“UMTS”)、全球互联微波接入(Worldwide Interoperability for Microwave Access，简称为“WiMAX”)通信系统或未来演进的PLMN(Public Land Mobile Network，公共陆地移动网络)通信系统(简称为“5G网络”)等。
应理解地，接收机的主要功能是将陆地、海洋或空中的射频信号转换为数字基带信号，以使后续的处理装置从该数字基带信号中解调出有用信号，如数据信息或语音信息等。其中，本发明实施例提供的接收机，可以内置于各种接收设备，所述接收设备包括但不限于用户设备(User Equipment，简称为“UE”)、移动台(Mobile Station，简称为“MS”)、GSM或CDMA中的基站(Base Transceiver Station，简称为“BTS”)、WCDMA中的基站(NodeB，简称为“NB”)、LTE中的演进型基站(Evolutional Node B，简称为“eNB”)或5G网络中的基站。
图1是本发明实施例中一种接收机的结构示意图。如图所示本发明实施例中的接收机至少可以包括高速采样模块110、模拟快速傅氏变换AFFT(Analog Fast Fourier Transform)模块120、选择开关模块130、低速模数转换ADC(Analog to Digital Converter)模块140以及控制模块150，其中：
高速采样模块110与AFFT模块120连接，AFFT模块120与选择开关模块130连接，选择开关模块130与低速ADC模块140连接，控制模块150分别与高速采样模块110、AFFT模块120、选择开关模块130和低速ADC模块140连接。
高速采样模块110用于对接收信号进行采样，并输出采样信号至AFFT模块120。其中，接收信号可以是天线接收到的射频信号，也可以是进一步经过滤波或放大的射频信号。
具体实现过程中，高速采样模块110包括1个输入端口和M个输出端口，M为大于2的整数，高速采样模块110根据配置的采样速率将输入端口依次切换连接到各个输出端口，以对接收信号进行采样，并将得到的采样信号输出至AFFT模块120。应理解地，由于输入端口是依次切换连接到各个输出端口的，因此M个输出端口只能周期性地获取接收信号，相当于对接收信号进行了采样，切换连接的速率越快，其采样速率越快。进一步地，本发明实施例将M个输出端口所输出的信号统称为采样信号。
需要指出的是，上述采样速率是由控制模块150配置并下发的。另外，输入端口依次切换连接到的输出端口可以是所有的输出端口，也可以是M个输出端口的一部分，可选地，输入端口依次切换连接到的输出端口的数目也是由控制模块150配置并下发的。
又可选地，如图1所示的接收机还包括时钟模块160，控制模块150通过时钟模块160与高速采样模块110连接，具体实现过程中，时钟模块160向高速采样模块110发送指定周期的时钟信号，其中指定周期等于采样速率的倒数，采样速率由控制模块150配置并下发到时钟模块160；高速采样模块110根据时钟信号将输入端口依次切换连接到各个输出端口。
进一步地，上文提到的采样速率应大于两倍的接收信号的带宽，以满足带通采样定律。并且，本发明实施例中，采样速率的上限值不低于6GHz，即至少可支持6GHz的带宽，其中，6GHz为5G网络的核心频点。还应理解地，高速采样模块110仅用于采样，因而硬件结构简单，故即使将其采样速率增大到GHz量级(本发明实施例中的“GHz量级”是指“大于1GHz的频量”，如6GHz等，后文不再赘述)，成本和复杂度也不会有明显增加；而ADC模块不仅用于采样还用于模数转换，因而硬件结构(例如电路结构)远远复杂于高速采样模块110，导致增大ADC模块的采样频率会使成本和复杂度明显增加，故本发明实施例选择高速采样模块110来对接收信号进行采样，具有成本低和复杂度低的优点。
AFFT模块120用于对采样信号进行时频转换，并输出模拟频域信号至选择开关模块130。
具体实现过程中，AFFT模块120包括M个输入端口和M个输出端口， AFFT模块120的M个输入端口分别与高速采样模块110的M个输出端口连接，AFFT模块120通过配置的快速傅氏变换的点数对其输入端口输入的采样信号进行时频转换，并将时频转换得到的模拟频域信号通过其输出端口输出至选择开关模块，其中，模拟频域信号是指频域(Frequency)的模拟信号(Analog signal)。更具体地，应保持一致地，当高速采样模块110的各个输出端口周期性地对接收信号进行采样并输出采样信号时，AFFT模块120的各个输入端口也周期性地接收采样信号，并分别在每个周期内对多个输入端口接收到的采样信号进行时频转换。应理解地，本发明实施例中的时频转换为快速傅氏变换(FFT，Fast Fourier Transform)，例如，假设输入的采样信号的向量表达式为X＝[x1(t),x2(t),x3(t),......,xN(t)]，其中，xN(t)为AFFT模块120的输入端口N输入的时域信号，N＝2n，n为大于1的整数，且N不大于M，X通过快速傅氏变换后，得到的向量为Y＝[y1(n),y2(n),y3(n),......,yN(n)]，其中yN(n)为AFFT模块120的输入端口N输出的频域信号。由于上述过程全为线性变换，因此不会对接收机的动态范围造成损失，其中动态范围是指接收机对接收信号检测而又使接收信号不失真的输入信号大小范围，动态范围过大会产生噪声，过小则无法检测到。
需要指出的是，上述快速傅氏变换的点数是由控制模块150配置并下发的，确保AFFT模块120获取正确的采样信号和输出正确的模拟频域信号。例如，假设M＝10，配置的N＝23＝8，则AFFT模块120只通过第1至第8个输入端口接收采样信号，并通过第1至第8个输出端口输出模拟频域信号，AFFT模块120的剩余2个输入端口不接收的采样信号，其中，可以不接收采样信号的原因在于：接收信号具有连续性的特点，当采样点总量足够时，舍弃部分采样点也不会对整个接收机的输出结果造成太大影响。
本发明实施例中的AFFT模块120用于实现快速傅氏变换，具有结构简单和成本低的特点。另外，AFFT模块120的通道带宽可以达到GHz量级。
本发明实施例中的接收机，未使用传统的接收机中的混频器或I/Q解调器，克服了工作带宽受限于混频器或I/Q解调器的问题，同时，高速采样模块110和AFFT模块120的通道带宽均可达到GHz量级，进而接收机的工作带宽可达到GHz量级。另外，由于混频器固有的相噪会导致接收信号的质量下降， 需增加降噪电路进行降噪处理，使得架构复杂、硬件面积大；由于I/Q解调器固有的载波泄露和直流不平衡泄露等问题会导致动态范围损失，需要增加防泄电路进行防泄处理，也使得架构复杂、硬件面积大；而高速采样模块110和AFFT模块120无需进行降噪处理和防泄处理，可以简化接收机的架构，减少硬件面积。
选择开关模块130用于将模拟频域信号传送至低速ADC模块140。
具体实现过程中，选择开关模块130包括M个输入端口和1个输出端口，选择开关模块的M个输入端口分别与AFFT模块120的M个输出端口连接，选择开关模块130通过配置的目标输入端口接收模拟频域信号，并通过输出端口将模拟频域信号传送至低速ADC模块，其中目标输入端口为选择开关模块130的M个输入端口的其中一个。
需要指出的是，上述目标输入端口的端口号是由控制模块150配置并下发的，确保低速ADC模块140获取到最佳的模拟频域信号。所述最佳的模拟频域信号为中心频点最小的模拟频域信号，具体地，AFFT模块120对采样信号进行快速傅氏变换后，得到N个中心频点不同的模拟频域信号输出，而模拟频域信号的中心频点越小，低速ADC模块140的采样带宽(模数转换器的采样带宽为完成模数转换的工作带宽)越小，进而低速ADC模块140的成本和复杂度越低，故选择开关模块130需根据配置的目标输入端口接收中心频点最小的模拟频域信号，例如：AFFT模块120输出的N个模拟频域信号中，其中一个模拟频域信号的中心频点为零(即零中频信号，零中频信号的中心频点是最小的)，假设该模拟频域信号从AFFT模块120的第2个输出端口输出至选择开关模块130的第2个输入端口，那么配置的目标输入端口即为选择开关模块130的第2个输入端口，选择开关模块130通过目标输入端口接收该模拟频域信号并传送至低速ADC模块140。
需要进一步说明的是，AFFT模块120输出的N个模拟频域信号均携带有完整的有用信息(数据信息或语音信息)，故只需选择一个最佳的模拟频域信号传送至低速ADC模块140即可，舍弃其它的模拟频域信号。下面简单介绍下，AFFT模块120输出的N个模拟频域信号均携带有完整的有用信息的原因：AFFT模块120的第1至第N个输入端口接收的采样信号，实质上是N个采样 脉冲，每个采样脉冲由基波和谐波组成，为了便于理解，我们把每个采样脉冲的基波和谐波用信号形式表达，例如第k个采样信号可用x(k)＝a(k)+j*b(k)表达；设AFFT模块120进行傅氏变换的公式如下，
Figure PCTCN2015074947-appb-000003
那么AFFT模块120的第n个输出端口输出的模拟频域信号为Y(n)，显然Y(n)包括x(1)至x(N)，即Y(n)包括a(1)+j*b(1)至a(N)+j*b(N)，也就是说，AFFT模块120的任意一个输出端口输出的模拟频域信号都携带有AFFT模块120的第1至第N个输入端口接收的采样脉冲的基波和谐波，例如：令N＝8且n＝1，也就是AFFT模块有8个输入和输出端口，其第1个输出端口输出的模拟频域信号为
Figure PCTCN2015074947-appb-000004
可见第1个输出端口输出的模拟频域信号携带有8个输入端口的采样脉冲的基波和谐波。因此，不难得出，AFFT模块120输出的N个模拟频域信号均携带有完整的有用信息。为了验证上述推断的准确性，本发明实施例对AFFT模块120的输入和输出进行了仿真，请参阅图6，图6中的脉冲信号即为AFFT模块120的输入端口接收的采样脉冲，可见每个采样脉冲由基波和谐波组成，请参阅图7，图7中的信号即为AFFT模块120的第1个输出端口输出的模拟频域信号，可见该模拟信号携带有所有输入端口接收的采样脉冲的信息。
还需要指出的是，AFFT模块120对采样信号进行快速傅氏变换后，得到N个中心频点不同的模拟频域信号，其中至少存在一个模拟频域信号的中心频点要低于原接收信号的中心频点，由于选择开关模块130选取接收了其中最小中心频点的模拟频域信号，故该模拟频域信号的中心频点必定低于原接收信号的中心频点，可见AFFT模块120和选择开关模块130对原接收信号实现了频谱的搬移，该模拟频域信号即为模拟基带信号。应理解地，传统的接收机中的混频器和I/Q解调器，其作用分别为混频和变频，目的也是为了实现对频谱搬移，因此，本发明实施例中的高速采样模块110、AFFT模块120和选择开关模块130三者可替代传统的接收机中的混频器或I/Q解调器，这也是本接收机未使用混频器或I/Q解调器的原因。特别地，本发明实施例提供的基于AFFT来实现变频或频谱搬移，可以大大简化接收机的复杂度，降低成本。
低速ADC模块140用于将模拟频域信号转换为数字基带信号。
进一步地，转换后的数字信号分为实部I(t)和虚部Q(t)输出，送入后续的处理装置，处理装置从该数字基带信号中解调出有用信号，如数据信息或语音信息等。
本发明实施例，通过使用AFFT模块120对采样信号进行时频转换，可以将采样信号由时域转换到频域，由于对频域的信号处理速度快于时域的信号，故提升了接收机的工作速率；另外，时频转换过程还对采样信号进行了频谱搬移，得到多个中心频点不同的模拟频域信号，并通过选择开关模块130从多个模拟频域信号中选出中心频点最低的模拟频域信号，而中心频点低的模拟频域信号对模数变换的采样带宽要求不高(应理解地，采样带宽等于中心频点即可)，可以避免使用高速ADC。可选地，本发明实施例中的低速ADC模块140的采样带宽低于2GHz，2GHz可以认为是一个临界值，超过2GHz，ADC的成本和复杂度会很高。
控制模块150用于配置高速采样模块110的采样速率、AFFT模块120进行时频转换所用的快速傅氏变换的点数和选择开关模块130的目标输入端口。
具体实现过程中，控制模块150根据公式(1)
Figure PCTCN2015074947-appb-000005
配置高速采样模块110的采样速率和AFFT模块120进行时频转换所用的快速傅氏变换的点数，其中，所述fs表示所述采样速率，所述N表示所述快速傅氏变换的点数，所述N＝2n，所述n为大于1的整数，且所述N不大于所述M，所述f0表示所述接收信号的中心频率，所述x表示任意自然数，所述B表示所述接收信号的带宽。需要说明的是，式中“N＝1/(f0/fs-x)”的表示：接收信号的中心频率必须在第x个奈奎斯特域，且在快速傅氏变换的第N点上，以确保快速傅氏变换的准确性；式中“fs＞B”的表示：采样速率必须大于接收信号的带宽。
上述公式(1)中，f0和B为系统预配置的参数，默认为控制模块150已知的，fs、N和x为未知的。控制模块150通过公式(1)中的一个等式和不等式，求出未知的fs、N和x。进一步地，若求出的fs、N和x有多组结果，则取fs最小的一组结果，原因在于，在fs＞B的条件下，fs越小，高速 采样模块110的复杂度越小，越容易实现。
控制模块150再根据公式(2)
Bin＝(f0-fs*x)/(fs/N)    (2)
配置选择开关模块130的目标输入端口，其中，所述Bin表示目标输入端口的端口号。需要指出的是，本发明实施例预先标识了选择开关模块130的输入端口的端口号，例如：分别使用第1至第N端口号预先标识选择开关模块130的第1至第N个输入端口。还需说明的是，根据公式(2)所求得的端口号，其对应接收到的模拟频域信号的中心频点相对其它端口是最小的。
例如，f0＝1.9GHz，B＝40MHz，则求得的fs＝0.304GHz，N＝1，x＝6，Bin＝1。又如，f0＝2.25GHz，B＝1GHz，则求得的fs＝1.5GHz，N＝2，x＝1，Bin＝1。
进一步地，控制模块150再将fs配置到高速采样模块110，或时钟模块160；将N点快速傅氏变换配置到AFFT模块120；将Bin配置到选择开关模块130。
由上可见，本发明实施例提供的接收机，通过高速采样模块对接收信号进行采样以获取采样信号，再通过AFFT模块对采样信号进行时频转换以获取模拟频域信号，最后通过低速ADC模块将模拟频域信号转换为数字基带信号，从而实现接收机的功能，其中，由于本发明实施例提供的接收机未使用传统的接收机中的混频器或I/Q解调器，故工作带宽不会受限于混频器或I/Q解调器的通道带宽，高速采样模块和AFFT模块的通道带宽均可达到GHz量级，进而接收机的工作带宽可达到GHz量级；由于经快速傅氏变换后得到的模拟频域信号的中心频点不高，故对模数变换的采样带宽要求不高(应理解地，采样带宽等于中心频点即可)，可以避免使用高速ADC，因而本发明实施例的接收机还具有成本低和复杂度低的优点。
图2是本发明实施例中另一种接收机的结构示意图。如图所示本发明实施例中的接收机至少包括高速采样模块110、模拟快速傅氏变换AFFT模块120、选择开关模块130、低速模数转换ADC模块140、控制模块150、时钟模块160接收天线170、滤波模块180以及低噪声放大器LNA(Low Noise Amplifier) 模块190，其中：
接收天线170与滤波模块180连接，滤波模块180与LNA模块190连接，LNA模块190与高速采样模块110连接，高速采样模块110与AFFT模块120连接，AFFT模块120与选择开关模块130连接，选择开关模块130与低速ADC模块140连接，控制模块150分别与高速采样模块110、AFFT模块120、选择开关模块130和低速ADC模块140连接，进一步地，控制模块150通过时钟模块160与高速采样模块110连接。
接收天线170用于接收陆地、海洋或空中的射频信号。
滤波模块180用于对射频信号进行滤波。目的是滤除杂波或干扰信号等无用信号。本发明实施例中，滤波模块180是带通滤波器。
LNA模块190用于对滤波后的射频信号进行放大以得到接收信号，即将射频信号放大为可检测的电平。可选地，LNA模块190具体可以是增益LNA电路。
具体实现中，当接收天线170接收的射频信号是连续宽带信号时，滤波模块180保持输出的滤波后的射频信号的带宽为B，LNA模块190的通道带宽大于B，LNA模块190将滤波后的射频信号的电平放大为高速采样模块110可以检测到的电平，放大后的信号为接收信号。
高速采样模块110用于对接收信号进行采样，并输出采样信号至AFFT模块120。
时钟模块160用于向高速采样模块110发送指定周期的时钟信号，其中指定周期等于采样速率的倒数，采样速率由控制模块150配置并下发到时钟模块160。相应地，高速采样模块110根据时钟信号将输入端口依次切换连接到各个输出端口。
AFFT模块120用于对采样信号进行时频转换，并输出模拟频域信号至选择开关模块130。
选择开关模块130用于将模拟频域信号传送至低速ADC模块140。
低速ADC模块140用于将模拟频域信号转换为数字基带信号。
控制模块150用于配置高速采样模块110的采样速率、AFFT模块120进行时频转换所用的快速傅氏变换的点数和选择开关模块130的目标输入端口。
综上所述，本发明实施例提供的接收机的信号流走向可归纳为：①模拟射频信号→②模拟采样信号→③模拟频域信号→④模拟基带信号→⑤数字基带信号。可见，本接收机的信号处理集中在模拟域(即①至④都是模拟域)，本发明实施例示出的接收机可以主要工作在模拟域，实现将射频信号转换成数字基带信号。
本发明实施例提供的接收机，通过高速采样模块对接收信号进行采样以获取采样信号，再通过AFFT模块对采样信号进行时频转换以获取模拟频域信号，最后通过低速ADC模块将模拟频域信号转换为数字基带信号，从而实现接收机的功能，其中，由于本发明实施例提供的接收机未使用传统的接收机中的混频器或I/Q解调器，故工作带宽不会受限于混频器或I/Q解调器的通道带宽，高速采样模块和AFFT模块的通道带宽均可达到GHz量级，进而接收机的工作带宽可达到GHz量级；由于经快速傅氏变换后得到的模拟频域信号的中心频点不高，故对模数变换的采样带宽要求不高(应理解地，采样带宽等于中心频点即可)，可以避免使用高速ADC，因而本发明实施例的接收机还具有成本低和复杂度低的优点。
图3是本发明实施例中一种信号处理的方法的流程示意图，可以包括：
S101，对接收信号进行采样，以获取采样信号。
具体地，接收机根据指定的采样速率对接收信号进行采样，以获取采样信号，其中，接收信号可以是天线接收到的射频信号，也可以是进一步经过滤波或放大的射频信号。
可选地，接收机先生成指定周期的时钟信号，指定周期等于采样速率的倒数；再根据时钟信号对接收信号进行采样。
进一步地，上文提到的采样速率应大于两倍的接收信号的带宽，以满足带通采样定律。并且，本发明实施例中，采样速率的上限值不低于6GHz，即至少可支持6GHz的带宽。
更进一步地，采样速率是根据公式(1)确定的，其中，所述fs表示所述采样速率，所述N表示所述快速傅氏变换的点数，所述N＝2n，所述n为大于1的整数，所述f0表示所述接收信号的中心频率，所述x表示任意自然数，所 述B表示所述接收信号的带宽。
又可选地，在对接收信号进行采样之前，接收机接收射频信号；对射频信号进行滤波；对滤波后的射频信号进行放大以获取接收信号。
S102，对所述采样信号进行时频转换，以获取模拟频域信号。
具体地，接收机通过快速傅氏变换对采样信号进行时频转换，以获取多个中心频点不同的模拟频域信号。
应理解地，本发明实施例中的时频转换为快速傅氏变换，由于该过程为线性变换，因此不会对接收机的动态范围造成损失，其中动态范围是指接收机对接收信号检测而又使接收信号不失真的输入信号大小范围，动态范围过大会产生失真和噪声，过小则无法检测到。
进一步地，快速傅氏变换的点数也是根据公式(1)确定的。
S103，对所述模拟频域信号进行筛选，以获取模拟基带信号。
具体地，接收机筛选出中心频点最小的一个模拟频域信号作为所述模拟基带信号。
需要指出的是，步骤S102得到的多个模拟频域信号均携带有完整的有用信息(数据信息或语音信息)，故只需选择一个最佳的模拟频域信号作为模拟基带信号即可，可以舍弃其它的模拟频域信号。多个模拟频域信号均携带有完整的有用信息的原因上文已经介绍过，这里不再赘述。
还需要指出的是，从多个模拟频域信号中筛选出的模拟基带信号的中心频点要低于原接收信号的中心频点，进一步地，筛选出的模拟基带信号的中心频点可以是零频点，可见本接收机对原接收信号实现了频谱的搬移。
S104，对所述模拟基带信号进行模数转换，以获取数字基带信号。
进一步地，转换后的数字信号分为实部I(t)和虚部Q(t)输出，送入后续的处理装置，处理装置从该数字基带信号中解调出有用信号，如数据信息或语音信息等。
图4是本发明实施例中的另一种接收机的结构示意图，如图4所示，该接收机可以包括：至少一个处理器401，例如CPU，至少一个天线接口403，存储器404，至少一个通信总线402。其中，通信总线402用于实现这些组件之间的连 接通信。其中，本发明实施例中的天线接口403用于接收射频信号。存储器404可以是高速RAM存储器，也可以是非易失的存储器(non-volatile memory)，例如至少一个磁盘存储器。可选的，存储器404还可以是至少一个位于远离前述处理器401的存储装置。存储器404中存储一组程序代码，且处理器401用于调用存储器404中存储的程序代码，执行以下操作：
对接收信号进行采样，以获取采样信号；
对所述采样信号进行时频转换，以获取模拟频域信号；
对所述模拟频域信号进行筛选，以获取模拟基带信号；
对所述模拟基带信号进行模数转换，以获取数字基带信号。
可选地，处理器401对接收信号进行采样，以获取采样信号的具体操作为：
根据指定的采样速率对接收信号进行采样，以获取采样信号。
进一步地，处理器401根据指定的采样速率对接收信号进行采样的具体操作为：
生成指定周期的时钟信号，所述指定周期等于采样速率的倒数；
根据所述时钟信号对接收信号进行采样。
可选地，所述采样速率大于两倍的所述接收信号的带宽。
进一步地，所述采样速率达到GHz量级。
可选地，处理器401对所述采样信号进行时频转换，以获取模拟频域信号的具体操作还可以为：
通过快速傅氏变换对所述采样信号进行时频转换，以获取多个中心频点不同的模拟频域信号。
相应地，所述采样速率和所述快速傅氏变换的点数是根据公式
Figure PCTCN2015074947-appb-000006
确定的，其中，所述fs表示所述采样速率，所述N表示所述快速傅氏变换的点数，所述N＝2n，所述n为大于1的整数，所述f0表示所述接收信号的中心频率，所述x表示任意自然数，所述B表示所述接收信号的带宽。
可选地，处理器401对所述模拟频域信号进行筛选，以获取模拟基带信号的具体操作为：
筛选出中心频点最小的一个模拟频域信号作为所述模拟基带信号
又可选地，处理器401对接收信号进行采样，以获取采样信号之前，还执行：
接收射频信号；对所述射频信号进行滤波；对滤波后的射频信号进行放大以获取所述接收信号。
本发明实施例还提出了一种计算机存储介质，所述计算机存储介质存储有程序，所述程序包括若干指令用以执行本发明实施例图1-图2所描述的一种信号处理的方法中的部分或全部的步骤。
由上可见，本发明实施例提供的接收机，通过高速采样模块对接收信号进行采样以获取采样信号，再通过AFFT模块对采样信号进行时频转换以获取模拟频域信号，最后通过低速ADC模块将模拟频域信号转换为数字基带信号，从而实现接收机的功能，其中，由于本发明实施例提供的接收机未使用传统的接收机中的混频器或I/Q解调器，故工作带宽不会受限于混频器或I/Q解调器的通道带宽，高速采样模块和AFFT模块的通道带宽均可达到GHz量级，进而接收机的工作带宽可达到GHz量级；由于经快速傅氏变换后得到的模拟频域信号的中心频点不高，故对模数变换的采样带宽要求不高(应理解地，采样带宽等于中心频点即可)，可以避免使用高速ADC，因而本发明实施例的接收机还具有成本低和复杂度低的优点。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (21)

  1. 一种接收机，其特征在于，所述接收机包括高速采样模块、模拟快速傅氏变换AFFT模块、选择开关模块、低速模数转换ADC模块以及控制模块，其中：
    所述高速采样模块与所述AFFT模块连接，所述AFFT模块与所述选择开关模块连接，所述选择开关模块与所述低速ADC模块连接，所述控制模块分别与所述高速采样模块、所述AFFT模块、所述选择开关模块和所述低速ADC模块连接；
    所述高速采样模块用于对接收信号进行采样，并输出采样信号至所述AFFT模块，所述AFFT模块用于对所述采样信号进行时频转换，并输出模拟频域信号至所述选择开关模块，所述选择开关模块用于将所述模拟频域信号传送至所述低速ADC模块，所述低速ADC模块用于将所述模拟频域信号转换为数字基带信号，所述控制模块用于配置所述高速采样模块的采样速率、所述AFFT模块进行时频转换所用的快速傅氏变换的点数和所述选择开关模块的目标输入端口。
  2. 如权利要求1所述的接收机，其特征在于，所述高速采样模块包括1个输入端口和M个输出端口，所述M为大于2的整数，
    所述高速采样模块，具体用于根据配置的所述采样速率将所述输入端口依次切换连接到各个所述输出端口，以对所述接收信号进行采样，并将得到的所述采样信号输出至所述AFFT模块。
  3. 如权利要求2所述的接收机，其特征在于，所述接收机还包括时钟模块，所述控制模块通过所述时钟模块与所述高速采样模块连接，
    所述时钟模块，用于向所述高速采样模块发送指定周期的时钟信号，所述指定周期等于所述采样速率的倒数；
    所述高速采样模块，具体用于根据所述时钟信号将所述输入端口依次切换连接到各个所述输出端口。
  4. 如权利要求2所述的接收机，其特征在于，所述采样速率大于两倍的所述接收信号的带宽。
  5. 如权利要求4所述的接收机，其特征在于，所述采样速率达到GHz量级。
  6. 如权利要求2-5任一项所述的接收机，其特征在于，所述AFFT模块包括M个输入端口和M个输出端口，所述AFFT模块的M个输入端口分别与所述高速采样模块的M个输出端口连接，
    所述AFFT模块，具体用于通过所述快速傅氏变换对所述输入端口输入的所述采样信号进行时频转换，并将时频转换得到的所述模拟频域信号通过所述输出端口输出至所述选择开关模块。
  7. 如权利要求6所述的接收机，其特征在于，所述选择开关模块包括M个输入端口和1个输出端口，所述选择开关模块的目标输入端口为所述M个输入端口的其中一个，所述选择开关模块的M个输入端口分别与所述AFFT模块的M个输出端口连接，所述选择开关模块，具体用于通过配置的所述目标输入端口接收所述模拟频域信号，并通过所述输出端口将所述模拟频域信号传送至所述低速ADC模块。
  8. 如权利要求1所述的接收机，其特征在于，所述低速ADC模块的采样带宽不高于2GHz。
  9. 如权利要求7所述的接收机，其特征在于，所述控制模块，具体用于根据公式
    Figure PCTCN2015074947-appb-100001
    配置所述高速采样模块的采样速率和所述AFFT模块进行时频转换所用的快速傅氏变换的点数，其中，所述fs表示所述采样速率，所述N表示所述快速傅氏变换的点数，所述N＝2n，所述n为大于1的整数，且所述N不大于 所述M，所述f0表示所述接收信号的中心频率，所述x表示任意自然数，所述B表示所述接收信号的带宽；所述控制模块，还具体用于根据公式
    Bin＝(f0-fs*x)/(fs/N)
    配置所述选择开关模块的所述目标输入端口，其中，所述Bin表示所述目标输入端口的端口号。
  10. 如权利要求1所述的接收机，其特征在于，所述接收机还包括接收天线、滤波模块和增益低噪声放大器LNA模块，其中：
    所述接收天线与所述滤波模块连接，所述滤波模块与所述增益LNA模块连接，所述增益LNA模块与所述高速采样模块连接，所述接收天线用于接收射频信号，所述滤波模块用于对所述射频信号进行滤波，所述增益LNA模块用于对滤波后的射频信号进行放大以得到所述接收信号。
  11. 一种数字基带信号的获取方法，其特征在于，所述方法包括：
    对接收信号进行采样，以获取采样信号；
    对所述采样信号进行时频转换，以获取模拟频域信号；
    对所述模拟频域信号进行筛选，以获取模拟基带信号；
    对所述模拟基带信号进行模数转换，以获取数字基带信号。
  12. 如权利要求11所述的方法，其特征在于，所述对接收信号进行采样，以获取采样信号，包括：根据指定的采样速率对接收信号进行采样，以获取采样信号。
  13. 如权利要求12所述的方法，其特征在于，所述根据指定的采样速率对接收信号进行采样，包括：
    生成指定周期的时钟信号，所述指定周期等于采样速率的倒数；
    根据所述时钟信号对接收信号进行采样。
  14. 如权利要求12所述的方法，其特征在于，所述采样速率大于两倍的所述接收信号的带宽。
  15. 如权利要求14所述的方法，其特征在于，所述采样速率达到GHz量级。
  16. 如权利要求12-15任一项所述的方法，其特征在于，所述对所述采样信号进行时频转换，以获取模拟频域信号，包括：通过快速傅氏变换对所述采样信号进行时频转换，以获取多个中心频点不同的模拟频域信号。
  17. 如权利要求16所述的方法，其特征在于，所述采样速率和所述快速傅氏变换的点数是根据公式
    Figure PCTCN2015074947-appb-100002
    确定的，其中，所述fs表示所述采样速率，所述N表示所述快速傅氏变换的点数，所述N＝2n，所述n为大于1的整数，所述f0表示所述接收信号的中心频率，所述x表示任意自然数，所述B表示所述接收信号的带宽。
  18. 如权利要求16所述的方法，其特征在于，所述对所述模拟频域信号进行筛选，以获取模拟基带信号，包括：
    筛选出中心频点最小的一个模拟频域信号作为所述模拟基带信号。
  19. 如权利要求11至18任一项所述的方法，其特征在于，
    所述对所述采样信号进行时频转换通过模拟快速傅氏变换AFFT来实现。
  20. 如权利要求11所述的方法，其特征在于，所述对接收信号进行采样，以获取采样信号之前，还包括：
    接收射频信号；对所述射频信号进行滤波；对滤波后的射频信号进行放大以获取所述接收信号。
  21. 一种计算机存储介质，其特征在于，所述计算机存储介质存储有程序，所述程序执行时包括权利要求11至19中任一项所述的步骤。
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