WO2016141613A1 - 一种芯片引脚复用的方法及系统 - Google Patents

一种芯片引脚复用的方法及系统 Download PDF

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Publication number
WO2016141613A1
WO2016141613A1 PCT/CN2015/075763 CN2015075763W WO2016141613A1 WO 2016141613 A1 WO2016141613 A1 WO 2016141613A1 CN 2015075763 W CN2015075763 W CN 2015075763W WO 2016141613 A1 WO2016141613 A1 WO 2016141613A1
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WIPO (PCT)
Prior art keywords
pin
timing control
control board
partition
board
Prior art date
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PCT/CN2015/075763
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English (en)
French (fr)
Inventor
吴宇
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/654,845 priority Critical patent/US20160313782A1/en
Publication of WO2016141613A1 publication Critical patent/WO2016141613A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21012—Configurable I-O
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
    • H04N13/106—Processing image signals
    • H04N13/167—Synchronising or controlling image signals

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method and system for chip pin multiplexing.
  • the movement board of the ultra-high-definition model has a signal of one partition and two partitions.
  • the timing control board needs to add a pin to select the data of one partition or two partitions. Mapping, so that the movement boards of different partition types can share the same timing control board.
  • the control pin When the movement board is in a partition mode, the control pin is set to H, and the timing control board detects the control.
  • Pin state when the control pin state is detected as H, the receiving mode of the timing control board is set to a partition; when the movement board is in the second partition mode, the synchronization will be control
  • the pin is set to L, and the timing control board detects the state of the control pin when the control is detected.
  • the receiving mode of the timing control board is set to two partitions; thus, the movement board and the timing control board are correspondingly matched.
  • the timing control board needs to add a pin to perform corresponding control, which increases the area of the timing control board, which is disadvantageous for reducing the cost, and occupies the timing control board and the machine.
  • the interface of the core board connects to a limited pin resource.
  • the object of the present invention is to provide a method and system for chip pin multiplexing, which aims to solve the movement board which is compatible with different partition types in the prior art, and the timing control board needs to add a pin to perform corresponding control.
  • This increases the area of the timing control board, which is disadvantageous for reducing the cost, and occupies the problem of limited pin resources of the interface between the timing control board and the movement board.
  • a method for chip pin multiplexing wherein the method is applied to a timing control board, and a partition of a core board is selected by a preset idle pin on the timing control board; wherein the pre- The pin that is idle at startup is set as a pin for the partition setting; the method includes:
  • the timing control board detects the state of the idle pin within the preset time after the timing control board is started
  • the timing control board sets the receiving mode to the receiving mode of the corresponding partition of the movement board
  • the step of setting the receiving mode to the receiving mode of the corresponding partition of the movement board according to the detected state specifically includes:
  • the timing control board When detecting that the state of the idle pin is a high level signal, the timing control board sets the receiving mode to a receiving mode of the partition of the movement board;
  • the timing control board sets the receiving mode to the receiving mode of the second partition of the movement board.
  • the free pin is a synchronous signal pin of the 3D mode.
  • a method for chip pin multiplexing the method being applied to a timing control board, wherein a partition of a movement board is selected by a preset idle pin on the timing control board; wherein the preset The idle pin at startup is the pin for the partition setting; the method includes:
  • the timing board detects the state of the idle pin
  • the timing control board sets the receiving mode to the receiving mode of the corresponding partition of the movement board.
  • the step of receiving the partition type sent by the movement board comprises:
  • the step of setting the corresponding state of the idle pin at the startup according to the partition type includes:
  • the step of the timing board detecting the state of the idle pin includes:
  • the timing control board detects the state of the idle pin within the preset time after the timing control board is activated.
  • the step of setting the receiving mode to the receiving mode of the corresponding partition of the movement board according to the detected state specifically includes:
  • the timing control board When detecting that the state of the idle pin is a high level signal, the timing control board sets the receiving mode to a receiving mode of the partition of the movement board;
  • the timing control board sets the receiving mode to the receiving mode of the second partition of the movement board.
  • the method further includes:
  • the idle pin is a sync signal pin of the 3D mode.
  • a chip pin multiplexing system wherein the system is applied to a timing control board, and a partition of a movement board is selected by a preset idle pin on the timing control board; wherein the preset The idle pin at startup is the pin for the partition setting; the system includes:
  • a receiving module configured to receive a partition type sent by the movement board after the timing control board is started
  • a setting module configured to set, according to the partition type, a corresponding state of the pin that is idle at startup;
  • a detecting module configured to detect the state of the idle pin
  • a partition setting module configured to set a receiving manner of the timing control board to a receiving manner of a corresponding partition of the movement board according to the detected state.
  • the receiving module is specifically configured to receive a partition type sent by the movement board within a preset time after the timing control board is started;
  • the setting module is specifically configured to set, according to the partition type, a corresponding state of the idle pin when starting, after a preset time after the timing control board is started;
  • the detecting module is specifically configured to detect the state of the idle pin within a preset time after the timing board is started.
  • the partition setting module is configured to: when the state of the idle pin is detected as a high level signal, the timing control board sets the receiving mode to a receiving manner of the partition of the movement board When the state of the idle pin is detected as a low level signal, the timing control board sets the receiving mode to the receiving mode of the second partition of the movement board.
  • the system further comprises:
  • a recovery module configured to restore the idle pin to the original function after the preset time.
  • the idle pin is a sync signal pin of the 3D mode.
  • the present invention can multiplex the pins of the partition setting with the idle pins at the startup, thereby achieving the interface without increasing the timing control board and occupying the interface between the timing control board and the movement board.
  • the function of the core board compatible with different partitions is achieved.
  • FIG. 1 is a schematic flowchart of an implementation process of a chip pin multiplexing method according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a system for chip pin multiplexing according to an embodiment of the present invention.
  • the pin set by the partition can be multiplexed with the pin that is idle at startup, so that the timing control board does not need to add another pin for corresponding control, and can be compatible with different partitions.
  • the type of movement board reduces the cost and does not occupy the problem of limited pin resources for the interface between the timing board and the movement board.
  • the method for chip pin multiplexing provided by the embodiment of the present invention is applied to a timing control board, and the partition of the movement board is selected by a preset idle pin on the timing control board.
  • the preset idle pin is the pin of the partition setting.
  • an implementation flow of a method for chip pin multiplexing according to an embodiment of the present invention includes the following steps:
  • step S101 after the timing control board is started, receiving a partition type sent by the movement board;
  • the method before step S101, further includes: setting a pin that is idle at startup to a pin of a partition setting.
  • step S102 according to the partition type, setting a corresponding state of the pin that is idle at startup;
  • step S103 the timing control board detects the state of the idle pin
  • step S104 according to the detected state, the timing control board sets the receiving mode to the receiving mode of the corresponding partition of the movement board.
  • step S101 receiving a partition type sent by the movement board within a preset time after the timing control board is started;
  • step S102 a preset state of the pin that is idle at startup is set according to the partition type within a preset time after the timing control board is started;
  • step S103 the timing control board detects the state of the idle pin within the preset time after the timing control board is started
  • step S104 when detecting that the state of the idle pin is a high level signal, the timing control board sets the receiving mode to the receiving mode of the partition of the movement board; when detecting When the state of the idle pin is a low level signal, the timing control board sets the receiving mode to the receiving mode of the second partition of the movement board.
  • the method further includes: after the preset time, the idle pin at the startup is restored to the original function.
  • the present invention will be described in detail below by taking a pin in which the sync signal pin of the 3D mode is set as a partition setting as an example.
  • This embodiment considers that the partition setting is a good action in the initialization stage of the timing control board, and the movement board does not change during the work process once the partition is determined; and as the left and right eye synchronization signals in the 3D mode.
  • LR_IN is valid only in 3D mode startup, and idle in 2D mode.
  • the whole machine must be powered on in 2D state and will not be turned on in 3D state; therefore, this embodiment can set the partition setting.
  • the pin is multiplexed with the 3D sync signal LR_IN pin.
  • the 3D synchronization signal LR_IN pin is used as a partition setting pin, and the timing control board detects the H/L state of the 3D synchronization signal LR_IN pin within 1 s to determine and The partition mode of the movement board is matched; for example, when the state of the 3D synchronization signal LR_IN pin is detected as H, the receiving mode of the timing control board is set to a partition; when the 3D synchronization signal LR_IN is detected When the state of the pin is L, the receiving mode of the timing control board is set to two partitions. During this time, the 3D sync signal LR_IN pin must be in a stable state.
  • the 3D sync signal LR_IN pin operates as the sync signal LR_IN pin of the 3D mode until the timing board is turned off.
  • the partition mode of the movement board is determined within 1 s after the timing control board is powered on, and both 2D and 3D operate in the same partition mode.
  • FIG. 2 is a schematic structural diagram of a system for chip pin multiplexing according to an embodiment of the present invention.
  • the chip pin multiplexing system includes: a receiving module 101, a setting module 102, a detecting module 103, and a partition setting module 104.
  • the chip pin multiplexing system may be a software unit, a hardware unit, or a combination of soft and hard units built in the timing control board.
  • the system for chip pin multiplexing provided by the embodiment of the present invention is applied to a timing control board, and the partition of the movement board is selected by a preset idle pin on the timing control board.
  • the preset idle pin is the pin of the partition setting.
  • the receiving module 101 is configured to receive, after the timing board is started, a partition type sent by the movement board;
  • the setting module 102 is configured to set, according to the partition type, a corresponding state of the pin that is idle at startup;
  • the detecting module 103 is configured to detect the state of the idle pin
  • the partition setting module 104 is configured to set a receiving manner of the timing control board to a receiving manner of a corresponding partition of the movement board according to the detected state.
  • the receiving module 101 is specifically configured to receive a partition type sent by the movement board within a preset time after the timing control board is started;
  • the setting module 102 is specifically configured to set, according to the partition type, a corresponding state of the idle pin when starting, after a preset time after the start of the timing control board;
  • the detecting module 103 is specifically configured to detect the state of the idle pin within a preset time after the timing control board is started.
  • the partition setting module 104 is configured to: when detecting that the state of the idle pin is a high level signal, the timing control board sets the receiving mode to receive the partition of the movement board When the state of the idle pin is detected as a low level signal, the timing control board sets the receiving mode to the receiving mode of the second partition of the movement board.
  • the chip pin multiplexing system further includes: a recovery module.
  • the recovery module is configured to restore the idle pin to the original function after the preset time.
  • the idle pin may be a synchronous signal pin of the 3D mode.
  • any pin that is idle at startup can be used as a pin for partition setting.
  • the embodiment of the present invention can multiplex the pins set by the partition with the idle pins at the startup, thereby achieving the area without increasing the timing control board and occupying the timing control board and the core board.
  • the function of the movement board compatible with different partitions is achieved.

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Abstract

芯片引脚复用的方法：时序控制板启动后，接收机芯板发送的分区类别；设置启动时空闲的引脚的相应状态；侦测空闲的引脚的状态；时序控制板将接收方式设定为机芯板相应分区的接收方式。在不增加时序控制板的面积及不占用时序控制板与机芯板的接口连接的引脚资源的情况下，达到兼容不同分区的机芯板的功能。

Description

一种芯片引脚复用的方法及系统 技术领域
本发明涉及显示技术领域，特别涉及一种芯片引脚复用的方法及系统。
 背景技术
目前，超高清机种的机芯板会有一分区和二分区的信号之分，为兼容不同分区类型的机芯板，时序控制板上需要增加一根引脚去选择一分区或二分区的数据映射，这样不同分区类型的机芯板便可以共用同一块时序控制板。
当机芯板是一分区方式时，同步将control pin置H，而时序控制板侦测该control pin状态，当侦测到control pin状态为H时，将时序控制板的接收方式设定为一分区；当机芯板是二分区方式时，同步将control pin置L，而时序控制板侦测该control pin状态，当侦测到control pin状态为L时，将时序控制板的接收方式设定为二分区；这样机芯板和时序控制板便对应起来了。
然而，上述为兼容不同分区类型的机芯板，时序控制板需要增加一根引脚去做对应控制，这样便增加了时序控制板的面积，对缩减成本不利，而且会占用时序控制板与机芯板的接口连接有限的引脚资源。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种芯片引脚复用的方法及系统，旨在解决现有技术中存在的为兼容不同分区类型的机芯板，时序控制板需要增加一根引脚去做对应控制，这样便增加了时序控制板的面积，对缩减成本不利，而且会占用时序控制板与机芯板的接口连接有限的引脚资源的问题。
 技术解决方案
一种芯片引脚复用的方法，其中所述方法应用于时序控制板中，通过所述时序控制板上预设的启动时空闲的引脚来选择机芯板的分区；其中，所述预设的启动时空闲的引脚作为分区设定的引脚；所述方法包括：
在所述时序控制板启动后的预设时间内，接收所述机芯板发送的分区类别；
在所述时序控制板启动后的预设时间内，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
在所述时序控制板启动后的所述预设时间内，所述时序控制板侦测所述空闲的引脚的所述状态；
根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式；
在所述预设时间之后，所述启动时空闲的引脚恢复至原功能。
优选的，其中根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式的步骤，具体包括：
当侦测到所述空闲的引脚的状态为高电平信号时，所述时序控制板将接收方式设定为所述机芯板一分区的接收方式；
当侦测到所述空闲的引脚的状态为低电平信号时，所述时序控制板将接收方式设定为所述机芯板二分区的接收方式。
优选的，其中所述空闲的引脚为3D模式的同步信号引脚。
一种芯片引脚复用的方法，所述方法应用于时序控制板中，通过所述时序控制板上预设的启动时空闲的引脚来选择机芯板的分区；其中，所述预设的启动时空闲的引脚作为分区设定的引脚；所述方法包括：
所述时序控制板启动后，接收所述机芯板发送的分区类别；
根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
所述时序控制板侦测所述空闲的引脚的所述状态；
根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式。
优选的，所述时序控制板启动后，接收所述机芯板发送的分区类别的步骤，具体包括：
在所述时序控制板启动后的预设时间内，接收所述机芯板发送的分区类别；
所述根据所述分区类别，设置所述启动时空闲的引脚的相应状态的步骤，具体包括：
在所述时序控制板启动后的预设时间内，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
所述时序控制板侦测所述空闲的引脚的所述状态的步骤，具体包括：
在所述时序控制板启动后的所述预设时间内，所述时序控制板侦测所述空闲的引脚的所述状态。
优选的，根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式的步骤，具体包括：
当侦测到所述空闲的引脚的状态为高电平信号时，所述时序控制板将接收方式设定为所述机芯板一分区的接收方式；
当侦测到所述空闲的引脚的状态为低电平信号时，所述时序控制板将接收方式设定为所述机芯板二分区的接收方式。
优选的，在所述根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式的步骤之后，还包括：
在所述预设时间之后，所述启动时空闲的引脚恢复至原功能。
优选的，所述空闲的引脚为3D模式的同步信号引脚。
一种芯片引脚复用的系统，所述系统应用于时序控制板中，通过所述时序控制板上预设的启动时空闲的引脚来选择机芯板的分区；其中，所述预设的启动时空闲的引脚作为分区设定的引脚；所述系统包括：
接收模块，用于所述时序控制板启动后，接收所述机芯板发送的分区类别；
设置模块，用于根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
侦测模块，用于侦测所述空闲的引脚的所述状态；
分区设定模块，用于根据侦测到的所述状态，将所述时序控制板的接收方式设定为所述机芯板相应分区的接收方式。
优选的，
所述接收模块，具体用于在所述时序控制板启动后的预设时间内，接收所述机芯板发送的分区类别；
所述设置模块，具体用于在所述时序控制板启动后的预设时间内，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
所述侦测模块，具体用于在所述时序控制板启动后的预设时间内，侦测所述空闲的引脚的所述状态。
优选的，
所述分区设定模块，具体用于当侦测到所述空闲的引脚的状态为高电平信号时，所述时序控制板将接收方式设定为所述机芯板一分区的接收方式；当侦测到所述空闲的引脚的状态为低电平信号时，所述时序控制板将接收方式设定为所述机芯板二分区的接收方式。
优选的，所述系统还包括：
恢复模块，用于在所述预设时间之后，所述启动时空闲的引脚恢复至原功能。
优选的，所述空闲的引脚为3D模式的同步信号引脚。
 有益效果
相对现有技术，本发明通过将分区设定的引脚与启动时空闲的引脚复用即可，从而达到在不增加时序控制板的面积及不占用时序控制板与机芯板的接口连接的引脚资源的情况下，达到兼容不同分区的机芯板的功能。
 附图说明
图1为本发明实施例提供的芯片引脚复用的方法的实现流程示意图；
图2为本发明实施例提供的芯片引脚复用的系统的结构示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指用作实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为意指“一个或多个”，除非另外指定或从上下文清楚导向单数形式。
在本发明实施例中，通过将分区设定的引脚与启动时空闲的引脚复用即可，这样，时序控制板不需要另外增加一根引脚去做对应控制，便能兼容不同分区类型的机芯板，缩减了成本，而且不会占用时序控制板与机芯板的接口连接有限的引脚资源的问题。
为了说明本发明所述的技术方案，下面通过具体实施例来进行说明。
在本发明实施例中，本发明实施例提供的芯片引脚复用的方法应用于时序控制板中，通过所述时序控制板上预设的启动时空闲的引脚来选择机芯板的分区；其中，所述预设的启动时空闲的引脚作为分区设定的引脚。
请参阅图1，为本发明实施例提供的芯片引脚复用的方法的实现流程，其主要包括以下步骤：
在步骤S101中，所述时序控制板启动后，接收所述机芯板发送的分区类别；
在本发明实施例中，在步骤S101之前，还包括：预先将启动时空闲的引脚设置为分区设定的引脚。
在步骤S102中，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
在步骤S103中，所述时序控制板侦测所述空闲的引脚的所述状态；
在步骤S104中，根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式。
下面详细描述各个步骤的实现流程：
在步骤S101中，在所述时序控制板启动后的预设时间内，接收所述机芯板发送的分区类别；
在步骤S102中，在所述时序控制板启动后的预设时间内，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
在步骤S103中，在所述时序控制板启动后的所述预设时间内，所述时序控制板侦测所述空闲的引脚的所述状态；
在步骤S104中，当侦测到所述空闲的引脚的状态为高电平信号时，所述时序控制板将接收方式设定为所述机芯板一分区的接收方式；当侦测到所述空闲的引脚的状态为低电平信号时，所述时序控制板将接收方式设定为所述机芯板二分区的接收方式。
在本发明实施例中，在步骤S104之后，还包括：在所述预设时间之后，所述启动时空闲的引脚恢复至原功能。
下面以将3D模式的同步信号引脚设置为分区设定的引脚为例，详细描述本发明。
本方案是应用在同时具有2D和3D的机型中。
本实施例考虑到分区设定是在时序控制板初始化阶段便匹配好的动作，而且机芯板一旦确定分区便不会在工作过程中更改；而作为3D模式下眼镜与画面左右眼同步信号的LR_IN，是仅在3D模式启动下才有效，2D模式时闲置；另外，整机开机一定是2D状态下开机，不会发生在3D状态下开机；因此，本实施例可将分区设定的引脚与3D同步信号LR_IN引脚复用。
具体工作模式如下：
时序控制板开机后的1s内，将该3D同步信号LR_IN引脚作为分区设定的引脚，时序控制板在这1s内侦测该3D同步信号LR_IN引脚的H/L状态，以决定与机芯板搭配的分区模式；例如，当侦测到3D同步信号LR_IN引脚的状态为H时，将时序控制板的接收方式设定为一分区；当侦测到所述3D同步信号LR_IN引脚的状态为L时，将时序控制板的接收方式设定为二分区。在此期间，该3D同步信号LR_IN引脚必须保持稳定的状态。
1s之后，该3D同步信号LR_IN引脚作为3D模式的同步信号LR_IN引脚工作，直到时序控制板关机。
然而，可以理解的是，时序控制板开机后的1s内确定了机芯板分区模式，2D与3D都以相同的分区模式工作。
请参阅图2，为本发明实施例提供的芯片引脚复用的系统的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。所述芯片引脚复用的系统包括：接收模块101、设置模块102、侦测模块103、以及分区设定模块104。所述芯片引脚复用的系统可以是内置于时序控制板中的软件单元、硬件单元或者是软硬结合的单元。
在本发明实施例中，本发明实施例提供的芯片引脚复用的系统应用于时序控制板中，通过所述时序控制板上预设的启动时空闲的引脚来选择机芯板的分区；其中，所述预设的启动时空闲的引脚作为分区设定的引脚。
所述接收模块101，用于所述时序控制板启动后，接收所述机芯板发送的分区类别；
所述设置模块102，用于根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
所述侦测模块103，用于侦测所述空闲的引脚的所述状态；
所述分区设定模块104，用于根据侦测到的所述状态，将所述时序控制板的接收方式设定为所述机芯板相应分区的接收方式。
在本发明实施例中，
所述接收模块101，具体用于在所述时序控制板启动后的预设时间内，接收所述机芯板发送的分区类别；
所述设置模块102，具体用于在所述时序控制板启动后的预设时间内，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
所述侦测模块103，具体用于在所述时序控制板启动后的预设时间内，侦测所述空闲的引脚的所述状态。
所述分区设定模块104，具体用于当侦测到所述空闲的引脚的状态为高电平信号时，所述时序控制板将接收方式设定为所述机芯板一分区的接收方式；当侦测到所述空闲的引脚的状态为低电平信号时，所述时序控制板将接收方式设定为所述机芯板二分区的接收方式。
作为本发明一实施例，所述芯片引脚复用的系统还包括：恢复模块。
所述恢复模块，用于在所述预设时间之后，所述启动时空闲的引脚恢复至原功能。
在本发明实施例中，所述空闲的引脚可以为3D模式的同步信号引脚。然而，并不限于此，凡是在启动时处于空闲的引脚都可以作为分区设定的引脚。
综上所述，本发明实施例通过将分区设定的引脚与启动时空闲的引脚复用即可，从而达到在不增加时序控制板的面积及不占用时序控制板与机芯板的接口连接的引脚资源的情况下，达到兼容不同分区的机芯板的功能。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种芯片引脚复用的方法，其中所述方法应用于时序控制板中，通过所述时序控制板上预设的启动时空闲的引脚来选择机芯板的分区；其中，所述预设的启动时空闲的引脚作为分区设定的引脚；所述方法包括：
    在所述时序控制板启动后的预设时间内，接收所述机芯板发送的分区类别；
    在所述时序控制板启动后的预设时间内，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
    在所述时序控制板启动后的所述预设时间内，所述时序控制板侦测所述空闲的引脚的所述状态；
    根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式；
    在所述预设时间之后，所述启动时空闲的引脚恢复至原功能。
  2. 根据权利要求1所述的方法，其中根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式的步骤，具体包括：
    当侦测到所述空闲的引脚的状态为高电平信号时，所述时序控制板将接收方式设定为所述机芯板一分区的接收方式；
    当侦测到所述空闲的引脚的状态为低电平信号时，所述时序控制板将接收方式设定为所述机芯板二分区的接收方式。
  3. 根据权利要求1所述的方法，其中所述空闲的引脚为3D模式的同步信号引脚。
  4. 一种芯片引脚复用的方法，其中所述方法应用于时序控制板中，通过所述时序控制板上预设的启动时空闲的引脚来选择机芯板的分区；其中，所述预设的启动时空闲的引脚作为分区设定的引脚；所述方法包括：
    所述时序控制板启动后，接收所述机芯板发送的分区类别；
    根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
    所述时序控制板侦测所述空闲的引脚的所述状态；
    根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式。
  5. 根据权利要求4所述的方法，其中所述时序控制板启动后，接收所述机芯板发送的分区类别的步骤，具体包括：
    在所述时序控制板启动后的预设时间内，接收所述机芯板发送的分区类别；
    所述根据所述分区类别，设置所述启动时空闲的引脚的相应状态的步骤，具体包括：
    在所述时序控制板启动后的预设时间内，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
    所述时序控制板侦测所述空闲的引脚的所述状态的步骤，具体包括：
    在所述时序控制板启动后的所述预设时间内，所述时序控制板侦测所述空闲的引脚的所述状态。
  6. 根据权利要求4或5所述的方法，其中根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式的步骤，具体包括：
    当侦测到所述空闲的引脚的状态为高电平信号时，所述时序控制板将接收方式设定为所述机芯板一分区的接收方式；
    当侦测到所述空闲的引脚的状态为低电平信号时，所述时序控制板将接收方式设定为所述机芯板二分区的接收方式。
  7. 根据权利要求4所述的方法，其中在所述根据侦测到的所述状态，所述时序控制板将接收方式设定为所述机芯板相应分区的接收方式的步骤之后，还包括：
    在所述预设时间之后，所述启动时空闲的引脚恢复至原功能。
  8. 根据权利要求4所述的方法，其中所述空闲的引脚为3D模式的同步信号引脚。
  9. 一种芯片引脚复用的系统，其中所述系统应用于时序控制板中，通过所述时序控制板上预设的启动时空闲的引脚来选择机芯板的分区；其中，所述预设的启动时空闲的引脚作为分区设定的引脚；所述系统包括：
    接收模块，用于所述时序控制板启动后，接收所述机芯板发送的分区类别；
    设置模块，用于根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
    侦测模块，用于侦测所述空闲的引脚的所述状态；
    分区设定模块，用于根据侦测到的所述状态，将所述时序控制板的接收方式设定为所述机芯板相应分区的接收方式。
  10. 根据权利要求9所述的系统，其中
    所述接收模块，具体用于在所述时序控制板启动后的预设时间内，接收所述机芯板发送的分区类别；
    所述设置模块，具体用于在所述时序控制板启动后的预设时间内，根据所述分区类别，设置所述启动时空闲的引脚的相应状态；
    所述侦测模块，具体用于在所述时序控制板启动后的预设时间内，侦测所述空闲的引脚的所述状态。
  11. 根据权利要求9或10所述的系统，其中
    所述分区设定模块，具体用于当侦测到所述空闲的引脚的状态为高电平信号时，所述时序控制板将接收方式设定为所述机芯板一分区的接收方式；当侦测到所述空闲的引脚的状态为低电平信号时，所述时序控制板将接收方式设定为所述机芯板二分区的接收方式。
  12. 根据权利要求9所述的系统，其中所述系统还包括：
    恢复模块，用于在所述预设时间之后，所述启动时空闲的引脚恢复至原功能。
  13. 根据权利要求9所述的系统，其中所述空闲的引脚为3D模式的同步信号引脚。
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