WO2020014879A1 - 降低集成电路功耗的方法及其控制电路 - Google Patents

降低集成电路功耗的方法及其控制电路 Download PDF

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Publication number
WO2020014879A1
WO2020014879A1 PCT/CN2018/096028 CN2018096028W WO2020014879A1 WO 2020014879 A1 WO2020014879 A1 WO 2020014879A1 CN 2018096028 W CN2018096028 W CN 2018096028W WO 2020014879 A1 WO2020014879 A1 WO 2020014879A1
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Prior art keywords
signal
pins
pin
command
power
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PCT/CN2018/096028
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English (en)
French (fr)
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王祎磊
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成都忆芯科技有限公司
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Priority to PCT/CN2018/096028 priority Critical patent/WO2020014879A1/zh
Publication of WO2020014879A1 publication Critical patent/WO2020014879A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of integrated circuits, and in particular, to reducing power consumption caused by pins of integrated circuits.
  • the solid-state storage device 102 is coupled to the host, and is configured to provide the host with storage capabilities.
  • the host and the solid-state storage device 102 can be coupled in a variety of ways, including, but not limited to, SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), SCSI (Small Computer System Interface) , SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus, Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe, high-speed peripheral component interconnect) , NVMe (NVM Expres, high-speed non-volatile storage), Ethernet, Fibre Channel, wireless communication network, etc.
  • SATA Serial Advanced Technology Attachment
  • Serial Advanced Technology Attachment SCSI
  • SAS Serial Attached SCSI
  • IDE Integrated Drive Electronics
  • USB Universal Serial Bus
  • PCIE Peripheral Component Interconnect Express
  • PCIe Peripheral Component Interconnect Express
  • NVMe NVM Expres, high-
  • the host may be an information processing device capable of communicating with the storage device in the above manner, for example, a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, and the like.
  • the storage device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and a DRAM (Dynamic Random Access Memory) 110.
  • NVM Non-Volatile Memory
  • DRAM Dynamic Random Access Memory
  • NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory, Magnetoresistive Memory), RRAM (Resistive Random Access Memory, Resistive Change Memory) are common NVMs.
  • the interface 103 may be adapted to exchange data with a host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, and the like.
  • the control unit 104 is used to control data transmission between the interface 103, the NVM chip 105, and the firmware memory 110, and is also used for storage management, mapping of a host logical address to a flash physical address, erasure balancing, bad block management, and the like.
  • the control section 104 may be implemented in various ways by software, hardware, firmware, or a combination thereof.
  • the control component 104 may be an FPGA (Field-Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.
  • the control unit 104 may also include a processor or a flash memory controller. Software is executed in the processor or the flash memory controller to manipulate the hardware of the control unit 104 to process IO commands.
  • the control unit 104 is also coupled to the DRAM 110 and has access to the data of the DRAM 110.
  • the DRAM can store FTL tables and / or buffered IO command data.
  • the control unit 104 includes a flash memory controller (also referred to as a flash channel controller, a media interface controller).
  • the flash memory controller is coupled to the NVM chip 105, and issues a command to the NVM chip 105 in a manner conforming to the interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105.
  • the interface protocols of the NVM chip 105 include existing technology interface protocols or standards such as “Toggle” and “ONFI”.
  • NVM chip manufacturers also provide different private commands or extended commands for NVM chips, so that the flash memory controller needs to be developed at a high price in order to adapt to NVM chips of different manufacturers and different specifications.
  • Microinstruction execution methods and devices for flash interface controllers are provided in Chinese patent applications CN201610009789.6 and CN201510253428.1, and Chinese patent application CN201610861793.5 provides microinstruction sequence scheduling methods and devices.
  • Chinese patent application CN20162016113754.0 provides Based on the IO command processing method and solid-state storage device, the Chinese patent application CN 201611213755.5 provides a large-capacity NVM interface controller, which is incorporated herein in its entirety.
  • the control component provides control signals and data signals to the NVM chip through multiple pins to implement communication between the control component and the NVM chip.
  • two chips such as the NVM chip and the control unit
  • the working states of the pins in each stage of the inter-chip communication are distinguished, so that the pins that do not need to communicate are in a power-off state, and the pins to be communicated are in a power-on state, so as to reduce the chip pins. Power consumption.
  • a method for controlling power consumption of a first integrated circuit comprising: determining one or more on one or more first pins without communication according to the first phase; The first pins are in a power-off state in the first phase; in response to the power-off state of one or more first pins in the first phase, the signal transmission of the one or more first pins is cut off in the first phase.
  • a second power consumption control method according to the first aspect of the present application, further including: on one or more second pins according to the second phase To communicate, determine that one or more second pins are powered on; in response to one or more second pins being powered on during the second phase, allow one or more first pins to be powered on during the second phase Signal transmission.
  • the chip select signal is The pins, command latch signal pins, address latch signal pins, write enable signal pins, and data bus signal pins are powered on.
  • the power consumption control method provides a fourth power consumption control method according to the first aspect of the present application, wherein, in response to a command cycle of entering a flash memory command, Make sure the data strobe signal pin and / or the read enable signal pin are powered off.
  • the power consumption control method provides a fifth power consumption control method according to the first aspect of the present application, wherein, in response to a command cycle of entering a flash memory command, Determine that the read enable signal pin and / or the data strobe signal pin are in a power-on state, and keep the output of the read enable signal pin and / or the data strobe signal pin at a high state.
  • the power consumption control method provides a sixth power consumption control method according to the first aspect of the present application, wherein, in response to entering a data cycle of a programming command, Make sure that the chip select signal pins, data strobe signal pins, and data bus signal pins are powered on.
  • the power consumption control method provides a seventh power consumption control method according to the first aspect of the present application, wherein, in response to entering a data cycle of a programming command, Make sure the command latch signal pin, address latch signal pin, and write enable signal pin are in the power-off state.
  • the power consumption control method provides an eighth power consumption control method according to the first aspect of the present application, wherein, in response to entering a data cycle of a programming command, Make sure that the read enable signal pin is powered off.
  • the power consumption control method provides a ninth power consumption control method according to the first aspect of the present application, wherein, in response to entering a data cycle of a programming command, Make sure that the read enable signal pin is in the power-on state, and the output of the read enable signal pin is in the high state.
  • the power consumption control method provides a tenth power consumption control method according to the first aspect of the present application, wherein, in response to entering a data cycle of a read command, Make sure the chip select signal pins, data strobe signal pins, and data bus signals are powered on.
  • the power consumption control method provides the eleventh power consumption control method according to the first aspect of the present application, wherein, in response to entering a data cycle of a read command , Confirm that the command latch signal pin, address latch signal pin, and read enable signal pin are in the power-off state.
  • the power consumption control method according to any one of the first to eleventh aspects of the first aspect of the present application, there is provided the twelfth power consumption control method according to the first aspect of the present application, in which data in response to an entry read command Cycle to confirm that the write enable signal pin is powered off.
  • a thirteenth power consumption control method according to the first aspect of the present application, wherein data in response to an entry read command Period, it is determined that the write enable signal pin is in a power-on state, and the output of the write enable signal pin is in a high state.
  • the power consumption control method provides a fourteenth power consumption control method according to the first aspect of the present application, wherein, in response to the data bus being idle, determining Pins other than the chip select signal pins are powered down.
  • the power consumption control method provides the fifteenth power consumption control method according to the first aspect of the present application, wherein, in response to the data bus being idle, determining All pins are powered down and the output of the chip select signal pins is high.
  • the power consumption control method provides a sixteenth power consumption control method according to the first aspect of the present application, wherein A plurality of third pins must output high levels to determine that one or more third pins are in a power-off state.
  • a sixteenth power consumption control method in which one or more fourth pins are to be output according to the fourth stage.
  • a low level determines that one or more fourth pins are powered on.
  • a control circuit including a switch control circuit and a plurality of pins.
  • the switch control circuit is coupled to the pin through a signal switch and sends and / or receives signals through the pin. ;
  • the switch control circuit determines that one or more first pins are powered off in the first stage according to the first stage without communication at one or more first pins; and the switch control circuit is also responsive to The signal switch is turned off when one or more first pins are in a power-off state, so as to cut off signal transmission of the one or more first pins in a first stage.
  • a second control circuit according to the second aspect of the present application, wherein the switch control circuit is to perform communication determination on one or more second pins according to the second phase.
  • One or more second pins are powered on; and the switch control circuit is further responsive to one or more second pins being powered on during the second phase to close the signal switch to allow one or more Signal transmission on multiple second pins.
  • a third control circuit according to the second aspect of the present application, wherein the switch control circuit is to output according to one or more third pins in the third stage.
  • a high level determines that one or more third pins are powered down.
  • control circuit according to any one of the first to third aspects of the second aspect of the present application provides a fourth control circuit according to the second aspect of the present application, wherein the switch control circuit Four pins need to output a low level to determine that one or more fourth pins are powered on.
  • the control circuit provides a fifth control circuit according to the second aspect of the present application, wherein the control circuit further includes a control signal generating circuit; the switch control circuit passes The first signal switch is coupled to the fifth pin, and the signal transmission from the control signal generating circuit to the fifth pin is allowed or disconnected through the first signal switch; the control signal generating circuit generates a control signal, and the control generated by the control signal generating circuit The signal is coupled to the fifth pin through the first signal switch.
  • a sixth control circuit according to the second aspect of the present application, wherein the control circuit further includes a data signal generating circuit: the switch control circuit is coupled to the sixth through a second signal switch.
  • the second signal switch allows or disconnects the signal transmission between the data generating circuit and the sixth pin; the data generating circuit generates a data signal, and the data signal generated by the data generating circuit is coupled to the sixth signal switch through the second signal switch. Pin.
  • a chip according to the third aspect of the present application is provided, including the control circuit described above.
  • a method for controlling power consumption of a first integrated circuit comprising: executing a first microinstruction to set a power state of one or more pins; Generate signals of the first stage of the first command of the communication protocol on the multiple pins; execute the second microinstruction to set the power state of the one or more pins; generate the communication protocol on the one or more pins The signal of the second stage of the first command.
  • a power consumption control method of a second integrated circuit according to the fourth aspect of the present application is provided, wherein the first micro instruction and the second micro instruction It is a micro instruction to set the power status register.
  • a power consumption control method of the third integrated circuit according to the fourth aspect of the present application further comprising: During the time period when the communication protocol performs communication, the third micro instruction is executed to set the power state of the one or more pins to the power-off state.
  • the first phase of the communication protocol is a command phase of an NVM command; and the second phase of the communication protocol is a data phase of an NVM command.
  • a power consumption control method of the fifth integrated circuit according to the fourth aspect of the present application wherein the one or more pins Is coupled to the NVM chip.
  • a sixth integrated circuit power consumption control method in which a first micro instruction is executed, and the one The signal switch of the receiving circuit of the pin transmitting the DQ signal among the plurality of pins is set to the power-off state; the second micro instruction is executed to set the pin transmitting the ALE and CLE signals among the one or more pins to Power off state.
  • a power consumption control method of a sixth integrated circuit according to the fourth aspect of the present application there is provided a power consumption control method of the seventh integrated circuit according to the fourth aspect of the present application, wherein the second micro instruction is executed, and the one or more The signal switch of the receiving circuit of the pin transmitting the DQ signal among the pins is set to a power-off state.
  • a power consumption control method of a sixth integrated circuit according to the fourth aspect of the present application there is provided a power consumption control method of the eighth integrated circuit according to the fourth aspect of the present application, wherein the second microinstruction is executed, and the one or more The signal switch of the transmitting circuit of the pin transmitting the DQ signal among the pins is set to a power-off state.
  • a first media interface controller including: a processor, a power status register, a signal switch, and a pin; the processor is coupled to the power status register, and The power status register is set by executing a micro instruction; the power status register is coupled to a signal switch and controls closing or opening of the signal switch; the signal switch is coupled to a pin and sets a power state of the pin.
  • a second media interface controller according to the fifth aspect of the present application, wherein when the signal switch is closed, the media interface controller transmits a signal through a pin, when When the signal switch is turned off, the signal transmission of the same pin of the media interface controller is cut off.
  • a third media interface controller according to the fifth aspect of the present application, wherein the processor executes a first micro instruction to set the power status register Is a first value; the processor executes a microinstruction sequence to generate a first phase signal of a first command of a communication protocol on a pin; the processor executes a second microinstruction to set the power status register to a second Value; the processor executes a microinstruction sequence on a pin to generate a signal of a second stage of a first command of a communication protocol.
  • a fourth media interface controller according to the fifth aspect of the present application, further comprising: during an initialization phase or a period during which communication is not required according to the communication protocol, The processor executes the third microinstruction to set the power status register to a third value, so that the power status of the pin is set to the power-off status.
  • a fifth media interface controller according to the fifth aspect of the present application, wherein the first phase of the communication protocol is a command phase of an NVM command; and The second phase of the communication protocol is the data phase of the NVM command.
  • a sixth media interface controller according to the fifth aspect of the present application, wherein the one or more pins are coupled to the NVM chip.
  • a seventh media interface controller according to the fifth aspect of the present application, wherein the media interface controller has a plurality of pins; and There are multiple signal switches of the media interface controller.
  • a power consumption control method for an integrated circuit including: setting a power state of one or more pins; and performing a signal on the one or more pins transmission.
  • Figure 1 is a block diagram of a solid-state storage device
  • FIG. 4 is a flowchart of a method for controlling power consumption of an integrated circuit according to an embodiment of the present application
  • FIG. 5 is a schematic diagram of power consumption control according to an ONFI protocol according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a control circuit for controlling a power state of a pin according to still another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a medium interface controller that controls a power state of a pin according to another embodiment of the present application.
  • FIG. 8 shows a microinstruction for setting a power status register according to an embodiment of the present application.
  • FIG. 9 shows a flowchart of a power consumption control method according to still another embodiment of the present application.
  • an embodiment according to the present application is described by taking the communication between the control part of the storage device and the NVM chip through the ONFI protocol as an example. Understandably, the embodiments of the present application are applicable to communication between any chips, and also applicable to multiple communication protocols.
  • Figures 2 and 3 show timing diagrams of commands for operating the NVM chip in the ONFI standard. The part in which the slash is filled indicates the time period of the "don't care" related signal.
  • NVM chips that comply with the ONFI standard include CE # (chip select signal), CLE (command latch signal), ALE (address latch signal), WE # (write enable signal), RE (read enable signal), DQS ( The data strobe signal), DQ (data bus signal) and other pins send electrical commands to the NVM chip by indicating electrical signals on the pins, and receive data or command execution results output from the NVM chip.
  • the commands for operating the NVM chip generally include a command cycle and a data cycle, and each cycle is divided into multiple phases.
  • Figure 2 shows the command phase of the command cycle.
  • the "Command” appearing on the DQ pin indicates the command.
  • Figure 3 shows the address phase of the command cycle. In the address phase, "Address” appears on the DQ pin to indicate the address of the command.
  • Figures 2 and 3 also show the state and time of the signals appearing on the pins such as CE #, CLE, ALE, WE #, RE, DQS, DQ, etc. at each stage. Among them, the signals transmitted by the pins such as CE #, CLE, ALE, WE, RE, and DQS are called control signals, and the signals transmitted by the DQ pins are called data signals.
  • a power state (such as a power-on state or a power-off state) of each pin is set according to a communication state of whether signals are to be transmitted on each pin. For example, the phases are divided according to the communication status of the CE # pin. At each stage, the power state is set for the CE # pin. The power state set for the CE # pin does not change in a single phase.
  • dotted lines 210, 220, 230, and 240 divide the command phase of the command cycle into three phases of S1, S2, and S3.
  • the CE # / CLE / ALE / DQ signals are in a "don't care" state, these signals do not need to communicate, and the WE # / RE / DQS signals need to be transmitted. Therefore, in the S1 phase, the pins of the CLE / ALE / DQ signal are set to the power-off state, and the pins of the WE # / RE / DQS signal are set to the power-on state.
  • each signal needs to be transmitted.
  • the S2 phase all pins transmitting related signals are set to the power-on state.
  • the CLE / ALE / WE # / DQ signals are in the "don't care" state, these signals do not need to communicate, and the RE / DQS signals need to be transmitted. Therefore, in the S3 phase, the pins transmitting the RE / DQS signals are set to the power-on state, and the pins transmitting other signals are set to the power-off state.
  • the phases of each pin are divided according to changes in the communication state of the pins of the respective signals.
  • the power state (such as power-on state or power-off state) of the pins of each signal is set according to whether the communication state of signal transmission is to be performed on the pins of each signal.
  • dotted lines 310, 320, 330, and 340 divide the address phase of the command cycle into three phases of S4, S5, and S6.
  • the CLE signal in the S4 phase, the CLE signal is in a "don't care" state, and it does not need to communicate. Therefore, in the S4 stage, the pin of the CLE signal is set to the power-off state.
  • the S5 phase the CLE signal needs to be transmitted. Therefore, in the S5 stage, the pin of the CLE signal is set to the power-on state.
  • the CLE signal is in a "don't care" state, and it does not need to communicate. Therefore, in the S6 stage, the pin of the CLE signal is set to the power-off state.
  • the power state of each pin is set according to a command cycle and a data cycle of a command for operating the NVM chip. In the command cycle or data cycle, once the power state of the pin is set, it does not change, which reduces the complexity.
  • FIG. 4 is a flowchart of a power consumption control method for an integrated circuit according to an embodiment of the present application.
  • the control unit determines whether a command to operate the NVM chip is sent to the NVM chip (410).
  • the pins are determined according to the communication status of the pins communicating with the NVM chip during the command cycle Power state (such as power-on state or power-off state) (430).
  • Power state such as power-on state or power-off state
  • the CE #, CLE, ALE, and WE # signals are to be transmitted, and the pins transmitting these signals are set to the power-on state.
  • the NVM chip does not care about the signals on the RE and DQS pins, so the pins transmitting these signals are set to the power-off state to reduce the power consumption caused by these pins.
  • the determined power state of each pin is applied to each pin (440), and signal transmission of a command cycle is performed.
  • the power state of each pin (such as on) is determined according to the communication status of each pin communicating with the NVM chip during the data cycle. Power state or power off state) (460).
  • CE #, DQS, and DQ signals are transmitted. Set the pins that transmit these signals to the power-on state.
  • the NVM chip does not care about the signals on the RE, ALE, CLE, and WE # pins, so the pins transmitting these signals are set to the power-off state to reduce the power consumption caused by these pins.
  • the determined power state of each pin is applied to each pin (470), and then a signal transmission of a data cycle is performed.
  • FIG. 5 is a schematic diagram of power consumption control according to an ONFI protocol according to another embodiment of the present application.
  • a signal switch is set on each pin that transmits a signal.
  • a unidirectional signal switch 510 is provided on the pin of the CE # signal
  • a unidirectional signal switch 520 is provided on the pin of the CLE signal
  • a unidirectional signal switch 530, WE # signal is provided on the pin of the ALE signal.
  • the signal on or off of the corresponding pin is controlled by a unidirectional signal switch or a bidirectional signal switch.
  • the unidirectional signal switch has a transmitting circuit (represented by TX), which is used for a pin to send a signal to the NVM chip.
  • the bidirectional signal switch has a transmitting circuit (represented by TX) and a receiving circuit (represented by RX). The transmitting circuit is used for pins to send signals to the NVM chip, and the receiving circuit is used for pins to receive signals from the NVM chip.
  • the programming command includes a command cycle and a data cycle (see a dashed box in FIG. 5).
  • the power state of each pin is set in the command cycle and the data cycle to reduce the power consumption of the chip.
  • the power state of each pin is set by controlling the signal on or off of the signal switch.
  • the CE #, CLE, ALE, WE #, and DQ signal pins are to transmit signals.
  • the unidirectional signal switch 510, the unidirectional signal switch 520, the unidirectional signal switch 530, and the unidirectional signal are transmitted.
  • the signal switch 540 and the bidirectional signal switch 560 are set to be turned on, and the pins of the RE and DQS signals are set to a power-off state, so as to reduce chip power consumption caused by signal transmission of the pins of the RE and DQS signals.
  • the pins of the RE and DQS signals are set to a power-off state.
  • the one-way signal switch 510, the two-way signal switch 560, and the two-way signal switch 570 are turned on, and the one-way signal switch 520, the one-way signal switch 530, the one-way signal switch 540, and the one-way signal switch are turned on.
  • 550 is set to disconnect.
  • the pin of the CLE signal is set to the power-on state during the entire command cycle. This reduces control complexity.
  • the pins of the RE and DQS signals are set to the power-off state.
  • the RE and DQS signals in the command cycle of the programming command should indicate a high level to the NVM chip.
  • the RE and DQS signals set to the power-off state will make the NVM chip feel To high (for example, high impedance).
  • the DQ and DQS signals are transmitted only in one direction, and the signal is provided from the control unit to the NVM chip. Therefore, the transmission circuits of the two-way signal switch 560 and the two-way signal switch 570 are set to be on, and the two-way signal switch is turned on. The receiving circuit of the 560 and the bidirectional signal switch 570 is set to be disconnected to further reduce power consumption. Still optionally, in the command cycle, the unidirectional signal switch 550 of the pin of the RE signal is set to be turned on to improve the quality of the RE signal provided to the NVM chip.
  • the DQ and DQS signals are transmitted only in one direction, and the signal is provided from the control unit to the NVM chip. Therefore, the transmission circuits of the two-way signal switch 560 and the two-way signal switch 570 are turned on, and the two-way signal is turned on. The receiving circuit of the switch 560 and the bidirectional signal switch 570 is set to be opened to further reduce power consumption.
  • the pins of the CE #, DQS, and DQ signals are set to the power-on state, and the pins of the ALE, CLE, and WE # signals are set to the power-off state.
  • the timing of CE #, CLE, ALE, WE #, RE and other signals is similar to the programming command.
  • the DQ and DQS signals are transmitted only in one direction, and signals are provided from the control unit to the NVM chip. Therefore, the transmission circuits of the two-way signal switch 560 and the two-way signal switch 570 are set to be conductive, and the two-way signal switch 560 and The receiving circuit of the bidirectional signal switch 570 is set to be turned off to further reduce power consumption.
  • the DQ and DQS signals are transmitted only in one direction, and the signals provided by the NVM chip to the control unit are received. Therefore, the sending circuits of the two-way signal switch 560 and the two-way signal switch 570 are set to open, and the two-way signal switch 560 is turned off.
  • the receiving circuit with the bidirectional signal switch 570 is set to be turned on.
  • the waiting time there is a long waiting time between the command cycle and the data cycle of the read command.
  • all signals except CE signals are set to the power-off state to further reduce power consumption.
  • the waiting time is specified according to a model and a use state of the NVM chip used.
  • the erase / reset command communication is also performed between the control unit and the NVM chip.
  • the communication of the erase / reset command only requires a command cycle, so the power control according to the command cycle of the programming command or the read command
  • the strategy sets the power state of each pin.
  • the pins of signals other than the CE # signal are set to the power-off state. To reduce the power consumption of the chip. Further, during the bus idle time, the CE # signal pin is also set to the power-off state, that is, all signal pins are set to the power-off state, thereby reducing the communication power consumption between the control part and the NVM chip. To the lowest.
  • the pin of the CE # signal that is set to the power-off state will make the NVM chip perceive the CE # signal of a high level (for example, a high impedance state), thereby preventing the NVM chip coupled to the CE # signal from being Gating by mistake.
  • FIG. 6 is a schematic diagram of a control circuit for controlling a power state of a pin according to still another embodiment of the present application.
  • the power state of the pins is set by providing a signal switch for one or more pins of the chip.
  • FIG. 6 shows pins 604 and 605, and a signal switch 606 for pin 604, and a signal switch 607 and 608 for pin 605.
  • the signal switch 606 is a unidirectional signal switch, and the signal switches 607 and 608 form a bidirectional signal switch. Understandably, a signal switch is provided for each of one, multiple, or all pins of the NVM chip such as the control component 104 to set its power state. In the embodiment shown in FIG. 6, for clarity purposes, only two pins (604 and 605) are shown.
  • FIG. 6 shows a control circuit 600, which is part of a media interface controller such as the control unit 104 (see FIG. 1).
  • the control circuit 600 includes a switch control circuit 601, a control signal generation circuit 602, and a data generation circuit 603.
  • Control circuit 600 is coupled to pins 604 and 605.
  • the control circuit 600 and the pins 604 and 605 belong to the same chip.
  • the control signal generating circuit 602 generates a control signal (for example, CE #, ALE, CLE, WE #, or RE signals in FIG. 5).
  • the control signal generated by the control signal generating circuit 602 is coupled to a pin 604 through a signal switch 606.
  • the signal switch 606 turns on or off the control signal provided by the control signal generating circuit 602 to the pin 604.
  • the signal switch 606 is used as a unidirectional signal switch (one of the signal switches 510-550) provided on a pin of the CE #, ALE, CLE, WE # or RE signal shown in FIG. 5.
  • the data generating circuit 603 generates a data signal (for example, a DQ signal in FIG. 5).
  • the data generating circuit 603 is coupled to a pin 605 through a signal switch 607 and a signal switch 608.
  • the signal switch 607 causes the data signal generated by the data generating circuit 603 to be provided to the pin 605, and the signal switch 608 causes the data signal received from the pin 605 from the NVM chip to be transmitted to the data generating circuit 603.
  • the signal switch 607 and the signal switch 608 are used as a bidirectional signal switch 560 provided on a pin of the DQ signal shown in FIG. 5.
  • the signal switch 607 functions as a transmission circuit of the bidirectional signal switch 560, and the signal switch 608 functions as a reception circuit of the bidirectional signal switch 560. Understandably, according to the ONFI protocol, the DQ signal has multiple pins, and only one of them is shown in the example of FIG. 6.
  • the switch control circuit 601 is coupled to the control terminals of the signal switch 606, the signal switch 607, and the signal switch 608, and controls the opening or closing of each signal switch.
  • the switch control circuit 601 determines that the one or more pins are in a power-off state at a certain stage in response to the fact that one or more pins do not need to communicate at a certain stage.
  • the switch control circuit 601 also turns off a signal switch coupled to the pin in response to the pin being in a power-off state to cut off signal transmission through the pin.
  • the switch control circuit 601 determines that one or more pins are in a power-on state at a certain stage in response to the one or more pins needing communication at a certain stage.
  • the switch control circuit 601 also closes a signal switch coupled to the pin in response to the pin being in the power-on state to allow signal transmission through the pin.
  • the switch control circuit 601 is also coupled to the control signal generation circuit 602 and the data generation circuit 603 to identify that the control signal generation circuit 602 and / or the data generation circuit 603 are to communicate through pins, for example, to send a command to operate an NVM chip, or to Enter a command cycle and / or data cycle of a command to operate the NVM chip.
  • pin 604 is used to provide an RE signal to the NVM chip.
  • the switch control circuit 601 determines that the pins of the RE signal are in a power-off state during the programming command in response to that the pins of the RE signal do not need to communicate during the programming command. Further, the switch control circuit 601 turns off the signal switch 606 in response to the RE signal being in a power-off state to cut off the signal provided to the pin 604.
  • the switch control circuit 601 determines that the pins of the DQ signal are in a power-on state during the programming command in response to the pins of the DQ signal to communicate during the programming command. Further, the switch control circuit 601 closes the signal switch 607 in response to the DQ signal being in the power-on state, so as to allow signal transmission at the pins of the DQ signal. Optionally, in order to further reduce the power consumption of the DQ signal pins, the switch control circuit 601 also turns off the signal switch 608 during the programming command. Still optionally, in order to reduce the complexity, the switch control circuit 901 uses a unified signal to control the opening or closing of the switches 607 and 608.
  • the power consumption of the chip for communication is reduced by turning off the power of the pins that do not need to communicate.
  • a micro instruction is executed in the medium interface controller to instruct the switch control circuit 601 to determine a power state of each pin.
  • a micro-instruction power status register is provided for each signal that needs to control the power status.
  • the value of the power status register reflects the current power status of the corresponding signal, such as the power-on status or power-off status.
  • two bits of the power status register are provided for signals having bidirectional signal switches to control the opening or closing of each signal switch, respectively.
  • FIG. 7 is a schematic diagram of a media interface controller that controls a power state of a pin according to another embodiment of the present application.
  • the media interface controller includes a scheduler 730, a processor 740, a status register 750, a media interface 760, a message queue 770, and one or more threads that can be scheduled by the scheduler 730 and run by the processor 740 ( (Eg, thread 700, thread 710, and thread 720).
  • the sequence of microinstructions that will be executed is called a thread. Because the same microinstruction sequence has its own execution state each time, multiple threads can be created based on the same microinstruction sequence.
  • the execution status is also stored in the status register 750 for each thread.
  • the message queue 770 provides messages for accessing the NVM chip.
  • the thread When the thread is run by the processor 740, it obtains a message to access the NVM chip from the message queue 770, and operates the media interface 760 to generate a command to operate the NVM chip.
  • the running status of the thread and / or the execution status of the command to operate the NVM chip is recorded in the status register 750.
  • the state of the thread is saved in the status register 750, and the scheduler 730 schedules other threads to execute on the processor 740.
  • the media interface 760 includes a power status register.
  • the medium interface is coupled to the pin 704 through a signal switch 706, and is coupled to the pin 705 through a signal switch 707 and a signal switch 708 constituting a bidirectional signal switch.
  • the signal switch 707 causes the data signal generated by the medium interface 760 to be provided to the pin 705, and the signal switch 708 causes the data signal received by the pin 705 from the NVM chip to be transmitted to the medium interface 760.
  • the signal switch 707 and the signal switch 708 are used as a bidirectional signal switch 560 provided on a pin of the DQ signal shown in FIG. 5.
  • the signal switch 707 functions as, for example, a transmitting circuit of the bidirectional signal switch 560, and the signal switch 708 functions as a receiving circuit of the bidirectional signal switch 560. Understandably, according to the ONFI protocol, the DQ signal has multiple pins, only one of which is shown in the example of FIG. 7; and multiple DQ signals are set to the same power state.
  • the signal switch 706 is used as a unidirectional signal switch 520 provided on a pin of the CLE signal shown in FIG. 5.
  • the power status register is coupled to the control terminals of the signal switch 606, the signal switch 607, and the signal switch 608.
  • Each bit of the power status register controls the opening or closing of each signal switch.
  • bit B1 of the power status register is coupled to signal switch 606,
  • bit B2 is coupled to signal switch 607,
  • bit B3 is coupled to signal switch 608.
  • Process its 740 execution thread When the microinstructions in the thread set the B1, B2, and / or B3 bits of the power status register, the signal switch 606, signal switch 607, and / or signal switch 608 are opened or closed, thereby achieving Control of the power state of the signal pins.
  • FIG. 8 shows a micro instruction for setting a power status register according to an embodiment of the present application.
  • the microinstruction to set the power status register includes opcode 810 and one or more operands (820, 822, 824, 826, and 828).
  • the operation code 810 is PCTRL, indicating that this is a micro-instruction for setting a power state and a storage period.
  • the name of operand 820 indicates the signal switch of the set pin.
  • the name of operand 820 is CE_TX_ON, indicating that the operand is used to set the ON or OFF of the one-way signal switch that sends the signal from the pin to the NVM chip of the CE signal pin.
  • each operand of the microinstruction of the power status register is set to correspond to one or more of a signal, a pin, or a unidirectional switch thereof.
  • operand 822 corresponds to a unidirectional signal switch that sends a signal from the pin to the NVM chip
  • operand 824 corresponds to a unidirectional signal switch that sends a signal to the NVM chip from the pin of the signal DQS.
  • the number 824 corresponds to the one-way signal switch of the pin of the signal DQS for receiving a signal from the NVM chip.
  • the one-way signal switch that sends the signal to the NVM chip from the pin of the operand 828 corresponding to the signal DQ.
  • the DQ signal corresponds to multiple pins, a single operand 828 is used to control all the pins of the DQ signal.
  • setting the power status register microinstruction may include multiple numbers of operands.
  • multiple types of setting power status register microinstructions are used, and each type of setting power status register microinstruction is used to turn on or off a signal switch of a pin for setting a different signal.
  • the microinstruction for setting the power status register includes an operand pair consisting of an index and a value, a signal switch of a pin that provides a signal to be set in the index operand, and a signal switch request in the corresponding value operand. The value being set.
  • the set micro-instruction of the power status register includes one or more operand pairs.
  • the following shows an example of using the microinstruction sequence for setting the microinstruction for setting the power status register in sending the NVM command.
  • the signals of the command cycle of the programming command are generated.
  • execute "pctrl, 0b111100010" to set the power status register microinstruction, where the operands of the signal switches corresponding to the pins of the CE, CLE, ALE, and WE signals (see also Figure 5) are set, and The operand of the signal switch of the transmitting circuit corresponding to the pin of the DQ signal is set, and the operation of the signal switch of the pin corresponding to the RE and DQS signals and the operation of the signal switch of the receiving circuit corresponding to the pin of the DQ signal are set.
  • the number is set to 0, so that CE, CLE, ALE, WE, and DQ signals are allowed to be transmitted to the NVM chip, while RE, DQS signals are prohibited from being transmitted, and signals received from the DQ signal pins are also prohibited.
  • the data cycle of the programming command is entered.
  • execute "pctrl, 0b100101010" to set the micro-instruction of the power status register, in which the operands of the signal switches corresponding to the pins of the CE and WE signals are set, and the The operands of the signal switches of the transmitting circuit are set, and the operands of the signal switches of the pins corresponding to the ALE, CLE, and RE signals and the pins of the receiving circuit of the pins corresponding to the DQS and DQ signals are set to 0. Therefore, it is allowed to transmit CE, WE, DQS, and DQ signals to the NVM chip, and prohibit transmission of ALE, CLE, and RE signals, and it is also prohibited to receive signals from the DQS and DQ signal pins.
  • the following shows an example of a microinstruction sequence that uses the microinstruction to set the power status register in an NVM command that sends read data.
  • the signals of the command cycle of the read command are generated.
  • execute "pctrl, 0b111100010” to set the micro-instruction of the power status register, thereby allowing CE, CLE, ALE, WE, and DQ signals to be transmitted to the NVM chip, and prohibiting the transmission of RE, DQS signals, and the DQ signal Receive a signal on the pin.
  • the data cycle of the read command is entered.
  • execute "pctrl, 0b100110101" to set the micro-instruction of the power status register, thereby allowing CE, WE, RE signals to be transmitted to the NVM chip, allowing DQS and DQ signals to be received from the NVM chip, and prohibiting transmission of ALE, CLE signals It is also forbidden to send signals from the DQS and DQ signal pins to the NVM chip.
  • FIG. 9 shows a flowchart of a power consumption control method according to still another embodiment of the present application.
  • the power consumption control method shown in FIG. 9 is implemented in, for example, an integrated circuit.
  • a power state of one or more pins is set (910).
  • the power state of one or more pins to be used in the next according to the communication protocol is set to the power-on state, and the power state of one or more pins that will not be used next is set to the power-off state.
  • the power state of the pins is set by, for example, a switch control circuit (see FIG. 6) or a processor (see FIG. 7) that executes microinstructions.
  • a signal is transmitted on one or more pins (920).
  • one or more pins are used for signal transmission according to a communication protocol. There is no need to care about one or more pins that are not used in the communication protocol at the current stage, because these pins have been set to the power-off state, and even if the signal state is set on these pins, there will be no coupling to the pins. Other circuits. It also helps to eliminate interference or misoperation caused by the signal state of undefined pins of the protocol.

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Abstract

一种降低集成电路功耗的方法及其控制电路。所提供的降低集成电路功耗的方法包括：设置一个或多个引脚的电源状态；在所述一个或多个引脚上进行信号传输。

Description

降低集成电路功耗的方法及其控制电路 技术领域
本申请涉及集成电路领域，具体地，涉及降低集成电路引脚引起的功耗。
背景技术
参看图1，展示了存储设备的框图。固态存储设备102同主机相耦合，用于为主机提供存储能力。主机同固态存储设备102之间可通过多种方式相耦合，耦合方式包括但不限于通过例如SATA(Serial Advanced Technology Attachment，串行高级技术附件)、SCSI(Small Computer System Interface，小型计算机系统接口)、SAS(Serial Attached SCSI，串行连接SCSI)、IDE(Integrated Drive Electronics，集成驱动器电子)、USB(Universal Serial Bus，通用串行总线)、PCIE(Peripheral Component Interconnect Express，PCIe，高速外围组件互联)、NVMe(NVM Expres s，高速非易失存储)、以太网、光纤通道、无线通信网络等连接主机与固态存储设备102。主机可以是能够通过上述方式同存储设备相通信的信息处理设备，例如，个人计算机、平板电脑、服务器、便携式计算机、网络交换机、路由器、蜂窝电话、个人数字助理等。存储设备102包括接口103、控制部件104、一个或多个NVM(非易失存储器，Non-Volatile Memory)芯片105以及DRAM(Dynamic Random Access Memory，动态随机访问存储器)110。NAND闪存、相变存储器、FeRAM(Ferroelectric RAM，铁电存储器)、MRAM(Magnetic Random Access Memory，磁阻存储器)、RRAM(Resistive Random Access Memory，阻变存储器)等是常见的NVM。接口103可适配于通过例如SATA、IDE、USB、PCIE、NVMe、SAS、以太网、光纤通道等方式与主机交换数据。控制部件104用于控制在接口103、NVM芯片105以及固件存储器110之间的数据传输，还用于存储管理、主机逻辑地址到闪存物理地址映射、擦除均衡、坏块管理等。可通过软件、硬件、固件或其组合的多种方式实现控制部件104。控制部件104可以是FPGA(Field-Programmable Gate Array，现场可编程门阵列)、ASIC(Application Specific Integrated Circuit，应用专用集成电路)或者其组合的形式。控制部件104也可以包括处理器或者闪存控制器，在处理器或闪存控制器中执行软件来操纵控制部件104的硬件来处理IO命令。控制部件104还耦合到DRAM 110，并可访问DRAM 110的数据。在DRAM可存储FTL表和/或缓存的IO命令的数据。
控制部件104包括闪存控制器(或称为闪存通道控制器，介质接口控制器)。闪存控制器耦合到NVM芯片105，并以遵循NVM芯片105的接口协议的方式向NVM芯片105发出命令，以 操作NVM芯片105，并接收从NVM芯片105输出的命令执行结果。NVM芯片105的接口协议包括“Toggle”、“ONFI”等现有技术的接口协议或标准。
在Toggle/ONFI等接口协议中定义了操作NVM芯片的多种时序与命令。NVM芯片厂商还为NVM芯片提供了不同的私有命令或扩展命令，使得闪存控制器为适配不同厂商、不同规格的NVM芯片，需要花费高昂的代价来开发。
在中国专利申请CN201610009789.6与CN201510253428.1中提供了用于闪存接口控制器的微指令执行方法与装置，中国专利申请CN 201610861793.5提供了微指令序列的调度方法与装置，中国专利申请CN 201611213754.0提供了IO命令处理方法与固态存储设备，中国专利申请CN 201611213755.5提供了大容量NVM接口控制器，将其全文合并于此。
在公开号为CN107783917A的中国专利申请中，提供了通过执行微指令在NVM芯片的控制管脚上产生控制信号，生成操作NVM芯片的命令，使单一闪存控制器兼容不同厂商、不同规模的NVM芯片。将其全文合并于此。
发明内容
控制部件通过多个引脚向NVM芯片提供控制信号与数据信号来实现控制部件与NVM芯片之间的通信。两个芯片之间(如NVM芯片与控制部件之间)进行通信时，并不是任何时刻所有信号都是必须的。
根据本申请的实施例，区分芯片间通信的各个阶段内引脚的工作状态，使无需通信的引脚处于关电状态，而使要进行通信的引脚处于开电状态，以降低芯片引脚上的功耗。
根据本申请的第一方面，提供了根据本申请第一方面的第一集成电路的功耗控制方法，包括：依据第一阶段在一个或多个第一引脚上无须通信而确定一个或多个第一引脚在第一阶段为关电状态；响应于在第一阶段一个或多个第一引脚为关电状态而在第一阶段切断一个或多个第一引脚的信号传输。
根据本申请的第一方面的第一功耗控制方法，提供了根据本申请第一方面的第二功耗控制方法，其中，还包括：依据第二阶段在一个或多个第二引脚上要进行通信确定一个或多个第二引脚为开电状态；响应于在第二阶段一个或多个第二引脚为开电状态而在第二阶段允许一个或多个第一引脚的信号传输。
根据本申请的第一方面的第一或第二功耗控制方法，提供了根据本申请第一方面的第三功耗控制方法，其中，响应于进入闪存命令的命令周期，确定片选信号引脚、命令锁存信号引脚、地址锁存信号引脚、写使能信号引脚以及数据总线信号引脚为开电状态。
根据本申请的第一方面的第一至第三中任一项的功耗控制方法，提供了根据本申请第一方面的第四功耗控制方法，其中，响应于进入闪存命令的命令周期，确定数据选通信号引脚和/或读使能信号引脚为关电状态。
根据本申请的第一方面的第一至第三中任一项的功耗控制方法，提供了根据本申请第一方面的第五功耗控制方法，其中，响应于进入闪存命令的命令周期，确定读使能信号引脚和/或数据选通信号引脚为开电状态，并保持读使能信号引脚和/或数据选通信号引脚的输出为高电平状态。
根据本申请的第一方面的第一至第五中任一项的功耗控制方法，提供了根据本申请第一方面的第六功耗控制方法，其中，响应于进入编程命令的数据周期，确定片选信号引脚、数据选通信号引脚以及数据总线信号引脚为开电状态。
根据本申请的第一方面的第一至第六中任一项的功耗控制方法，提供了根据本申请第一方面的第七功耗控制方法，其中，响应于进入编程命令的数据周期，确定命令锁存信号引脚、地址锁存信号引脚、写使能信号引脚为关电状态。
根据本申请的第一方面的第一至第七中任一项的功耗控制方法，提供了根据本申请第一方面的第八功耗控制方法，其中，响应于进入编程命令的数据周期，确定读使能信号引脚为关电状态。
根据本申请的第一方面的第一至第七中任一项的功耗控制方法，提供了根据本申请第一方面的第九功耗控制方法，其中，响应于进入编程命令的数据周期，确定读使能信号引脚为开电状态，并使读使能信号引脚的输出为高电平状态。
根据本申请的第一方面的第一至第九中任一项的功耗控制方法，提供了根据本申请第一方面的第十功耗控制方法，其中，响应于进入读命令的数据周期，确定片选信号引脚、数据选通信号引脚以及数据总线信号为开电状态。
根据本申请的第一方面的第一至第十中任一项的功耗控制方法，提供了根据本申请第一方面的第十一功耗控制方法，其中，响应于进入读命令的数据周期，确定命令锁存信号引脚、地址锁存信号引脚、读使能信号引脚为关电状态。
根据本申请的第一方面的第一至第十一中任一项的功耗控制方法，提供了根据本申请第一方面的第十二功耗控制方法，其中，响应于进入读命令的数据周期，确定写使能信号引脚为关电状态。
根据本申请的第一方面的第一至第十一中任一项的功耗控制方法，提供了根据本申请第一方面的第十三功耗控制方法，其中，响应于进入读命令的数据周期，确定写使能信号引脚为开电状态，并使写使能信号引脚的输出为高电平状态。
根据本申请的第一方面的第一至第十三中任一项的功耗控制方法，提供了根据本申请第一方面的第十四功耗控制方法，其中，响应于数据总线空闲，确定片选信号引脚之外的引脚为关电状态。
根据本申请的第一方面的第一至第十三中任一项的功耗控制方法，提供了根据本申请第一方面的第十五功耗控制方法，其中，响应于数据总线空闲，确定全部引脚为关电状态，并使片选信号引脚的输出为高电平状态。
根据本申请的第一方面的第一至第十五中任一项的功耗控制方法，提供了根据本申请第一方面的第十六功耗控制方法，其中，依据在第三阶段一个或多个第三引脚要输出高电平确定一个或多个第三引脚为关电状态。
根据本申请的第一方面的第十六功耗控制方法，提供了根据本申请第一方面的第十七功耗控制方法，其中，依据第四阶段在一个或多个第四引脚要输出低电平确定一个或多个第四引脚为开电状态。
根据本申请的第二方面，提供了根据本申请第二方面的控制电路，包括开关控制电路和多个引脚，开关控制电路通过信号开关耦合到引脚并通过引脚发送和/或接收信号；开关控制电路依据第一阶段在一个或多个第一引脚无须通信而确定一个或多个第一引脚在第一阶段为关电状态；并且，开关控制电路还响应于在第一阶段一个或多个第一引脚为关电状态而断开信号开关，以在第一阶段切断一个或多个第一引脚的信号传输。
根据本申请的第二方面的第一控制电路，提供了根据本申请第二方面的第二控制电路，其中，开关控制电路依据第二阶段在一个或多个第二引脚上要进行通信确定一个或多个第二引脚为开电状态；并且，开关控制电路还响应于在第二阶段一个或多个第二引脚为开电状态而闭合信号开关，以在第二阶段允许一个或多个第二引脚的信号传输。
根据本申请的第二方面的第一或第二控制电路，提供了根据本申请第二方面的第三控制电路，其中，开关控制电路依据在第三阶段一个或多个第三引脚要输出高电平确定一个或多个第三引脚为关电状态。
根据本申请的第二方面的第一至第三中任一项的控制电路，提供了根据本申请第二方面的第四控制电路，其中，开关控制电路依据第四阶段在一个或多个第四引脚要输出低电平确定一个或多个第四引脚为开电状态。
根据本申请的第二方面的第一至第四中任一项的控制电路，提供了根据本申请第二方面的第五控制电路，其中，控制电路还包括控制信号生成电路；开关控制电路通过第一信号开关耦合到第五引脚，并通过第一信号开关允许或断开从控制信号生成电路到第五引脚的信号传输；控 制信号生成电路生成控制信号，控制信号生成电路生成的控制信号通过第一信号开关耦合到第五引脚。
根据本申请的第二方面的第五控制电路，提供了根据本申请第二方面的第六控制电路，其中，控制电路还包括数据信号生成电路：开关控制电路通过第二信号开关耦合到第六引脚，并通过第二信号开关允许或断开数据生成电路与第六引脚之间的信号传输；数据生成电路生成数据信号，数据生成电路生成的数据信号通过第二信号开关耦合到第六引脚。
根据本申请的第三方面，提供了根据本申请第三方面的芯片，包括上述的控制电路。
根据本申请的第四方面，提供了根据本申请第四方面的第一集成电路的功耗控制方法，包括：执行第一微指令设置一个或多个引脚的电源状态；在所述一个或多个引脚上生成通信协议的第一命令的第一阶段的信号；执行第二微指令设置所述一个或多个引脚的电源状态；在所述一个或多个引脚上生成通信协议的第一命令的第二阶段的信号。
根据本申请第四方面的第一集成电路的功耗控制方法，提供了根据本申请第四方面的第二集成电路的功耗控制方法，其中所述第一微指令与所述第二微指令是设置电源状态寄存器微指令。
根据本申请第四方面的第一或第二集成电路的功耗控制方法，提供了根据本申请第四方面的第三集成电路的功耗控制方法，还包括：在初始化阶段或无须根据所述通信协议进行通信的时间段，执行第三微指令将所述一个或多个引脚的电源状态都设置为关电状态。
根据本申请第四方面的第一至第三集成电路的功耗控制方法之一，提供了根据本申请第四方面的第四集成电路的功耗控制方法，其中
所述通信协议的第一阶段是NVM命令的命令阶段；以及所述通信协议的第二阶段是NVM命令的数据阶段。
根据本申请第四方面的第一至第四集成电路的功耗控制方法之一，提供了根据本申请第四方面的第五集成电路的功耗控制方法，其中所述一个或多个引脚被耦合到NVM芯片。
根据本申请第四方面的第四或第五集成电路的功耗控制方法，提供了根据本申请第四方面的第六集成电路的功耗控制方法，其中执行第一微指令，将所述一个或多个引脚中传输DQ信号的引脚的接收电路的信号开关设置为关电状态；执行第二微指令，将所述一个或多个引脚中传输ALE、CLE信号的引脚设置为关电状态。
根据本申请第四方面的第六集成电路的功耗控制方法，提供了根据本申请第四方面的第七集成电路的功耗控制方法，其中执行第二微指令，还将所述一个或多个引脚中传输DQ信号的引脚的接收电路的信号开关设置为关电状态。
根据本申请第四方面的第六集成电路的功耗控制方法，提供了根据本申请第四方面的第八集成电路的功耗控制方法，其中执行第二微指令，还将所述一个或多个引脚中传输DQ信号的引脚的发送电路的信号开关设置为关电状态。
根据本申请的第五方面，提供了根据本申请第五方面的第一介质接口控制器，包括：处理器、电源状态寄存器、信号开关与引脚；所述处理器耦合到电源状态寄存器，并通过执行微指令设置所述电源状态寄存器；所述电源状态寄存器耦合到信号开关，并控制信号开关的闭合或断开；信号开关同引脚耦合，并设置引脚的电源状态。
根据本申请第五方面的第一介质接口控制器，提供了根据本申请第五方面的第二介质接口控制器，其中当信号开关闭合时，所述介质接口控制器通过引脚传输信号，当所述信号开关断开时，切断所述介质接口控制器同引脚的信号传输。
根据本申请第五方面的第一或第二介质接口控制器，提供了根据本申请第五方面的第三介质接口控制器，其中所述处理器执行第一微指令将所述电源状态寄存器设置为第一值；所述处理器执行微指令序列在引脚上生成通信协议的第一命令的第一阶段的信号；所述处理器执行第二微指令将所述电源状态寄存器设置为第二值；所述处理器执行微指令序列在引脚上生成通信协议的第一命令的第二阶段的信号。
根据本申请第五方面的第三介质接口控制器，提供了根据本申请第五方面的第四介质接口控制器，还包括：在初始化阶段或无须根据所述通信协议进行通信的时间段，所述处理器执行第三微指令将所述电源状态寄存器设置为第三值，使得引脚的电源状态被设置为关电状态。
根据本申请第五方面的第三或第四介质接口控制器，提供了根据本申请第五方面的第五介质接口控制器，其中所述通信协议的第一阶段是NVM命令的命令阶段；以及所述通信协议的第二阶段是NVM命令的数据阶段。
根据本申请第五方面的第三至第五介质接口控制器之一，提供了根据本申请第五方面的第六介质接口控制器，其中所述一个或多个引脚被耦合到NVM芯片。
根据本申请第五方面的第一至第六介质接口控制器之一，提供了根据本申请第五方面的第七介质接口控制器，其中所述介质接口控制器的引脚有多个；以及所述介质接口控制器的信号开关有多个。
根据本申请第六方面，提供了根据本申请第六方面的集成电路的功耗控制方法，包括：设置一个或多个引脚的电源状态；以及在所述一个或多个引脚上进行信号传输。
附图说明
当连同附图阅读时，通过参考后面对示出性的实施例的详细描述，将最佳地理解本申请以及优选的使用模式和其进一步的目的和优点，其中附图包括：
图1是固态存储设备的框图；
图2与图3展示了ONFI标准中操作NVM芯片的命令的波形图；
图4是本申请实施例的集成电路的功耗控制方法的流程图；
图5是根据本申请又一实施例的根据ONFI协议实施功耗控制的示意图；
图6是根据本申请再一实施例的控制引脚的电源状态的控制电路的示意图；
图7是根据本申请另一实施例的控制引脚的电源状态的介质接口控制器的示意图；
图8展示了根据本申请实施例的设置电源状态寄存器微指令；以及
图9展示了根据本申请依然又一实施例的功耗控制方法的流程图。
具体实施方式
在下文中，以存储设备的控制部件与NVM芯片之间通过ONFI协议进行通信为例描述根据本申请的实施例。可以理解地，本申请实施例适用于任何芯片之间的通信，以及也适用于多种通信协议。
图2与图3展示了ONFI标准中操作NVM芯片的命令的时序图。其中用斜线填充部分指示“无需关心”(don’t care)相关信号的时间段。遵循ONFI标准的NVM芯片包括CE#(片选信号)、CLE(命令锁存信号)、ALE(地址锁存信号)、WE#(写使能信号)、RE(读使能信号)、DQS(数据选通信号)、DQ(数据总线信号)等引脚，通过在引脚上指示电信号向NVM芯片发送命令，并接收从NVM芯片输出的数据或命令执行结果。操作NVM芯片的命令大体上包括命令周期(Command Cycle)与数据周期(Data Cycle)，各周期又分为多个阶段。
图2展示了命令周期的命令阶段。在命令阶段，DQ引脚上出现的“Command”指示命令。图3展示了命令周期的地址阶段。在地址阶段，DQ引脚上出现的“Address”用来指示命令的地址。图2与图3还展示了在各个阶段，CE#、CLE、ALE、WE#、RE、DQS、DQ等引脚上出现的信号的状态与时间。其中，将CE#、CLE、ALE、WE、RE与DQS等引脚传输的信号称为控制信号，将DQ引脚传输的信号称为数据信号。
在根据本申请的实施例中，根据各引脚上是否要进行信号传输的通信状态，而设置各引脚的电源状态(如开电状态或关电状态)。例如，根据CE#引脚的通信状态划分阶段。在各阶段，为CE#引脚设置电源状态。在单一阶段内，为CE#引脚设置的电源状态不发生变化。
如图2所示，虚线210、220、230与240将命令周期的命令阶段又分为S1、S2与S3三个阶段。在S1阶段，CE#/CLE/ALE/DQ信号为“无需关心”状态，这些信号无须进行通信，而 WE#/RE/DQS信号需要进行传输。因此在S1阶段，将CLE/ALE/DQ信号的引脚设置为关电状态，而将WE#/RE/DQS信号的引脚设置为开电状态。在S2阶段的至少部分时间段，各信号都需要传输。因而在S2阶段，将传输相关信号的所有引脚设置为开电状态。在S3阶段，CLE/ALE/WE#/DQ信号为“无需关心”状态，这些信号无须进行通信，而RE/DQS信号要进行传输。因而在S3阶段，将传输RE/DQS信号的引脚设置为开电状态，而将传输其他信号的引脚设置为关电状态。
设置为关电状态的引脚的信号传输被禁止，从而降低这些引脚引起的功耗。
作为另一个例子，根据各个信号的引脚的通信状态的变化情况来为每个引脚划分阶段。在各阶段，根据各个信号的引脚上是否要进行信号传输的通信状态，而设置每个信号的引脚的电源状态(如开电状态或关电状态)。
如图3所示，虚线310、320、330与340将命令周期的地址阶段又分为S4、S5与S6三个阶段。以CLE信号为例，在S4阶段，CLE信号为“无需关心”状态，其无须进行通信。因此在S4阶段，将CLE信号的引脚设置为关电状态。在S5阶段，CLE信号需要传输。因而在S5阶段，将CLE信号的引脚设置为开电状态。在S6阶段，CLE信号为“无需关心”状态，其无须进行通信。因而在S6阶段，将CLE信号的引脚设置为关电状态。
根据每个信号的通信状态设置传输信号的引脚的电源状态，有助于最大程度的降低引脚传输信号引起的功耗，但也增加了控制各引脚的电源状态的复杂度。根据本申请的又一实施例，根据操作NVM芯片的命令的命令周期与数据周期来设置各引脚的电源状态。在命令周期或数据周期内，引脚的电源状态一经设置而不再改变，从而降低了复杂度。
图4是本申请实施例的集成电路的功耗控制方法的流程图。
以控制部件(也参看图1，控制部件104)为例，控制部件判断是否要向NVM芯片发送操作NVM芯片的命令(410)。在向NVM芯片发送操作NVM芯片的命令期间，响应于识别出进入了操作NVM芯片的命令的命令周期(420)，根据命令周期内同NVM芯片通信的各引脚的通信状态，确定各引脚的电源状态(如开电状态或关电状态)(430)。作为举例，在命令周期内，CE#、CLE、ALE、WE#信号要进行信号传输，将传输这些信号的引脚设置为开电状态。而在命令周期内NVM芯片不关心RE与DQS引脚上的信号，因而将传输这些信号的引脚设置为关电状态，以减少这些引脚引起的功耗。相应地，将所确定的各引脚的电源状态施加给各引脚(440)，进而进行命令周期的信号传输。
命令周期传输结束后，响应于识别出进入了操作NVM芯片的命令的数据周期(450)，根据数据周期内同NVM芯片通信的各引脚的通信状态，确定各引脚的电源状态(如开电状态或关电状态)(460)。作为举例，在数据周期内，CE#、DQS与DQ信号要进行信号传输，将传输这些 信号的引脚设置为开电状态。而在数据周期内NVM芯片不关心RE、ALE、CLE、WE#引脚上的信号，因而将传输这些信号的引脚设置为关电状态，以减少这些引脚引起的功耗。相应地，将所确定的各引脚的电源状态施加给各引脚(470)，进而进行数据周期的信号传输。
图5是根据本申请又一实施例的根据ONFI协议实施功耗控制的示意图。
为设置引脚的电源状态，在传输信号的各引脚上设置信号开关。参看图5，CE#信号的引脚上设有单向信号开关510，CLE信号的引脚上设有单向信号开关520，ALE信号的引脚上设有单向信号开关530，WE#信号的引脚上设有单向信号开关540，RE信号的引脚上设有单向信号开关550，DQ信号的引脚上设有双向信号开关560，DQS信号的引脚上设有双向信号开关570。
通过单向信号开关或双向信号开关控制相应引脚的信号导通或信号断开。单向信号开关具有发送电路(用TX表示)，用于引脚向NVM芯片发送信号。双向信号开关具有发送电路(用TX表示)和接收电路(用RX表示)，发送电路用于引脚向NVM芯片发送信号，而接收电路用于引脚从NVM芯片接收信号。
编程命令包括命令周期和数据周期(参见图5的虚线框)。在根据图5的实施例中，在命令周期和数据周期分别设置各引脚的电源状态，以减少芯片的功耗。
根据要进行命令周期的信号传输还是数据周期的信号传输，通过控制信号开关的信号导通或信号断开来设置各引脚的电源状态。
例如，在编程命令的命令周期，CE#、CLE、ALE、WE#、与DQ信号的引脚要传输信号，将单向信号开关510、单向信号开关520、单向信号开关530、单向信号开关540以及双向信号开关560设置为导通，而将RE与DQS信号的引脚设置为关电状态，以减少RE与DQS信号的引脚的信号传输带来的芯片功耗。通过将单向信号开关550与双向信号开关570设置为断开来将RE与DQS信号的引脚设置为关电状态。而在数据周期，将单向信号开关510、双向信号开关560以及双向信号开关570设置为导通，而将单向信号开关520、单向信号开关530、单向信号开关540以及单向信号开关550设置为断开。
根据图5的实施例，在例如命令周期，虽然根据协议，诸如CLE信号仅在部分时间需要传输信息，但在整个命令周期，都将CLE信号的引脚设置为开电状态。从而降低控制复杂度。
在上面的例子中，在命令周期，将RE与DQS信号的引脚设置为关电状态。虽然根据ONFI协议(也参看图2或图3)，在编程命令的命令周期RE与DQS信号应当向NVM芯片指示高电平，被设置为关电状态的RE与DQS信号，将使NVM芯片感知到高电平(例如高阻态)。
可选地，在命令周期，DQ与DQS信号仅单向传输，从控制部件向NVM芯片提供信号，因而将双向信号开关560与双向信号开关570的发送电路设置为导通，而将双向信号开关560 与双向信号开关570的接收电路设置为断开，以进一步降低功耗。依然可选地，在命令周期，将RE信号的引脚的单向信号开关550设置为导通，以提升提供给NVM芯片的RE信号的质量。
依然可选地，在数据周期，DQ与DQS信号仅单向传输，从控制部件向NVM芯片提供信号，因而将双向信号开关560与双向信号开关570的发送电路设置为导通，而将双向信号开关560与双向信号开关570的接收电路设置为断开，以进一步降低功耗。作为另一个例子，在数据周期，将CE#、DQS与DQ信号的引脚设置为开电状态，将ALE、CLE与WE#信号的引脚设置为关电状态。
对于ONFI标准中NV-DDR2的读命令,CE#、CLE、ALE、WE#、RE等信号的时序同编程命令相似。
在读命令的命令周期，DQ与DQS信号仅单向传输，从控制部件向NVM芯片提供信号，因而将双向信号开关560与双向信号开关570的发送电路设置为导通，而将双向信号开关560与双向信号开关570的接收电路设置为断开，以进一步降低功耗。在读命令的数据周期，DQ与DQS信号仅单向传输，接收NVM芯片提供给控制部件的信号，因而将双向信号开关560与双向信号开关570的发送电路设置为断开，而将双向信号开关560与双向信号开关570的接收电路设置为导通。
在大量读写的情况下，控制部件和NVM芯片之间交换数据的周期会占用大部分总线时间。在编程命令的数据周期，关闭部分引脚(ALE、CLE、WE#与RE信号的引脚，以及DQS与DQ信号的双向信号开关的接收电路)，可以大幅度节省芯片的功耗。
可选地或进一步地，在读命令的命令周期与数据周期之间，存在较长的等待时间。在等待时间(约50us)内，将(除CE信号之外的)所有信号设置为关电状态，以进一步降低功耗。可选地，根据所使用的NVM芯片的型号与使用状态，指定上述等待时间。
控制部件与NVM芯片之间还进行擦除(erase)/重置(reset)命令的通信，擦除/重置命令的通信只需要命令周期，因而根据编程命令或读命令的命令周期的电源控制策略设置各引脚的电源状态。
在一个可选的实施例中，若数据总线空闲(控制部件与NVM芯片之间没有待传输或正在传输的命令)，将CE#信号之外的其他信号的引脚均设置为关电状态，以降低芯片的功耗。进一步地，在总线空闲时间内，将CE#信号引脚也设置为关电状态，即将所有信号的引脚均设置为关电状态，从而使在控制部件与NVM芯片之间的通信功耗降到最低。在此情况下，被设置为关电状态的CE#信号的引脚将使NVM芯片感知到高电平(例如高阻态)的CE#信号，从而避免该CE#信号所耦合的NVM芯片被误选通。
图6是根据本申请再一实施例的控制引脚的电源状态的控制电路的示意图。
根据图6展示的的实施例，通过为芯片的一个或多个引脚提供信号开关来设置引脚的电源状态。图6中示出了引脚604与605，以及用于引脚604的信号开关606，用于引脚605的信号开关607与608。其中信号开关606是单向信号开关，信号开关607与608形成双向信号开关。可以理解地，对于诸如控制部件104耦合到NVM芯片的一个、多个或所有引脚的每个，分别提供信号开关，来设置其电源状态。在图6展示的实施例中，为了清楚的目的，仅展示了两个引脚(604与605)。
图6展示了控制电路600，其是例如控制部件104(参看图1)的介质接口控制器的部分。
控制电路600包括开关控制电路601、控制信号生成电路602与数据生成电路603。控制电路600耦合到引脚604和605。控制电路600与引脚604和605属于同一芯片。
控制信号生成电路602生成控制信号(例如，图5中的CE#、ALE、CLE、WE#或RE信号)。控制信号生成电路602生成的控制信号通过信号开关606耦合到引脚604。信号开关606导通或切断控制信号生成电路602提供给引脚604的控制信号。作为一个例子，信号开关606被用作图5中展示的CE#、ALE、CLE、WE#或RE信号的引脚上被设置的单向信号开关(信号开关510-550之一)。
数据生成电路603生成数据信号(例如，图5中的DQ信号)。数据生成电路603通过信号开关607和信号开关608耦合到引脚605。信号开关607使数据生成电路603生成的数据信号提供给引脚605，信号开关608使引脚605接收到的来自NVM芯片的数据信号传输至数据生成电路603。作为一个例子，信号开关607与信号开关608被用作图5中展示的DQ信号的引脚上被设置的双向信号开关560。信号开关607作为例如双向信号开关560的发送电路，而信号开关608作为双向信号开关560的接收电路。可以理解地，根据ONFI协议，DQ信号有多个引脚，图6的例子中仅展示了其中之一。
开关控制电路601耦合到信号开关606、信号开关607与信号开关608的控制端，并控制各信号开关的断开或闭合。
开关控制电路601响应于在某个阶段一个或多个引脚无须通信而确定该一个或多个引脚在该阶段为关电状态。开关控制电路601还响应于引脚为关电状态而断开耦合到该引脚的信号开关，以切断通过该引脚的信号传输。开关控制电路601响应于在某个阶段一个或多个引脚需要通信而确定该一个或多个引脚在该阶段为开电状态。开关控制电路601还响应于引脚为开电状态而闭合耦合到该引脚的信号开关，以允许通过该引脚的信号传输。
开关控制电路601还耦合到控制信号生成电路602与数据生成电路603，以识别控制信号生成电路602和/或数据生成电路603要通过引脚进行通信，例如要发送操作NVM芯片的命令，或者要进入操作NVM芯片的命令的命令周期和/或数据周期。
作为举例，也参看图5，引脚604用于向NVM芯片提供RE信号。开关控制电路601响应于在编程命令期间RE信号的引脚无须通信而确定RE信号的引脚在编程命令期间为关电状态。进而开关控制电路601还响应于RE信号为关电状态而断开信号开关606，以切断提供给引脚604的信号。
开关控制电路601响应于在编程命令期间DQ信号的引脚要进行通信而确定DQ信号的引脚在编程命令期间为开电状态。进而开关控制电路601还响应于DQ信号为开电状态而闭合信号开关607，以允许DQ信号的引脚的信号传输。可选地，为了进一步降低DQ信号的引脚的功耗，在编程命令期间，开关控制电路601还断开信号开关608。依然可选地，为了降低复杂度，开关控制电路901的采用统一信号控制开关607与开关608的断开或闭合。
本申请实施例在命令的各个周期或各个周期的各个阶段内，通过关闭无须通信的引脚的电源，降低了芯片进行通信所需的功耗。
根据本申请的又一个实施例，介质接口控制器中执行微指令来指示开关控制电路601确定各引脚的电源状态。作为举例，为需要控制电源状态的每个信号提供可由微指令操作的电源状态寄存器，电源状态寄存器的值体现了对应信号当前的电源状态，例如开电状态或关电状态。可选地，为具有双向信号开关的信号提供电源状态寄存器的两位来分别控制每个信号开关的断开或导通。
通过执行微指令来设置或改变电源状态寄存器。从而在执行微指令控制产生的NVM命令时，插入设置电源状态寄存器的微指令，来实现在命令的各个周期或各个周期的各个阶段内控制各信号的引脚的电源状态。
图7是根据本申请另一实施例的控制引脚的电源状态的介质接口控制器的示意图。
如图7所示，介质接口控制器包括调度器730、处理器740、状态寄存器750、介质接口760、消息队列770以及可被调度器730调度并由处理器740运行的一个或多个线程(例如，线程700、线程710与线程720)。将可被执行的微指令序列被称作线程。由于同一微指令序列在每次执行时拥有自己的执行状态，从而可基于同一微指令序列创建多个线程。在状态寄存器750中还为每个线程存储执行状态。
消息队列770提供访问NVM芯片的消息。线程被处理器740运行时，从消息队列770获取访问NVM芯片的消息，并操作介质接口760生成操作NVM芯片的命令。线程的运行状态和/或操作NVM芯片的命令的执行状态被记录在状态寄存器750。从而在等待NVM芯片执行命令时，在状态寄存器750中保存线程的状态，调度器730调度其他线程在处理器740上执行。
介质接口760包括电源状态寄存器。介质接口通过信号开关706耦合到引脚704，并通过构成双向信号开关的信号开关707与信号开关708耦合到引脚705。
信号开关707使介质接口760生成的数据信号提供给引脚705，信号开关708使引脚705接收到的来自NVM芯片的数据信号传输至介质接口760。作为一个例子，信号开关707与信号开关708被用作图5中展示的DQ信号的引脚上被设置的双向信号开关560。信号开关707作为例如双向信号开关560的发送电路，而信号开关708作为双向信号开关560的接收电路。可以理解地，根据ONFI协议，DQ信号有多个引脚，图7的例子中仅展示了其中之一；以及DQ信号的多个被设置相同的电源状态。作为又一个例子，信号开关706被用作图5中展示的CLE信号的引脚上被设置的单向信号开关520。
电源状态寄存器耦合到信号开关606、信号开关607与信号开关608的控制端，电源状态寄存器的各位控制各信号开关的断开或闭合。例如，电源状态寄存器的B1位被耦合到信号开关606，而B2位被耦合到信号开关607，B3位被耦合到信号开关608。处理其740执行线程，当线程中的微指令设置了电源状态寄存器的B1、B2和/或B3位，使得信号开关606、信号开关607和/或信号开关608被断开或闭合，从而实现对信号的引脚的电源状态的控制。
图8展示了根据本申请实施例的设置电源状态寄存器微指令。
设置电源状态寄存器微指令包括操作码810与一个或多个操作数(820、822、824、826与828)。参看图8，作为举例，操作码810为PCTRL，指示这是一条设置电源状态及储存期微指令。操作数820的名字指示了其设置的引脚的信号开关。例如操作数820的名字是CE_TX_ON，指示该操作数用于设置CE信号的引脚的从引脚向NVM芯片发送信号的单向信号开关的导通或断开，操作数820被置位时，指示单向开关导通，而操作数820未被置位时，指示单向开关断开。
继续参看图8，设置电源状态寄存器微指令的每个操作数对应信号、引脚或其单向开关的一个或多个。例如操作数822对应信号CLE的引脚的从引脚向NVM芯片发送信号的单向信号开关，操作数824对应信号DQS的引脚的从引脚向NVM芯片发送信号的单向信号开关，操作数824对应信号DQS的引脚的用于从NVM芯片接收信号的单向信号开关。依然作为举例，操作数828对应信号DQ的引脚的从引脚向NVM芯片发送信号的单向信号开关，虽然DQ信号对应多个引脚，采用单一操作数828来控制DQ信号的所有引脚的向NVM芯片发送信号的单向信号开关。
可以理解地，为控制多种数量的信号引脚，设置电源状态寄存器微指令可包括多种数量的操作数。可选地，使用多种类型的设置电源状态寄存器微指令，每种类型的设置电源状态寄存器微指令用于设置不同的信号的引脚的信号开关的导通或断开。
依然可选地，设置电源状态寄存器微指令包括由索引与值组成的操作数对，在索引操作数中提供要设置的信号的引脚的信号开关，而对应的值操作数中提供信号开关要被设置的值。进一步地，设置电源状态寄存器微指令中包括一个或多个操作数对。
以图8展示的设置电源状态寄存器微指令为例，下面展示了在发送NVM命令中使用设置电源状态寄存器微指令的微指令序列的例子。
在没有NVM命令需要发送，或者在控制部件初始化阶段，执行“pctrl,0x0”设置电源状态寄存器微指令，微指令的所有操作数被设置为0(0x0)以将所有用于传输ONFI信号的引脚的信号开关关闭。
接下来，如果需要，执行微指令来为发送NVM命令做初始化或相关准备。以编程命令为例，要获取编程命令的NVM芯片的地址，待写入NVM芯片的数据缓存地址等。
接下来开始生成编程命令的命令周期的各信号。响应于进入命令周期，执行“pctrl,0b111100010”设置电源状态寄存器微指令，其中将对应于CE、CLE、ALE与WE信号(也参看图5)的引脚的信号开关的操作数置位，将对应于DQ信号的引脚的发送电路的信号开关的操作数置位，将对应于RE、DQS信号的引脚的信号开关操作数以及对应于DQ信号的引脚的接收电路的信号开关的操作数设为0，从而允许向NVM芯片传输CE、CLE、ALE、WE与DQ信号，而禁止传输RE、DQS信号，也禁止从DQ信号的引脚上接收信号。
接下来，执行后续的微指令以完成编程命令的命令周期的信号传输。
在命令周期之后，进入编程命令的数据周期。响应于进入数据周期，执行“pctrl,0b100101010”设置电源状态寄存器微指令，其中将对应于CE、WE信号的引脚的信号开关的操作数置位，将对应于DQS与DQ信号的引脚的发送电路的信号开关的操作数置位，将对应于ALE、CLE、RE信号的引脚的信号开关操作数以及对应于DQS与DQ信号的引脚的接收电路的信号开关的操作数设为0，从而允许向NVM芯片传输CE、WE、DQS与DQ信号，而禁止传输ALE、CLE、RE信号，也禁止从DQS与DQ信号的引脚上接收信号。
接下来，执行后续的微指令以完成编程命令的数据周期的信号传输。
Figure PCTCN2018096028-appb-000001
Figure PCTCN2018096028-appb-000002
下面展示了在发送读数据的NVM命令中使用设置电源状态寄存器微指令的微指令序列的例子。
在没有NVM命令需要发送，或者在控制部件初始化阶段，执行“pctrl,0x0”设置电源状态寄存器微指令，微指令的所有操作数被设置为0(0x0)以将所有用于传输ONFI信号的引脚的信号开关关闭。
接下来，如果需要，执行微指令来为发送NVM命令做初始化或相关准备。以读命令为例，要获取读命令的NVM芯片的地址，待读出数据的缓存地址等。
接下来开始生成读命令的命令周期的各信号。响应于进入命令周期，执行“pctrl,0b111100010”设置电源状态寄存器微指令，从而允许向NVM芯片传输CE、CLE、ALE、WE与DQ信号，而禁止传输RE、DQS信号，也禁止从DQ信号的引脚上接收信号。
接下来，执行后续的微指令以完成读命令的命令周期的信号传输。
在命令周期之后，进入读命令的数据周期。响应于进入数据周期，执行“pctrl,0b100110101”设置电源状态寄存器微指令，从而允许向NVM芯片传输CE、WE、RE信号，允许从NVM芯片接收DQS与DQ信号，而禁止传输ALE、CLE信号，也禁止从DQS与DQ信号的引脚向NVM芯片发送信号。
接下来，执行后续的微指令以完成读命令的数据周期的信号传输。
Figure PCTCN2018096028-appb-000003
图9展示了根据本申请依然又一实施例的功耗控制方法的流程图。
在例如集成电路中实施根据图9所展示的功耗控制方法。参看图9，为实施控制控制，设置一个或多个引脚的电源状态(910)。例如，将在接下来根据通信协议要使用一个或多个引脚的电 源状态设置为开电状态，而将接下来不会被用的一个或多个引脚的电源状态设置为关电状态。通过例如开关控制电路(参看图6)或执行微指令的处理器(参看图7)来设置引脚的电源状态。
接下来，在一个或多个引脚上进行信号传输(920)。例如，根据通信协议使用一个或多个引脚进行信号传输。无须关心在当前阶段，通信协议中未使用的一个或多个引脚，因为这些引脚已被设置为关电状态，即使在这些引脚上设置了信号状态，也不会对耦合到引脚的其他电路产生影响。从而也有助于消除协议未定义引脚的信号状态所产生的干扰或误操作。
这些实施方式所涉及的、从上面描述和相关联的附图中呈现的教导获益的领域中的技术人员将认识到这里记载的本申请的很多修改和其他实施方式。因此，应该理解，本申请不限于公开的具体实施方式，旨在将修改和其他实施方式包括在所附权利要求书的范围内。尽管在这里采用了特定的术语，但是仅在一般意义和描述意义上使用它们并且不是为了限制的目的而使用。

Claims (19)

  1. 一种集成电路的功耗控制方法，包括：
    设置一个或多个引脚的电源状态；以及
    在所述一个或多个引脚上进行信号传输。
  2. 根据权利要求1所述的功耗控制方法，其中，
    依据第一阶段在一个或多个第一引脚上无须通信而确定一个或多个第一引脚在第一阶段为关电状态；
    响应于在第一阶段一个或多个第一引脚为关电状态而在第一阶段切断所述一个或多个第一引脚的信号传输。
  3. 根据权利要求1或2所述的功耗控制方法，其特征在于，还包括：
    依据第二阶段在一个或多个第二引脚上要进行通信确定一个或多个第二引脚为开电状态；
    响应于在第二阶段一个或多个第二引脚为开电状态而在第二阶段允许所述一个或多个第一引脚的信号传输。
  4. 根据权利要求1-3之一所述的功耗控制方法，其特征在于，响应于进入NVM芯片命令的命令周期，确定片选信号引脚、命令锁存信号引脚、地址锁存信号引脚、写使能信号引脚以及数据总线信号引脚为开电状态。
  5. 根据权利要求1-4中任一项所述的功耗控制方法，其特征在于，响应于进入NVM芯片命令的命令周期，确定数据选通信号引脚和/或读使能信号引脚为关电状态。
  6. 根据权利要求1-4中任一项所述的功耗控制方法，其特征在于，响应于进入NVM芯片命令的命令周期，确定读使能信号引脚和/或数据选通信号引脚为开电状态，并保持读使能信号引脚和/或数据选通信号引脚的输出为高电平状态。
  7. 根据权利要求1-6中任一项所述的功耗控制方法，其特征在于，响应于进入编程命令的数据周期，确定片选信号引脚、数据选通信号引脚以及数据总线信号引脚为开电状态。
  8. 根据权利要求1-7中任一项所述的功耗控制方法，其特征在于，响应于进入读命令的数据周期，确定片选信号引脚、数据选通信号引脚以及数据总线信号为开电状态。
  9. 根据权利要求1-8中任一项所述的功耗控制方法，其特征在于，响应于进入读命令的数据周期，确定命令锁存信号引脚、地址锁存信号引脚、读使能信号引脚为关电状态。
  10. 根据权利要求1所述的功耗控制方法，其中，
    执行第一微指令设置所述一个或多个引脚的电源状态；以及
    通过在一个或多个引脚上生成通信协议的第一命令的第一阶段的信号来在所述一个或多个引脚上进行信号传输。
  11. 根据权利要求10所述的功耗控制方法，还包括：
    执行第二微指令设置所述一个或多个引脚的电源状态；以及
    在一个或多个引脚上生成通信协议的第一命令的第二阶段的信号。
  12. 根据权利要求10或11所述的功耗控制方法，还包括：
    在初始化阶段或无须根据所述通信协议进行通信的时间段，执行第三微指令将所述一个或多个引脚的电源状态都设置为关电状态。
  13. 根据权利要求10-12之一所述的方法，其中
    所述通信协议的第一阶段是NVM命令的命令阶段；以及
    所述通信协议的第二阶段是NVM命令的数据阶段。
  14. 根据权利要求13所述的方法，其中
    执行第一微指令，将所述一个或多个引脚中传输DQ信号的引脚的接收电路的信号开关设置为关电状态；
    执行第二微指令，将所述一个或多个引脚中传输ALE、CLE信号的引脚设置为关电状态。
  15. 一种控制电路，包括：处理器、电源状态寄存器、信号开关与引脚；所述处理器耦合到电源状态寄存器，并通过执行微指令设置所述电源状态寄存器；所述电源状态寄存器耦合到信号开关，并控制信号开关的闭合或断开；信号开关同引脚耦合，并设置引脚的电源状态。
  16. 根据权利要求15所述的控制电路，其中
    当信号开关闭合时，所述控制电路通过引脚传输信号，当所述信号开关断开时，切断所述控制电路同引脚的信号传输。
  17. 根据权利要求15或16所述的控制电路，其中
    所述处理器执行第一微指令将所述电源状态寄存器设置为第一值；
    所述处理器执行微指令序列在引脚上生成通信协议的第一命令的第一阶段的信号；
    所述处理器执行第二微指令将所述电源状态寄存器设置为第二值；
    所述处理器执行微指令序列在引脚上生成通信协议的第一命令的第二阶段的信号。
  18. 根据权利要求17所述的控制电路，还包括：
    在初始化阶段或无须根据所述通信协议进行通信的时间段，所述处理器执行第三微指令将所述电源状态寄存器设置为第三值，使得引脚的电源状态被设置为关电状态。
  19. 根据权利要求17或18所述的控制电路，其中
    所述通信协议的第一阶段是NVM命令的命令阶段；以及
    所述通信协议的第二阶段是NVM命令的数据阶段。
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