WO2016127424A1 - Method for optimizing metal planarization process - Google Patents

Method for optimizing metal planarization process Download PDF

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Publication number
WO2016127424A1
WO2016127424A1 PCT/CN2015/073086 CN2015073086W WO2016127424A1 WO 2016127424 A1 WO2016127424 A1 WO 2016127424A1 CN 2015073086 W CN2015073086 W CN 2015073086W WO 2016127424 A1 WO2016127424 A1 WO 2016127424A1
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Prior art keywords
polishing process
metal layer
interconnection structure
thickness
top surface
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PCT/CN2015/073086
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French (fr)
Inventor
Yinuo JIN
Jian Wang
Hui Wang
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ACM Research Shanghai Inc
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ACM Research Shanghai Inc
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Priority to SG11201706624UA priority Critical patent/SG11201706624UA/en
Priority to PCT/CN2015/073086 priority patent/WO2016127424A1/en
Priority to KR1020177026005A priority patent/KR102379960B1/en
Priority to CN201580076084.XA priority patent/CN107210209B/en
Publication of WO2016127424A1 publication Critical patent/WO2016127424A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation

Definitions

  • the present invention generally relates to semiconductor manufacture, and more particularly relates to a method for optimizing metal planarization process.
  • interconnection structure planarization technology has more stringent requirements compared with the past.
  • there at least two kinds of planarization technologies are used for planarizing metal on the interconnection structure, including stressed polishing process, such as CMP and stress free polishing process, such as electrochemical polishing.
  • the CMP utilizes slurry and down force to remove the metal.
  • the CMP is still the most commonly used planarization technology, however, with the development of semiconductor technology, the bottlenecks and problems existing in the CMP process are gradually exposed.
  • the CMP has several deleterious effects on the underlying structures of the interconnection structure because of the relatively strong mechanical force involved. Especially, when the k value of the dielectric materials increasingly reduces, the mechanical force may cause permanent damage to the dielectric materials.
  • the electrochemical polishing utilizes charged electrolyte to remove the metal on the interconnection structure. Because there only the charged electrolyte contacts the metal surface, the electrochemical polishing process has no mechanical force and will not cause damage to the low k dielectric materials. The charged electrolyte is ejected to the metal surface and reacts with the metal. The metal ions are transferred to cathode. In the electrochemical polishing process, the metal surface could be considered as an anode. Hence, as byproducts, huge bubbles are generated on the metal surface, which causes the metal surface roughness becomes bad. As we know, the amount of the bubbles on the metal surface is less, that after the electrochemical polishing, the metal surface roughness is better.
  • the amount of the bubbles on the metal surface must be controlled.
  • the amount of the bubbles is proportional to the electrochemical polishing time.
  • the electrochemical polishing time is shorter, that the amount of the bubbles is less.
  • the electrochemical polishing time is proportional to the electrochemical polishing removing thickness.
  • the electrochemical polishing removing thickness is less, that the electrochemical polishing time is shorter. Based on the relationships, it is obtained that the electrochemical polishing removing thickness is less, after the electrochemical polishing, the metal surface roughness is better.
  • the CMP and electrochemical polishing are combined for planarizing the metal on the interconnection structure. Firstly, remove the bulk metal on the top surface of the interconnection structure by CMP and remain a continuous metal layer covering the top surface of the interconnection structure. The continuous metal layer can resist mechanical force of CMP for protecting the low k dielectric material from damaging. Then, remove the continuous metal layer on the top surface of the interconnection structure by electrochemical polishing and expose the underlying structure of the interconnection structure, such as barrier layer. How to find an optimal remaining thickness after CMP, that is also the removing thickness of the electrochemical polishing, is very important for the final metal surface roughness and dishing control.
  • the thickness of the remained metal layer after CMP is too thin, it is hard to ensure whether the metal layer can fully cover the top surface of the interconnection structure, and probably the low k dielectric material will be damaged during the process. If the thickness of the remained metal layer after CMP is too thick, that means the electrochemical polishing removing thickness is thick, which causes the metal surface roughness after the electrochemical polishing is not good.
  • the present invention provides a method for optimizing metal planarization process, comprising the following steps:
  • the remained metal layer being a continuous layer covering the top surface of the interconnection structure, wherein the remained metal layer has a first surface mean roughness Ra1 induced by the stressed polishing process;
  • the top surface of the metal layer in recessed areas in the interconnection structure being lower than the top surface of the interconnection structure by a dishing value H2 after the stress free polishing process, wherein the metal layer in the recessed areas has a second surface mean roughness Ra2 induced by the stress free polishing process, dividing the removing thickness of the stress free polishing process by Ra2 for obtaining a ratio ⁇ ;
  • FIG. 1 is a cross-sectional view of an interconnection structure on which metal layer isn’ t removed.
  • FIG. 2 is a cross-sectional view showing the bulk metal layer on the top surface of the interconnection structure is removed by CMP.
  • FIG. 3 is a cross-sectional view showing the remained metal layer on the top surface of the interconnection structure is completely removed by electrochemical polishing.
  • FIG. 4 is a cross-sectional view showing a critical state of the remained metal layer on the top surface of the interconnection structure being removed by electrochemical polishing, and there are some residual metal on space areas of the interconnection structure.
  • FIG. 5 is a cross-sectional view showing the residual metal on space areas of the interconnection structure is completely removed by electrochemical polishing.
  • FIG. 6 is a graph showing the relationship between the electrochemical polishing removing thickness and the mean roughness after CMP and electrochemical polishing processes.
  • FIG. 7 is a graph showing the relationship between the electrochemical polishing removing thickness and the mean roughness induced by electrochemical polishing process.
  • FIG. 8 is a graph showing the corresponding relationship among the electrochemical polishing removing thickness and the mean roughness Ra1 induced by CMP process, the mean roughness Ra after CMP and electrochemical polishing processes, the mean roughness Ra2 induced by electrochemical polishing process, ⁇ which is got through dividing the electrochemical polishing removing thickness by the mean roughness Ra2 induced by electrochemical polishing process.
  • FIG. 9 is a cross-sectional view showing the bulk metal layer on the top surface of an interconnection structure with different line width and line density is removed by CMP.
  • the present invention provides a method for optimizing metal planarization process, through controlling the thickness of remained metal layer on the top surface of an interconnection structure after CMP process, to improve the metal surface roughness after the remained metal layer is removed by electrochemical polishing process.
  • the exemplary interconnection structure has a substrate 101, a first dielectric layer 102 formed on the substrate 101, a second dielectric layer 103 formed on the first dielectric layer 102, a hard mask layer 104 formed on the second dielectric layer 103, recessed areas 108, for example, trenches, vias, etc., formed on the hard mask layer 104, the second dielectric layer 103 and the first dielectric layer 102, a first barrier layer 105 formed on the hard mask layer 104, sidewall of the recessed areas 108 and bottom of the recessed areas 108, a second barrier layer 106 formed on the first barrier layer 105, and a metal layer 107 formed on the second barrier layer 106 and filling the recessed areas 108.
  • the subsequent process is to remove the metal layer 107 on the top surface of the interconnection structure.
  • use stressed polishing process such as CMP to remove the bulk metal layer 107 and remain a certain thickness of the metal layer 107.
  • CMP stressed polishing process
  • the thickness of the remained metal layer 107 after CMP is preferably as thin as possible and the remained metal layer 107 is a continuous layer covering the top surface of the interconnection structure, as shown in FIG. 2.
  • the second barrier layer 106 is exposed.
  • the surface of the metal layer 107 in the recessed areas 108 is flush with the top surface of the second dielectric layer 103 or slightly lower than the top surface of the second dielectric layer 103.
  • the present invention will introduce how to obtain the thickness of the remained metal layer 107 after CMP hereinafter.
  • the metal layer has the same thickness over the top surface of the interconnection structure.
  • the thickness of the metal layer on the top surface of the interconnection structure is the same.
  • Rt is the metal surface maximum roughness after CMP and electrochemical polishing processes are completed
  • Rt1 is the metal surface roughness induced by CMP process
  • Rt2 is the metal surface roughness induced by electrochemical polishing process.
  • Ra is the metal surface mean roughness after CMP and electrochemical polishing processes are completed. The relation could be described as:
  • Ra1 is the metal surface mean roughness induced by CMP process
  • Ra2 is the metal surface mean roughness induced by electrochemical polishing process
  • dishing H2 is equal to top surface height of the second barrier layer 106 minus top surface height of the metal layer 107 in the recessed area 108.
  • the top surface of the metal layer 107 in the recessed area 108 is flush with the top surface of the second barrier layer 106.
  • the residual metal height H1 is equal to Rt. It can be seen that the metal surface roughness after CMP and electrochemical polishing processes are completed, especially Rt, determines the minimum dishing.
  • the dishing H2 must be not smaller than the Rt (H2 ⁇ Rt) . Only meeting the condition of H2 ⁇ Rt, the residual metal can be completely removed.
  • the relation between the thickness of the remained metal layer 107 after CMP and the minimum dishing satisfies the following equation:
  • Y is the optimal thickness of the remained metal layer after CMP
  • H2 is the minimum dishing which is a target value set according to process requirement
  • H2 is a known quantity
  • ⁇ is equal to dividing the electrochemical polishing removing thickness by Ra2
  • ⁇ is an empirical equation got through experiments.
  • the ratio ⁇ is determined by electrolyte type, viscosity, temperature, substrate spin speed, horizontal movement speed, current, voltage and so on.
  • Y’ is the actual thickness of the remained metal layer after CMP
  • Y b is the total thickness of the second barrier layer 106 and the first barrier layer 105
  • Y m is the thickness of the hard mask layer 104.
  • an interconnection structure has different line width and line density.
  • the line width and line density cause the step height difference between different line areas, which determines the metal layer height uniformity.
  • the height of the metal layer covering a space area could be considered as 0 Angstrom and as a reference plane. Normally, the height of the metal layer covering on the wide line is lower than the reference plane. Conversely, the height of the metal layer covering on the narrow line is higher than the reference plane. In order to completely remove the metal layer on the top surface of the interconnection structure, the metal layer on the narrow line must be ensured to fully remove.
  • electrochemical polishing process is a conformal process
  • electrochemical polishing process will induce the dishing of the wide line.
  • the depth of the dishing is determined by the step height difference after CMP process and the line’s density.
  • the dishing satisfies the following equation:
  • Rx is the dishing of line width x area
  • Tmin is the step height of the minimum line width relative to the reference plane
  • Dx is the density of line width x area
  • Tx is the step height of the line width x area relative to the reference plane.
  • the dishing of line width 10um area is equal to:
  • Tmin is the step height of the minimum line width relative to the reference plane.
  • Ra2’ is obtained according to the following two aspects:
  • the thickness of the remained metal layer after CMP should satisfy the equation requirement, and the within die step height difference should be as low as possible, especially the narrow line step height should be optimized and trend to zero.

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Abstract

The present invention provides a method for optimizing metal planarization process, comprising: removing a bulk metal layer on a top surface of an interconnection structure by a stressed polishing process until the thickness of the remained metal layer reaches a predetermined value Y, the remained metal layer being a continuous layer covering the top surface of the interconnection structure, wherein the remained metal layer has a first surface mean roughness Ra1 induced by the stressed polishing process; removing the remained metal layer on the top surface of the interconnection structure by a stress free polishing process, the top surface of the metal layer in recessed areas in the interconnection structure being lower than the top surface of the interconnection structure by a dishing value H2 after the stress free polishing process, wherein the metal layer in the recessed areas has a second surface mean roughness Ra2 induced by the stress free polishing process, dividing the removing thickness of the stress free polishing process by Ra2 for obtaining a ratio a; wherein when setting a dishing value, for obtaining the minimum metal surface roughness after the stress free polishing process, the thickness of the remained metal layer after the stressed polishing process satisfies the following equation: Y= α/6 *H2-αRa1.

Description

METHOD FOR OPTIMIZING METAL PLANARIZATION PROCESS BACKGROUND OF THE INVENTION
1.Field of the Invention
The present invention generally relates to semiconductor manufacture, and more particularly relates to a method for optimizing metal planarization process.
2.The Related Art
In interconnection structure manufacturing process, with the shrinking of line width and the application of copper and low k dielectric materials, interconnection structure planarization technology has more stringent requirements compared with the past. At present, there at least two kinds of planarization technologies are used for planarizing metal on the interconnection structure, including stressed polishing process, such as CMP and stress free polishing process, such as electrochemical polishing. The CMP utilizes slurry and down force to remove the metal. Although the CMP is still the most commonly used planarization technology, however, with the development of semiconductor technology, the bottlenecks and problems existing in the CMP process are gradually exposed. The CMP has several deleterious effects on the underlying structures of the interconnection structure because of the relatively strong mechanical force involved. Especially, when the k value of the dielectric materials increasingly reduces, the mechanical force may cause permanent damage to the dielectric materials.
The electrochemical polishing utilizes charged electrolyte to remove the metal on the interconnection structure. Because there only the charged electrolyte contacts the metal surface, the electrochemical polishing process has no mechanical force and will not cause damage to the low k dielectric materials. The charged electrolyte is ejected to the metal surface and reacts with the metal. The metal ions are transferred to cathode. In the electrochemical polishing process, the metal surface  could be considered as an anode. Hence, as byproducts, huge bubbles are generated on the metal surface, which causes the metal surface roughness becomes bad. As we know, the amount of the bubbles on the metal surface is less, that after the electrochemical polishing, the metal surface roughness is better. Therefore, for improving the metal surface roughness, the amount of the bubbles on the metal surface must be controlled. The amount of the bubbles is proportional to the electrochemical polishing time. The electrochemical polishing time is shorter, that the amount of the bubbles is less. Further, the electrochemical polishing time is proportional to the electrochemical polishing removing thickness. The electrochemical polishing removing thickness is less, that the electrochemical polishing time is shorter. Based on the relationships, it is obtained that the electrochemical polishing removing thickness is less, after the electrochemical polishing, the metal surface roughness is better.
For improving planarization efficiency and reducing the electrochemical polishing removing thickness, the CMP and electrochemical polishing are combined for planarizing the metal on the interconnection structure. Firstly, remove the bulk metal on the top surface of the interconnection structure by CMP and remain a continuous metal layer covering the top surface of the interconnection structure. The continuous metal layer can resist mechanical force of CMP for protecting the low k dielectric material from damaging. Then, remove the continuous metal layer on the top surface of the interconnection structure by electrochemical polishing and expose the underlying structure of the interconnection structure, such as barrier layer. How to find an optimal remaining thickness after CMP, that is also the removing thickness of the electrochemical polishing, is very important for the final metal surface roughness and dishing control. If the thickness of the remained metal layer after CMP is too thin, it is hard to ensure whether the metal layer can fully cover the top surface of the interconnection structure, and probably the low k dielectric material will be damaged during the process. If the thickness of the remained metal layer after CMP is too thick,  that means the electrochemical polishing removing thickness is thick, which causes the metal surface roughness after the electrochemical polishing is not good.
SUMMARY
The present invention provides a method for optimizing metal planarization process, comprising the following steps:
removing a bulk metal layer on a top surface of an interconnection structure by a stressed polishing process until the thickness of the remained metal layer reaches a predetermined value Y, the remained metal layer being a continuous layer covering the top surface of the interconnection structure, wherein the remained metal layer has a first surface mean roughness Ra1 induced by the stressed polishing process；
removing the remained metal layer on the top surface of the interconnection structure by a stress free polishing process, the top surface of the metal layer in recessed areas in the interconnection structure being lower than the top surface of the interconnection structure by a dishing value H2 after the stress free polishing process, wherein the metal layer in the recessed areas has a second surface mean roughness Ra2 induced by the stress free polishing process, dividing the removing thickness of the stress free polishing process by Ra2 for obtaining a ratio α；
wherein when setting the dishing value H2, for obtaining the minimum metal surface roughness after the stress free polishing process, the thickness Y of the remained metal layer after the stressed polishing process satisfies the following equation: Y＝ α/6 *H2-αRa1.
As described above, for resisting the mechanical force of the stressed polishing process to avoid the underlying structures of the interconnection structure damaging, and improving the metal surface roughness after the stress free polishing process, the thickness of the remained metal layer after the stressed polishing process needs to meet the following requirements: the thickness of the remained metal layer is  as thin as possible； the remained metal layer is a continuous layer covering the top surface of the interconnection structure； when setting a target dishing value, the thickness of the remained metal layer satisfies the equation: Y＝ α/6 *H2-αRa1.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be apparent to those skilled in the art by reading the following description of embodiments thereof, with reference to the attached drawings, in which:
FIG. 1 is a cross-sectional view of an interconnection structure on which metal layer isn’ t removed.
FIG. 2 is a cross-sectional view showing the bulk metal layer on the top surface of the interconnection structure is removed by CMP.
FIG. 3 is a cross-sectional view showing the remained metal layer on the top surface of the interconnection structure is completely removed by electrochemical polishing.
FIG. 4 is a cross-sectional view showing a critical state of the remained metal layer on the top surface of the interconnection structure being removed by electrochemical polishing, and there are some residual metal on space areas of the interconnection structure.
FIG. 5 is a cross-sectional view showing the residual metal on space areas of the interconnection structure is completely removed by electrochemical polishing.
FIG. 6 is a graph showing the relationship between the electrochemical polishing removing thickness and the mean roughness after CMP and electrochemical polishing processes.
FIG. 7 is a graph showing the relationship between the electrochemical polishing removing thickness and the mean roughness induced by electrochemical polishing process.
FIG. 8 is a graph showing the corresponding relationship among the electrochemical polishing removing thickness and the mean roughness Ra1 induced by CMP process, the mean roughness Ra after CMP and electrochemical polishing processes, the mean roughness Ra2 induced by electrochemical polishing process, α which is got through dividing the electrochemical polishing removing thickness by the mean roughness Ra2 induced by electrochemical polishing process.
FIG. 9 is a cross-sectional view showing the bulk metal layer on the top surface of an interconnection structure with different line width and line density is removed by CMP.
DETAILED DESCRIPTION OF EMBODIMENTS
The present invention provides a method for optimizing metal planarization process, through controlling the thickness of remained metal layer on the top surface of an interconnection structure after CMP process, to improve the metal surface roughness after the remained metal layer is removed by electrochemical polishing process.
Referring to FIG. 1, an exemplary interconnection structure is illustrated. It is recognized that the formation of the interconnection structure is not limited to the exemplary interconnection structure shown in FIG. 1. According to different process requirement, the formation of the interconnection structure may be different. As shown in FIG. 1, the exemplary interconnection structure has a substrate 101, a first dielectric layer 102 formed on the substrate 101, a second dielectric layer 103 formed on the first dielectric layer 102, a hard mask layer 104 formed on the second dielectric layer 103, recessed areas 108, for example, trenches, vias, etc., formed on the hard mask layer 104, the second dielectric layer 103 and the first dielectric layer 102, a first barrier layer 105 formed on the hard mask layer 104, sidewall of the recessed areas 108 and bottom of the recessed areas 108, a second barrier layer 106 formed on the  first barrier layer 105, and a metal layer 107 formed on the second barrier layer 106 and filling the recessed areas 108.
After the metal layer 107 is formed on the second barrier layer 106 and fills the recessed areas 108, the subsequent process is to remove the metal layer 107 on the top surface of the interconnection structure. Firstly, use stressed polishing process, such as CMP to remove the bulk metal layer 107 and remain a certain thickness of the metal layer 107. For resisting the mechanical force of CMP to avoid the underlying structures of the interconnection structure damaging, and improving the metal surface roughness after electrochemical polishing, the thickness of the remained metal layer 107 after CMP is preferably as thin as possible and the remained metal layer 107 is a continuous layer covering the top surface of the interconnection structure, as shown in FIG. 2.
Then use stress free polishing process, such as electrochemical polishing to remove the remained metal layer 107 on the top surface of the interconnection structure, as shown in FIG. 3. After the remained metal layer 107 on the top surface of the interconnection structure is removed, the second barrier layer 106 is exposed. In consideration of the second barrier layer 106 and the first barrier layer 105 on the top surface of the interconnection structure and the hard mask layer 104 being removed in the next process, the surface of the metal layer 107 in the recessed areas 108 is flush with the top surface of the second dielectric layer 103 or slightly lower than the top surface of the second dielectric layer 103.
The present invention will introduce how to obtain the thickness of the remained metal layer 107 after CMP hereinafter.
In order to simplify calculation, as a hypothesis, the metal layer has the same thickness over the top surface of the interconnection structure. In other words, regardless of whether the line width and the line density of the interconnection structure are the same or not, before the metal layer on the top surface of the interconnection structure is removed by CMP, the thickness of the metal layer on the  top surface of the interconnection structure is the same. After CMP and electrochemical polishing processes are completed, the metal surface maximum roughness satisfies the following equation:
Rt＝Rt1+Rt2
wherein Rt is the metal surface maximum roughness after CMP and electrochemical polishing processes are completed, Rt1 is the metal surface roughness induced by CMP process, and Rt2 is the metal surface roughness induced by electrochemical polishing process.
Based on statistics normal distribution, in 3 sigma condition, Rt＝6Ra, Ra is the metal surface mean roughness after CMP and electrochemical polishing processes are completed. The relation could be described as:
Rt＝Rt1+Rt2＝6Ra1+6Ra2
wherein Ra1 is the metal surface mean roughness induced by CMP process, and Ra2 is the metal surface mean roughness induced by electrochemical polishing process.
Referring to FIG. 5, if not considering of the second barrier layer 106 and the first barrier layer 105 on the top surface of the interconnection structure and the hard mask layer 104 removed in the next process, dishing H2 is equal to top surface height of the second barrier layer 106 minus top surface height of the metal layer 107 in the recessed area 108.
As shown in FIG. 4, in a critical state that the remained metal layer on the top surface of the interconnection structure is removed by electrochemical polishing, the top surface of the metal layer 107 in the recessed area 108 is flush with the top surface of the second barrier layer 106. There are some residual metal 107 on space areas of the interconnection structure, and normally the residual metal height H1 is equal to Rt. It can be seen that the metal surface roughness after CMP and electrochemical polishing processes are completed, especially Rt, determines the  minimum dishing. The dishing H2 must be not smaller than the Rt (H2≥Rt) . Only meeting the condition of H2≥Rt, the residual metal can be completely removed. The relation between the thickness of the remained metal layer 107 after CMP and the minimum dishing satisfies the following equation:
Y＝ α/6 (H2-Rt1) ＝ α/6 *H2-αRa1
wherein Y is the optimal thickness of the remained metal layer after CMP, H2 is the minimum dishing which is a target value set according to process requirement, in this equation, H2 is a known quantity, α is equal to dividing the electrochemical polishing removing thickness by Ra2, α is an empirical equation got through experiments. The ratio α is determined by electrolyte type, viscosity, temperature, substrate spin speed, horizontal movement speed, current, voltage and so on.
As described above, for resisting the mechanical force of CMP to avoid the underlying structures of the interconnection structure damaging, and improving the metal surface roughness after electrochemical polishing, the thickness of the remained metal layer after CMP needs to meet the following requirements: the thickness of the remained metal layer is as thin as possible； the remained metal layer is a continuous layer covering the top surface of the interconnection structure； when setting a target dishing value, the thickness of the remained metal layer satisfies the equation: Y＝ α/6 (H2-Rt1) ＝ α/6 *H2-αRa1
If considering of the second barrier layer 106 and the first barrier layer 105 on the top surface of the interconnection structure and the hard mask layer 104 being removed in the next process, the actual thickness of the remained metal layer after CMP satisfies the following equation:
Y’＝Y-Yb-Ym
wherein Y’ is the actual thickness of the remained metal layer after CMP, Yb is the total thickness of the second barrier layer 106 and the first barrier layer 105, Ym is the thickness of the hard mask layer 104.
Referring to FIG. 9, in another embodiment of the present invention, an interconnection structure has different line width and line density. In plating process, the line width and line density cause the step height difference between different line areas, which determines the metal layer height uniformity. The height of the metal layer covering a space area could be considered as 0 Angstrom and as a reference plane. Normally, the height of the metal layer covering on the wide line is lower than the reference plane. Conversely, the height of the metal layer covering on the narrow line is higher than the reference plane. In order to completely remove the metal layer on the top surface of the interconnection structure, the metal layer on the narrow line must be ensured to fully remove. On the other hand, because electrochemical polishing process is a conformal process, when the metal layer on the narrow line is fully removed, electrochemical polishing process will induce the dishing of the wide line. The depth of the dishing is determined by the step height difference after CMP process and the line’s density. The dishing satisfies the following equation:
Rx＝Tmin/Dx -Tx
wherein Rx is the dishing of line width x area, Tmin is the step height of the minimum line width relative to the reference plane, Dx is the density of line width x area, Tx is the step height of the line width x area relative to the reference plane.
For instance, if the line width of the minimum narrow line is 28nm, the step height of the minimum narrow line relative to the reference plane is 200 Angstrom, and the line width of a wide line is 10um, the step height of the wide line relative to the reference plane is -100 Angstrom, and the density of the wide line is 50％, when the metal layer on the minimum narrow line is fully removed, the dishing of line width 10um area is equal to:
R10＝ Tmin/D10-T10 ＝ 200/50％- (-100) ＝ 500 Angstrom
Combined with the equation Y’ ＝Y-Yb-Ym, if the interconnection structure has different line width and line density, the actual thickness of the remained metal layer after CMP satisfies the following equation:
Y”＝ α’ /6 (H2+Tmin-Rt1) ＝ α’ /6 * (H2+Tmin) -α’ Ra1
α’＝ (Y’ +Tmin) /Ra2’
wherein Y” is the actual thickness of the remained metal layer after the stressed polishing process, Tmin is the step height of the minimum line width relative to the reference plane.
Ra2’ is obtained according to the following two aspects:
1) the thickness Y’ +Tmin removed by electrochemical polishing (the stress free polishing process) ； and
2) the relationship between the electrochemical polishing removing thickness and the metal surface mean roughness induced by electrochemical polishing process, as shown in FIG. 7.
As described above, in order to completely remove the metal layer on the top surface of the interconnection structure and meanwhile obtain the target dishing and the minimum metal surface roughness, the thickness of the remained metal layer after CMP should satisfy the equation requirement, and the within die step height difference should be as low as possible, especially the narrow line step height should be optimized and trend to zero.
The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. Such modifications and variations that may be apparent to those skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims.

Claims (7)

  1. A method for optimizing metal planarization process, comprising:
    removing a bulk metal layer on a top surface of an interconnection structure by a stressed polishing process until the thickness of the remained metal layer reaches a predetermined value Y, the remained metal layer being a continuous layer covering the top surface of the interconnection structure, wherein the remained metal layer has a first surface mean roughness Ra1 induced by the stressed polishing process；
    removing the remained metal layer on the top surface of the interconnection structure by a stress free polishing process, the top surface of the metal layer in recessed areas in the interconnection structure being lower than the top surface of the interconnection structure by a dishing value H2 after the stress free polishing process, wherein the metal layer in the recessed areas has a second surface mean roughness Ra2 induced by the stress free polishing process, dividing the removing thickness of the stress free polishing process by Ra2 for obtaining a ratio α；
    wherein when setting the dishing value H2, for obtaining the minimum metal surface roughness after the stress free polishing process, the thickness Y of the remained metal layer after the stressed polishing process satisfies the following equation:
    Y＝α/6*H2-αRa1
  2. The method of claim 1, wherein before the metal layer on the top surface of the interconnection structure is removed by the stressed polishing process, the metal layer has the same thickness over the top surface of the interconnection structure.
  3. The method of claim 1, wherein after the stressed polishing process and the stress free polishing process are completed, the metal surface maximum roughness satisfies the following equation:
    Rt＝Rt1+Rt2
    wherein Rt is the metal surface maximum roughness after the stressed polishing process and the stress free polishing process are completed, Rt1 is the metal surface roughness induced by the stressed polishing process, Rt2 is the metal surface roughness induced by the stress free polishing process.
  4. The method of claim 3, wherein based on statistics normal distribution, in 3 sigma condition, the Rt satisfies the following equation:
    Rt＝Rt1+Rt2＝6Ra1+6Ra2
  5. The method of claim 3, wherein the dishing value H2≥Rt.
  6. The method of claim 1, wherein the interconnection structure includes at least one barrier layer and a hard mask layer, considering of the barrier layer on the top surface of the interconnection structure and the hard mask layer being removed, the actual thickness of the remained metal layer after the stressed polishing process satisfies the following equation:
    Y’＝Y-Yb-Ym
    wherein Y’ is the actual thickness of the remained metal layer after the stressed polishing process, Yb is the thickness of the barrier layer, Ym is the thickness of the hard mask layer.
  7. The method of claim 6, wherein the interconnection structure has different line width, the height of the metal layer covering a space area is used as a reference plane, the actual thickness of the remained metal layer after the stressed polishing process satisfies the following equation:
    Y”＝α’/6* (H2+Tmin) -α’ Ra1
    α’＝ (Y’+Tmin) /Ra2’
    wherein Y” is the actual thickness of the remained metal layer after the stressed polishing process, Tmin is the step height of the minimum line width relative to the reference plane, Ra2’ is obtained according to the followings:
    the thickness Y’ +Tmin removed by the stress free polishing process； and
    the relationship between the thickness removed by the stress free polishing process and the metal surface mean roughness induced by the stress free polishing process.
PCT/CN2015/073086 2015-02-15 2015-02-15 Method for optimizing metal planarization process Ceased WO2016127424A1 (en)

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JP2005217360A (en) * 2004-02-02 2005-08-11 Hitachi Chem Co Ltd Metal polishing solution and polishing method
US7229907B2 (en) * 2004-09-15 2007-06-12 Tom Wu Method of forming a damascene structure with integrated planar dielectric layers
CN101992421A (en) * 2009-08-14 2011-03-30 中芯国际集成电路制造(上海)有限公司 Chemical-mechanical polishing method in copper interconnection process
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