JP2005500687A - Formation of semiconductor structures using a combination of planarization and electropolishing. - Google Patents

Formation of semiconductor structures using a combination of planarization and electropolishing. Download PDF

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JP2005500687A
JP2005500687A JP2003522140A JP2003522140A JP2005500687A JP 2005500687 A JP2005500687 A JP 2005500687A JP 2003522140 A JP2003522140 A JP 2003522140A JP 2003522140 A JP2003522140 A JP 2003522140A JP 2005500687 A JP2005500687 A JP 2005500687A
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conductive layer
method
layer
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surface
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イー,ペイハウアー
カオ チャン,ル
ユー ヤオ,シャン
ワン,フイ
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エーシーエム リサーチ,インコーポレイティド
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Priority to PCT/US2002/026167 priority patent/WO2003017330A2/en
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25FPROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00Electrolytic etching or polishing
    • C25F3/16Polishing
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23HWORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H5/00Combined machining
    • B23H5/06Electrochemical machining combined with mechanical working, e.g. grinding or honing
    • B23H5/08Electrolytic grinding
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for planarizing and electropolishing a conductive layer on a semiconductor structure includes forming a dielectric layer with recessed areas and non-recessed areas on the semiconductor wafer. A conductive layer is formed over the dielectric layer to cover the recessed areas and non-recessed areas. The surface of the conductive layer is then planarized to reduce variations in the topology of the surface. The planarized conductive layer is then electropolished to expose the non-recessed area.

Description

【Technical field】
[0001]
The present invention relates generally to semiconductor devices, and more particularly to a method for planarizing a metal damascus structure using a combination of planarization and electropolishing.
[Background]
[0002]
Semiconductor devices are manufactured or fabricated on a semiconductor wafer using a number of different processing steps to create transistors and interconnect elements. Conductive (eg, metal) trenches, vias, and others are formed as part of the semiconductor device in the dielectric material to electrically connect the transistor terminals associated with the semiconductor wafer. The trench and bias couple electrical signals and power between the transistors, the internal circuitry of the semiconductor device, and circuitry external to the semiconductor device.
[0003]
In forming the interconnect elements, the semiconductor wafer is masked, etched, and deposited, for example, to form the necessary electronic circuits of the semiconductor device. In particular, a number of masking and etching steps can be performed to form a dielectric layer on the semiconductor wafer that acts as a trench and bias for the interconnect lines. A deposition process is then performed to deposit a metal layer on the semiconductor wafer to deposit the metal in both the trench and the bias and on the non-recessed areas of the dielectric layer. The metal deposited on the non-recessed area of the semiconductor wafer is removed to isolate the pattern of the recessed area and form an interconnect element.
[0004]
Conventional methods for removing metal deposited on non-recessed areas of a dielectric layer on a semiconductor wafer include, for example, chemical mechanical polishing (CMP). CMP methods are widely used in the semiconductor industry to polish and planarize trenches with non-recessed areas of dielectric layers and metal layers in the bias to form interconnect lines.
[0005]
In the CMP process, the wafer assembly is positioned on a CMP pad located on a surface plate or web. The wafer assembly includes a support having interconnect elements formed in one or more layers and / or shapes, eg, a dielectric layer. A force is then applied to press the wafer assembly against the CMP pad. As the CMP pad and support assembly are moved relative to and relative to each other, a force is applied to polish and planarize the wafer surface. A polishing solution (often referred to as a polishing slurry) is dispensed onto the CMP pad. Typically, the polishing slurry contains an abrasive and removes unwanted materials, such as metal layers, from the chemically reactive and wafer more rapidly than other materials, such as dielectric materials.
DISCLOSURE OF THE INVENTION
[Problems to be solved by the invention]
[0006]
Thus, CMP can be used to achieve global and local planarization of the surface on the wafer. Furthermore, CMP can be used to remove the material layer and expose the underlying structure or layer. However, the CMP method may have some detrimental effects on the underlying semiconductor structure due to the relatively strong mechanical forces involved. For example, there may be a large difference between the mechanical properties of conductive materials, such as copper and low-k thin layers used in typical damascus processes, when the interconnect position moves below 13 microns. . For example, a low k dielectric thin layer may have a Young's modulus greater than 10 times that of copper. After all, the relatively strong mechanical forces applied to the dielectric thin layer and copper in the CMP process, among other things, are stress related defects including delamination, medium to low warpage, erosion, thin layer lift, scratching or others. May be caused for semiconductor structures.
[Means for Solving the Problems]
[0007]
In one example, a method for forming a semiconductor structure is provided. The method forms a dielectric layer on a semiconductor wafer, wherein the dielectric layer includes a recessed area and a non-recessed area, and forms a conductive layer on the dielectric layer to cover the recessed area and the non-recessed area. And planarizing the surface of the conductive layer to reduce the topological variation of the surface of the conductive layer, and then electropolishing the conductive layer to expose non-recessed areas.
The present invention will be more fully understood in view of the detailed description in conjunction with the accompanying drawings and claims.
BEST MODE FOR CARRYING OUT THE INVENTION
[0008]
In order to provide a more complete understanding of the present invention, numerous specific details are set forth below, such as specific materials, parameters, and the like. However, it should be recognized that the description is not intended to limit the scope of the invention and instead provides a better description of typical embodiments.
[0009]
Chemical mechanical polishing (CMP) is a known method for planarizing and polishing a semiconductor surface, but CMP is a stress related defect to the underlying structure, such as medium to low warpage, corrosion, thin layers May cause floating, scratching or other problems. In contrast, electropolishing is a method of polishing a metal (eg, copper) that provides a relatively stress free polishing method. However, as will be described later, electropolishing is an isotropic etching process in which the metal layer is etched at approximately the same rate regardless of the height difference. Thus, if the topological structure or general shape of the metal layer is non-planar before electropolishing, the non-planar structure or general shape of the metal layer topology typically remains after electropolishing.
[0010]
1A and 1B illustrate a typical process flow of an electropolishing method for polishing a semiconductor structure having a non-planar topology. FIG. 1A illustrates a dielectric layer 102 patterned with indented and non-indented areas formed on a support 100. A barrier / seed layer 105 is formed on the dielectric layer 102 and the support 100. Finally, a metal layer 106 is deposited on the barrier / seed layer 105, for example, by electroplating, covering the recessed and non-recessed areas of the dielectric layer 102. Metal layer 106 has a non-planar topology including humps 108 and depressions 112 located on various structures in the dielectric layer. The non-planar topology of the metal layer 106 can be caused, for example, by plating chemistry in an electroplating process.
[0011]
Referring now to FIG. 1B, the metal layer 106 in the recessed area, i.e., the metal layer 106 is typically polished to the surface of the non-recessed area so that the trenches are isolated to form metal interconnect lines. Returned. In general, it is desirable that the upper surface of the metal layer 106 in the indented area be flush with the upper surface of the non-indented area surrounding the metal layer 106 formed in the indented area.
[0012]
Reference to a plane is not intended or implied that the top surface of the metal layer 106 is absolutely flush with the top surface of the non-recessed area, but rather the top surface of the metal layer 106. It should be appreciated that the level is intended to inform that the level of the upper surface of the indentation area is even higher. Thus, it is generally advantageous to reduce the variation between the upper surface level of the metal layer 106 and the upper surface level of the indentation area.
[0013]
In this example, it is assumed that the metal layer 106 is electropolished. Further, as depicted in FIG. 1A, it is assumed that the topological structure or general shape of the metal layer 106 is non-planar before electropolishing. As previously mentioned, electropolishing is an isotropic etching process. As such, as depicted in FIG. 1B, the non-planar structure or general shape of the topology of the metal layer 106 can remain after electropolishing.
[0014]
More specifically, in this example, it is assumed that the topology of the metal layer 106 includes a hump 108 and a recessed portion 112 prior to electropolishing, as depicted in FIG. 1A. As depicted in FIG. 1B, it is assumed that hump 108 and recessed portion 112 (FIG. 1A) remain as residue 110 and recessed 114 after electropolishing. Residue 110 is a region of metal layer 106 that is at a height H above dielectric layer 102. Residue 110 may cause an electrical short between interconnect lines formed in the trench region below residue 110. The recess 114 is a recess or trench in the metal layer 106 where the surface of the metal layer 106 in the trench is at a depth R below the surface of the dielectric layer 102. Recess 114 can reduce metal and copper in the trench, thereby reducing the conductance of the formed interconnect line. Thus, as described above, it is advantageous to reduce variations in the surface height of the metal layer 106 above and below the surface of the non-recessed area.
[0015]
Thus, in one exemplary embodiment, after planarizing the metal layer formed over the patterned dielectric layer, the metal layer is electropolished to isolate the interconnect lines. One advantage of planarizing the metal layer before electropolishing back is less damage to the structure underlying the metal layer compared to conventional planarization techniques, thus increasing the reliability of the interconnect element. Increasingly, metal interconnect lines can be formed in the dielectric layer. This is because most damage to the structure occurs when the indented metal is exposed to the CMP pad.
[0016]
2A-2D illustrate an exemplary process flow of a method for planarizing and electropolishing an exemplary semiconductor structure including a metal layer 106 having a non-planar topology. FIG. 2A illustrates a cross-sectional view of an exemplary semiconductor structure having indented areas 102r and non-indented areas 102n formed in dielectric layer 102. FIG. The recessed area 102r and the non-recessed area 102n form a pattern of interconnect lines in the dielectric layer 102. The dielectric layer 102 is deposited on the support layer 100 using any conventional deposition method, such as thermal or plasma chemical vapor deposition, spin-on, sputtering, or the like. It can be conveniently deposited and formed. Further, the dielectric layer 102 can be patterned by known patterning methods such as photomasking, photolithography, microlithography, or the like. The dielectric material is, for example, silicon dioxide (SiO 2 ). For many applications, it is desirable to select a dielectric layer material (often referred to as a low “k” value material) having a low dielectric constant. Low-k materials (ie, below about 3.0) provide better electrical isolation between interconnect lines by reducing capacitance coupling and “crosstalk” between adjacent lines. Such low-k materials include fluorosilicate glass, polyimide, fluorinated polyimide, hybrid / composite, siloxane, organic polymer, [α] -C: F, Si-O-C, parylene / fluorinated. Includes parylene, polytetrafluoroethylene, nanoporous silica, nanoporous organic material, or others.
[0017]
A dielectric layer 102 is formed on the support layer 100. The support layer 100 can be, for example, an underlying semiconductor wafer, a pre-formed dielectric layer, or other semiconductor structure. The support layer 100 can include, for example, silicon and / or various other semiconductor materials, such as gallium arsenide, or others, depending on the particular application.
[0018]
Also, the barrier and / or seed layer 105 may be formed in various ways, for example, chemically, so that the barrier layer covers the patterned dielectric layer 102 including the walls of the dielectric layer 102 in the recessed area 102r. It can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or others. After the metal layer 106 is subsequently deposited, the barrier layer serves to prevent diffusion of metal (eg, copper) into the dielectric layer 102 (FIG. 2B). Any diffusion of copper into the dielectric layer 102 will increase the dielectric constant of the dielectric layer 102 in the negative direction. The barrier / seed layer 105 may be formed from a suitable material that is resistant to copper diffusion, such as titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, or other suitable material. it can. In some applications, the barrier layer can be omitted. For example, the barrier layer can be omitted if the dielectric material is sufficiently resistant to diffusion of the metal layer 106 or if the diffusion of the metal layer 106 does not adversely affect the performance of the semiconductor device.
[0019]
For example, if the metal layer 106 is subsequently electroplated on the dielectric layer 102, a seed layer is typically deposited. Typically, the seed layer is a thin layer of copper or other conductive material on which the metal layer 106 can be electroplated. Further, a single layer or material of the barrier / seed layer 105 can act as both a barrier layer and a seed layer.
[0020]
Referring now to FIG. 2B, a metal layer 106 is deposited on the surface of the barrier / seed layer 105, or on the dielectric layer 102 if the barrier / seed layer 105 is omitted. The metal layer 106 fills the trench or indentation area 102r and covers the non-indentation area 102n. The metal layer 106 can be deposited by PVD, CVD, ALD, electroplating, electroless plating, or other convenient method. The metal layer 106 may be, for example, copper or other suitable conductive material such as aluminum, nickel, chromium, zinc, cadmium, silver, gold, rhodium, palladium, platinum, tin, lead, iron, indium, or others. is there.
[0021]
As shown in FIG. 2B, the topology of the metal layer 106 may not be coplanar with variations in that topology. For example, deposition of the metal layer 106 may result in a hump 108 and / or a recessed portion 112 above various shapes of the dielectric layer 102. In particular, when the metal layer 106 is electroplated on the dielectric layer 102, the hump 108 can be formed above the narrow high density trench region of the dielectric layer 102, and the recessed portion 112 has a wide low density. It can be formed above the trench region. This effect may be particularly prevalent when electroplating the metal layer 106 over the dielectric layer 102 due to plating chemistry. However, the shape and location of the hump 108 and the recessed portion 112 are for illustrative purposes only, and other non-planar topological features of the metal layer 106 are possible as described below with respect to FIGS. 4A and 4B. It should be recognized.
[0022]
Referring now to FIG. 2C, the metal layer 106 is planarized smoothly or topology features are reduced. For example, a chemical mechanical polishing (CMP) process can be applied to the structure to polish and planarize the metal layer 106. The CMP metal layer 106 smoothes the metal layer 106 prior to electropolishing the metal layer 106 by reducing the topology of the metal layer 106, i.e., humps 108, depressions 112, and other non-planar topological features. For example, a CMP process is performed to polish the metal layer 106 to a first height “a” above the underlying support 100, where “a” is a height equal to the height of the dielectric layer 102. higher than b ”. Thus, the CMP process removes the metal layer 106 at a distance from the non-recessed area 102n of the dielectric layer 102 and prevents contact with the dielectric layer 102 if possible. Rather, the CMP process polishes the metal layer 106 to planarize the metal layer 106 and reduce variations in its topology.
[0023]
Referring specifically to the metal layer 106, references to planarization and planarization are not intended or implied that the surface of the metal layer 106 is absolutely planar, but rather the metal layer 106. It should be recognized that it is intended to inform that the surface of the surface is more smooth or flat. In essence, planarization of the surface of the metal layer 106 reduces variations in the topology of the metal layer 106 prior to electropolishing.
[0024]
Since the polishing pad of the CMP apparatus (FIG. 5) does not directly contact the underlying structure, for example, the dielectric layer 102, this example does not emphasize much about the preservation of the dielectric layer 102 and the underlying structure. The CMP process of the method can be optimized for planarization efficiency. For example, the stiffness or hardness of the polishing pad can be adjusted to preserve the underlying dielectric layer 102. In the CMP portion of the example method, a rigid pad with an embedded diamond tip or the like can be used. Further, a polishing process that does not use a slurry or abrasive can be used to reduce scratching in the metal layer 106.
[0025]
Polishing pad pressure may be a factor in controlling and preventing damage to the patterned dielectric layer 102 and interconnect structures, particularly for integrated schemes using copper and low-k dielectric films. Typically, the pressure of the polishing pad is in the range of 0.1 pound-force / square inch (PSI) to 10 PSI, for example, 5 PSI. The thickness of the metal layer 106 removed during the CMP process depends at least in part on the topology of the metal layer 106 formed on the dielectric layer 102 and the planarization efficiency of the CMP process used. Typically, the removed thickness is greater than or equal to the difference between the high and low points of the metal layer topology.
[0026]
It should be appreciated that the CMP process is described herein for illustrative purposes only. Alternative methods of planarizing the metal layer 106 can be used in place of or in conjunction with the typical CMP process described above. For example, a sacrificial material is added on the metal layer 106 to planarize the surface above the metal layer 106. The sacrificial material can be a conductive or non-conductive material, such as spin-on-glass, photoresist, metal alloy, metal compound, or the like. The metal layer 106 can then be planarized, for example, by etching away the sacrificial material and a portion of the metal layer 106. The sacrificial material and the metal layer 106 should have the same or similar etch rate so that the etching process removes the sacrificial layer and the metal layer 106 at a similar rate. Etching the planarized metal layer 106 and the sacrificial layer at a similar rate to remove the sacrificial layer and a portion of the metal layer 106 results in a planarized metal layer 106. An example of this process is depicted in FIG. 4A and described below.
[0027]
The etching process can be a dry etching process or a wet etching process. Dry etching processes include plasma etching, chemical vapor etching, and others. Plasma etch sources can include high density plasma sources, such as helicon plasma sources, inductively coupled plasma sources (ICPs), and others. The etching gas can include a halogen group, for example, a chlorine based gas. Two examples of plasma etching process conditions are detailed in the table below:
[0028]
[Table 1]
[0029]
[Table 2]
[0030]
After step 1, the upper part of copper and copper compound is copper chloride (CuCl x ) Will be converted.
Step 2:
CuCl by using dilute HCl solution x The compound is wet etched. The HCl concentration can range from 1 to 6 wt%, preferably 3 wt%.
[0031]
Optionally, after plating the metal layer 106, following a planarization technique similar to that used in the flat panel display industry to anneal amorphous Si (a-Si) to poly-Si on glass, A laser can be used to reflow the copper to relax the metal layer 106 and produce a planarized surface. Another alternative involves a high frequency, short pulse laser that can radiate from a direction parallel to the support 100 to remove higher portions of the metal layer 106 by evaporation. A short pulse of the laser is used to protect most copper and the surrounding dielectric material from the high temperature effects generated by the laser, i.e., reduce thermoelectric costs. The laser is a solid laser, such as a ruby laser, Nd-glass laser, Nd: YAG (yttrium aluminum garnet, Y Three Al Five O 12 ) Laser, gas laser, eg He-Ne laser, CO 2 It can be a laser, HF laser, or others. The metal layer 106 is planarized by scanning the entire surface of the support 100 with a laser beam. Further, in such a process, a non-contact surface topology sensor can be used as an endpoint detector. Typical conditions for this planarization process are detailed in the following table:
[0032]
[Table 3]
[0033]
Next, referring to FIG. 2D, after the metal layer 106 is planarized, the metal layer 106 is electropolished. Specifically, the metal layer 106 is electropolished from the non-recessed area 102n of the dielectric layer 102 so that the metal layer 106 is isolated within the recessed area 102r or trench to form an interconnect line. The metal layer 106 can be polished to the same height as the non-recessed area. Optionally, the metal layer 106 can be polished to a height below the non-recessed area. The metal layer 106 can be electropolished by an electropolishing apparatus that directs the flow of electrolyte fluid (not shown) to the metal layer 106 (FIG. 6). The electrolyte fluid can be, for example, any convenient electrolyte fluid such as phosphoric acid, orthophosphoric acid (H Three PO Four ), Or other.
[0034]
Further, the barrier / seed layer 105 is removed from the exposed region of the non-recessed area 102n of the dielectric layer 102. If layer 105 is or includes a seed layer, for example, an electropolishing process that polishes metal layer 106 can remove it. If layer 105 is or includes a barrier layer, it can be removed, for example, by plasma dry etching, wet etching or the like. In addition, if the metal layer 106 is electropolished to a lower height than the non-recessed area, the non-recessed area can be etched at this time to planarize the surface. The following table, Table 4, provides a typical range of parameters that can be used in the plasma dry etching process to remove the barrier layer:
[0035]
[Table 4]
[0036]
These parameters are the possible dielectric layer 102 material SiO 2 Yields removal rates of the two possible barrier layers 105, TaN and TiN, greater than the removal rate of. Selectivity can be selected in this manner to reduce etching or damage of the underlying dielectric layer 102 during removal of the barrier layer 105. However, it should be noted that other selectivities can be obtained by changing the parameters.
[0037]
FIG. 3 is a flowchart illustrating an exemplary damascus process 300 that includes a planarization process and an electroplating process. A wafer having a recessed area and a non-recessed area is prepared at block 302. A patterned dielectric layer prepared on the wafer can define indented and non-indented areas. A patterned dielectric layer can be formed on an underlying semiconductor structure, including other previously formed dielectric layers, wafers, or the like. In addition, the wafer can be divided into individual dice including recessed and non-recessed areas that will be separated into individual semiconductor devices in a post-processed state. The metal layer is then deposited at block 304 so that the metal layer fills the recessed areas in the dielectric layer as well as covers the non-recessed areas of the dielectric layer. The metal layer is then planarized at block 306. For example, the metal layer is subjected to a CMP process to planarize and smooth the topology of the metal layer. The planarized metal layer is then electropolished at block 308 to expose the non-recessed areas of the dielectric layer and isolate the metal layer within the recessed areas to form metal interconnect lines.
[0038]
It should be appreciated that many changes can be made to the exemplary process 300 depicted in the flowchart. For example, after the barrier / seed layer is added as needed, a metal layer is deposited at block 304, where the barrier / seed layer is etched from the dielectric layer after exposing the non-recessed areas. . In addition, each block in FIG. 3 performs a number of processes not explicitly described herein, such as masking and etching to form recessed areas, or cleansing of the metal layer before and / or after surface planarization. Can be included. Further, the typical Damascus process 300 is applicable to both single and double embedded processes.
[0039]
4A and 4B illustrate additional exemplary topologies of the metal layer 106 that can be planarized and then electropolished to form an interconnect structure. Referring to FIG. 4A, the metal layer 106 has a topology that roughly corresponds to the shape of the underlying dielectric layer 102. Such a topology could be created, for example, by sputtering a metal layer 106 over the dielectric layer 102. The sacrificial material 107 is then added, and the metal layer 106 is then planarized by etching the sacrificial material 107 and a portion of the metal layer 106 such that the metal layer 106 is planarized to the dashed line “P”. As described above, the sacrificial material 107 can be a metal, a metal-solvent complex, a copper-solvent complex, spin-on-glass, photoresist, or the like. The sacrificial material 107 can be any material having an etch rate similar to that of the underlying metal layer 106, and the etching process has no selectivity between the sacrificial material 107 and the metal layer 106, and is conventional. It can be dry or wet etching.
[0040]
The position of the line “P” is for illustrative purposes only and can be adjusted up or down depending on the application and planarization method. After the topological features of the metal layer 106 are planarized, the metal layer 106 is then electropolished as described above with respect to FIG. 2D, as in FIG. 2C.
[0041]
FIG. 4B illustrates another exemplary metal layer 106 having an irregular surface topology. The irregular surface topology of the metal layer 106 may be due to a number of causes ranging from the deposition process to the underlying structure. The metal layer 106 is first polished as in FIG. 4A by planarizing the surface to line “P”, adding a sacrificial material, etching back, and heating the metal layer 106 for some time with a laser or the like. Next, the metal layer 106 is electropolished. From FIGS. 4A and 4B, it should be appreciated that a number of metal layers can be planarized and electropolished without undue damage to the underlying dielectric layer 102 by this method.
[0042]
Referring now to FIG. 5, an exemplary CMP apparatus 400 and process is described. A CMP apparatus 400 can be used to planarize the metal layer 106. A typical CMP process proceeds by pressing and rotating the wafer surface against a wet polishing surface. This process is controlled by the chemical, pressure, and temperature conditions of the CMP apparatus 400. A typical CMP apparatus 400 includes a rotatable polishing platen 411 and a polishing pad 412 mounted on the polishing platen 411. The CMP apparatus 400 also includes a rotatable wafer carrier 413. Wafer carrier 413 positions wafer 401 and applies force to wafer 401 in the direction indicated by arrow 414. Chemical slurry is applied to the CMP apparatus 400 through the nozzle 417 and dispensed onto the polishing pad 412. Chemical slurry is fed through nozzle 417 from a temperature controlled reservoir (not shown), for example. In addition, the chemical slurry contains an abrasive, such as alumina, silica, or the like, which is used as an abrasive with other selected chemicals to polish the surface of the wafer 401.
[0043]
The main parameters that affect the polishing rate are the downward pressure 414 on the wafer 401 relative to the polishing pad 414, the rotational speed of the polishing platen 411 and wafer carrier 413, the composition and temperature of the chemical slurry, and the polishing pad 412 Composition. Adjustment of these parameters makes it possible to control the polishing rate and the planarization efficiency of the CMP apparatus 400.
[0044]
The CMP apparatus 400 and process described with reference to FIG. 5 is for illustrative purposes only. It should be appreciated that other CMP apparatus configurations and configurations can be used. For example, instead of the rotatable polishing platen 411 and polishing pad 412, a belt that moves the polishing pad 412 relative to the wafer carrier 413 can be used. Also, as will be appreciated, movement of the wafer 401 relative to the polishing pad 412 can be accomplished in a number of ways. Accordingly, the CMP apparatus 400 depicted in FIG. 5 is not intended to limit the CMP apparatus or method that can be used.
[0045]
FIG. 6 is a typical cross-sectional view of an electropolishing apparatus 500 that can be used for electropolishing a metal layer 506 formed on a semiconductor wafer 501. The semiconductor wafer 501 can further include, for example, a support layer 100, a dielectric layer 102, and a barrier / seed layer 105 (FIGS. 2A-2D). Further, the topology of the metal layer 506 will be planarized by, for example, a CMP apparatus 400 (FIG. 5) prior to electropolishing.
[0046]
The nozzle 540 of the electropolishing apparatus 500 directs the flow of the electrolyte fluid 520 toward the surface of the metal layer 506. In other examples, the wafer 501 can be fully or partially immersed in the electrolyte fluid 520. The electrolyte fluid 520 can be any conventional electropolishing fluid such as phosphoric acid, orthophosphoric acid (H Three PO Four ), Or others. For example, in one example, the electrolyte fluid is orthophosphoric acid at a concentration of about 60 wt% to about 85 wt%. Further, the electrolyte fluid 520 can include, for example, 10-40% (based on acid mass) glycol. However, it should be recognized that the concentration and composition of the electrolyte fluid can be varied depending on the particular application.
[0047]
When the electropolishing apparatus 500 directs the flow of the electrolyte fluid 520 to the metal layer 506, the power supply 550 counters the electrode 530 (cathode) positioned in the nozzle 540 and the electrode (anode) coupled to the metal layer 506. To supply the charge. The power supply device 550 can operate, for example, in a constant current or constant voltage mode. A power supply 550 configured to positively charge the electrolyte fluid 520 with respect to the metal layer 506 is used to remove metal ions from the metal layer 506 from the surface. In this method, the flow of electrolyte fluid 520 electropolishes the portion of metal layer 506 that contacts it.
[0048]
Further, as depicted in FIG. 6, the wafer 501 is rotated and translated along the axis X to locate the surface of the metal layer 506 during the flow of the electrolyte fluid 520 and to electrolyze the surface uniformly. Grind. For example, by rotating the wafer 501 and simultaneously translating the wafer 501 in the X direction, the electrolyte fluid 520 can follow a spiral path along the surface of the metal layer 506. Optionally, the nozzle 540 is moved while holding the wafer 501 stationary to apply a flow of electrolyte fluid 520 to the required portion of the metal layer 506. Further, both the wafer 501 and the nozzle 540 can be moved to apply a flow of electrolyte fluid 520 to the required portion of the metal layer 506. Exemplary descriptions of electropolishing methods and apparatus are described in the following US patent applications and patent specifications: US Patent Application No. 09 / 497,894, entitled “Electropolishing Metal Interconnects on Semiconductor Devices” Method and apparatus ", filed Feb. 4, 2000, and U.S. Patent No. 6,395,152, entitled" Method and apparatus for electropolishing metal interconnects on semiconductor elements ", filed July 2, 1999, them Both of which are hereby incorporated by reference.
[0049]
In addition, it should be recognized that the metal layer 106 can be electropolished using other electropolishing methods and apparatus. For example, the wafer 501 including the metal layer 506 can be partially or fully immersed in a bath of electrolyte fluid.
[0050]
The above description is provided to illustrate exemplary aspects and is not intended to be limiting. As those skilled in the art will appreciate, many modifications and variations are possible within the scope of the present invention. For example, a number of interconnected structures formed in a single or double embedded damascus tool, such as a combination of dielectric layers, barrier layers, seed layers, and mask layers are described. Can be planarized and electropolished in accordance with other methods. In addition, a number of planarization and electropolishing methods can be combined to planarize and electropolish the interconnect structure. Also, as will be apparent to those skilled in the art, a metal layer having a non-planar topology created for reasons other than those described herein can be conveniently planarized according to the methods and apparatus described herein. And electropolishing. Accordingly, the present invention is defined by the appended claims and is not limited by the description herein.
[Brief description of the drawings]
[0051]
FIGS. 1A-1B illustrate an exemplary electropolishing process for a semiconductor device.
FIGS. 2A-2D illustrate an exemplary planarization and electropolishing process of a semiconductor device.
FIG. 3 illustrates a flowchart of a typical damascus process.
FIGS. 4A-4B illustrate a typical topology of a metal layer formed on a semiconductor structure that can be planarized and polished.
FIG. 5 shows a cross-sectional view of a typical chemical mechanical polishing apparatus.
FIG. 6 shows a cross-sectional view of an electropolishing apparatus.

Claims (69)

  1. A method of forming a semiconductor structure, comprising:
    Forming a dielectric layer on the semiconductor wafer, wherein the dielectric layer includes recessed and non-recessed areas;
    Forming a conductive layer on the dielectric layer to cover the indented and non-indented areas;
    Planarizing the surface of the conductive layer to reduce variations in the topology of the surface of the conductive layer, and after planarizing the surface of the conductive layer, electropolishing the conductive layer to expose non-recessed areas ,
    Comprising the steps of:
  2. The method of claim 1, wherein the step of planarizing the surface of the conductive layer comprises chemical mechanical polishing (CMP) of the conductive layer.
  3. The method of claim 2, wherein CMP planarizes the surface of the conductive layer without exposing non-recessed areas of the conductive layer.
  4. The method of claim 2, wherein the CMP comprises a polishing pad and the polishing pad does not contact non-recessed areas of the conductive layer.
  5. The method of claim 2, wherein the CMP comprises a slurry-free polishing process.
  6. Planarizing the surface of the conductive layer forms a sacrificial material on the surface of the conductive layer, wherein the sacrificial material is planarized, and etching the sacrificial material and a portion of the conductive layer. The method of claim 1 comprising:
  7. The method of claim 6, wherein the etching step has no selectivity between the sacrificial material and the conductive layer.
  8. The method of claim 6, wherein the sacrificial material is spin-on-glass.
  9. The method of claim 1, wherein the step of forming the conductive layer includes deposition of the conductive layer.
  10. The method of claim 1, wherein the step of forming the conductive layer includes electroplating of the conductive layer.
  11. The method of claim 1, further comprising forming a seed layer disposed between the conductive layer and the dielectric layer.
  12. The method of claim 11, wherein the electropolishing step removes a portion of the seed layer from the non-recessed area.
  13. The method of claim 1, wherein the electropolishing step includes directing a flow of electrolyte fluid to the conductive layer surface.
  14. The method of claim 1, wherein the electropolishing step comprises immersing at least a portion of the conductive layer in an electrolyte fluid.
  15. The method of claim 1, further comprising forming a barrier layer disposed between the conductive layer and the dielectric layer.
  16. The method of claim 15, wherein the barrier layer is removed from the non-recessed area of the dielectric layer by plasma dry etching.
  17. The method of claim 15, wherein the barrier layer is removed from the non-recessed area of the dielectric layer by wet etching.
  18. The method of claim 1, wherein the conductive layer is copper.
  19. The method of claim 1, wherein the conductive layer is planarized to a first height and electropolished to a second height, wherein the second height is less than the first height.
  20. 20. The method of claim 19, wherein the second height is flush with the height of the non-recessed area.
  21. The method of claim 19, wherein the second height is less than the height of the non-recessed area.
  22. A method of manufacturing a semiconductor device, comprising forming a dielectric layer on a semiconductor structure, wherein the dielectric layer includes a recessed area and a non-recessed area.
    Forming a conductive layer to cover the dielectric layer and filling the non-recessed area;
    Planarizing the surface of the conductive layer to a first height above the semiconductor structure, wherein the first height is greater than the height of the non-recessed area and the surface of the conductive layer is above the semiconductor structure; Electropolishing to a height of 2, wherein the second height is less than the first height.
  23. 23. The method of claim 22, wherein the second height is flush with the height of the non-recessed area.
  24. 24. The method of claim 22, wherein the second height is less than the height of the non-recessed area.
  25. 24. The method of claim 22, wherein the step of planarizing the conductive layer comprises chemical mechanical polishing (CMP) of the conductive layer.
  26. 26. The method of claim 25, wherein the CMP does not expose structures underlying the conductive layer.
  27. 26. The method of claim 25, wherein the CMP includes a polishing pad, and the polishing pad does not contact the structure underlying the conductive layer.
  28. 26. The method of claim 25, wherein CMP comprises a slurry-free polishing process.
  29. Planarizing the conductive layer surface forms a sacrificial material on the conductive layer surface, wherein the sacrificial material is planarized, and etching the sacrificial material and the conductive layer, wherein the sacrificial material 23. The method of claim 22, comprising the step of: no selectivity between the conductive layer and the conductive layer.
  30. 30. The method of claim 29, wherein the sacrificial material is spin-on-glass.
  31. 23. The method of claim 22, wherein the step of forming the conductive layer includes deposition of the conductive layer.
  32. 24. The method of claim 22, wherein the step of forming the conductive layer includes electroplating of the conductive layer.
  33. 23. The method of claim 22, further comprising forming a seed layer disposed between the conductive layer and the dielectric layer.
  34. 34. The method of claim 33, wherein the electropolishing step removes a portion of the seed layer from the non-recessed area.
  35. 23. The method of claim 22, wherein the electropolishing step includes directing a flow of electrolyte fluid to the conductive layer surface.
  36. 23. The method of claim 22, wherein the electropolishing step comprises immersing at least a portion of the conductive layer in an electrolyte fluid.
  37. 23. The method of claim 22, further comprising forming a barrier layer disposed between the conductive layer and the dielectric layer.
  38. 38. The method of claim 37, wherein the barrier layer is removed from the non-recessed area of the dielectric layer by plasma dry etching.
  39. 38. The method of claim 37, wherein the barrier layer is removed from the non-recessed areas of the dielectric layer by wet etching.
  40. 24. The method of claim 22, wherein the conductive layer is copper.
  41. A method of making an interconnect structure,
    Forming a semiconductor structure, wherein the semiconductor structure is patterned with openings to form interconnects;
    Forming a conductive layer on the semiconductor structure and in the opening;
    Planarizing the surface of the conductive layer to reduce non-planar variations and electropolishing the planarized conductive layer to isolate the conductive layer in the opening.
  42. 42. The method of claim 41, wherein the semiconductor structure includes a dielectric layer having an opening formed therein.
  43. 43. The method of claim 42, wherein the semiconductor structure further comprises a barrier layer formed between the dielectric layer and the conductive layer.
  44. 44. The method of claim 43, wherein the barrier layer is removed from a portion of the dielectric layer by plasma dry etching.
  45. 44. The method of claim 43, wherein the barrier layer is removed from a portion of the dielectric layer by wet etching.
  46. 43. The method of claim 42, further comprising forming a seed layer disposed between the conductive layer and the dielectric layer.
  47. The method of claim 46, wherein the electropolishing step removes a portion of the seed layer.
  48. 42. The method of claim 41, wherein the step of planarizing the conductive layer surface comprises chemical mechanical polishing (CMP) of the conductive layer.
  49. 49. The method of claim 48, wherein the CMP does not expose structures underlying the conductive layer.
  50. 49. The method of claim 48, wherein the CMP includes a polishing pad, and the polishing pad does not contact the structure underlying the conductive layer.
  51. 49. The method of claim 48, wherein the CMP comprises a slurry-free polishing process.
  52. The step of planarizing the surface of the conductive layer includes
    Forming a sacrificial material on the surface of the conductive layer, wherein the sacrificial material is planarized, and etching the sacrificial material and a portion of the conductive layer, wherein the sacrificial material is between the conductive material and the conductive layer; 42. The method of claim 41, wherein the method comprises a step of no selectivity.
  53. 53. The method of claim 52, wherein the sacrificial material is spin-on-glass.
  54. 42. The method of claim 41, wherein the step of forming the conductive layer includes deposition of the conductive layer.
  55. 42. The method of claim 41, wherein the step of forming the conductive layer includes electroplating of the conductive layer.
  56. 42. The method of claim 41, wherein the electropolishing step includes directing a flow of electrolyte fluid to the conductive layer surface.
  57. 42. The method of claim 41, wherein the electropolishing step comprises immersing at least a portion of the conductive layer in an electrolyte fluid.
  58. 42. The method of claim 41, wherein the conductive layer is copper.
  59. A conductive layer and a dielectric layer having recessed and non-recessed areas,
    Here, the conductive layer fills the non-recessed areas to form interconnect lines, and the non-recessed areas are exposed by planarizing the conductive layer surface and then electropolishing the conductive layer surface. Semiconductor structure.
  60. 60. The structure of claim 59, wherein the conductive layer is planarized by chemical mechanical polishing (CMP).
  61. 61. The structure of claim 60, wherein the CMP does not expose non-recessed areas of the dielectric layer.
  62. The conductive layer is
    61. The structure of claim 60, wherein the structure is planarized by forming a planar sacrificial material on the surface of the conductive layer and etching the sacrificial material and a portion of the conductive layer.
  63. 64. The structure of claim 62, wherein the etching step has no selectivity between the sacrificial material and the conductive layer.
  64. 64. The structure of claim 62, wherein the sacrificial material comprises spin-on-glass.
  65. 64. The structure of claim 62, wherein the sacrificial material comprises a photoresist.
  66. 64. The structure of claim 62, wherein the sacrificial material comprises a metal.
  67. A semiconductor structure formed by the method of claim 1.
  68. 23. A semiconductor device formed according to the method of claim 22.
  69. 42. A semiconductor structure formed on a semiconductor wafer by the method of claim 41.
JP2003522140A 2001-08-17 2002-08-15 Formation of semiconductor structures using a combination of planarization and electropolishing. Pending JP2005500687A (en)

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CN103692293B (en) * 2012-09-27 2018-01-16 盛美半导体设备(上海)有限公司 non-stress polishing device and polishing method
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