WO2016125485A1 - Dispositif de traitement de signal et procédé de traitement de signal - Google Patents

Dispositif de traitement de signal et procédé de traitement de signal Download PDF

Info

Publication number
WO2016125485A1
WO2016125485A1 PCT/JP2016/000521 JP2016000521W WO2016125485A1 WO 2016125485 A1 WO2016125485 A1 WO 2016125485A1 JP 2016000521 W JP2016000521 W JP 2016000521W WO 2016125485 A1 WO2016125485 A1 WO 2016125485A1
Authority
WO
WIPO (PCT)
Prior art keywords
correction
error
signal processing
signal
error correction
Prior art date
Application number
PCT/JP2016/000521
Other languages
English (en)
Japanese (ja)
Inventor
正夫 森江
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2016573224A priority Critical patent/JP6365695B2/ja
Publication of WO2016125485A1 publication Critical patent/WO2016125485A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present invention relates to a signal processing device and a signal processing method, and more particularly, to a signal processing device and a signal processing method capable of reducing power consumption.
  • a coherent optical receiver is used to demodulate signal light.
  • FIG. 10 is a block diagram showing a configuration of a general coherent optical receiver 800.
  • the coherent optical receiver 800 includes a front end 801, an analog-digital converter (ADC) 802, a local oscillation light source 803, and a signal processor (digital signal processor (DSP) 900).
  • the local oscillation light source 803 is a light source, for example, a semiconductor laser.
  • the front end 801 outputs a beat signal between the local oscillation light and the signal light output from the local oscillation light source 803 as an analog reception signal.
  • the front end 801 has a known configuration including, for example, a beam splitter, a 90-degree hybrid, and a photodiode.
  • the analog reception signal is converted into a digital reception signal by the ADC 802.
  • the digital received signal is input to the DSP 900.
  • the DSP 900 outputs data obtained by performing arithmetic processing on the digital reception signal as reception data.
  • the DSP 900 also performs error correction on the digital received signal.
  • an error correction code called an LDPC (low density parity check) code may be used.
  • FIG. 11 is a block diagram showing a configuration of a general DSP 900 used in the coherent optical receiver 800.
  • the DSP 900 includes a demodulation unit 901, an error correction unit 902, and a framer 903.
  • the demodulator 901 performs symbol determination on the digital reception signal input from the ADC 802 and generates digital data.
  • the error correction unit 902 corrects an error in the demodulated digital data.
  • the framer 903 converts the digital data into received data having a frame of a predetermined format and outputs the received data.
  • Patent Document 1 describes a decoding device that decodes an LDPC code frame by frame.
  • the error correction unit 902 performs error correction processing on the input digital data.
  • the error correction unit 902 consumes constant power regardless of the load. For this reason, the DSP 900 described in FIGS. 10 and 11 has a problem of high power consumption and a large amount of heat generation. Further, the DSP 900 has a problem that the design cost and the parts cost for driving and cooling the DSP 900 are high. On the other hand, if the scale of the error correction unit 902 is reduced in order to reduce power consumption, the necessary error correction capability may not be ensured.
  • An object of the present invention is to provide a signal processing device and a signal processing method capable of achieving both reduction of power consumption and ensuring of error correction capability.
  • a signal processing apparatus includes: an error correction unit in which a plurality of calculation units that perform error correction of an input signal are connected in series; an error correction unit that is connected in parallel; and the calculation unit for the signal Control means for controlling the operating state of each of the correction blocks based on the number of error corrections.
  • the signal processing method of the present invention performs error correction of a signal input by an error correction unit in which a correction block in which a plurality of calculation units are connected in series is connected in parallel, and the signal in any of the calculation units The operation state of each of the correction blocks is controlled based on the number of error corrections.
  • the signal processing apparatus and the signal processing method of the present invention have an effect that it is possible to achieve both reduction of power consumption and securing of error correction capability.
  • DSP common signal processor
  • FIG. 1 is a block diagram illustrating a configuration of a signal processing device 100 according to the first embodiment.
  • the signal processing apparatus 100 of the present embodiment is a signal processing processor (digital signal processor, DSP) mounted on an optical receiver.
  • a digital received signal is input to the signal processing apparatus 100.
  • the digital reception signal is a signal obtained by digitizing an analog reception signal obtained by photoelectrically converting signal light at the front end of the optical receiver by the ADC.
  • the digital received signal includes phase information of phase-modulated signal light.
  • the signal processing apparatus 100 demodulates the digital received signal, corrects the error, puts it on a frame of a predetermined format, and outputs it as received data.
  • the signal processing apparatus 100 includes a demodulation unit 101, an error correction unit 102, a framer 103, and a control unit 104.
  • the demodulator 101 performs symbol determination on the digital reception signal input from the ADC and converts it into digital data.
  • the error correction unit 102 corrects digital data errors.
  • the framer 103 converts the digital data into frame data of a predetermined format and outputs it as received data.
  • the demodulator 101 is sometimes called a de-mapper. Since the configurations and operations of the demodulator 101 and the framer 103 are known, detailed description thereof will be omitted.
  • the control unit 104 controls the operation of each unit of the signal processing apparatus 100.
  • the control unit 104 may control the operation of the signal processing device 100 by executing a program as a central processing unit (central processing unit, CPU).
  • the program is recorded on a fixed recording medium provided inside or outside the signal processing apparatus 100.
  • the recording medium is, for example, a semiconductor memory, a magnetic fixed disk, or an optical disk, but is not limited thereto.
  • the control unit 104 is described as a block independent of the demodulation unit 101, the error correction unit 102, and the framer 103. However, the function of the control unit 104 may be included in any of the functions of the demodulation unit 101, the error correction unit 102, and the framer 103.
  • the control unit 104 may be provided outside the signal processing apparatus 100 and may remotely control the demodulation unit 101, the error correction unit 102, and the framer 103.
  • the error correction unit 102 performs error correction on digital data using soft-decision forward error correction (SD-FEC).
  • SD-FEC soft-decision forward error correction
  • An error correction code called a low density parity check (LDPC) code is used as an error correction code for digital data.
  • the LDPC code can be decoded at high speed by parallel processing.
  • FIG. 2 is a block diagram illustrating a configuration of the error correction unit 102 included in the signal processing apparatus 100.
  • the error correction unit 102 includes N (N is a natural number) correction blocks 301 to 30N.
  • the error correction unit 102 performs error correction on the digital data input from the demodulation unit 101, and outputs the corrected digital data to the framer 103.
  • the error correction unit 102 performs error correction by using the correction blocks 301 to 30N connected in parallel. For example, the error correction unit 102 divides digital data in time according to the number of correction blocks in operation, and distributes the data so that the amount of data input to each of the correction blocks in operation is equal. Perform block load balancing. However, the load distribution procedure for the correction block is not particularly limited.
  • the error correction unit 102 combines the digital data output from each correction block in time series order and outputs the combined data to the framer 103.
  • the control unit 104 may control such distribution, division, and combination of digital data with respect to the error correction unit 102. In this case, the control unit 104 dynamically distributes the digital data only to the correction block being operated. In this embodiment, digital data is not input to a correction block that is not operating.
  • FIG. 3 is a block diagram illustrating a configuration of the correction block 301 included in the error correction unit 102.
  • the correction block 301 is described as an example, but the other correction blocks 302 to 30N have the same configuration.
  • the correction block 301 includes M (M is a natural number) arithmetic units 401 to 40M.
  • the arithmetic units 401 to 40M are connected in series inside the correction block 301.
  • any of the correction blocks 301 to 30N includes M operation units.
  • the number M of the calculation units may not be the same in each of the correction blocks 301 to 30N.
  • the digital data input from the demodulator 101 is first subjected to error correction processing in the arithmetic unit 401. If an error remains as a result of the error correction processing in the calculation unit 401, the calculation unit 402 further performs error correction.
  • the correction block 301 performs error correction processing on the digital data using the M arithmetic units, and outputs the processed digital data to the framer 103.
  • the other correction blocks 302 to 30N included in the error correction unit 102 also perform error correction processing on the digital data, and output the processed digital data to the framer 103.
  • the correction block 301 shown in FIG. 3 further has a function of outputting the number of error corrections in the arithmetic units 401 to 40M to the control unit 104.
  • the number of error corrections is, for example, the number of error corrections of each arithmetic unit per fixed time or the number of error corrections per fixed amount of data, but is not limited thereto.
  • the control unit 104 collects the number of error corrections of the calculation units 401 to 40M for each of the correction blocks 301 to 30N.
  • FIG. 4 is a graph showing an example of the number of error corrections of the arithmetic units 401 to 40M included in the correction block 301.
  • the vertical axis of FIG. 4 indicates the number of error corrections of the arithmetic units 401 to 40M, and the horizontal axis indicates the number of stages of the arithmetic units.
  • the number of error corrections is an arbitrary scale.
  • the number of stages in the calculation unit is a number in which the input side of digital data is 1, and the output side (final stage) is M, and corresponds to the calculation units 401, 402,.
  • the arithmetic units 401 to 403 close to the input of the correction block 301 have a relatively large number of error corrections, and the arithmetic units close to the output of the correction block 301 have a small number of error corrections. This is because the error of the received data generally decreases as it approaches the output of the correction block due to a plurality of error correction processes in the arithmetic unit.
  • the control unit 104 controls the operation state of the correction blocks 301 to 30N based on the number of error corrections of the arithmetic units 401 to 40M output from each of the correction blocks 301 to 30N.
  • the control unit 104 determines the error of the correction block including the calculation unit. Stop the correction process.
  • the control unit 104 distributes digital data to correction blocks for which error correction processing has not been stopped, and does not distribute digital data to correction blocks for which error correction processing has been stopped.
  • stopping (or operating) the error correction processing of the correction block is simply referred to as “stopping (or operating) the correction block”.
  • the control unit 104 may operate or stop each correction block by executing or stopping power supply for each correction block. Note that the control unit 104 may continue the distribution of digital data to correction blocks with sufficiently few errors and stop only error correction processing of the correction blocks.
  • the control unit 104 stops the correction block 302. Then, the control unit 104 continues the digital data error correction processing by parallel processing using the remaining correction blocks 301 and 303 to 30N. As described above, the control unit 104 can suppress the power consumption of the error correction unit 102 by stopping the correction blocks having a small number of error corrections (that is, the load of error correction is small).
  • FIG. 5 is a diagram illustrating an example of an operation state of the correction blocks 301 to 30N when the load of the error correction unit is small.
  • the stopped correction blocks are indicated by broken lines.
  • the number of error corrections output from the operation unit 40M at the last stage of the correction block 301 shown in FIG. 5 is equal to or greater than the first threshold.
  • the number of error corrections output from the final stage calculation unit 40M of each of the correction blocks 302 to 30N is less than the first threshold value. Therefore, the control unit 104 operates the correction block 301 and stops the correction blocks 302 to 30N. By stopping the correction blocks with a light load among the correction blocks 301 to 30N, power consumption and heat generation of the error correction unit 102 are suppressed.
  • the control unit 104 gives an instruction to start error correction processing to one of the stopped correction blocks.
  • the second threshold is greater than the first threshold.
  • the control unit 104 starts the operation of the correction block 302. Then, the control unit 104 continues digital data error correction processing by parallel processing using the correction blocks 301 and 302.
  • the control unit 104 ensures the necessary error correction capability by resuming the operation of the stopped correction block. Note that the number of correction blocks whose operations are started simultaneously may not be one.
  • the control unit 104 defines in advance A correction block for starting the operation may be selected based on the determined priority.
  • the control unit 104 starts the operation of, for example, the correction block that has been stopped in the past among the correction blocks that have been stopped.
  • FIG. 6 is a diagram illustrating an example of an operation state of the correction blocks 301 to 30N when the load of error correction processing is large.
  • the load of the final stage operation unit of each of the correction blocks 301 to 30N shown in FIG. 6 is equal to or greater than the first threshold value.
  • the control unit 104 operates all of the correction blocks 301 to 30N. In this way, the error correction processing capability of the error correction unit 102 is ensured.
  • FIG. 7 is a diagram showing another example of the operation state of the correction blocks 301 to 30N.
  • the correction blocks 304 to 30N are stopped because the number of error corrections in the last-stage arithmetic unit has become less than the first threshold in the past.
  • the number of error corrections at the last stage of the correction blocks 301 to 303 is not less than the first threshold and not more than the second threshold.
  • the correction blocks 301 to 303 operate and the correction blocks 304 to 30N are stopped. Since the number of error corrections in the last calculation unit of the correction blocks 301 to 303 is less than or equal to the second threshold value, the control unit 104 does not instruct the correction blocks 304 to 30N to start the operation.
  • the number of error corrections used for determining the load of error correction processing is not limited to the number of error corrections of the last-stage arithmetic unit 40M.
  • the control unit 104 corrects the correction based on the comparison result between the first and second threshold values and the total, average value, or maximum value of the number of error corrections of the plurality of arithmetic units located in the last stage and the preceding stage. An increase or decrease in the error correction load of the block may be determined. Further, the control unit 104 obtains the total, average value, or maximum value of the number of error corrections of all the calculation units 401 to 40M for each correction block, and based on the comparison result between these values and the first and second threshold values. Thus, an increase or decrease in error correction load of the correction block may be determined.
  • control unit 104 controls the operation state of each correction block based on the number of error corrections in any of the arithmetic units. Specifically, the control unit 104 dynamically changes the number of correction blocks to be operated from 1 to N based on the comparison result between the number of error corrections of the arithmetic unit and a predetermined threshold value.
  • FIG. 8 is a flowchart showing an example of control of the error correction unit 102 by the control unit 104.
  • the procedure of steps S11 to S15 is started at the start of the operation of the correction blocks 301 to 30N, and is performed in parallel with the correction blocks 301 to 30N being operated.
  • the control unit 104 collects the number of error corrections P output from the calculation units 401 to 40M included in the correction blocks 301 to 30N, respectively (Step S11 in FIG. 8).
  • the control unit 104 determines whether the error correction number P is less than the first threshold (S12).
  • the first threshold is a threshold for determining whether or not to stop the operation of the correction block because the error correction processing load is low.
  • the error correction number P the error correction number of the arithmetic unit 40M at the last stage (M stage) of each correction block may be used.
  • the control unit 104 stops the correction block including the arithmetic unit that has output the error correction number P (S13). The power consumption of the error correction unit 102 is suppressed by stopping the correction block.
  • step S13 The correction block stopped in step S13 is stopped until an operation start instruction is received from the control unit 104 in step S15 described below. For this reason, the flow of FIG. 8 with respect to the said correction block is once complete
  • the control unit 104 instructs the correction block whose operation is to be restarted to start the procedure from step S15.
  • the correction block stopped in step S13 receives an operation start instruction from the control unit 104, the correction block resumes operation (S15 to S11).
  • step S13 all the correction blocks of the error correction unit 102 may be stopped due to the stop of the correction block. In such a case, the control unit 104 does not have to stop the correction block regardless of the determination result of step S12.
  • the control unit 104 determines whether or not the error correction number P exceeds the second threshold value (S14).
  • the second threshold value is a threshold value for determining whether to start the operation of another correction block that is stopped because the load of error correction processing is high, and is larger than the first threshold value.
  • the error correction number P the error correction number of the operation unit 40M at the last stage of each correction block may be used.
  • the control unit 104 selects one or more stopped correction blocks and starts the operation of the selected correction block (S15).
  • control unit 104 selects a correction block whose operation is to be restarted based on, for example, a predetermined priority order.
  • the control unit 104 does not instruct the stopped correction block to start the operation.
  • step S14 When the error correction number P is equal to or greater than the first threshold value, the operation of the correction block in which the error correction number P is output and the control unit 104 regardless of the comparison result with the second threshold value in step S14.
  • the collection of the number of error corrections P of the correction block according to is continued. That is, after steps S14 and S15, the flow returns to step S11.
  • the procedure shown in FIG. 8 is also executed in the correction block that receives the operation start instruction from the control unit 104 in step S15.
  • the error correction processing capability of the error correction unit 102 is ensured by resuming the operation of the stopped correction block when the error correction processing load increases.
  • step S15 when all the correction blocks 301 to 30N included in the error correction unit 102 are already operating, the correction block cannot be operated any more. In such a case, the control unit 104 does not have to control other correction blocks regardless of the determination result of step S14.
  • the signal processing apparatus 100 dynamically changes the number of correction blocks to be operated based on the number of error corrections of the arithmetic unit. As a result, the signal processing apparatus 100 has an effect that it is possible to achieve both reduction of power consumption of the signal processing apparatus and ensuring of error correction capability.
  • the signal processing apparatus 100 of the first embodiment can also be obtained by a signal processing apparatus that includes only the error correction unit 102 and the control unit 104. That is, referring to FIG. 1 and FIG. 2, the signal processing apparatus with the minimum configuration includes an error correction unit 102 and a control unit 104.
  • the error correction unit 102 includes correction blocks 301 to 30N connected in parallel.
  • the correction blocks 301 to 30N are configured by connecting a plurality of arithmetic units 401 to 40M that perform error correction of an input signal in series.
  • the control unit 104 controls the operation state of the correction blocks 301 to 30N based on the number of error corrections in the arithmetic units 401 to 40M for the signals input to the correction blocks 301 to 30N.
  • the signal processing apparatus having such a configuration can also dynamically change the number of correction blocks to be operated based on the number of error corrections of the arithmetic unit. Therefore, the signal processing device with the minimum configuration also has an effect that both the error correction capability of the signal processing device can be ensured and the power consumption can be reduced.
  • FIG. 9 is a block diagram illustrating a configuration of an optical receiver 200 according to the second embodiment of this invention.
  • the optical receiver 200 includes a front end 201, an analog-digital converter (ADC) 202, a local oscillation light source 203, and a signal processing device 204.
  • the local oscillation light source 203 is a light source such as a semiconductor laser.
  • the front end 201 outputs a beat signal of local light and signal light output from the local oscillation light source 203 as an analog reception signal.
  • the front end 201 is configured using, for example, a known 90-degree hybrid.
  • the analog reception signal is converted into a digital reception signal by the ADC 202.
  • the digital received signal is input to the signal processing device 204.
  • the signal processing device 204 has the same configuration and function as the signal processing device 100 described in the first embodiment.
  • the signal processing device 204 outputs data obtained by performing arithmetic processing on the digital reception signal output from the ADC 202 as reception data.
  • the optical receiver 200 of the second embodiment includes the signal processing device 100 described in the first embodiment as the signal processing device 204. That is, the optical receiver 200 dynamically changes the number of correction blocks to be operated based on the number of error corrections of the arithmetic unit of the signal processing device 204. As a result, the optical receiver 200 has an effect that it is possible to achieve both reduction in power consumption of the signal processing device and securing of error correction capability.
  • the present invention can be applied to apparatuses other than the coherent optical receiver. That is, the signal processing apparatus 100 described in the first embodiment can reduce the power consumption of an apparatus that requires error correction processing.
  • a low density parity check (LDPC) code is used as the error correction code, and the error correction unit performs error correction of digital data using soft decision forward error correction (SD-FEC). did.
  • SD-FEC soft decision forward error correction
  • the error correction code and the error correction determination procedure are not limited to these.
  • An error correction means in which a correction block in which a plurality of arithmetic means for performing error correction of an input signal are connected in series is connected; and Control means for controlling the operating state of each of the correction blocks based on the number of error corrections in any of the arithmetic means for the signal;
  • a signal processing apparatus comprising:
  • the arithmetic means outputs the error correction number to the control means,
  • the control means includes Calculate the correction processing load of the correction block based on the number of error correction obtained from each of the arithmetic means, Stopping a correction block whose load is less than a first threshold;
  • Appendix 3 If the load exceeds a second threshold greater than the first threshold, any one of the stopped correction blocks is activated;
  • the signal processing apparatus described in Appendix 2 characterized by the above.
  • the load is the number of error corrections of one arithmetic means selected from the arithmetic means included in the one correction block in operation.
  • the load is described in any one of appendices 1 to 3 Signal processing device.
  • Appendix 5 The signal processing apparatus according to appendix 4, wherein the selected one arithmetic means is an arithmetic means arranged at the last stage of the arithmetic means connected in series in the correction block. .
  • the load is an average value of the number of error corrections of a plurality of arithmetic means selected from the arithmetic means included in one of the correction blocks in operation. Signal processing apparatus.
  • the load is a maximum value of the number of error corrections of a plurality of the calculation means selected from the calculation means included in one correction block in operation.
  • the described signal processing device is a maximum value of the number of error corrections of a plurality of the calculation means selected from the calculation means included in one correction block in operation.
  • Appendix 8 Demodulating means for performing symbol determination of the input digital received signal, converting the digital received signal into digital data and inputting the digital data to the error correcting means; A framer that converts the signal output from the error correction means into a frame of a predetermined format and outputs it as received data;
  • the signal processing device according to any one of appendices 1 to 7, further comprising:
  • Appendix 9 A front end that converts the signal light into an analog received signal and outputs it; Analog-to-digital conversion means for converting the analog reception signal into a digital reception signal; The signal processing device according to appendix 7, which receives the digital reception signal and outputs the reception data; With optical receiver.
  • An error correction means in which a correction block in which a plurality of arithmetic means are connected in series is connected in parallel performs error correction of the input signal, Controlling the operation state of each of the correction blocks based on the number of error corrections for the signal in any of the computing means; Signal processing method.
  • Appendix 14 further, A procedure for outputting the error correction number to the control means; A procedure for calculating a correction processing load of the correction block based on the number of error corrections acquired from each of the arithmetic means; Stopping a correction block whose load is less than a first threshold; The program described in appendix 11 to be executed.
  • ADC Analog-digital converter
  • DSP Signal Processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Error Detection And Correction (AREA)

Abstract

Afin de simultanément réduire la consommation d'énergie et garantir une capacité de correction d'erreur, un appareil de traitement de signal est pourvu d'un moyen de correction d'erreur dans lequel une liaison en parallèle est établie parmi les blocs de correction dans lesquels une pluralité de moyens de calcul destinés à corriger des erreurs de signaux entrés sont reliés en série, et d'un moyen de commande destiné à commander l'état de fonctionnement des blocs de correction sur la base du nombre de corrections d'erreur effectuées par l'un quelconque des moyens de calcul sur les signaux.
PCT/JP2016/000521 2015-02-03 2016-02-02 Dispositif de traitement de signal et procédé de traitement de signal WO2016125485A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2016573224A JP6365695B2 (ja) 2015-02-03 2016-02-02 信号処理装置及び信号処理方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015018978 2015-02-03
JP2015-018978 2015-02-03

Publications (1)

Publication Number Publication Date
WO2016125485A1 true WO2016125485A1 (fr) 2016-08-11

Family

ID=56563839

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/000521 WO2016125485A1 (fr) 2015-02-03 2016-02-02 Dispositif de traitement de signal et procédé de traitement de signal

Country Status (2)

Country Link
JP (1) JP6365695B2 (fr)
WO (1) WO2016125485A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58224416A (ja) * 1982-06-24 1983-12-26 Mitsubishi Electric Corp Ｐｃｍ再生装置
JP2002064579A (ja) * 2000-08-21 2002-02-28 Hitachi Kokusai Electric Inc 多値変調方式の伝送装置
WO2008038337A1 (fr) * 2006-09-26 2008-04-03 Hitachi Communication Technologies, Ltd. Récepteur de champ électrique optique et système de transmission optique
JP2009260882A (ja) * 2008-04-21 2009-11-05 Sumitomo Electric Ind Ltd 復号化装置及び光通信システムの宅内装置
JP2011175728A (ja) * 2011-04-04 2011-09-08 Fujitsu Semiconductor Ltd エラー訂正方法
JP2012248933A (ja) * 2011-05-25 2012-12-13 Mitsubishi Electric Corp 移動無線通信システム及び移動無線通信方法
JP2013153291A (ja) * 2012-01-24 2013-08-08 Nippon Hoso Kyokai <Nhk> 送信装置、送信方法、受信装置及び受信方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58224416A (ja) * 1982-06-24 1983-12-26 Mitsubishi Electric Corp Ｐｃｍ再生装置
JP2002064579A (ja) * 2000-08-21 2002-02-28 Hitachi Kokusai Electric Inc 多値変調方式の伝送装置
WO2008038337A1 (fr) * 2006-09-26 2008-04-03 Hitachi Communication Technologies, Ltd. Récepteur de champ électrique optique et système de transmission optique
JP2009260882A (ja) * 2008-04-21 2009-11-05 Sumitomo Electric Ind Ltd 復号化装置及び光通信システムの宅内装置
JP2011175728A (ja) * 2011-04-04 2011-09-08 Fujitsu Semiconductor Ltd エラー訂正方法
JP2012248933A (ja) * 2011-05-25 2012-12-13 Mitsubishi Electric Corp 移動無線通信システム及び移動無線通信方法
JP2013153291A (ja) * 2012-01-24 2013-08-08 Nippon Hoso Kyokai <Nhk> 送信装置、送信方法、受信装置及び受信方法

Also Published As

Publication number Publication date
JPWO2016125485A1 (ja) 2017-11-24
JP6365695B2 (ja) 2018-08-01

Similar Documents

Publication Publication Date Title
JP4194999B2 (ja) 後方互換的ｄｖｂ−ｓ規格送信システム
US20130311840A1 (en) Method and device for estimating input bit error ratio
EP1936904A1 (fr) Circuit de calcul du logarithme de rapport de vraisemblance, appareil emetteur, procede et programme de calcul du logarithme de rapport de vraisemblance
US10548158B2 (en) Message passing algorithm decoder and methods
US20210135778A1 (en) Distribution matching circuit, distribution dematching circuit, distribution matching method, distribution dematching method, and optical transmission system
JP6365695B2 (ja) 信号処理装置及び信号処理方法
US20210409145A1 (en) Receiving apparatus and decoding method
US11271658B2 (en) Optical receiver, light signal receiving method, and data reproduction device
JP6265938B2 (ja) 誤り訂正装置、光受信器および光伝送装置
JP2011205511A (ja) 受信装置および受信方法
JP7344094B2 (ja) 送信装置および受信装置
US11431354B2 (en) Encoding circuit, decoding circuit, encoding method, decoding method, and transmitting device
CA3080025C (fr) Appareil de reception et procede de decodage correspondant
JP2022116176A (ja) インターリービング深度を調整するための装置及び方法
JP6454397B1 (ja) 誤り訂正装置、誤り訂正方法及び光通信システム
US11880611B2 (en) Data processing apparatus, data processing method and program
JP6992742B2 (ja) 光空間通信の受信装置およびその制御方法
EP3657697B1 (fr) Système et procédé de transmission de signaux
JP6593808B2 (ja) Ａｄ変換器、半導体集積回路および回転検出装置
US20170373785A1 (en) Receiving device and local light control method
US8880846B2 (en) Semiconductor device
US10484017B2 (en) Data processing apparatus, and data processing method
US20120221912A1 (en) Optical transmission and reception system and optical reception device
US11671119B2 (en) Signal processing apparatus and signal processing method
JP2010278829A (ja) ソフトウェア無線機

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16746317

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2016573224

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16746317

Country of ref document: EP

Kind code of ref document: A1