WO2016123881A1 - 非挥发性阻变存储器件及其制备方法 - Google Patents

非挥发性阻变存储器件及其制备方法 Download PDF

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WO2016123881A1
WO2016123881A1 PCT/CN2015/079005 CN2015079005W WO2016123881A1 WO 2016123881 A1 WO2016123881 A1 WO 2016123881A1 CN 2015079005 W CN2015079005 W CN 2015079005W WO 2016123881 A1 WO2016123881 A1 WO 2016123881A1
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metal electrode
layer
resistive
resistive memory
functional layer
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French (fr)
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刘琦
刘明
孙海涛
吕杭炳
龙世兵
白纳吉⋅瑞塔姆
张康玮
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the invention belongs to the field of microelectronics, and in particular relates to a nanoporous graphene intercalation-based resistive memory cell structure and a manufacturing method thereof capable of controlling a growth position of a conductive filament.
  • non-volatile memory With the demand for high-capacity, low-power storage, such as multimedia applications and mobile communications, the market share of non-volatile memories, especially flash memory, has become more and more important, and it has gradually become a very important memory. .
  • the main feature of non-volatile memory is that it can store stored information for a long time without power. It has both the characteristics of read-only memory and high access speed.
  • Non-volatile memory on the market currently uses flash memory as the mainstream, but flash memory devices have excessive operating voltage, slow operation speed, insufficient durability, and too little tunneling oxide layer during device miniaturization, which will result in memory time. Long defects.
  • the ideal non-volatile memory should have low operating voltage, simple structure, non-destructive reading, fast operation speed, long memory time, small device area, and good durability.
  • many new materials and devices have been studied in an attempt to achieve the above objectives. A considerable number of new memory devices use a change in resistance value as a memory means, including a resistive memory and a solid electrolyte material. Resistive memory.
  • Non-volatile resistive memory has attracted many domestic advantages due to its simple device structure (metal-insulator-metal), high device density, low power consumption, and fast programming/erasing speed. Foreign companies and research institutes are highly concerned.
  • the resistive memory technology is based on the fact that the resistance of the material can be reversibly converted between a high-resistance state and a low-resistance state under voltage control.
  • organic polymers such as polyimide (PI), AI DCN, and CuTCNQ
  • multi-metal oxides such as magnetoresistive material Pr 0.7 Ca 0.3 MnO 3 and La 0.7 Ca 0.3 MnO 3 , etc., doped SrTiO 3 and SrZrO 3 , etc.
  • binary transition metal oxides such as NiO, Nb 2 O 5 , CuO x , ZrO 2 , HfO 2 , Ta 2 O 5 , TiO 2 , etc.
  • solid electrolyte materials such as CuS, AgS, AgGeSe, and the like.
  • a sandwich structure based on an oxidizable metal/solid electrolyte/inert metal can constitute an important type of non-volatile resistive memory (RRAM) memory, commonly referred to as solid electrolyte-based RRAM, programmable metallization.
  • RRAM resistive memory
  • PMC Programmable Metallization Cell Memory
  • CBRAM Conductive Bridging Random Access Memory
  • the working principle is: under the action of external electric excitation, the anode of the metal electrode A is easily oxidized (such as Cu, Ag and Ni) to be oxidized by the electric field to become metal ion A+, and the metal ion A+ acts in the electric field.
  • the transfer is carried out in the solid electrolyte B, moving toward the cathode and finally reaching the inert lower electrode C, at which the metal ion A+ is reduced to the metal A.
  • the device resistance is in a low resistance state; under the action of the reverse electric field, the metal conductive bridge is broken, The device returns to a high impedance state.
  • the electrical properties of the device are highly discrete (such as programming voltage and high and low resistance). If the formation process of the conductive filaments can be controlled, the uniformity of the electrical parameters of the device will be greatly improved.
  • the object of the present invention is to overcome the above technical difficulties, and to provide a controllable conductive filament by controlling the formation position of the conductive filament based on the deficiencies of the resistive memory based on the formation and fracture principle of the metal conductive filament.
  • the process of forming a new device structure and its manufacturing method to reduce the dispersion of the electrical parameters of the resistive memory improves the performance and reliability of the device.
  • the present invention provides a non-volatile resistive memory comprising an inert metal electrode, a resistive functional layer, and an oxidizable metal electrode, characterized in that a nanometer-containing nanoparticle is interposed between the oxidizable metal electrode and the resistive functional layer.
  • the graphene barrier layer of the pores can control the oxidation of the metal of the easily oxidizable metal electrode during the device programming process, and the formed metal ions can only enter the resistive functional layer through the position of the nanopore.
  • the material of the oxidizable metal electrode is, for example, Cu, Ag, Ni, Sn, Co, Fe, At least one of Mg, or a combination thereof; alternatively, the thickness thereof is from 5 nm to 500 nm.
  • the material of the resistive functional layer is a solid electrolyte or a binary oxide material having a resistance change property, such as CuS, AgS, AgGeSe, CuI x S y , ZrO 2 , HfO 2 , TiO 2 , SiO 2 , WO Any one of x , NiO, CuO x , ZnO, TaO x , Y 2 O 3 or a combination thereof; alternatively, the thickness thereof is 2 nm to 200 nm.
  • the material of the inert metal electrode is, for example, any one of Pt, W, Au, Pd or a combination thereof; alternatively, the thickness thereof is, for example, 5 nm to 500 nm.
  • the graphene barrier layer is at least one of a single layer or a plurality of graphene films; alternatively, the thickness thereof is from 0.4 nm to 20 nm.
  • each nanopore has a diameter of 1 nm to 20 nm; alternatively, the nanopore is single or multiple.
  • the present invention also provides a non-volatile resistive memory manufacturing method comprising: forming an oxidizable metal electrode on an insulating substrate; forming a graphene barrier layer containing nanopores on the oxidizable metal electrode; and forming a graphene barrier layer on the oxidizable metal electrode; Forming a resistive functional layer; forming an inert metal electrode on the resistive functional layer, wherein the nanoporous graphene layer can control the position of the metal ion formed only through the nanopore after the oxidation of the easily oxidized electrode metal during device programming Enter the resistance change function layer.
  • the forming process of the inert metal electrode and/or the resistive functional layer and/or the oxidizable metal electrode is electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, magnetron sputtering or sol-gel method.
  • the graphene barrier layer is formed by film transfer, tape stripping or chemical vapor deposition.
  • the thickness of the inert metal electrode and/or the oxidizable metal electrode is 5 nm to 500 nm; alternatively, the thickness of the resistive functional layer is 2 nm to 200 nm; alternatively, the thickness of the graphene barrier layer is 0.4 nm to 20 nm.
  • the material of the oxidizable metal electrode is, for example, at least one of Cu, Ag, Ni, Sn, Co, Fe, Mg, or a combination thereof; alternatively, the material of the resistive functional layer is a solid having resistance change characteristics or a binary oxide electrolyte material, for example, CuS, AgS, AgGeSe, CuI x S y, ZrO 2, HfO 2, TiO 2, SiO 2, WO x, NiO, CuO x, ZnO, TaO x, Y 2 O Any one or a combination of 3 ; alternatively, the material of the inert metal electrode is, for example, any one of Pt, W, Au, Pd or a combination thereof.
  • each nanopore has a diameter of 1 nm to 20 nm; alternatively, the nanopore is single or multiple.
  • the nanopores are formed in the graphene barrier layer by electron beam etching or ion beam etching; optionally, each nanopore has a diameter of 1 nm to 20 nm; alternatively, the nanometer The holes are single or multiple.
  • a plurality of nano-protrusions are formed by etching or depositing on the oxidizable metal electrode, and the formed graphene barrier layer is broken at the plurality of nano-protrusions to form a plurality of nano-holes.
  • a periodic structure is formed at an interface between the oxidizable metal electrode and the resistive functional layer.
  • the projected area of the graphene barrier layer and the oxidizable metal electrode is larger than the resistive functional layer and the inert metal electrode, and an electrode contact is formed on the exposed graphene barrier layer.
  • the inert metal electrode is a plurality of splits.
  • a graphene intercalation structure containing nanopores is added between the oxidizable metal electrode and the resistive functional layer to block diffusion of metal ions, so that the device is in the programming process.
  • the metal ions formed in the oxidized metal electrode can only enter the resistive functional layer through the position of the nanopore, thereby controlling the growth position of the conductive filament.
  • FIG. 1 is a schematic view of a non-volatile resistive memory device in accordance with the present invention.
  • 2A-2E are schematic views of a method of fabricating a nonvolatile resistive memory device in accordance with the present invention.
  • FIG. 3 is a schematic flow chart of a method of fabricating a non-volatile resistive memory device in accordance with the present invention.
  • a schematic diagram of a resistive memory device includes an insulating substrate 11, an oxidizable metal electrode 12, a graphene barrier layer 13 (containing a plurality of nanoholes 13A), and a resistive functional layer 14. And an inert metal electrode 15.
  • the material of the inert metal electrode 15 is at least one of Pt, W, Au, Pd or a combination thereof
  • the resistive functional layer 14 is a solid electrolyte or a binary oxide material having resistance change characteristics
  • the graphene barrier layer 13 is a single-layer or multi-layer graphene film having an array of a plurality of nanopores 13A in the graphene layer 13, and the oxidizable metal electrode 12 material is at least one of Cu, Ag, Ni, Sn, Co, Fe, Mg, or a combination thereof .
  • the graphene layer is used as a barrier layer for the cation, and the conductive filament can be controlled to grow only from the nano-via position in the graphene layer, thereby reducing the randomness of the growth of the conductive filament, thereby reducing the device.
  • FIG. 3 are schematic views corresponding to respective steps of a method of manufacturing a resistive memory device in accordance with the present invention.
  • an oxidizable metal electrode 12 is formed on the insulating substrate 11.
  • An insulating substrate 11 is provided, which may be silicon oxide on a Si substrate, a buried oxide layer of an SOI substrate, a hard substrate such as sapphire (aluminum oxide), aluminum nitride, glass, quartz, or the like, or may be a resin or a plastic.
  • a flexible substrate The deposition of an easily oxidizable metal material on the insulating substrate 12 by electron beam evaporation, chemical vapor deposition (including PECVD, HDPCVD, MOCVD, etc.), pulsed laser deposition, atomic layer deposition (ALD) or magnetron sputtering.
  • the oxidized metal electrode 12 is, for example, at least one of Cu, Ag, Ni, Sn, Co, Fe, Mg, or a combination thereof (for example, in the form of an alloy or a laminate), and has a thickness of 5 nm to 500 nm, preferably 10 ⁇ 300 nm and most preferably 50 to 100 nm, for example 80 nm.
  • a metal ion blocking layer 13 composed of graphene is formed on the easily oxidizable metal electrode 12.
  • the formation of the graphene film layer may be a film transfer process, and the graphene layer may be prepared by mechanical peeling (for example, tape peeling) or chemical vapor deposition.
  • the graphene barrier layer has a thickness of from 0.4 nm to 20 nm, preferably from 0.8 nm to 16 nm.
  • graphene has a hexagonal cavity diameter of 65 pm, which is much smaller than the atomic size or ion size of most atoms, and is therefore a very effective atomic diffusion barrier material. .
  • the graphene barrier layer 13 may be a single layer of graphene or a multilayer graphene. Compared with other hard barrier layers such as Ta, Ti, TiN, and TaN materials, the graphene barrier layer 13 may be a single layer, or each of the multilayer structures may be flexible and bendable, and thus the resistive device The thickness of itself can be greatly Reduced, easier to fabricate on flexible substrates, and further reduce overall impedance, so it can be applied to wearable or low-power electronic devices.
  • the projected area of the graphene barrier layer and the oxidizable metal electrode is larger than the resistive functional layer and the inert metal electrode to be formed later, thereby forming an electrode contact on the graphene barrier layer, having a step structure as shown in FIG. 2D. This can further increase the area of the graphene and oxidizable metal electrodes to lower the resistance of the device itself for use in low power devices.
  • the graphene barrier layer 13 is etched to form a plurality of nanopores 13A.
  • Electron beam etching or ion beam etching is used to drive electrons or ions directly to bombard the surface of the graphene film 13 under the action of a high-intensity electromagnetic field, and single or a plurality of nano-scale holes 13A are sputtered in the selected device region.
  • a single metal filament can be formed in a single hole in each RRAM, and the distribution and size of the metal filaments are uniquely controlled to accurately control the resistance value.
  • a plurality of holes 13A may be formed, for example, such that each RRAM has 2 to 32 holes, and the spacing between each holes is 3 nm to 50 nm, preferably 5 to 20 nm. In this way, a uniform distribution of metal filaments can be obtained in a larger area of RRAM in order to increase the uniformity of current density and avoid accidental melting of the metal filaments due to local overheating.
  • a resistive functional layer 14 is formed on the graphene barrier layer 13.
  • the resistive functional layer 14 may also be referred to as a resistive memory dielectric layer to provide insulation isolation between the upper and lower electrodes.
  • the atoms of the easily oxidizable metal electrode 12 are ionized, but blocked by the graphene barrier layer 13 having a pore size smaller than the atomic size, and the ionized atoms can only enter through the plurality of holes 13A.
  • the array of the holes 13A can be appropriately adjusted to control the growth of the conductive filaments only along the positions of the nanopores, thereby achieving the process of controlling the growth of the conductive filaments.
  • the formation process of the resistive functional layer 14 is electron beam evaporation, pulsed laser deposition, magnetron sputtering or sol-gel method.
  • the resistive functional layer 14 is a solid electrolyte or a binary oxide material having resistance change characteristics, specifically CuS, AgS, AgGeSe, CuI x S y , ZrO 2 , HfO 2 , TiO 2 , SiO 2 , WO x , NiO Any one or a combination of CuO x , ZnO, TaO x , Y 2 O 3 (including various forms such as mixing, lamination, doping modification, etc.), and has a thickness of 2 nm to 200 nm, preferably 5 nm to 100 nm, and most preferably 10 nm. ⁇ 60nm, the best 40nm.
  • an inert metal electrode 15 is formed on the resistive functional layer 14.
  • the electrode 15 is formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or magnetron sputtering, and the material thereof is an inert metal material, for example, any one of Pt, W, Au, Pd or a combination thereof;
  • the thickness thereof is, for example, 5 nm to 500 nm, preferably 10 to 350 nm and most preferably 60 to 150 nm, for example 100 nm.
  • a periodic pattern (not shown) is formed on the top surface of the resistive functional layer 14 by using a mask or periodically controlling the deposition process parameters or etching after deposition to increase the electrode 15
  • the underlying resist ively changes the contact area between the functional layers 14, thereby improving programming and erasing efficiency.
  • the electrode layer 15 is formed by etching or by using a mask to deposit the electrode layer 15, so that the electrode 15 is a plurality of small areas, thereby improving the uniformity of current distribution in the resistive switching device and improving device reliability.
  • the drawing of the present invention shows that the electrode 12 and the graphene layer 13 have a larger area than the upper resistive functional layers 14, 15, these layers may also be of equal area.
  • an 80 nm Cu film is magnetron-sputtered as a lower conductive electrode layer on a Si substrate with an insulating layer of 200 nm thick SiO 2 by an electron beam evaporation process;
  • a single layer of graphene grown on a Cu foil substrate is transferred onto a lower conductive electrode layer; then, using a focused ion beam etching function, a diameter of 5 nm and a spacing of 200 nm are prepared on a single layer of graphene.
  • Nanopore array for forming multiple RRAM devices at one time); then depositing a 20 nm SiO 2 resistive functional layer by magnetron sputtering deposition; then using electron beam lithography in nano An upper conductive electrode paste pattern with a diameter of 50 nm and a spacing of 200 nm is formed above the hole position. Finally, a Pt of 50 nm is magnetron-sputtered as an upper conductive electrode layer, and a complete device structure is formed after de-glue, and then diced or formed into an electrically isolated structure. A plurality of RRAM devices are formed.
  • Figure 2 shows a schematic diagram of the process flow of this embodiment.
  • the inert metal electrode layer 15, the resistive functional layer 14, the graphene barrier layer 13 having the plurality of nanoholes 13A, and the oxidizable metal electrode layer 12 may be sequentially deposited on the insulating substrate 11.
  • Other materials and dimensions are as described above.
  • the nanopores are etched after deposition of the graphene barrier layer, but are etched on the oxidizable metal electrode 12 before the formation of the graphene barrier layer 13 (periodically adjusting process parameters)
  • the deposition forms a plurality of nano-protrusions (not shown), and the graphene barrier layer 13 formed thereafter is broken at the plurality of nano-protrusions to form a plurality of nano-holes 13A.
  • the remaining steps are similar to the previous embodiment.
  • a graphene intercalation structure containing nanopores is added between the oxidizable metal electrode and the resistive functional layer to block diffusion of metal ions, so that the device is in the programming process.
  • the metal ions formed in the oxidized metal electrode can only enter the resistive functional layer through the position of the nanopore, thereby controlling the conductive filament Growing position.

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Abstract

一种非挥发性阻变存储器，包括惰性金属电极（15）、阻变功能层（14）、易氧化金属电极（12），其特征在于：在易氧化金属电极（12）与阻变功能层（14）之间插入含多个纳米孔（13A）的石墨烯阻挡层（13），能够控制器件编程过程中易氧化金属电极（12）的金属氧化后，形成的金属离子只能通过多个纳米孔（13A）的位置进入到阻变功能层（14）中。该非挥发性阻变存储器件的制造方法，在易氧化金属电极（12）与阻变功能层（14）之间增加含有纳米孔（13A）的石墨烯插层（13）结构，阻挡金属离子的扩散，器件在编程过程中易氧化金属电极（12）中形成的金属离子只能通过纳米孔（13A）的位置处进入到阻变功能层（14），从而控制导电细丝生长位置。

Description

非挥发性阻变存储器件及其制备方法 技术领域
本发明属于微电子技术领域，尤其涉及一种可控制导电细丝生长位置的基于纳米孔石墨烯插层的阻变存储器单元结构及制作方法。
背景技术
随着多媒体应用、移动通信等对大容量、低功耗存储的需要，非挥发性存储器、特别是闪存所占的半导体器件市场份额变得越来越大，也逐渐成为一种相当重要的存储器。非挥发性存储器的主要特点是在不加电的情况下也能够长期保存所存储的信息，其既有只读存储器的特点，又有很高的存取速度。
当前市场上的非挥发性存储器以闪存为主流，但是闪存器件存在操作电压过大、操作速度慢、耐久力不够好以及由于在器件微缩化过程中过薄的隧穿氧化层将导致记忆时间不过长等缺点。理想的非挥发性存储器应具备操作电压低、结构简单、非破坏性读取、操作速度快、记忆时间长、器件面积小、耐久了好等条件。目前已经对好多新型材料和器件进行了研究，试图来达到上述的目标，其中有相当部分的新型存储器器件都采用电阻值的改变来作为记忆的方式，包括阻变存储器及采用固态电解液材料的阻变存储器。
非挥发性阻变存储器(RRAM：resistive switching memory)由于具有简单的器件结构(金属-绝缘体-金属)、高的器件密度、低的功耗、快的编程/擦除速度等优点，引起了国内外大公司和科研院所的高度关注。阻变存储技术是以材料的电阻在电压的控制下可以在高阻态和低阻态之间实现可逆转换为基础的。有多种类型的材料被证明具有电阻转变特性：(1)有机聚合物，如聚酰亚胺(PI)、AI DCN以及CuTCNQ等；(2)多元金属氧化物，如磁阻材料Pr0.7Ca0.3MnO3和La0.7Ca0.3MnO3等，掺杂的SrTiO3和SrZrO3等；(3)二元过渡族金属氧化物，如NiO、Nb2O5、CuOx、ZrO2、HfO2、Ta2O5、TiO2等；(4)固态电解液材料，如CuS，AgS，AgGeSe等。
基于易氧化金属/固态电解液/惰性金属的三明治结构，能够构成一类重要的非挥发性阻变存储器(RRAM，resistive switching memory)存储器，通常被称为固态电解液基RRAM，可编程金属化器件(PMC：Programmable Metallization Cell Memory)或导电桥随机存储器(CBRAM：Conductive Bridging Random Access Memory)。这类存储器具有结构简单、速度快、功耗低等优点，被受产业界的重视，成为下一代非挥发性存储技术的有力竞争者之一。其工作原理是：在外加电激励的作用下，金属上电极A的阳极易氧化金属(如，Cu、Ag和Ni等)在电场作用下氧化成为金属离子A+，金属离子A+在电场的作用下在固态电解液B中进行传输，向阴极移动并最终达到惰性下电极C，在下电极C处金属离子A+被还原成为金属A。随着金属不断在下电极C处沉积，最终达到上电极A，形成连通上下电极的细丝状的金属导电桥，器件电阻处于低阻状态；在反向电场作用下，该金属导电桥断开，器件恢复到高阻状态。这两种电阻状态可以在外加电场的作用相互转换。
然而，由于导电细丝成核和生长过程是一个随机的过程，导致器件的相关电学特性具有很大的离散性(如编程电压和高低阻态)。如果能够对导电细丝的形成过程进行控制，那么器件的电学参数的均匀性将会得到极大的提高。
发明内容
由上所述，本发明的目的在于克服上述技术困难，基于金属导电细丝的形成与断裂原理的阻变存储器存在的不足，提供了一种能够控制导电细丝形成位置、通过控制导电细丝形成的过程来减小阻变存储器电学参数的离散性的新器件结构及其制造方法，提高了器件的性能以及可靠性。
为此，本发明提供了一种非挥发性阻变存储器，包括惰性金属电极、阻变功能层、易氧化金属电极，其特征在于：在易氧化金属电极与阻变功能层之间插入含纳米孔的石墨烯阻挡层，能够控制器件编程过程中易氧化金属电极的金属氧化后，形成的金属离子只能通过纳米孔的位置进入到阻变功能层中。
其中，易氧化金属电极的材料例如为Cu、Ag、Ni、Sn、Co、Fe、 Mg中的至少一种、或其组合；可选地，其厚度为5nm～500nm。
其中，阻变功能层的材料为具有电阻转变特性的固态电解液或二元氧化物材料，例如为CuS、AgS、AgGeSe、CuIxSy，ZrO2、HfO2、TiO2、SiO2、WOx、NiO、CuOx、ZnO、TaOx、Y2O3的任意一种或其组合；可选地，其厚度为2nm～200nm。
其中，惰性金属电极的材料例如为Pt、W、Au、Pd的任意一种或其组合；可选地，其厚度例如5nm～500nm。
其中，石墨烯阻挡层为单层或多层石墨烯薄膜的至少一种；可选地，其厚度为0.4nm～20nm。
其中，每个纳米孔的直径为1nm～20nm；可选地，纳米孔为单个或多个。
本发明还提供了一种非挥发性阻变存储器制造方法，包括：在绝缘衬底上形成易氧化金属电极；在易氧化金属电极上形成含有纳米孔的石墨烯阻挡层；在石墨烯阻挡层上形成阻变功能层；在阻变功能层上形成惰性金属电极，其中含纳米孔的石墨烯层能够控制器件编程过程中易氧化电极金属氧化后，形成的金属离子只能通过纳米孔的位置进入到阻变功能层中。
其中，惰性金属电极和/或阻变功能层和/或易氧化金属电极的形成工艺为电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积、磁控溅射或溶胶—凝胶法。
其中，石墨烯阻挡层的形成方法为薄膜转移、胶带剥离或化学气相沉积。
其中，惰性金属电极和/或易氧化金属电极的厚度为5nm～500nm；可选的，阻变功能层的厚度为2nm～200nm；可选的，石墨烯阻挡层的厚度为0.4nm～20nm。
其中，易氧化金属电极的材料例如为Cu、Ag、Ni、Sn、Co、Fe、Mg中的至少一种、或其组合；可选的，阻变功能层的材料为具有电阻转变特性的固态电解液或二元氧化物材料，例如为CuS、AgS、AgGeSe、CuIxSy，ZrO2、HfO2、TiO2、SiO2、WOx、NiO、CuOx、ZnO、TaOx、Y2O3的任意一种或其组合；可选的，惰性金属电极的材料例如为Pt、W、Au、Pd的任意一种或其组合。
其中，采用电子束刻蚀或离子束刻蚀中在石墨烯阻挡层中生成纳 米孔；可选地，每个纳米孔的直径为1nm～20nm；可选地，纳米孔为单个或多个。
其中，形成石墨烯阻挡层之后，采用电子束刻蚀或离子束刻蚀中在石墨烯阻挡层中生成纳米孔；可选地，每个纳米孔的直径为1nm～20nm；可选地，纳米孔为单个或多个。
其中，在形成石墨烯阻挡层之前，在易氧化金属电极上刻蚀或者沉积形成多个纳米突起，之后形成的石墨烯阻挡层在多个纳米突起处断裂形成多个纳米孔。
其中，在易氧化金属电极与阻变功能层之间的界面形成周期性结构。
其中，石墨烯阻挡层与易氧化金属电极的投影面积大于阻变功能层和惰性金属电极，并且在露出的石墨烯阻挡层上形成电极接触。
其中，惰性金属电极为分裂的多个。
依照本发明的非挥发性阻变存储器件及其制造方法，在易氧化金属电极与阻变功能层之间增加含有纳米孔的石墨烯插层结构，阻挡金属离子的扩散，使得器件在编程过程中易氧化金属电极中形成的金属离子只能通过纳米孔的位置处进入到阻变功能层，从而控制导电细丝生长位置。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1为依照本发明的非挥发性阻变存储器件的示意图；
图2A-2E为依照本发明的非挥发性阻变存储器件制造方法的示意图；以及
图3为依照本发明的非挥发性阻变存储器件制造方法的示意流程图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了在易氧化金属电极与阻变功能层之间增加含有纳米孔的石墨烯插层结构的非挥发性阻变存储器件及其制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中 所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
如图1所示，为依照本发明的阻变存储器件的示意图，其包括绝缘衬底11、易氧化金属电极12、石墨烯阻挡层13(含有多个纳米孔13A)、阻变功能层14、以及惰性金属电极15。其中，惰性金属电极15材料为Pt、W、Au、Pd的至少一种或其组合，阻变功能层14为具有电阻转变特性的固态电解液或二元氧化物材料，石墨烯阻挡层13为单层或多层石墨烯薄膜，石墨烯层13中具有多个纳米孔13A的阵列，易氧化金属电极12材料为Cu、Ag、Ni、Sn、Co、Fe、Mg的至少一种或其组合。编程过程中，采用石墨烯层作为阳离子的阻挡层，控制导电细丝只能从石墨烯层中的纳米通孔位置处进行生长，减小了导电细丝生长的随机性，从而达到减小器件电学参数离散性的目的。
如图2A-2E以及图3所示，为依照本发明的阻变存储器件制造方法的各个步骤对应的示意图。
具体地，如图2A所示，在绝缘衬底11上形成易氧化金属电极12。提供绝缘衬底11，其可以为Si衬底上的氧化硅、SOI衬底的埋氧层、蓝宝石(氧化铝)、氮化铝、玻璃、石英等硬质衬底，还可以是树脂、塑料等柔性衬底。采用电子束蒸发、化学气相沉积(包括PECVD、HDPCVD、MOCVD等)、脉冲激光沉积、原子层沉积(ALD)或磁控溅射方法，在绝缘衬底12上沉积由易氧化金属材料构成的易氧化金属电极12，例如为Cu、Ag、Ni、Sn、Co、Fe、Mg中的至少一种、或其组合(例如以合金形式或叠层方式)，其厚度为5nm～500nm、优选为10～300nm并最佳50～100nm，例如80nm。
随后，如图2B所示，在易氧化金属电极12上形成石墨烯构成的金属离子阻挡层13。形成石墨烯薄膜层可以是采用薄膜转移的工艺，石墨烯层的制备可以采用机械剥离(例如胶带剥离)或者是化学气相沉积的方法。所述石墨烯阻挡层的厚度为0.4nm至20nm，优选0.8nm～16nm。石墨烯作为一种六边形网格的二维结构，其六边形的空洞直径为65pm，远远小于大部分原子的原子尺寸或离子尺寸，因此是一种非常有效的原子扩散阻挡层材料。石墨烯阻挡层13可以是单层石墨烯，也可以是多层石墨烯。与其他例如Ta、Ti、TiN、TaN材质的硬质阻挡层相比，石墨烯阻挡层13由于可以为单层，或者多层结构中的每一层均为柔性可弯折，因此阻变器件自身厚度可以大大 降低，更易于在柔性衬底上制备，也进一步降低了整体阻抗，因此可以应用于可穿戴式或低功耗电子设备。优选地，石墨烯阻挡层与易氧化金属电极的投影面积大于后续要形成的阻变功能层和惰性金属电极，由此在石墨烯阻挡层上形成电极接触，如图2D所示具有台阶结构，如此可以进一步提高石墨烯和易氧化金属电极的面积从而降低器件自身的电阻，以便用于低功耗器件。
接着，如图2C所示，刻蚀石墨烯阻挡层13，形成多个纳米孔洞13A。采用电子束刻蚀或离子束刻蚀，在高强电磁场作用下驱动电子或离子直接轰击石墨烯薄膜13表面，在选定的器件区域内溅射出单个或多个纳米级孔洞13A。在本发明一个优选实施例中，仅有单个孔洞13A，其直径为1nm～20nm，优选3nm～15nm，最佳5nm。如此，可以在每个RRAM中仅通过单个孔洞形成单个金属细丝，唯一地控制了金属细丝的分布和尺寸，以便精确控制电阻值。在本发明其他实施例中，也可以形成多个孔洞13A，例如使得每个RRAM具有2～32个孔洞，每个孔洞之间的间距为3nm～50nm，优选5～20nm。如此，可以在较大面积的RRAM中获得均匀的金属细丝分布，以便提高电流密度的均匀性，避免局部过热导致金属细丝意外熔断。
随后，如图2D所示，在石墨烯阻挡层13上形成阻变功能层14。阻变功能层14也可以称作阻变存储介质层，在上下电极之间起到绝缘隔离作用。在后续编程过程中，在大电场作用下，易氧化金属电极12的原子被电离，然而受到孔洞尺寸小于原子尺寸的石墨烯阻挡层13的阻挡，电离的原子仅能通过多个孔洞13A而进入后续固态电解液的阻变功能层14中，因此可以通过合理调整排列孔洞13A的阵列从而控制导电细丝只能沿着纳米孔的位置处进行生长，从而达到控制导电细丝生长的过程，减小由此导致的器件电学参数的离散性。阻变功能层14的形成工艺为电子束蒸发、脉冲激光沉积、磁控溅射或溶胶—凝胶法。阻变功能层14为具有电阻转变特性的固态电解液或二元氧化物材料，具体为CuS、AgS、AgGeSe、CuIxSy，ZrO2、HfO2、TiO2、SiO2、WOx、NiO、CuOx、ZnO、TaOx、Y2O3的任意一种或其组合(包括混合、层叠、掺杂改性等多种形式)，厚度为2nm～200nm、优选5nm～100nm、最佳10nm～60nm，最佳40nm。
最后，如图2E所示，在阻变功能层14上形成惰性金属电极15。采用电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积或磁控溅射方法形成电极15，其材料为惰性金属材料，例如为Pt、W、Au、Pd的任意一种或其组合；其厚度例如5nm～500nm、优选为10～ 350nm并最佳60～150nm，例如100nm。优选地，沉积电极15之前，采用掩模板或者周期性控制沉积工艺参数、或者沉积之后刻蚀，在阻变功能层14的顶表面形成周期性图形(未示出)，以增大电极15与其下的阻变功能层14之间的接触面积，从而提高编程、擦除效率。优选地，形成电极层15之后通过刻蚀，或者利用掩模沉积电极层15，使得电极15为小面积的多个，由此提高电流在阻变器件中的分布均匀性，提高器件可靠性。虽然本发明附图显示电极12、石墨烯层13面积大于上层的阻变功能层14、15，但是这些层也可以面积相等。
在本发明的一个实施例中，首先，利用电子束蒸发工艺，在带有200nm厚SiO2的绝缘层的Si衬底上，磁控溅射80nm的Cu薄膜作为下导电电极层；然后，采用PMMA转移的方法，将生长在Cu箔衬底上的单层石墨烯转移到下导电电极层上；然后利用聚焦离子束的刻蚀功能，在单层石墨烯上制备出直径为5nm，间隔200nm的纳米孔阵列(用于一次性形成多个RRAM器件)；然后利用磁控溅射沉积的方法，淀积一层20nm的SiO2阻变功能层；然后采用电子束光刻的方法，在纳米孔位置的上方形成直径50nm，间隔200nm的上导电电极胶图形，最后磁控溅射50nm的Pt作为上导电电极层，去胶后形成完整的器件结构，之后划片切割或者形成电隔离结构而形成多个RRAM器件。图2给出了该实施例的工艺流程示意图。通过对比不含纳米孔石墨烯插层的相同工艺条件下生长的阻变存储器件的电学特性，发现增加这层纳米孔石墨烯插层能够显著减小器件的操作电压和高、低阻态的离散性。
在本发明另一实施例中，也可以在绝缘衬底11上依次沉积惰性金属电极层15、阻变功能层14、具有多个纳米孔13A的石墨烯阻挡层13、易氧化金属电极层12，其他材料和尺寸如上所述。
在本发明另一实施例中，不同于沉积石墨烯阻挡层之后刻蚀形成纳米孔，而是在形成石墨烯阻挡层13之前，在易氧化金属电极12上刻蚀或者(周期性调节工艺参数)沉积形成多个纳米突起(未示出)，之后形成的石墨烯阻挡层13在多个纳米突起处断裂形成多个纳米孔13A。其余步骤与之前实施例类似。
依照本发明的非挥发性阻变存储器件及其制造方法，在易氧化金属电极与阻变功能层之间增加含有纳米孔的石墨烯插层结构，阻挡金属离子的扩散，使得器件在编程过程中易氧化金属电极中形成的金属离子只能通过纳米孔的位置处进入到阻变功能层，从而控制导电细丝 生长位置。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构或方法流程做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (13)

  1. 一种非挥发性阻变存储器，包括惰性金属电极、阻变功能层、易氧化金属电极，其特征在于：在易氧化金属电极与阻变功能层之间插入含纳米孔的石墨烯阻挡层，能够控制器件编程过程中易氧化金属电极的金属氧化后，形成的金属离子只能通过纳米孔的位置进入到阻变功能层中。
  2. 如权利要求1的非挥发性阻变存储器，其中，易氧化金属电极的材料例如为Cu、Ag、Ni、Sn、Co、Fe、Mg中的至少一种、或其组合；可选地，其厚度为5nm～500nm。
  3. 如权利要求1的非挥发性阻变存储器，其中，阻变功能层的材料为具有电阻转变特性的固态电解液或二元氧化物材料，例如为CuS、AgS、AgGeSe、CuIxSy，ZrO2、HfO2、TiO2、SiO2、WOx、NiO、CuOx、ZnO、TaOx、Y2O3的任意一种或其组合；可选地，其厚度为2nm～200nm。
  4. 如权利要求1的非挥发性阻变存储器，其中，惰性金属电极的材料例如为Pt、W、Au、Pd的任意一种或其组合；可选地，其厚度例如5nm～500nm。
  5. 如权利要求1的非挥发性阻变存储器，其中，石墨烯阻挡层为单层或多层石墨烯薄膜的至少一种；可选地，其厚度为0.4nm～20nm。
  6. 如权利要求1的非挥发性阻变存储器，其中，每个纳米孔的直径为1nm～20nm；可选地，纳米孔为单个或多个。
  7. 一种非挥发性阻变存储器制造方法，包括：
    在绝缘衬底上形成易氧化金属电极；
    在易氧化金属电极上形成含有纳米孔的石墨烯阻挡层；
    在石墨烯阻挡层上形成阻变功能层；
    在阻变功能层上形成惰性金属电极，
    其中含纳米孔的石墨烯层能够控制器件编程过程中易氧化电极金属氧化后，形成的金属离子只能通过纳米孔的位置进入到阻变功能层中。
  8. 如权利要求7的非挥发性阻变存储器制造方法，其中，惰性金属电极和/或阻变功能层和/或易氧化金属电极的形成工艺为电子 束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积、磁控溅射或溶胶—凝胶法。
  9. 如权利要求7的非挥发性阻变存储器制造方法，其中，采用薄膜转移、胶带剥离或化学气相沉积方法形成单层或多层的石墨烯阻挡层。
  10. 如权利要求7的非挥发性阻变存储器制造方法，其中，惰性金属电极和/或易氧化金属电极的厚度为5nm～500nm；可选的，阻变功能层的厚度为2nm～200nm；可选的，石墨烯阻挡层的厚度为0.4nm～20nm。
  11. 如权利要求7的非挥发性阻变存储器制造方法，其中，易氧化金属电极的材料例如为Cu、Ag、Ni、Sn、Co、Fe、Mg中的至少一种、或其组合；可选的，阻变功能层的材料为具有电阻转变特性的固态电解液或二元氧化物材料，例如为CuS、AgS、AgGeSe、CuIxSy，ZrO2、HfO2、TiO2、SiO2、WOx、NiO、CuOx、ZnO、TaOx、Y2O3的任意一种或其组合；可选的，惰性金属电极的材料例如为Pt、W、Au、Pd的任意一种或其组合。
  12. 如权利要求9的非挥发性阻变存储器制造方法，其中，形成石墨烯阻挡层之后，采用电子束刻蚀或离子束刻蚀中在石墨烯阻挡层中生成纳米孔；可选地，每个纳米孔的直径为1nm～20nm；可选地，纳米孔为单个或多个。
  13. 如权利要求9的非挥发性阻变存储器制造方法，其中，在形成石墨烯阻挡层之前，在易氧化金属电极上刻蚀或者沉积形成单个或多个纳米突起，之后形成的石墨烯阻挡层在每个纳米突起处断裂形成纳米孔。
PCT/CN2015/079005 2015-02-05 2015-05-14 非挥发性阻变存储器件及其制备方法 Ceased WO2016123881A1 (zh)

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