WO2016115783A1 - 薄膜晶体管结构及其制备方法、阵列基板、掩模板 - Google Patents

薄膜晶体管结构及其制备方法、阵列基板、掩模板 Download PDF

Info

Publication number
WO2016115783A1
WO2016115783A1 PCT/CN2015/076957 CN2015076957W WO2016115783A1 WO 2016115783 A1 WO2016115783 A1 WO 2016115783A1 CN 2015076957 W CN2015076957 W CN 2015076957W WO 2016115783 A1 WO2016115783 A1 WO 2016115783A1
Authority
WO
WIPO (PCT)
Prior art keywords
bent portion
thin film
film transistor
transistor structure
drain
Prior art date
Application number
PCT/CN2015/076957
Other languages
English (en)
French (fr)
Inventor
李哲
尚飞
邱海军
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/892,091 priority Critical patent/US20160351670A1/en
Publication of WO2016115783A1 publication Critical patent/WO2016115783A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • Embodiments of the present disclosure relate to a thin film transistor structure and a method of fabricating the same, an array substrate, and a mask.
  • the rising current passes the formula It is calculated that I on is the rising current, W/L is the channel width to length ratio, C ox is the capacitance between the gate line layer and the active layer per unit area, u is the electron mobility, and V gs is the applied voltage and charging. The difference between the post voltages, Vth is the voltage threshold.
  • An embodiment of the present disclosure provides a thin film transistor structure including: a source and a drain disposed in the same layer, wherein the source includes a first bent portion, and the drain includes a second bent portion.
  • the first bent portion and the second bent portion are nested and spaced apart from each other.
  • Another embodiment of the present disclosure provides an array substrate including the above-described thin film transistor structure.
  • a reticle including a reticle body, the reticle body including a light transmissive area and a opaque area, the opaque area including a first opaque area and a second a light transmitting region, the first opaque region is configured to cover a source including the first bent portion, and the second opaque region is configured to cover a drain including the second bent portion, the first The bent portion and the second bend are nested and spaced apart from each other.
  • Yet another embodiment of the present disclosure provides a method of fabricating a thin film transistor structure, including: forming an active layer; and forming a pattern including a source and a drain on the active layer by a patterning process, wherein the source The pole includes a first bent portion, and the drain includes a second bent portion, and the first bent portion and the second bent portion are nested and spaced apart from each other.
  • FIG. 1 is a schematic view showing a structure of a thin film transistor in the related art
  • FIG. 2 is a schematic diagram of a structure of a thin film transistor according to an embodiment of the present disclosure
  • 3A is a partial enlarged view of the source of FIG. 2;
  • 3B is a partial enlarged view of the drain of FIG. 2;
  • 3C is a partial enlarged view of the source and drain of FIG. 2;
  • FIG. 4 is a schematic diagram of another thin film transistor structure according to an embodiment of the present disclosure.
  • Figure 5 is a partial enlarged view of the source and drain of Figure 4.
  • FIG. 6 is a schematic view of a mask forming the source and drain electrodes of FIG. 4;
  • Figure 7 is a schematic illustration of a mask forming the source and drain of Figure 5.
  • the increase in the rising current I on can be achieved by increasing the channel width to length ratio (Width/Length, hereinafter referred to as W/L).
  • W/L channel width to length ratio
  • L means the distance between the source 11 and the drain 12
  • W means the relative width between the source 11 and the drain 12 which are perpendicular to L.
  • the increase in the rising current is insufficient by increasing the channel width-to-length ratio, resulting in a lower charging rate of the thin film transistor structure.
  • Embodiments of the present disclosure provide a thin film transistor structure, a method for fabricating the same, an array substrate, and a mask, which can solve the problem of low charging efficiency of the thin film transistor structure.
  • the thin film transistor structure 20 provided by the embodiment of the present disclosure includes a source 21 and a drain 22 disposed in the same layer, and the source 21 includes a first bent portion 23 of a non-linear configuration ( Referring to the dashed oval in FIG. 3A), the drain 22 includes a second bent portion 24 of a continuous non-linear configuration (see the dashed oval in FIG. 3B), the first bent portion 23 and the second bent portion Part 24 is constructed as Nested and spaced apart from each other.
  • the first bent portion 23 and the second bent portion 24 are configured to have a plurality of corners, respectively.
  • the projection of the first bent portion 23 on the second bent portion 24 covers at least a portion of the second bent portion 24. In one example, the spacing L between the first bent portion 23 and the second bent portion 24 is constant.
  • the source 21 and the drain 22 respectively include first and second bent portions, and the first and second bent portions are nested and spaced apart from each other, and the source 21 is bent.
  • a portion of the projection on the bend of the drain 22 covers at least a portion of the drain 22.
  • the relative width W between the source 21 and the drain 22 is equal to W 1 , W 2 , W 3 , W 4 .
  • the sum of W 5 the thin film transistor structure of the embodiment of the present disclosure can greatly increase the source compared to the relative width W between the source 11 and the drain 12 in the related art thin film transistor structure shown in FIG. 1 .
  • the relative width W between 21 and the drain 22, that is, the channel width to length ratio W/L can increase the corresponding rising current, thereby increasing the charging rate of the thin film transistor structure 20.
  • the first bent portion 23 and the second bent portion 24 are both spiral.
  • the shape of the first bent portion 23 and the second bent portion 24 is any one of the following: a square spiral shape, an arbitrary polygonal spiral shape, a circular spiral shape, or an elliptical spiral shape.
  • the first bent portion 23 and the second bent portion 24 are both in a zigzag shape.
  • the shape of the first bent portion 23 and the second bent portion 24 is any one of the following: a square zigzag shape, a triangular zigzag shape, or a circular arc shape.
  • the thin film transistor structure 20 further includes a gate layer 25, and an active layer 26 disposed on the gate layer 25.
  • the source 21 and the drain 22 are disposed on the active layer 26.
  • the gate layer 25 and the active layer 26 are both circular structures.
  • Embodiments of the present disclosure also provide an array substrate including the thin film transistor structure 20 described above.
  • the source and the drain each include a bent portion, and the bent portions of the two are nested and spaced apart from each other, the relative width between the source and the drain can be increased. That is, the channel width-to-length ratio W/L is increased, so that the corresponding rising current can be increased, and the charging rate of the thin film transistor structure can be improved.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • the display device in the embodiment of the present disclosure may be: a liquid crystal display panel, an electronic paper, an organic light emitting diode panel (Organic Light-Emitting Diode, referred to as OLED panel), mobile phones, tablets, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • OLED panel Organic Light-Emitting Diode
  • the display device provided by the embodiment of the present disclosure can increase the relative width W between the source and the drain, since the source and the drain each include a bent portion, and the bent portions of the two are nested and spaced apart from each other. That is, the channel width to length ratio W/L is increased, so that the corresponding rising current can be increased, and the charging rate of the thin film transistor structure can be improved.
  • the embodiment of the present disclosure further provides a mask, including a mask body 30.
  • the mask body 30 includes a light transmitting region 31 and an opaque region 32, and the opaque region includes the first a light transmissive region 33 for forming a source 21 including a first bent portion 23, and a second opaque region 34 for forming a second bend
  • the drain 22 of the portion 24, the first bent portion 23 and the second continuous bent portion 24 are nested and spaced apart from each other.
  • the projection of the first bent portion 23 on the second bent portion 24 covers at least a portion of the structure of the second bent portion 24.
  • the source electrode 21 and the drain electrode 22 formed by using the mask provided by the embodiment of the present disclosure each include a bent portion, the bent portions of the two are nested and spaced apart from each other, and the bent portion of the source 21 is at the drain 22
  • the projection on the bent portion covers at least part of the structure of the drain 22, so that the relative width W between the source 21 and the drain 22 can be increased, that is, the channel width to length ratio W/L is increased, so that the correspondence can be improved.
  • the rising current increases the charging rate of the thin film transistor structure 20.
  • the embodiment of the present disclosure further provides a method for fabricating a thin film transistor structure for improving a charging rate of a thin film transistor structure, the preparation method comprising:
  • the source includes a first bent portion
  • the drain includes a second bent portion
  • the first bent portion and the second bent portion are mutually connected
  • the sleeve is nested and spaced apart, and the projection of the first bend on the second bend covers at least a portion of the structure of the second bend.
  • the patterning process in step 802 may be a conventional patterning process, and may include, for example, photoresist coating, exposure, development, etching, and photoresist stripping.
  • the source and the drain each include a bent portion
  • the bent portions of the two are nested and spaced apart from each other, and the bent portion of the source is bent at the drain.
  • the projection on the folded portion covers at least part of the structure of the drain, so that the relative width W between the source and the drain can be increased, that is, the channel width to length ratio W/L is increased, so that the corresponding rising current can be increased. Further, the charging rate of the thin film transistor structure can be increased.
  • first bent portion and the second bent portion may both be spiral.
  • the shape of the first bent portion and the second bent portion is any one of the following: a square spiral shape, an arbitrary polygonal spiral shape, a circular spiral shape, or an elliptical spiral shape. Since the spiral first bent portion and the spiral second bent portion are nested and spaced apart from each other on the active layer, the relative width W between the source and the drain can be further increased, so that Further increasing the charging rate of the thin film transistor structure.
  • the first bent portion and the second bent portion are both in a zigzag shape.
  • the shape of the first bent portion and the second bent portion is any one of the following: a square zigzag shape, a triangular zigzag shape, or a circular arc shape. Since the first bent portion of the tooth shape and the second bent portion of the zigzag shape are nested and spaced apart from each other, the relative width W between the source and the drain can be further increased, so that the thin film transistor structure can be further improved. Charging rate.
  • the array substrate and the display device provided by the embodiments of the present disclosure may have the advantages of the thin film transistor structure 20 provided by the above embodiments.
  • the structure implementation refer to the description of the thin film transistor structure 20 in the above embodiment, and details are not described herein again.
  • the thin film transistor structure and the preparation method thereof, the array substrate, and the reticle provided by the embodiments of the present disclosure may be adapted to implement a display function, but are not limited thereto.
  • a thin film transistor structure comprising: a source and a drain provided in the same layer, wherein the source includes a first bent portion, and the drain includes a second bent portion, the first bend The fold portion and the second bent portion are nested and spaced apart from each other.
  • the thin film transistor structure according to any one of (1) to (5), wherein the thin film transistor structure further includes a gate layer, and an active layer provided on the gate layer, The source and the drain are disposed on the active layer, and the gate layer and the active layer are both circular structures.
  • An array substrate comprising the thin film transistor structure according to any one of (1) to (6).
  • a mask comprising a mask body, the mask body comprising a light transmissive region and an opaque region, the opaque region comprising a first opaque region and a second opaque region, The first opaque region is configured to cover a source including the first bent portion, and the second opaque region is configured to cover a drain including the second bent portion, the first bent portion and the The second bends are nested and spaced apart from one another.
  • a method of fabricating a thin film transistor structure comprising:
  • a pattern including a source and a drain on the active layer by a patterning process, wherein the source includes a first bent portion, and the drain includes a second bent portion, the first bent portion And the second bent portion is nested and spaced apart from each other.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管结构及其制备方法、阵列基板、掩模板。所述薄膜晶体管结构(20)包括：同层设置的源极(21)和漏极(22)，其中，所述源极(21)包括第一弯折部(23)，所述漏极(22)包括第二弯折部(23)，所述第一弯折部(23)与所述第二弯折部(24)彼此套嵌且间隔开。

Description

薄膜晶体管结构及其制备方法、阵列基板、掩模板 技术领域
本公开实施例涉及薄膜晶体管结构及其制备方法、阵列基板、掩模板。
背景技术
随着显示技术的发展，人们对各项显示性能的要求也越来越高。在影响薄膜晶体管的显示性能的参数中，上升电流备受关注，提高上升电流能够有效提高薄膜晶体管结构的充电速率。其中，上升电流通过公式
Figure PCTCN2015076957-appb-000001
计算得到，Ion为上升电流，W/L为沟道宽长比，Cox为单位面积上栅线层与有源层之间的电容，u为电子迁移率，Vgs为外加电压与充电后电压之间的差值，Vth为电压阈值。
发明内容
本公开的一实施例提供一种薄膜晶体管结构，包括：同层设置的源极和漏极，其中，所述源极包括第一弯折部，所述漏极包括第二弯折部，所述第一弯折部与所述第二弯折部彼此套嵌且间隔开。
本公开的另一实施例提供一种阵列基板，包括上述薄膜晶体管结构。
本公开的又一实施例提供一种掩模板，包括掩模板主体，所述掩模板主体包括透光区和不透光区，所述不透光区包括第一不透光区和第二不透光区，所述第一不透光区用于掩盖包括第一弯折部的源极，所述第二不透光区用于掩盖包括第二弯折部的漏极，所述第一弯折部与所述第二弯折彼此套嵌且间隔开。
本公开的又一实施例提供一种薄膜晶体管结构的制备方法，包括：形成有源层；以及通过构图工艺在所述有源层上形成包括源极和漏极的图形，其中，所述源极包括第一弯折部，所述漏极包括第二弯折部，所述第一弯折部与所述第二弯折部彼此套嵌且间隔开。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为相关技术中薄膜晶体管结构的示意图；
图2为本公开实施例提供的薄膜晶体管结构的示意图；
图3A为图2中源极的局部放大示意图；
图3B为图2中漏极的局部放大示意图；
图3C为图2中源极和漏极的局部放大示意图；
图4为本公开实施例提供的另一种薄膜晶体管结构的示意图；
图5为图4中源极和漏极的局部放大示意图；
图6为形成图4中源极和漏极的掩模板的示意图；
图7为形成图5中源极和漏极的掩模板的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
通过提高沟道宽长比(Width/Length，以下简称：W/L)，可实现对上升电流Ion的提高。请参阅图1，在相关技术的薄膜晶体管结构中，L是指源极11和漏极12之间的距离，W是指垂直于L的源极11和漏极12之间的相对宽度。然而，由于图1所示的薄膜晶体管结构存在限制，通过提高沟道宽长比对上升电流的提高不够，从而导致薄膜晶体管结构的充电速率仍较低。
本公开的实施例提供一种薄膜晶体管结构及其制备方法、阵列基板、掩模板，能够解决薄膜晶体管结构的充电效率较低的问题。
请参阅图3A-3C及图5，本公开实施例提供的薄膜晶体管结构20包括：同层设置的源极21和漏极22，源极21包括非直线构型的第一弯折部23(参见图3A中的虚线椭圆所示)，漏极22包括连续非直线构型的第二弯折部24(参见图3B中的虚线椭圆所示)，第一弯折部23与第二弯折部24构造为 彼此套嵌且间隔开。在图3A-3C以及图5所示实施例中，第一弯折部23和第二弯折部24构造为分别具有多个拐角。第一弯折部23在第二弯折部24上的投影覆盖第二弯折部24的至少一部分。在一个示例中，第一弯折部23和第二弯折部24之间的间距L恒定。
本公开实施例提供的薄膜晶体管结构，源极21和漏极22分别包括第一和第二弯折部，且第一和第二弯折部彼此套嵌且间隔开，源极21的弯折部分在漏极22的弯折部上的投影覆盖漏极22的至少一部分，请参阅图3C，源极21和漏极22之间的相对宽度W等于W1、W2、W3、W4及W5之和，与图1所示的相关技术的薄膜晶体管结构中源极11和漏极12之间的相对宽度W相比，本公开实施例的薄膜晶体管结构可以极大地增大源极21和漏极22之间的相对宽度W，即增大沟道宽长比W/L，从而可以提高对应的上升电流，进而可以提高薄膜晶体管结构20的充电速率。
为了进一步增大源极21和漏极22之间的相对宽度W，请参阅图3A-3C，第一弯折部23和第二弯折部24均为螺旋状。
可选地，第一弯折部23和第二弯折部24的形状为下述任一种：正方形螺旋状、任意多边形螺旋状、圆形螺旋状或椭圆形螺旋状。
为了进一步增大源极21和漏极22之间的相对宽度W，请参阅图5，第一弯折部23和第二弯折部24均为锯齿状。
可选地，第一弯折部23和第二弯折部24的形状为下述任一种：方形锯齿状、三角形锯齿状或圆弧形锯齿状。
例如，请参阅图2及图4，薄膜晶体管结构20还包括栅极层25，以及设于栅极层25上的有源层26，源极21和漏极22设置在有源层26上，栅极层25和有源层26均为圆形结构。
本公开实施例还提供了一种阵列基板，包括上述的薄膜晶体管结构20。
本公开实施例提供的阵列基板，由于源极和漏极均包括弯折部分，且二者的弯折部分彼此套嵌且间隔开，因此可以增大源极和漏极之间的相对宽度W，即增大沟道宽长比W/L，从而可以提高对应的上升电流，进而可以提高薄膜晶体管结构的充电速率。
本公开实施例还提供了一种显示装置，包括上述的阵列基板。本公开实施例中的显示装置可以为：液晶显示面板、电子纸、有机发光二极管面板 (Organic Light-Emitting Diode，简称OLED面板)、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供的显示装置，由于源极和漏极均包括弯折部分，二者的弯折部分彼此套嵌且间隔开，因此可以增大源极和漏极之间的相对宽度W，即增大沟道宽长比W/L，从而可以提高对应的上升电流，进而可以提高薄膜晶体管结构的充电速率。
本公开实施例还提供了一种掩模板，包括掩模板主体30，请参阅图6及图7，掩模板主体30包括透光区31和不透光区32，不透光区包括第一不透光区33和第二不透光区34，第一不透光区33用于形成包括第一弯折部23的源极21，第二不透光区34用于形成包括第二弯折部24的漏极22，第一弯折部23与第二连续弯折部24彼此套嵌且间隔开。第一弯折部23在第二弯折部24上的投影覆盖第二弯折部24的至少部分结构。
采用本公开实施例提供的掩模板所形成的源极21和漏极22均包括弯折部分，二者的弯折部分彼此套嵌且间隔开，并且源极21的弯折部分在漏极22的弯折部上的投影覆盖漏极22的至少部分结构，因此可以增大源极21和漏极22之间的相对宽度W，即增大沟道宽长比W/L，从而可以提高对应的上升电流，进而可以提高薄膜晶体管结构20的充电速率。
本公开实施例还提供了一种薄膜晶体管结构的制备方法，用于提高薄膜晶体管结构的充电速率，所述制备方法包括：
801、形成有源层。
802、通过构图工艺在有源层上形成包括源极和漏极的图形，源极包括第一弯折部，漏极包括第二弯折部，第一弯折部与第二弯折部彼此套嵌且间隔开，且第一弯折部在第二弯折部上的投影覆盖第二弯折部的至少部分结构。
其中，步骤802中的构图工艺可以为传统的构图工艺，例如可以包括：光刻胶涂敷、曝光、显影、刻蚀及光刻胶剥离。
本公开实施例提供的薄膜晶体管结构的制备方法，由于源极和漏极均包括弯折部分，二者的弯折部分彼此套嵌且间隔开，并且源极的弯折部分在漏极的弯折部上的投影覆盖漏极的至少部分结构，因此可以增大源极和漏极之间的相对宽度W，即增大沟道宽长比W/L，从而可以提高对应的上升电流， 进而可以提高薄膜晶体管结构的充电速率。
可选地，第一弯折部和第二弯折部可以均为螺旋状。其中，第一弯折部和第二弯折部的形状为下述任一种：正方形螺旋状、任意多边形螺旋状、圆形螺旋状或椭圆形螺旋状。由于螺旋状的第一弯折部和螺旋状的第二弯折部彼此套嵌且间隔开设置在有源层上，因此能够进一步增大源极和漏极之间的相对宽度W，从而可以进一步提高薄膜晶体管结构的充电速率。
可选地，第一弯折部和第二弯折部均为锯齿状。其中，第一弯折部和第二弯折部的形状为下述任一种：方形锯齿状、三角形锯齿状或圆弧形锯齿状。由于齿状的第一弯折部和锯齿状的第二弯折部彼此套嵌且间隔开设置，因此能够进一步增大源极和漏极之间的相对宽度W，从而可以进一步提高薄膜晶体管结构的充电速率。
本公开实施例提供的阵列基板和显示装置可以具有上述实施例提供的薄膜晶体管结构20的优点，其结构实现请参见上述实施例对薄膜晶体管结构20的说明，在此不再赘述。本公开实施例提供的薄膜晶体管结构及其制备方法、阵列基板、掩模板可以适用于实现显示功能，但不仅限于此。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
根据上述描述，根据本公开的实施例至少可以提供以下结构和方法：
(1)一种薄膜晶体管结构，包括：同层设置的源极和漏极，其中，所述源极包括第一弯折部，所述漏极包括第二弯折部，所述第一弯折部与所述第二弯折部彼此套嵌且间隔开。
(2)根据(1)所述的薄膜晶体管结构，其中，所述第一弯折部和所述第二弯折部均为螺旋状。
(3)根据(2)所述的薄膜晶体管结构，其中，所述第一弯折部和所述第二弯折部的形状为下述任一种：正方形螺旋状、任意多边形螺旋状、圆形螺旋状或椭圆形螺旋状。
(4)根据(1)所述的薄膜晶体管结构，其中，所述第一弯折部和所述第二弯折部均为锯齿状。
(5)根据(4)所述的薄膜晶体管结构，其中，所述第一弯折部和所述第二弯折部的形状为下述任一种：方形锯齿状、三角形锯齿状或圆弧形锯齿 状。
(6)根据(1)至(5)中任一项所述的薄膜晶体管结构，其中，所述薄膜晶体管结构还包括栅极层，以及设于所述栅极层上的有源层，所述源极和所述漏极设置在所述有源层上，所述栅极层和所述有源层均为圆形结构。
(7)一种阵列基板，包括(1)至(6)中任一项所述的薄膜晶体管结构。
(8)一种掩模板，包括掩模板主体，所述掩模板主体包括透光区和不透光区，所述不透光区包括第一不透光区和第二不透光区，所述第一不透光区用于掩盖包括第一弯折部的源极，所述第二不透光区用于掩盖包括第二弯折部的漏极，所述第一弯折部与所述第二弯折彼此套嵌且间隔开。
(9)一种薄膜晶体管结构的制备方法，包括：
形成有源层；以及
通过构图工艺在所述有源层上形成包括源极和漏极的图形，其中所述源极包括第一弯折部，所述漏极包括第二弯折部，所述第一弯折部与所述第二弯折部彼此套嵌且间隔开。
(10)根据(9)所述的制备方法，其中，所述第一弯折部和所述第二弯折部均为螺旋状；所述第一弯折部和所述第二弯折部的形状为下述任一种：正方形螺旋状、任意多边形螺旋状、圆形螺旋状或椭圆形螺旋状。
(11)根据(9)所述的制备方法，其中，所述第一弯折部和所述第二弯折部均为锯齿状；所述第一弯折部和所述第二弯折部的形状为下述任一种：方形锯齿状、三角形锯齿状或圆弧形锯齿状。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本申请要求于2015年1月21日递交的中国专利申请第201510030108.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种薄膜晶体管结构，包括：同层设置的源极和漏极，其中，所述源极包括第一弯折部，所述漏极包括第二弯折部，所述第一弯折部与所述第二弯折部彼此套嵌且间隔开。
  2. 根据权利要求1所述的薄膜晶体管结构，其中，所述第一弯折部和所述第二弯折部均为螺旋状。
  3. 根据权利要求2所述的薄膜晶体管结构，其中，所述第一弯折部和所述第二弯折部的形状为下述任一种：正方形螺旋状、任意多边形螺旋状、圆形螺旋状或椭圆形螺旋状。
  4. 根据权利要求1所述的薄膜晶体管结构，其中，所述第一弯折部和所述第二弯折部均为锯齿状。
  5. 根据权利要求4所述的薄膜晶体管结构，其中，所述第一弯折部和所述第二弯折部的形状为下述任一种：方形锯齿状、三角形锯齿状或圆弧形锯齿状。
  6. 根据权利要求1至5中任一项所述的薄膜晶体管结构，其中，所述薄膜晶体管结构还包括栅极层，以及设于所述栅极层上的有源层，所述源极和所述漏极设置在所述有源层上，所述栅极层和所述有源层均为圆形结构。
  7. 一种阵列基板，包括：权利要求1至6中任一项所述的薄膜晶体管结构。
  8. 一种掩模板，包括掩模板主体，所述掩模板主体包括透光区和不透光区，所述不透光区包括第一不透光区和第二不透光区，所述第一不透光区用于掩盖包括第一弯折部的源极，所述第二不透光区用于掩盖包括第二弯折部的漏极，所述第一弯折部与所述第二弯折彼此套嵌且间隔开。
  9. 一种薄膜晶体管结构的制备方法，包括：
    形成有源层；以及
    通过构图工艺在所述有源层上形成包括源极和漏极的图形，其中所述源极包括第一弯折部，所述漏极包括第二弯折部，所述第一弯折部与所述第二弯折部彼此套嵌且间隔开。
  10. 根据权利要求9所述的制备方法，其中，所述第一弯折部和所述第 二弯折部均为螺旋状；所述第一弯折部和所述第二弯折部的形状为下述任一种：正方形螺旋状、任意多边形螺旋状、圆形螺旋状或椭圆形螺旋状。
  11. 根据权利要求9所述的制备方法，其中，所述第一弯折部和所述第二弯折部均为锯齿状；所述第一弯折部和所述第二弯折部的形状为下述任一种：方形锯齿状、三角形锯齿状或圆弧形锯齿状。
PCT/CN2015/076957 2015-01-21 2015-04-20 薄膜晶体管结构及其制备方法、阵列基板、掩模板 WO2016115783A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/892,091 US20160351670A1 (en) 2015-01-21 2015-04-20 Thin film transistor structure and manufacturing method thereof, array substrate, and mask

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510030108.X 2015-01-21
CN201510030108.XA CN104600124A (zh) 2015-01-21 2015-01-21 薄膜晶体管结构及其制备方法、阵列基板、掩膜板

Publications (1)

Publication Number Publication Date
WO2016115783A1 true WO2016115783A1 (zh) 2016-07-28

Family

ID=53125768

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/076957 WO2016115783A1 (zh) 2015-01-21 2015-04-20 薄膜晶体管结构及其制备方法、阵列基板、掩模板

Country Status (3)

Country Link
US (1) US20160351670A1 (zh)
CN (1) CN104600124A (zh)
WO (1) WO2016115783A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916651B (zh) * 2015-07-07 2018-06-15 京东方科技集团股份有限公司 阵列基板和显示装置
CN108873530B (zh) * 2018-07-30 2021-10-08 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN111092092A (zh) * 2018-10-08 2020-05-01 Tcl集团股份有限公司 a-Si TFT器件驱动的主动背光LED光源板及背光模组
CN110634932B (zh) * 2019-09-27 2022-08-16 京东方科技集团股份有限公司 一种可弯曲显示面板的设计方法及可弯曲显示面板
US11581423B2 (en) 2020-06-04 2023-02-14 Samsung Electronics Co., Ltd. Integrated circuit devices including an element having a non-linear shaped upper surface and methods of forming the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030603A (zh) * 2006-03-03 2007-09-05 中华映管股份有限公司 薄膜晶体管与薄膜晶体管阵列基板
CN102800692A (zh) * 2012-08-09 2012-11-28 深圳市华星光电技术有限公司 具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路
CN102867853A (zh) * 2011-07-08 2013-01-09 新唐科技股份有限公司 金属氧化物半场效晶体管
JP2014110323A (ja) * 2012-12-03 2014-06-12 Japan Display Inc 表示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001017029A1 (en) * 1999-08-31 2001-03-08 E Ink Corporation Transistor for an electronically driven display
US7358530B2 (en) * 2003-12-12 2008-04-15 Palo Alto Research Center Incorporated Thin-film transistor array with ring geometry
CN202142535U (zh) * 2011-07-22 2012-02-08 京东方科技集团股份有限公司 一种薄膜场效应晶体管和液晶显示器
KR102072803B1 (ko) * 2013-04-12 2020-02-04 삼성디스플레이 주식회사 박막 반도체 장치 및 유기 발광 표시 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030603A (zh) * 2006-03-03 2007-09-05 中华映管股份有限公司 薄膜晶体管与薄膜晶体管阵列基板
CN102867853A (zh) * 2011-07-08 2013-01-09 新唐科技股份有限公司 金属氧化物半场效晶体管
CN102800692A (zh) * 2012-08-09 2012-11-28 深圳市华星光电技术有限公司 具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路
JP2014110323A (ja) * 2012-12-03 2014-06-12 Japan Display Inc 表示装置

Also Published As

Publication number Publication date
CN104600124A (zh) 2015-05-06
US20160351670A1 (en) 2016-12-01

Similar Documents

Publication Publication Date Title
WO2016115783A1 (zh) 薄膜晶体管结构及其制备方法、阵列基板、掩模板
JP6460582B2 (ja) Ａｍｏｌｅｄバックパネルの製造方法
US9508747B2 (en) Thin film transistor array substrate
US10505002B2 (en) Thin film transistor and manufacturing method thereof, display substrate and display panel
US9704884B2 (en) Low temperature poly-silicon (LTPS) thin film transistor based liquid crystal display
US10734460B2 (en) Display device having conductive line
JP6483843B2 (ja) アレイ基板及びその製造方法、表示装置
WO2016045423A1 (en) Array substrate, fabrication method thereof and display device
US8853066B2 (en) Method for manufacturing pixel structure
JP2007027735A5 (zh)
WO2019179146A1 (zh) 薄膜晶体管及其制造方法、柔性显示屏及显示装置
WO2018166190A1 (zh) 阵列基板及其制备方法、显示面板
US9450103B2 (en) Thin film transistor, method for manufacturing the same, display device and electronic product
WO2016090725A1 (zh) 一种ltps阵列基板
US10727307B2 (en) Display substrate and fabrication method thereof, and display device
WO2018214802A1 (zh) Oled基板及其制备方法、显示装置及其制备方法
WO2016058321A1 (zh) 薄膜晶体管、其制作方法、阵列基板及显示装置
US10923597B2 (en) Transistor and method for manufacturing the same, display substrate, and display apparatus
WO2016107017A1 (zh) 阵列基板及其制作方法及显示装置
WO2015062271A1 (zh) 一种底发射基板、显示装置及该基板的制造方法
WO2019052265A1 (zh) 薄膜晶体管、其制造方法及电子装置
US20170148884A1 (en) Thin film transistor, array substrate and display device having the same, and fabricating method thereof
US10134765B2 (en) Oxide semiconductor TFT array substrate and method for manufacturing the same
TW200837957A (en) Semiconductor structure of liquid crystal display and manufacturing method thereof
WO2018006412A1 (en) Thin film transistor, gate drive on array and display apparatus having the same, and fabricating method thereof

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14892091

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15878459

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15878459

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 02.02.2018)

122 Ep: pct application non-entry in european phase

Ref document number: 15878459

Country of ref document: EP

Kind code of ref document: A1