WO2016107311A1 - Amoled阵列基板及其制造方法、显示装置 - Google Patents

Amoled阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2016107311A1
WO2016107311A1 PCT/CN2015/094754 CN2015094754W WO2016107311A1 WO 2016107311 A1 WO2016107311 A1 WO 2016107311A1 CN 2015094754 W CN2015094754 W CN 2015094754W WO 2016107311 A1 WO2016107311 A1 WO 2016107311A1
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auxiliary line
array substrate
auxiliary
electrode
projection
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PCT/CN2015/094754
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English (en)
French (fr)
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曹昆
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京东方科技集团股份有限公司
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Priority to US15/121,960 priority Critical patent/US9831297B2/en
Priority to EP15874992.9A priority patent/EP3242326B1/en
Publication of WO2016107311A1 publication Critical patent/WO2016107311A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/814—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to an active matrix organic light emitting diode display (AMOLED) array substrate, a method of fabricating an AMOLED array substrate, and a display device having the array substrate.
  • AMOLED active matrix organic light emitting diode display
  • the top electrode of the OLED device since the top electrode of the OLED device needs to transmit light, the top electrode is usually made thin. When the panel size is increased, the internal resistance of the top electrode is large. The high top electrode in-plane resistance increases the IR Drop. Excessive IR Drop can cause uneven in-plane brightness, which affects the uniformity of the picture.
  • the top electrode is usually formed as a monolithic planar electrode, which is also referred to as a plate electrode, and thus the present invention is hereinafter referred to as a plate electrode.
  • the present invention has been proposed in order to improve or improve the uniformity of the in-plane resistance of the plate-shaped electrode of the top-emitting AMOLED and to reduce the in-plane resistance of the plate-shaped electrode.
  • an AMOLED array substrate comprising: a plate electrode, wherein the plate electrode is electrically connected to an electrode lead disposed at a periphery of the plate electrode; and a plurality of pixel electrodes arranged in an array; An organic light-emitting body between the plurality of pixel electrodes and the plate-shaped electrode; at least one first auxiliary line disposed in the same layer as the pixel electrode and not intersecting the pixel electrode; and at least one second auxiliary line and the data line of the AMOLED array substrate And the source and drain electrodes do not intersect and are disposed in the same layer as the source and drain electrodes of the AMOLED array substrate, wherein: the projection of the first auxiliary line and the second auxiliary line on the plate electrode is located on the pixel defining layer of the AMOLED array substrate on the plate electrode And at least partially overlapping; and the first auxiliary line is electrically connected to the second auxiliary line through the first via and electrically connected to the plate electrode through a second
  • the at least one first auxiliary line includes a plurality of first auxiliary lines, and the first auxiliary lines are parallel to the gate lines of the AMOLED array substrate;
  • the at least one second auxiliary line includes a plurality of second auxiliary lines, and the second auxiliary The line is parallel to the data line of the AMOLED array substrate;
  • the projection of the plurality of first auxiliary lines and the plurality of second auxiliary lines on the plate electrode is a mesh projection formed by a plurality of meshes.
  • the pixel electrodes are in one-to-one correspondence with the mesh of the mesh projection, and the projection of each pixel electrode on the plate electrode is located in a corresponding one of the mesh projections.
  • the projection of the second via on the plate electrode is located within a coincident projection of the first auxiliary line and the second auxiliary line, and the projections of the first via and the second via on the plate electrode coincide.
  • each of the first auxiliary lines is disposed corresponding to the gate lines, and the projection of the first auxiliary lines and the corresponding gate lines on the plate electrodes at least partially coincide.
  • the AMOLED array substrate further includes a passivation layer disposed between the layer where the source and drain electrodes are located and the pixel electrode, the first via hole passing through the passivation layer to electrically connect the first auxiliary line and Second auxiliary line.
  • the AMOLED array substrate further includes a planar layer disposed between the passivation layer and the pixel electrode, the first via extending through the passivation layer and the planarization layer to electrically connect the first auxiliary line and the second auxiliary line.
  • the electrode lead is disposed around the entire circumference of the plate electrode; and at least one end of each auxiliary line is electrically connected to the electrode lead.
  • the projection of the coincidence of the first auxiliary line and the second auxiliary line is at least located in a central region of the plate electrode.
  • a display device comprising any one of the above AMOLED array substrates.
  • a method of fabricating an AMOLED array substrate comprising: a plurality of pixel electrodes arranged in an array; a plate electrode, a plate electrode and a plate disposed on the plate An electrode lead around the electrode is electrically connected; and an organic illuminator disposed between the pixel electrode and the plate electrode, the method comprising the steps of: forming at least one first auxiliary disposed in the same layer as the pixel electrode and not intersecting the pixel electrode a line forming at least one second auxiliary line disposed in a same layer as the source and drain electrodes of the AMOLED array substrate, the first auxiliary line and the second auxiliary line being on the plate electrode
  • the projection is located on the projection of the pixel defining layer of the AMOLED array substrate on the plate electrode and at least Sub-coinciding; forming a first via for electrically connecting the first auxiliary line and the second auxiliary line at a position corresponding to a coincident
  • the step of forming the at least one second auxiliary line comprises forming a plurality of first auxiliary lines, and the first auxiliary lines are formed in parallel with the gate lines of the AMOLED array substrate; and the step of forming at least one second auxiliary line
  • the method includes forming a plurality of second auxiliary lines, and the second auxiliary lines are formed to be parallel to the data lines of the AMOLED array substrate, such that the projections of the plurality of first auxiliary lines and the plurality of second auxiliary lines on the plate electrodes are A mesh projection formed by a plurality of meshes.
  • the pixel electrodes are formed in one-to-one correspondence with the mesh of the mesh projection, and the projection of each pixel electrode on the plate electrode is located in the mesh projection formed by the first auxiliary line and the second auxiliary line. Corresponding to a grid.
  • the second via hole is formed at a position corresponding to the coincident projection of the first auxiliary line and the second auxiliary line, and the projection of the first via hole and the second via hole on the plate electrode coincide.
  • each of the first auxiliary lines is formed corresponding to the gate lines, and the projection of the first auxiliary lines and the corresponding gate lines on the plate electrodes at least partially coincide.
  • a passivation layer is formed between the layer where the source drain electrode is located and the pixel electrode, and the first via hole passes through the passivation layer to electrically connect the first auxiliary line and the second auxiliary line.
  • a planarization layer is formed between the passivation layer and the pixel electrode, the first via hole penetrating the passivation layer and the planarization layer to electrically connect the first auxiliary line and the second auxiliary line.
  • the first auxiliary line is made of the same material as the material of the pixel electrode, and the pixel electrode and the first auxiliary line are simultaneously formed by one patterning process; and the second auxiliary line is formed by the source and drain electrodes
  • the material is made of the same material, and the source and drain electrodes and the second auxiliary line are simultaneously formed by one patterning process.
  • the method further comprises the step of blocking the second via hole when the organic light emitter is applied to prevent the organic light emitter from entering the second via.
  • the electrode lead is disposed around the entire circumference of the plate electrode; and the method further includes the step of electrically connecting at least one end of each of the auxiliary lines to the electrode lead.
  • the at least one first auxiliary line formed includes a first auxiliary line projected through the central region of the plate electrode on the plate electrode, and at least one second auxiliary formed The line includes a second auxiliary line projected through the central region of the plate electrode on the plate electrode.
  • the first auxiliary line is electrically connected to the second auxiliary line through the first via hole, and is electrically connected to the plate electrode through the second via hole formed in the pixel defining layer of the AMOLED array substrate, thereby being first
  • the resistor network formed by the auxiliary line and the second auxiliary line is directly connected in parallel with the plate electrode, which can reduce the in-plane resistance of the plate electrode and improve the uniformity of the in-plane resistance of the plate electrode.
  • FIG. 1 is a schematic plan view of an AMOLED array substrate provided by an exemplary embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of the AMOLED array substrate taken along line L in FIG. 1.
  • an embodiment of the present invention provides an AMOLED array substrate, including:
  • the plate electrode 10 is electrically connected to the electrode lead 20 disposed at the periphery of the plate electrode 10;
  • An organic light-emitting body 40 disposed between the plurality of pixel electrodes 30 and the plate-like electrode 10;
  • At least one first auxiliary line 50 disposed in the same layer as the pixel electrode 30 and not intersecting the pixel electrode;
  • the at least one second auxiliary line 60 does not intersect with the data line DL and the source/drain electrodes of the AMOLED array substrate and is disposed in the same layer as the source and drain electrodes of the AMOLED array substrate;
  • the projection of the first auxiliary line 50 and the second auxiliary line 60 on the plate electrode 10 is located in the projection of the pixel defining layer 80 of the AMOLED array substrate on the plate electrode 10, and the first auxiliary line 50 Projecting at least partially coincident with the projection of the second auxiliary line 60 on the plate electrode 10;
  • the first auxiliary line 50 is electrically connected to the second auxiliary line 60 through the first via 92, wherein the projection of the first via 92 on the plate electrode 10 is located at the first auxiliary line 50 and the second auxiliary line 60 is at the plate electrode Within the coincident projection on 10, and the first auxiliary line 50 is electrically connected to the plate electrode 10 through a second via 94 formed in the pixel defining layer 80 of the AMOLED array substrate.
  • the AMOLED array substrate further includes a base substrate 120, and the above structures are all disposed on the base substrate 120.
  • the base substrate 120 may be made of a material such as glass, transparent resin, quartz, sapphire or the like, which is not limited in the present invention.
  • the OLED (Organic Light-Emitting Diode) in the AMOLED array substrate provided by the embodiment of the present invention may be a common OLED or a WOLED (White Light Organic Light Emitting Diode), which is not limited by the present invention.
  • the plate electrode 10 can serve as a cathode of the OLED.
  • the pixel electrode 30 serves as an anode of the OLED.
  • the plate electrode 10 can also serve as an anode of the OLED, and the pixel electrode 30 serves as a cathode of the OLED device. Thereby forming an inverted OLED structure.
  • the invention is not limited thereto, and can be selected according to the design requirements of the device.
  • the first auxiliary line 50 is electrically connected to the second auxiliary line 60 through the first via 92, and passes through the second via 94 and the plate formed in the pixel defining layer 80 of the AMOLED array substrate.
  • the electrodes 10 are electrically connected such that the resistor network formed by the first auxiliary line 50 and the second auxiliary line 60 is directly connected in parallel with the plate electrode 10.
  • the in-plane resistance of the plate electrode 10 can be lowered, and the uniformity of the in-plane resistance of the plate electrode 10 can be improved.
  • the at least one first auxiliary line includes a plurality of first auxiliary lines 50, and the first auxiliary lines 50 are parallel to the gate lines GL of the AMOLED array substrate; the at least one second auxiliary line includes a plurality of second auxiliary lines 60 And the second auxiliary line 60 is parallel to the data line DL of the AMOLED array substrate; the projection of the plurality of first auxiliary lines 50 and the plurality of second auxiliary lines 60 on the plate electrode 10 is composed of a plurality of grids The resulting mesh projection is shown in Figure 1. At this time, the projections of the first auxiliary line 50 and the second auxiliary line 60 on the plate-like electrode 10 have overlapping portions (intersection points), as shown by the symbol A in FIG. 1, and hereinafter, these intersections are referred to as projections. Intersection.
  • the first auxiliary line 50 and the second auxiliary line 60 are substantially evenly distributed, so that the electrical connection points of the first auxiliary line 50 and the plate electrode 10 are substantially evenly distributed, so that the entire plate electrode 10 can be further improved.
  • the uniformity of the in-plane resistance further increases the in-plane of the plate electrode 10 Uniformity of brightness.
  • first auxiliary line 50 and the second auxiliary line 60 may also be disposed in parallel, which is not limited in the present invention, as long as the projections of the first auxiliary line 50 and the second auxiliary line 60 on the plate electrode 10 are located in the pixel definition.
  • the layer 80 is at least partially overlapped in the projection on the plate electrode 10, the first auxiliary line 50 does not intersect with the pixel electrode 30 disposed in the same layer, and the second auxiliary line 60 does not intersect with the source and drain electrodes disposed in the same layer. .
  • a first auxiliary line 50 is disposed corresponding to each of the gate lines GL
  • a second auxiliary line 60 is disposed corresponding to each of the gate DL lines.
  • the electrodes 30 correspond one-to-one with the mesh in the mesh projection, and the projection of each of the pixel electrodes 30 on the plate electrode 10 is located within a corresponding one of the mesh projections.
  • the resistor network formed by the plurality of first auxiliary lines 50 and the plurality of second auxiliary lines 60 can be in electrical contact with the plate electrodes 10 at four points, thereby ensuring the The uniformity of the in-plane resistance of the portion corresponding to each pixel structure.
  • the second via 94 can also be disposed such that its projection on the plate electrode 10 is within the coincident projection of the first auxiliary line 50 and the second auxiliary line 60 on the plate electrode 10. .
  • the positions at which each of the first via holes 92 and each of the second via holes 94 are disposed correspond to the respective projection intersections.
  • the projections of the first via 92 and the second via 94 on the plate electrodes may coincide. In this way, the space of the non-light-emitting region of the array substrate can be effectively utilized.
  • the projection intersection of the first auxiliary line 50 and the second auxiliary line 60 includes a projection intersection substantially located at a central area of the plate electrode 10 (ie, a projection intersection of the first auxiliary line 50 and the second auxiliary line 60 is at least substantially Located in the central area of the plate electrode 10).
  • the center of the plate electrode 10 is generally farthest from the electrode lead 20. Electrically connecting the center of the plate electrode 10 to the resistance network formed by the auxiliary line helps to improve the uniformity of the in-plane resistance of the entire plate electrode 10.
  • first auxiliary line 50 and one second auxiliary line 60 may be used, and the projection intersections of the two auxiliary lines are substantially at the center position of the plate electrode 10.
  • first auxiliary line 50 corresponding to each gate line GL
  • second auxiliary lines 60 in FIG. 2 may also be reduced.
  • the numbers of the first auxiliary line 50 and the second auxiliary line 60 are not necessarily equal, but in order to ensure the uniformity of the in-plane resistance of the entire plate electrode 10, the first auxiliary line 50 and the second auxiliary line 60 should be substantially evenly distributed.
  • the projection of the plurality of pixel electrodes 30 on the plate electrode 10 is located within the same grid in the mesh projection, that is, the plurality of pixel electrodes 30 correspond to one grid.
  • each of the first auxiliary lines 50 is disposed corresponding to the gate lines GL, and the projection of the first auxiliary lines 50 and the corresponding gate lines GL on the plate electrodes 10 at least partially coincide. Since the gate line and the data line enclose the pixel structure in the AMOLED array substrate, the first auxiliary line 50 and the gate line GL are disposed to overlap each other, and the first auxiliary line 50 and the pixel electrode 30 are prevented from being in electrical contact with each other while avoiding The space occupied by the first auxiliary line 50 is reduced, that is, the space of the pixel electrode 30 is increased.
  • the AMOLED array substrate may further include a passivation layer 110 disposed between the source/drain electrode layer 70 (hereinafter, simply referred to as the source/drain electrode layer 70) and the pixel electrode 30.
  • the first via hole 92 passes through the passivation layer 110 of the AMOLED array substrate to electrically connect the first auxiliary line 50 and the corresponding second auxiliary line 60.
  • the AMOLED array substrate may further include a planar layer 100 disposed between the passivation layer 110 and the pixel electrode 30.
  • the first via 92 passes through the passivation layer 110 and the planarization layer 100 of the AMOLED array substrate.
  • the first auxiliary line 50 and the corresponding second auxiliary line 60 are electrically connected.
  • the electrode lead 20 is disposed around the entire circumference of the plate electrode 10; and at least one end of each of the auxiliary lines 50, 60 is electrically connected to the electrode lead 20.
  • the resistance network formed by the auxiliary lines 50 and 60 is directly connected in parallel with the plate electrode 10, and the uniformity of the in-plane resistance of the entire plate electrode 10 can be remarkably improved.
  • Vias 92 and/or 94 may be provided at locations corresponding to a portion of the coincident projection as desired.
  • Embodiments of the present invention also provide a display device including the above-described AMOLED array substrate.
  • the display device may be: an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • the in-plane resistance of the plate electrode 10 can be reduced, and the uniformity of the in-plane resistance of the entire plate electrode 10 can be improved, so that the display performance of the display panel can be improved.
  • the first auxiliary line 50 is electrically connected to the second auxiliary line 60 through the first via 92, and passes through the second via 94 and the plate formed in the pixel defining layer 80 of the AMOLED array substrate.
  • the electrodes 10 are electrically connected such that the resistor network formed by the first auxiliary line 50 and the second auxiliary line 60 is directly connected in parallel with the plate electrode 10.
  • Embodiments of the present invention also provide a method of fabricating an AMOLED array substrate having the above characteristics.
  • the AMOLED array substrate includes: a plurality of pixel electrodes arranged in an array; a plate electrode, the plate electrode is connected to the electrode lead disposed at the periphery of the plate electrode; and is disposed between the plurality of pixel electrodes and the plate electrode Organic illuminant.
  • the method of manufacturing an AMOLED array substrate according to the present invention may include the following steps:
  • the projection on the electrode 10 is located within the projection of the pixel defining layer 80 of the AMOLED array substrate on the plate electrode 10 and at least partially coincides;
  • a second via 94 for electrically connecting the first auxiliary line 50 to the plate electrode 10 is formed in the pixel defining layer of the AMOLED array substrate.
  • a plurality of first auxiliary lines 50 and a plurality of second auxiliary lines 60 may be formed.
  • the first auxiliary lines 50 are parallel to the gate lines GL of the AMOLED array substrate, and the second auxiliary lines 60 and the data lines of the AMOLED array substrate are formed.
  • the DLs are parallel, and the projection of the plurality of first auxiliary lines and the plurality of second auxiliary lines on the plate electrode 10 is a mesh projection formed by a plurality of meshes.
  • the first auxiliary line 50 and the second auxiliary line 60 are substantially evenly distributed, so that the electrical connection points of the first auxiliary line 50 and the plate electrode 10 are substantially evenly distributed, thereby further increasing the surface of the entire plate electrode 10. The uniformity of the internal resistance.
  • the pixel electrodes 30 are formed to correspond one-to-one with the mesh of the mesh projection, and the projection of each pixel electrode on the plate electrode 10 is located at a mesh projection formed by the first auxiliary line 50 and the second auxiliary line 60. In the corresponding one of the grids.
  • the resistance network formed by the plurality of first auxiliary lines 50 and the plurality of second auxiliary lines 60 can be at four points. The electrical contact with the plate electrode 10 ensures the uniformity of the in-plane resistance of the corresponding plate electrode of each pixel structure.
  • the second via 94 may also be formed at a position corresponding to the coincident projection of the first auxiliary line 50 and the second auxiliary line 60.
  • the positions at which each of the first via holes 92 and each of the second via holes 94 are disposed correspond to the respective projection intersections.
  • the projections of the first via 92 and the second via 94 on the plate electrode 10 may coincide. In this way, the space of the non-light-emitting region of the AMOLED array substrate can be effectively utilized.
  • the at least one first auxiliary line formed includes a first auxiliary line projected through the central region of the plate electrode on the plate electrode, and the at least one second auxiliary line formed is included on the plate electrode A second auxiliary line that projects through the central region of the plate electrode.
  • the projection intersection of the first auxiliary line 50 and the second auxiliary line 60 includes a projection intersection substantially at a central area of the plate electrode 10. In the case where the electrode lead 20 is disposed around the entire circumference of the plate electrode 10, the center of the plate electrode 10 is generally farthest from the electrode lead 20. Electrically connecting the center of the plate electrode 10 with the resistance network formed by the auxiliary lines 50 and 60 contributes to improving the uniformity of the in-plane resistance of the entire plate electrode 10.
  • each of the first auxiliary lines 50 is disposed corresponding to the gate line GL, and the projection of the first auxiliary line 50 and the corresponding gate line GL on the plate electrode 10 at least partially coincides. . Since the gate line GL and the data line DL enclose the pixel structure in the AMOLED array substrate, the first auxiliary line 50 and the gate line GL are disposed to overlap each other, while avoiding the first auxiliary line 50 from being in electrical contact with the pixel electrode 30. It is also possible to minimize the space of the non-display area occupied by the first auxiliary line 50, that is, to increase the space of the pixel electrode 30.
  • a passivation layer 110 may be formed between the source/drain electrode layer 70 and the pixel electrode 30.
  • the first via hole 92 passes through the passivation layer 110 of the AMOLED array substrate to be electrically connected.
  • a planarization layer 100 may also be formed between the passivation layer 110 and the pixel electrode 30, and the first via 92 passes through the passivation layer 110 and the planarization layer 100 of the AMOLED array substrate to electrically The first auxiliary line 50 and the second auxiliary line 60 are connected.
  • the first auxiliary line 50 is made of the same material as that of the pixel electrode 30, and the pixel electrode 30 and the first auxiliary line 50 are simultaneously formed by one patterning process; and the second auxiliary line 60 is The material forming the source/drain electrode layer 70 is made of the same material, and The source drain and the second auxiliary line 60 are simultaneously formed by one patterning process.
  • the patterning process may generally include photoresist coating, exposure, development, etching, photoresist stripping, etc.; of course, in reality, there is a case where no mask is used for patterning, for example, printing, printing, etc.
  • Other patterning methods as long as the process of forming a desired pattern can be referred to as a patterning process, the present invention is not limited thereto.
  • the material forming the first auxiliary line 50 can enter the first via 92 to thereby connect the first auxiliary line 50 with the first via 92.
  • the second auxiliary line 60 below is electrically connected.
  • the material forming the plate electrode 10 may enter the second via hole 94 to electrically connect the plate electrode 10 with the first auxiliary line 50 under the second via hole 94, thereby It is electrically connected to the second auxiliary line 60.
  • the method may further include the step of blocking the second via 94 when the organic illuminant 40 is applied to prevent the organic illuminant 40 from entering the second via 94.
  • the method further includes a step of electrically connecting at least one end of each of the auxiliary wires to the electrode lead 20.
  • the resistor network formed by the auxiliary line is directly connected in parallel with the plate electrode 10, thereby remarkably improving the uniformity of the in-plane resistance of the entire plate electrode 10.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种AMOLED阵列基板，包括：板状电极（10）；像素电极（30）；有机发光体（40）；至少一条第一辅助线（50），与像素电极（30）同层设置且与像素电极（30）不相交；及至少一条第二辅助线（60），与阵列基板的数据线（DL）及源漏电极不相交且与阵列基板的源漏电极同层设置；其中：第一与第二辅助线在板状电极（10）上的投影位于阵列基板的像素定义层（80）在板状电极（10）上的投影内并至少部分重合；且第一辅助线（50）通过第一过孔（92）与第二辅助线（60）电连接，并通过形成在阵列基板的像素定义层（80）中的第二过孔（94）与板状电极（10）电连接，第一过孔（92）在板状电极（10）上的投影位于第一和第二辅助线重合的投影内。还提供一种显示装置和制造阵列基板的方法。可降低板状电极的面内电阻，提高板状电极面内电阻的均匀性。

Description

AMOLED阵列基板及其制造方法、显示装置 技术领域
本发明的实施例涉及显示技术领域，尤其涉及一种主动矩阵有机发光二极管显示器(AMOLED)阵列基板、一种制造AMOLED阵列基板的方法、一种具有该阵列基板的显示装置。
背景技术
在顶发射AMOLED面板设计中，因为OLED器件的顶电极需要透光，所以顶电极通常做得很薄。当面板尺寸增大时，顶电极面内电阻较大。高的顶电极面内电阻会增大压降(IR Drop)，过大的IR Drop会导致面内亮度不均匀，从而影响画面的均一度。在AMOLED中，顶电极通常形成为整块的平面电极，又被称为板状电极，因此本发明以下均将其称作板状电极。
发明内容
为提高或改善顶发射AMOLED的板状电极面内电阻的均匀性，降低板状电极的面内电阻，提出本发明。
根据本发明的实施例的一个方面，提出了一种AMOLED阵列基板，包括：板状电极，板状电极与设置在板状电极周边的电极引线电连接；阵列布置的多个像素电极；设置在多个像素电极与板状电极之间的有机发光体；至少一条第一辅助线，与像素电极同层设置且与像素电极不相交；以及至少一条第二辅助线，与AMOLED阵列基板的数据线及源漏电极不相交且与AMOLED阵列基板的源漏电极同层设置，其中：第一辅助线与第二辅助线在板状电极上的投影位于AMOLED阵列基板的像素定义层在板状电极上的投影内且至少部分重合；且第一辅助线通过第一过孔与第二辅助线电连接，并通过形成在AMOLED阵列基板的像素定义层中的第二过孔与板状电极电连接，其中，所述第一过孔在板状电极上的投影位于所述第一辅助线与第二辅助线的重合的投影内。
可选地，至少一条第一辅助线包括多条第一辅助线，且第一辅助线与AMOLED阵列基板的栅线平行；至少一条第二辅助线包括多条第二辅助线，且第二辅助线与AMOLED阵列基板的数据线平行；所述多条第一辅助线和所述多条第二辅助线在板状电极上的投影为由多个网格形成的网状投影。
进一步可选地，像素电极与网状投影的网格一一对应，且每一个像素电极在板状电极上的投影位于网状投影中的对应的一个网格之内。
可选地，第二过孔在板状电极上的投影位于第一辅助线与第二辅助线的重合的投影内，并且第一过孔和第二过孔在板状电极上的投影重合。
上述阵列基板中，可选地，每一条第一辅助线与栅线对应设置，且第一辅助线与对应的栅线在板状电极上的投影至少部分重合。
上述阵列基板中，可选地，AMOLED阵列基板还包括设置在源漏电极所在层和像素电极之间的钝化层，所述第一过孔穿过钝化层以电连接第一辅助线和第二辅助线。
进一步可选地，AMOLED阵列基板还包括设置在钝化层和像素电极之间的平坦层，所述第一过孔贯穿钝化层和平坦层以电连接第一辅助线和第二辅助线。
上述阵列基板中，可选地，电极引线围绕板状电极的整个周边设置；且每一条辅助线的至少一端与该电极引线电连接。
上述阵列基板中，可选地，第一辅助线与第二辅助线的重合的投影至少位于板状电极的中心区域。
根据本发明的实施例的另一方面，提出了一种显示装置，包括上述任意一种AMOLED阵列基板。
根据本发明的实施例的再一方面，提出了一种制造AMOLED阵列基板的方法，其中，所述AMOLED阵列基板包括：阵列布置的多个像素电极；板状电极，板状电极与设置在板状电极周边的电极引线电连接；和设置在像素电极与板状电极之间的有机发光体，所述方法包括步骤：形成与像素电极同层设置且与像素电极不相交的至少一条第一辅助线；形成与AMOLED阵列基板的数据线及源漏电极不相交且与AMOLED阵列基板的源漏电极同层设置的至少一条第二辅助线，第一辅助线与第二辅助线在板状电极上的投影位于AMOLED阵列基板的像素定义层在板状电极上的投影上且至少部 分重合；在与第一辅助线和第二辅助线的重合的投影对应的位置处形成用于将第一辅助线与第二辅助线电连接的第一过孔；和在AMOLED阵列基板的像素定义层中形成用于将第二辅助线与板状电极电连接的第二过孔。
上述方法中，可选地，形成至少一条第二辅助线的步骤包括形成多条第一辅助线，且第一辅助线形成为与AMOLED阵列基板的栅线平行；形成至少一条第二辅助线的步骤包括形成多条第二辅助线，且第二辅助线形成为与AMOLED阵列基板的数据线平行，使得所述多条第一辅助线和所述多条第二辅助线在板状电极上的投影为由多个网格形成的网状投影。
进一步可选地，像素电极形成为与网状投影的网格一一对应，且每一个像素电极在板状电极上的投影位于第一辅助线和第二辅助线所形成的网状投影中的对应的一个网格之内。
上述方法中，可选地，第二过孔形成在与第一辅助线和第二辅助线的重合的投影对应的位置处，并且第一过孔和第二过孔在板状电极上的投影重合。
上述方法中，可选地，每一条第一辅助线与栅线对应形成，且第一辅助线与对应的栅线在板状电极上的投影至少部分重合。
上述方法中，可选地，在源漏电极所在层和像素电极之间形成钝化层，所述第一过孔穿过钝化层以电连接第一辅助线和第二辅助线。
上述方法中，可选地，在钝化层和像素电极之间形成平坦层，所述第一过孔贯穿钝化层和平坦层以电连接第一辅助线和第二辅助线。
上述方法中，可选地，第一辅助线由与像素电极的材料相同的材料制成，利用一次构图工艺同时形成像素电极和第一辅助线；且第二辅助线由与形成源漏电极的材料相同的材料制成，利用一次构图工艺同时形成源漏电极和第二辅助线。
上述方法中，可选地，所述方法还包括在施加有机发光体时遮挡第二过孔以免有机发光体进入第二过孔的步骤。
上述方法中，可选地，电极引线围绕板状电极的整个周边设置；且所述方法还包括使得每一条辅助线的至少一端与该电极引线电连接的步骤。
上述方法中，可选地，形成的至少一条第一辅助线包括在板状电极上的投影穿过板状电极的中心区域的第一辅助线，形成的至少一条第二辅助 线包括在板状电极上的投影穿过板状电极的所述中心区域的第二辅助线。
本发明的上述技术方案的有益效果如下：
上述技术方案中，第一辅助线通过第一过孔与第二辅助线电连接，并通过形成在AMOLED阵列基板的像素定义层中的第二过孔与板状电极电连接，从而由第一辅助线和第二辅助线所形成的电阻网络与板状电极直接并联，可以降低板状电极的面内电阻，提高板状电极的面内电阻的均一性。
附图说明
图1为本发明的一个示例性实施例提供的AMOLED阵列基板的示意性俯视图。
图2是沿图1中的线L所截得的AMOLED阵列基板的示意性截面图。
具体实施方式
下面结合附图，对本发明实施例提供的AMOLED阵列基板及其制造方法、显示装置进行详细地说明。
附图中各部件的大小和形状不反映AMOLED阵列基板的真实比例，目的只是示意说明本发明的内容。
如图1和图2所示，本发明实施例提出了一种AMOLED阵列基板，包括：
板状电极10，板状电极10与设置在板状电极10周边的电极引线20电连接；
阵列布置的多个像素电极30；
设置在多个像素电极30与板状电极10之间的有机发光体40；
至少一条第一辅助线50，与像素电极30同层设置且与像素电极不相交；以及
至少一条第二辅助线60，与AMOLED阵列基板的数据线DL及源漏电极不相交且与AMOLED阵列基板的源漏电极同层设置；
其中：
第一辅助线50与第二辅助线60在板状电极10上的投影位于AMOLED阵列基板的像素定义层80在板状电极10上的投影内，并且第一辅助线50 与第二辅助线60在板状电极10上的投影至少部分重合；且
第一辅助线50通过第一过孔92与第二辅助线60电连接，其中第一过孔92在板状电极10上的投影位于第一辅助线50和第二辅助线60在板状电极10上的重合的投影内，并且第一辅助线50通过形成在AMOLED阵列基板的像素定义层80中的第二过孔94与板状电极10电连接。
如图2所示，AMOLED阵列基板还包括衬底基板120，上述结构均设置在衬底基板120上。衬底基板120可以采用玻璃、透明树脂、石英、蓝宝石等材料，本发明不做限制。
本发明实施例提供的AMOLED阵列基板中的OLED(Organic Light-Emitting Diode，有机发光二极管)可以为普通的OLED，也可以为WOLED(白光有机发光二极管)，本发明不做限制。
另外，所述板状电极10可以作为OLED的阴极，此时像素电极30作为OLED的阳极；作为替代，所述板状电极10也可以作为OLED的阳极，此时像素电极30作为OLED器件的阴极，从而形成为反置型OLED结构。本发明对此不做限制，可以根据器件的设计需要进行选择。
在本发明的技术方案中，第一辅助线50通过第一过孔92与第二辅助线60电连接，并通过形成在AMOLED阵列基板的像素定义层80中的第二过孔94与板状电极10电连接，从而由第一辅助线50和第二辅助线60形成的电阻网络与板状电极10直接并联。这样，可以降低板状电极10的面内电阻，提高板状电极10的面内电阻的均一性。
在一个实例中，至少一条第一辅助线包括多条第一辅助线50，且第一辅助线50与AMOLED阵列基板的栅线GL平行；至少一条第二辅助线包括多条第二辅助线60，且第二辅助线60与AMOLED阵列基板的数据线DL平行；所述多条第一辅助线50和所述多条第二辅助线60在板状电极10上的投影为由多个网格形成的网状投影，如图1所示。此时，第一辅助线50与第二辅助线60在板状电极10上的投影具有重合的部分(交点)，如图1中符号A所示的部分，在下文中，将这些交点称为投影交点。
在这种情况下，第一辅助线50和第二辅助线60大致均匀分布，从而第一辅助线50与板状电极10的电连接点大致均匀分布，从而可进一步提高整个板状电极10的面内电阻的均一性，进一步提高板状电极10的面内 亮度的均一性。
当然，第一辅助线50和第二辅助线60也可以平行设置，本发明对此不进行限定，只要第一辅助线50和第二辅助线60在板状电极10上的投影均位于像素定义层80在板状电极10上的投影内且至少部分重合，第一辅助线50与同层设置的像素电极30不相交，并且第二辅助线60与同层设置的源漏电极不相交即可。
进一步地，在如图1所示的示例中，对应于每一条栅线GL都设置一条第一辅助线50，并且对应于每一条栅DL线都设置一条第二辅助线60，此时，像素电极30与网状投影中的网格一一对应，且每一个像素电极30在板状电极10上的投影位于网状投影中的对应的一个网格之内。这样，对于每一个像素结构，多个第一辅助线50和多个第二辅助线60所形成的电阻网络可以在四个点处与板状电极10电接触，从而确保了板状电极的与每一个像素结构对应的部分的面内电阻的均一性。
在一个可选的实施例中，第二过孔94也可以设置为其在板状电极10上的投影位于第一辅助线50和第二辅助线60在板状电极10上的重合的投影内。在这种情况下，各第一过孔92和各第二过孔94所设置的位置对应于各投影交点。进一步地，如图2所示，第一过孔92和第二过孔94在板状电极上的投影可以重合。如此，可以有效利用阵列基板的非发光区域的空间。
进一步优选地，第一辅助线50与第二辅助线60的投影交点包括大致位于板状电极10的中心区域的投影交点(即，第一辅助线50与第二辅助线60的投影交点至少大致位于板状电极10的中心区域)。在电极引线20围绕板状电极10整个周边设置的情况下，板状电极10的中心一般距离电极引线20最远。使得板状电极10的中心与辅助线所形成的电阻网络电连接有助于提高整个板状电极10的面内电阻的均一性。
需要指出的是，为了节约成本，可以仅仅使用一条第一辅助线50和一条第二辅助线60，这两条辅助线的投影交点大致位于板状电极10的中心位置。
需要指出的是，为了节约成本，可以不必对应于每一条栅线GL都设置一条第一辅助线50，或者也可以减少图2中的第二辅助线60的数量， 而且第一辅助线50和第二辅助线60的数量也不必相等，但为了确保整个板状电极10的面内电阻的均一性，第一辅助线50和第二辅助线60都应大致均匀分布。在这种情况下，多个像素电极30在板状电极10上的投影位于网状投影中同一个网格之内，即，多个像素电极30对应一个网格。
在一个示例中，每一条第一辅助线50与栅线GL对应设置，且第一辅助线50与对应的栅线GL在板状电极10上的投影至少部分重合。由于在AMOLED阵列基板中，栅线和数据线围合像素结构，所以，将第一辅助线50与栅线GL重合设置，在避免第一辅助线50与像素电极30电接触的同时，可以尽量减少第一辅助线50所占用的空间，即增大像素电极30的空间。
如图2所示，AMOLED阵列基板还可包括设置在源漏电极所在层70(以下，简称为源漏电极层70)和像素电极30之间的钝化层110，此时，第一过孔92穿过AMOLED阵列基板的钝化层110以电连接第一辅助线50和相应的第二辅助线60。可选的，AMOLED阵列基板还可包括设置在钝化层110和像素电极30之间的平坦层100，此时，第一过孔92穿过AMOLED阵列基板的钝化层110和平坦层100以电连接第一辅助线50和对应的第二辅助线60。
如图1所示，电极引线20围绕板状电极10的整个周边设置；且每一条辅助线50、60的至少一端与该电极引线20电连接。这样，将辅助线50和60所形成的电阻网络与板状电极10直接并联，可以显著提高整个板状电极10的面内电阻的均一性。
需要指出的是，在本发明中，并非需要在与第一辅助线50和第二辅助线60的每一个重合的投影对应的位置处都设置过孔92和94以电连接两者并将第一辅助线50连接到板状电极10。可以根据需要在与一部分重合的投影对应的位置处设置过孔92和/或94。
本发明的实施例还提供一种显示装置，其包括上述的AMOLED阵列基板。所述显示装置可以为：OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。基于上述的AMOLED阵列基板，可以降低板状电极10的面内电阻，提高整个板状电极10的面内电阻的均一性，从而可以提高显示面板的显示性能。
在本发明的技术方案中，第一辅助线50通过第一过孔92与第二辅助线60电连接，并通过形成在AMOLED阵列基板的像素定义层80中的第二过孔94与板状电极10电连接，从而由第一辅助线50和第二辅助线60所形成的电阻网络与板状电极10直接并联。
本发明的实施例还提供制造具有上述特性的AMOLED阵列基板的方法。其中，所述AMOLED阵列基板包括：阵列布置的多个像素电极；板状电极，板状电极与设置在板状电极周边的电极引线相连；和设置在多个像素电极与板状电极之间的有机发光体。
根据本发明的制造AMOLED阵列基板的方法可以包括如下步骤：
形成与像素电极30同层设置且与像素电极30不相交的至少一条第一辅助线50；
形成与AMOLED阵列基板的数据线DL及源漏电极不相交且与AMOLED阵列基板的源漏电极同层设置的至少一条第二辅助线60，第一辅助线50与第二辅助线60在板状电极10上的投影位于AMOLED阵列基板的像素定义层80在板状电极10上的投影内且至少部分重合；
在与第一辅助线50和第二辅助线60的重合的投影对应的位置处形成用于将第一辅助线50与第二辅助线60电连接的第一过孔92；和
在AMOLED阵列基板的像素定义层中形成用于将第一辅助线50与板状电极10电连接的第二过孔94。
在上述方法中，可以形成多条第一辅助线50和多条第二辅助线60，第一辅助线50与AMOLED阵列基板的栅线GL平行，第二辅助线60与AMOLED阵列基板的数据线DL平行，且使得所述多条第一辅助线和所述多条第二辅助线在板状电极10上的投影为由多个网格形成的网状投影。在这种情况下，第一辅助线50和第二辅助线60大致均匀分布，从而第一辅助线50与板状电极10的电连接点大致均匀分布，从而进一步提高整个板状电极10的面内电阻的均一性。
进一步地，像素电极30形成为与网状投影的网格一一对应，且每一个像素电极在板状电极10上的投影位于第一辅助线50和第二辅助线60所形成的网状投影中的对应的一个网格之内。这样，对于每一个像素结构，多个第一辅助线50和多个第二辅助线60所形成的电阻网络可以在四个点 处与板状电极10电接触，从而确保了每一个像素结构对应的板状电极的面内电阻的均一性。
上述方法中，在一个可选的实施例中，第二过孔94也可以形成在与第一辅助线50和第二辅助线60的重合的投影对应的位置处。在这种情况下，各第一过孔92和各第二过孔94所设置的位置对应于各投影交点。进一步地，如图2所示，第一过孔92和第二过孔94在板状电极10上的投影可以重合。如此，可以有效利用AMOLED阵列基板的非发光区域的空间。
进一步可选地，形成的至少一条第一辅助线包括在板状电极上的投影穿过板状电极的中心区域的第一辅助线，形成的至少一条第二辅助线包括在板状电极上的投影穿过板状电极的所述中心区域的第二辅助线。这样，第一辅助线50与第二辅助线60的投影交点包括大致位于板状电极10的中心区域的投影交点。在电极引线20围绕板状电极10整个周边设置的情况下，板状电极10的中心一般距离电极引线20最远。将板状电极10的中心与辅助线50和60所形成的电阻网络电连接有助于提高整个板状电极10的面内电阻的均一性。
上述方法中，在一个可选的实施例中，每一条第一辅助线50与栅线GL对应设置，且第一辅助线50与对应的栅线GL在板状电极10上的投影至少部分重合。由于在AMOLED阵列基板中，栅线GL和数据线DL围合像素结构，所以，将第一辅助线50与栅线GL重合设置，在避免第一辅助线50与像素电极30电接触的同时，还可以尽量减少第一辅助线50所占用的非显示区域的空间，即增大像素电极30的空间。
上述方法中，如图2所示，可以在源漏电极层70和像素电极30之间形成钝化层110，此时，第一过孔92穿过AMOLED阵列基板的钝化层110以电连接第一辅助线50和第二辅助线60。在一个可选的实施例中，还可以在钝化层110和像素电极30之间形成平坦层100，此时第一过孔92穿过AMOLED阵列基板的钝化层110和平坦层100以电连接第一辅助线50和第二辅助线60。
上述方法中，为了节约成本，第一辅助线50由与像素电极30的材料相同的材料制成，利用一次构图工艺同时形成像素电极30和第一辅助线50；且第二辅助线60由与形成源漏电极层70的材料相同的材料制成，利 用一次构图工艺同时形成源漏极和第二辅助线60。其中，构图工艺通常可以包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺；当然，现实中还存在无需采用mask进行构图的情况，比如可以为打印、印刷等更多其他的构图方式，只要可以形成所需的图案的工艺都可以称为构图工艺，本发明对此不做限制。
如本领域技术人员所知的，在形成第一辅助线50的时候，形成第一辅助线的50材料可以进入到第一过孔92中从而将第一辅助线50与在第一过孔92下方的第二辅助线60电连接。在形成板状电极10的时候，形成板状电极10的材料可以进入到第二过孔94中从而将板状电极10与在第二过孔94下方的第一辅助线50电连接，从而也与第二辅助线60电连接。
所述方法还可包括在施加有机发光体40时遮挡第二过孔94以免有机发光体40进入到第二过孔94中的步骤。
上述方法中，在电极引线20围绕板状电极10的整个周边设置的情况下，所述方法还包括使得每一条辅助线的至少一端与该电极引线20电连接的步骤。这样，辅助线所形成的电阻网络与板状电极10直接并联，从而显著提高整个板状电极10的面内电阻的均一性。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (21)

  1. 一种AMOLED阵列基板，其特征在于，包括：
    板状电极，板状电极与设置在板状电极周边的电极引线电连接；
    阵列布置的多个像素电极；
    设置在多个像素电极与板状电极之间的有机发光体；
    至少一条第一辅助线，所述至少一条第一辅助线与像素电极同层设置且与像素电极不相交；以及
    至少一条第二辅助线，所述至少一条第二辅助线与AMOLED阵列基板的数据线及源漏电极不相交且与AMOLED阵列基板的源漏电极同层设置，
    其中：
    第一辅助线与第二辅助线在板状电极上的投影位于AMOLED阵列基板的像素定义层在板状电极上的投影内并至少部分重合；且
    第一辅助线通过第一过孔与第二辅助线电连接，并通过形成在AMOLED阵列基板的像素定义层中的第二过孔与板状电极电连接，其中第一过孔在板状电极上的投影位于第一辅助线和第二辅助线的重合的投影内。
  2. 根据权利要求1所述的AMOLED阵列基板，其特征在于，
    至少一条第一辅助线包括多条第一辅助线，且第一辅助线与AMOLED阵列基板的栅线平行；
    至少一条第二辅助线包括多条第二辅助线，且第二辅助线与AMOLED阵列基板的数据线平行；
    所述多条第一辅助线和所述多条第二辅助线在板状电极上的投影为由多个网格形成的网状投影。
  3. 根据权利要求2所述的AMOLED阵列基板，其特征在于，
    像素电极与网状投影的网格一一对应，且每一个像素电极在板状电极上的投影位于网状投影中的对应的一个网格之内。
  4. 根据权利要求1-3中任一项所述的AMOLED阵列基板，其特征在于，
    每一条第一辅助线与栅线对应设置，且第一辅助线与对应的栅线在板状电极上的投影至少部分重合。
  5. 根据权利要求1所述的AMOLED阵列基板，其特征在于，
    第二过孔在板状电极上的投影位于第一辅助线和第二辅助线的重合的投影内，并且第一过孔和第二过孔在板状电极上的投影重合。
  6. 根据权利要求1所述的AMOLED阵列基板，其特征在于，
    AMOLED阵列基板还包括设置在源漏电极所在层和像素电极之间的钝化层，所述第一过孔穿过钝化层以电连接第一辅助线和第二辅助线。
  7. 根据权利要求6所述的AMOLED阵列基板，其特征在于，
    AMOLED阵列基板还包括设置在钝化层和像素电极之间的平坦层，所述第一过孔贯穿钝化层和平坦层以电连接第一辅助线和第二辅助线。
  8. 根据权利要求1-7中任一项所述的AMOLED阵列基板，其特征在于，
    电极引线围绕板状电极的整个周边设置；且
    每一条辅助线的至少一端与该电极引线电连接。
  9. 根据权利要求1-7中任一项所述的AMOLED阵列基板，其特征在于，
    第一辅助线与第二辅助线的重合的投影至少位于板状电极的中心区域。
  10. 一种显示装置，其特征在于，包括根据权利要求1-9中任一项所述的AMOLED阵列基板。
  11. 一种制造AMOLED阵列基板的方法，其中：
    所述AMOLED阵列基板包括：
    阵列布置的多个像素电极；
    板状电极，板状电极与设置在板状电极周边的电极引线电连接；和
    设置在多个像素电极与板状电极之间的有机发光体，
    其特征在于，所述方法包括步骤：
    形成与像素电极同层设置且与像素电极不相交的至少一条第一辅助线；
    形成与AMOLED阵列基板的数据线及源漏电极不相交且与AMOLED阵列基板的源漏电极同层设置的至少一条第二辅助线，第一辅助线与第二辅助线在板状电极上的投影位于AMOLED阵列基板的像素定义层在板状电极上的投影内且至少部分重合；
    在与第一辅助线和第二辅助线的重合的投影对应的位置处形成用于将第一辅助线与第二辅助线电连接的第一过孔；和
    在AMOLED阵列基板的像素定义层中形成用于将第一辅助线与板状电极电连接的第二过孔。
  12. 根据权利要求11所述的方法，其特征在于，
    形成至少一条第二辅助线的步骤包括形成多条第一辅助线，并且第一辅助线形成为与AMOLED阵列基板的栅线平行；
    形成至少一条第二辅助线的步骤包括形成多条，第二辅助线，并且第二辅助线形成为与AMOLED阵列基板的数据线平行，使得所述多条第一辅助线和所述多条第二辅助线在板状电极上的投影为由多个网格形成的网状投影。
  13. 根据权利要求12所述的方法，其特征在于，
    像素电极形成为与网状投影的网格一一对应，且每一个像素电极在板状电极上的投影位于第一辅助线和第二辅助线所形成的网状投影中的对应的一个网格之内。
  14. 根据权利要求11-13中任一项所述的方法，其特征在于，
    每一条第一辅助线与栅线对应形成，且第一辅助线与对应的栅线在板状电极上的投影至少部分重合。
  15. 根据权利要求11所述的方法，其特征在于，
    第二过孔形成在与第一辅助线和第二辅助线的重合的投影对应的位置处，并且第一过孔和第二过孔在板状电极上的投影重合。
  16. 根据权利要求11所述的方法，其特征在于，所述方法还包括步骤：
    在源漏电极所在层和像素电极之间形成钝化层，所述第一过孔穿过钝化层以电连接第一辅助线和第二辅助线。
  17. 根据权利要求16所述的方法，其特征在于，所述方法还包括步骤：
    在钝化层和像素电极之间形成平坦层，所述第一过孔贯穿钝化层和平坦层以电连接第一辅助线和第二辅助线。
  18. 根据权利要求11所述的方法，其特征在于，
    第一辅助线由与像素电极的材料相同的材料制成，利用一次构图工艺同时形成像素电极和第一辅助线；且
    第二辅助线由与形成源漏电极的材料相同的材料制成，利用一次构图工艺同时形成源漏电极和第二辅助线。
  19. 根据权利要求11所述的方法，其特征在于，
    所述方法还包括在施加有机发光体时遮挡第二过孔以免有机发光体进入第二过孔的步骤。
  20. 根据权利要求11-19中任一项所述的方法，其特征在于，
    电极引线围绕板状电极的整个周边设置；且
    所述方法还包括使得每一条辅助线的至少一端与该电极引线电连接的步骤。
  21. 根据权利要求11-19中任一项所述的方法，其特征在于，
    形成的至少一条第一辅助线包括在板状电极上的投影穿过板状电极 的中心区域的第一辅助线，形成的至少一条第二辅助线包括在板状电极上的投影穿过板状电极的所述中心区域的第二辅助线。
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