WO2016106895A1 - 薄膜晶体管及薄膜晶体管的制备方法 - Google Patents

薄膜晶体管及薄膜晶体管的制备方法 Download PDF

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Publication number
WO2016106895A1
WO2016106895A1 PCT/CN2015/071185 CN2015071185W WO2016106895A1 WO 2016106895 A1 WO2016106895 A1 WO 2016106895A1 CN 2015071185 W CN2015071185 W CN 2015071185W WO 2016106895 A1 WO2016106895 A1 WO 2016106895A1
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thin film
semiconductor layer
film transistor
hole
layer
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PCT/CN2015/071185
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English (en)
French (fr)
Inventor
石龙强
曾志远
李文辉
苏智昱
吕晓文
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深圳市华星光电技术有限公司
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Priority to US14/440,679 priority Critical patent/US9620647B2/en
Publication of WO2016106895A1 publication Critical patent/WO2016106895A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a method for fabricating a thin film transistor and a thin film transistor.
  • a thin film transistor is widely used as a switching element in an electronic device such as a liquid crystal display device.
  • Thin film transistors have gained wide attention due to their application to high pixel per inch (high PPI) display devices.
  • high PPI high pixel per inch
  • a high on-state current can increase the switching speed of the transistor.
  • increasing the width of the channel in the thin film transistor lowers the aperture ratio of the liquid crystal display device; reducing the length of the channel of the thin film transistor causes a short channel effect.
  • the on-state current of the thin film transistor in the prior art is small, resulting in a slow switching speed of the thin film transistor.
  • the present invention provides a thin film transistor having a large on-state current and a relatively fast switching speed.
  • the thin film transistor includes:
  • a source and a drain respectively covering the two ends of the second semiconductor, wherein the etch barrier layer is respectively provided with a first through hole corresponding to the source and the drain Second through hole
  • the source is connected to the first semiconductor layer through the first through hole
  • the drain is connected to the first semiconductor layer through a second through hole.
  • the thin film transistor further includes a first conductive portion, the first conductive portion is configured to connect the source and the first conductive layer, and connect the source and the second semiconductor layer, the first The first conductive portion is connected to the first covering portion, and the first protruding portion is received in the first through hole. The other end of the first protruding portion is connected to the first semiconductor layer, the first covering portion is disposed on the etching stopper layer, covering the first through hole, and the first covering portion Connected to the source.
  • the thin film transistor further includes a second conductive portion, the second conductive portion is configured to connect the drain and the first semiconductor layer, and connect the drain and the second semiconductor layer, the first The second conductive portion includes a second protruding portion and one second covering portion, one end of the second protruding portion is connected to one end of the second covering portion, and the second protruding portion is received in the second through hole Internally connecting the other end of the second protrusion to the first semiconductor layer, the second cover portion is disposed on the etch barrier layer, covering the second through hole, and the second A cover is connected to the drain.
  • the thin film transistor further includes a first ohmic contact layer disposed between the first through hole and the first semiconductor layer.
  • the thin film transistor further includes a second ohmic contact layer disposed between the second through hole and the first semiconductor layer.
  • the invention also provides a method for preparing a thin film transistor, which has a large on-state current and a fast switching speed.
  • the thin film transistor includes two semiconductor layers of a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer and the second The two semiconductor layers of the semiconductor are connected to the source and the drain, and the first semiconductor layer functions as a semiconductor layer and also serves as a gate of the second semiconductor layer.
  • an on-state current of the thin film transistor is the first a sum of a current and the second current.
  • the thin film transistor of the present invention can effectively increase the on-state current of the thin film transistor, and therefore, the thin film transistor has a faster switching speed.
  • the method for preparing the thin film transistor includes:
  • a gate electrode, a gate insulating layer, a first semiconductor layer, an etch barrier layer, and a second semiconductor layer are sequentially stacked on a surface of the substrate;
  • the method for preparing the thin film transistor further includes:
  • the first conductive portion includes a first protruding portion and a first covering portion, one end of the first protruding portion is connected to the first covering portion, and the first protruding portion receives In the first through hole, the other end of the first protrusion is connected to the first semiconductor layer, and the first cover portion is disposed on the etching barrier layer to cover the first through hole a hole, and the first cover is connected to the source.
  • the method for preparing the thin film transistor further includes:
  • the second conductive portion includes a second protruding portion and a second covering portion, one end of the second protruding portion is connected to one end of the second covering portion, and the second protruding portion The portion is received in the second through hole such that the other end of the second protruding portion is connected to the first semiconductor layer, and the second covering portion is disposed on the etching stopper layer to cover the first portion a through hole, and the second cover is connected to the drain.
  • the method for preparing the thin film transistor further includes:
  • the method for preparing the thin film transistor further includes:
  • the thin film transistor includes two semiconductor layers of a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer and The two semiconductor layers of the second semiconductor are both connected to the source and the drain,
  • the first semiconductor layer functions as a semiconductor layer while also serving as a gate of the second semiconductor layer.
  • an on-state current of the thin film transistor is the first a sum of a current and the second current.
  • the thin film transistor of the present invention can effectively increase the on-state current of the thin film transistor, and therefore, the thin film transistor has a faster switching speed.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 2 is a flow chart of a method of fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • 3 to 7 are cross-sectional views of corresponding thin film transistors in respective fabrication processes of a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional structural diagram of a thin film transistor according to a preferred embodiment of the present invention.
  • the thin film transistor 100 includes a substrate 110, and a gate electrode 120, a gate insulating layer 130, a first semiconductor layer 140, an etch barrier layer 150, and a second semiconductor layer 160 disposed on a surface of the substrate 110 are sequentially stacked.
  • the thin film transistor 100 further includes a source 170 and a drain 180, and the source 170 and the drain 180 respectively cover both ends of the second semiconductor 160.
  • a first via hole 151 and a second through hole 152 are respectively disposed on the etch barrier layer 150 corresponding to the source 170 and the drain 180, and the source 170 passes through the first through hole
  • the first semiconductor layer 140 is connected to the first semiconductor layer 140
  • the drain 180 is connected to the first semiconductor layer 140 through the second through hole 152.
  • the thin film transistor 100 is a bottom gate thin film transistor.
  • the substrate 110 is a glass substrate. It is to be understood that in other implementations, the substrate 110 is not limited to a glass substrate, and the substrate 110 may also be a plastic substrate.
  • the substrate 110 includes a first surface a and a second surface b opposite to the first surface a.
  • the gate electrode 120, the gate insulating layer 130, the first semiconductor layer 140, the etch stop layer 150, and the second semiconductor layer 160 are sequentially stacked on the substrate 100. On the first surface a.
  • the gate 120, the gate insulating layer 130, the first semiconductor layer 140, the etch stop layer 150, and the second semiconductor layer 160 are sequentially stacked on On the second surface b of the substrate 100.
  • the thin film transistor 100 further includes a buffer layer (not shown).
  • the buffer layer is disposed on the first surface a of the substrate 110.
  • the gate 120, the gate insulating layer 130, the first semiconductor layer 140, and the etch stop layer 150 And the second semiconductor layer 160 is stacked on the first surface a of the substrate 110 through the buffer layer.
  • the buffer layer is used to buffer stress applied by the substrate 110 during the preparation of the thin film transistor 100 to avoid damage or cracking of the substrate 110.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the buffer layer may also be disposed on the second surface b of the substrate 110.
  • the gate 120, the gate insulating layer 130, the The first semiconductor layer 140, the etch stop layer 150, and the second semiconductor layer 160 are stacked on the second surface b of the substrate 110 through the buffer layer.
  • the gate 120 is disposed at a middle portion of the first surface a of the substrate 110, and the gate 120 may be formed as follows.
  • a first metal layer is formed on the first surface a of the substrate 110, and the first metal layer is patterned to form the gate electrode 120 in a middle portion of the first surface a of the substrate 110.
  • the material of the first metal layer is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the gate insulating layer 130 covers the gate 120 and does not cover the first surface a of the gate 120.
  • the material of the gate insulating layer 130 is selected from one of silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the first semiconductor layer 140 is disposed at a middle portion of the gate insulating layer 130.
  • the etching block A layer 150 is disposed on the gate insulating layer 130 and on the gate insulating layer 130.
  • the etch stop layer 150 serves to prevent damage to layers such as the first semiconductor layer 140 and the gate insulating layer 130 covered by the etch barrier layer 150 during the formation of the thin film transistor 100.
  • the etch stop layer 150 is provided with the first through hole 151 and the second through hole 152, and the first through hole 151 and the second through hole 152 respectively correspond to the two first semiconductor layers 140 End settings.
  • the second semiconductor layer 160 is disposed at a middle portion of the etch stop layer 150 , and the second semiconductor layer 160 is disposed at a position corresponding to the first through hole 151 and the second through hole 152 .
  • the second semiconductor layer 160 is disposed at a middle portion of the etch barrier layer 150 , and the second semiconductor layer 160 does not cover the first through hole 151 and the second through hole 152 .
  • the source 170 and the drain 180 are respectively disposed at two ends of the second semiconductor layer 160, and the source 170 is connected to the first semiconductor layer 140 through the first through hole 151.
  • the drain electrode 180 is connected to the first semiconductor layer 140 through the second through hole 152.
  • the thin film transistor 100 further includes a first conductive portion 191 for connecting the source 170 and the first semiconductor layer 140 and connecting the source 170 and the second semiconductor layer 160.
  • the first conductive portion 191 includes a first protruding portion 1911 and a first covering portion 1912. One end of the first protruding portion 1911 is connected to the first covering portion 1912, and the first protruding portion 1911 is received in the first through hole 151 to make the first protruding portion 1911 One end is connected to the first semiconductor layer 140.
  • the first covering portion 1912 is disposed on the etching stopper layer 150 to cover the first through hole 151 , and the first covering portion 1912 is connected to the source 180 .
  • the thin film transistor 100 further includes a second conductive portion 192 for connecting the drain 180 and the first semiconductor layer 140 and connecting the drain 180 and the second semiconductor layer 160.
  • the second conductive portion 192 includes a second protruding portion 1921 and a second covering portion 1922. One end of the second protruding portion 1921 is connected to one end of the second covering portion 1922 , and the second protruding portion 1921 is received in the second through hole 152 to make the second protruding portion 1921 The other end is connected to the first semiconductor layer 140.
  • the second covering portion 1922 is disposed on the etching stopper layer 150 to cover the second through hole 152, and the second covering portion 1922 is connected to the drain 180.
  • the thin film transistor 100 further includes a first ohmic contact layer (not shown), and the first ohmic contact layer is disposed on the first through hole 151 and the first semiconductor layer 140 between.
  • the first ohmic contact layer is configured to reduce the first protrusion disposed in the first through hole 151 The contact resistance between the portion 1911 and the first semiconductor layer 140.
  • the thin film transistor 100 further includes a second ohmic contact layer (not shown), and the second ohmic contact layer is disposed between the second through hole 152 and the first semiconductor layer 140 .
  • the second ohmic contact layer serves to reduce a contact resistance between the second protrusion 1921 and the first semiconductor layer 140 disposed in the second through hole 152.
  • the thin film transistor 100 includes two semiconductor layers of a first semiconductor layer 140 and a second semiconductor layer 160, and the first semiconductor layer 140 and the second semiconductor layer The two semiconductor layers are connected to the source 170 and the drain 180, and the first semiconductor layer 140 functions as a semiconductor layer and also serves as a gate of the second semiconductor layer 160.
  • the thin film transistor 100 operates, assuming that the current in the first semiconductor layer 140 is the first current Ion1 and the circuit in the second semiconductor layer 160 is the second current Ion2, the thin film transistor 100 is turned on.
  • the state current is the sum of the first current Ion1 and the second current Ion2.
  • the thin film transistor of the present invention can effectively increase the on-state current of the thin film transistor, and therefore, the thin film transistor 100 has a faster switching speed.
  • FIG. 2 is a flow chart of a method for fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • the method of fabricating the thin film transistor 100 includes, but is not limited to, the following steps.
  • the substrate 110 is provided.
  • the substrate 110 is a glass substrate. It is to be understood that in other embodiments, the substrate 110 is not limited to a glass substrate, and the substrate 110 may also be a plastic substrate. Referring to FIG. 3, the substrate 110 includes a first surface a and a second surface b opposite to the first surface a.
  • a gate electrode 120, a gate insulating layer 130, a first semiconductor layer 140, an etching stopper layer 150, and a second semiconductor layer 160 are sequentially stacked on the surface of the substrate 110.
  • the gate 120, the gate insulating layer 130, the first semiconductor layer 140, the etch stop layer 150, and the second semiconductor layer 160 are sequentially The stacked on the first surface a of the substrate 100.
  • the gate 120, the gate insulating layer 130, the first semiconductor layer 140, the etch stop layer 150, and the second semiconductor layer 160 are sequentially stacked on On the second surface b of the substrate 100.
  • the gate 120 is disposed at a middle portion of the first surface a of the substrate 110.
  • the gate electrode 120 can be formed as follows. A first metal layer is formed on the first surface a of the substrate 110, and the first metal layer is patterned to form the gate electrode 120 in a middle portion of the first surface a of the substrate 110.
  • the material of the first metal layer is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the gate insulating layer 130 covers the gate 120 and does not cover the first surface a of the gate 120.
  • the material of the gate insulating layer 130 is selected from one of silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the first semiconductor layer 140 is disposed at a middle portion of the gate insulating layer 130.
  • the etch stop layer 150 is disposed on the gate insulating layer 130 and on the gate insulating layer 130.
  • the etch stop layer 150 serves to prevent damage to layers such as the first semiconductor layer 140 and the gate insulating layer 130 covered by the etch barrier layer 150 during the formation of the thin film transistor 100.
  • the etch stop layer 150 is provided with the first through hole 151 and the second through hole 152, and the first through hole 151 and the second through hole 152 respectively correspond to the two first semiconductor layers 140 End settings.
  • the second semiconductor layer 160 is disposed at a middle portion of the etch stop layer 150 , and the second semiconductor layer 160 is disposed at a position corresponding to the first through hole 151 and the second through hole 152 .
  • the second semiconductor layer 160 is disposed at a middle portion of the etch barrier layer 150 , and the second semiconductor layer 160 does not cover the first through hole 151 and the second through hole 152 .
  • the method for manufacturing the thin film transistor 100 further includes step I between the step S101 and the step S102.
  • Step I forming a buffer layer (not shown) on the surface of the substrate 110, the gate electrode 120, the gate insulating layer 130, the first semiconductor layer 140, the etch stop layer 150, and the The second semiconductor layer 160 is sequentially stacked on the surface of the substrate 110 through the buffer layer.
  • a buffer layer is formed on the first surface a of the substrate 110, the gate electrode 120, the gate insulating layer 130, the first semiconductor layer 140, the etch stop layer 150, and The second semiconductor layer 160 is sequentially stacked on the first surface a of the substrate 110 through the buffer layer.
  • a buffer layer is formed on the second surface b of the substrate 110, the gate electrode 120, the gate insulating layer 130, the first semiconductor layer 140, the etch stop layer 150, and The second semiconductor layer 160 is sequentially stacked on the second surface b of the substrate 110 through the buffer layer.
  • the buffer layer is used to buffer the substrate 110 in preparing the thin film transistor 100 The stress experienced in the process avoids damage or cracking of the substrate 110.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • Step S103 covering the second semiconductor layer 160 and forming a source 170 and a drain 180 respectively corresponding to both ends of the second semiconductor layer 160.
  • the source 170 and the associated drain 180 can be formed as follows. First forming a second metal layer on the second semiconductor layer 160, patterning the second metal layer, and retaining a second metal layer at both ends of the second semiconductor layer 160 to form a corresponding second semiconductor layer 160 Source 170 and drain 180 at both ends.
  • the material of the second metal layer is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof. It can be understood that the material of the second metal layer may be the same as the material of the first metal layer, or may be different from the material of the first metal layer.
  • Step S104 forming a first through hole 151 and a second through hole 152 corresponding to the source 170 and the drain 180 on the etching stopper layer 150, respectively, so that the source 170 passes through the first through
  • the hole 151 is connected to the first semiconductor layer 140, and the drain 180 is connected to the first semiconductor layer 140 through the second through hole 152.
  • the method for preparing the thin film transistor 100 further includes step S105, please refer to FIG. 6 together.
  • Step S105 forming a first conductive portion 191, the first conductive portion 191 includes a first protruding portion 1911 and a first covering portion 1912, and one end of the first protruding portion 1911 is connected to the first covering portion 1912
  • the first protruding portion 1911 is received in the first through hole 151 such that the other end of the first protruding portion 1911 is connected to the first semiconductor layer 140, and the first covering portion 1912 is disposed.
  • the first through hole 151 is covered on the etch stop layer 150, and the first cover portion 1912 is connected to the source 170.
  • the method for preparing the thin film transistor 100 further includes step S106, please refer to FIG. 7 together.
  • Step S106 forming a second conductive portion 192, the second conductive portion 192 includes a second protruding portion 1921 and a second covering portion 1922, and one end of the second protruding portion 1921 and the second covering portion 1922
  • the second protruding portion 1921 is received in the second through hole 152 to connect the other end of the second protruding portion 1921 to the first semiconductor layer 140, and the second covering portion is connected 1922 is disposed on the etch stop layer 150 to cover the second through hole 152, and the second cover portion 1922 is connected to the drain 180.
  • the method of manufacturing the thin film transistor 100 further includes a step S107.
  • Step S107 forming a first ohmic contact layer disposed between the first through hole 151 and the first semiconductor layer 140.
  • the first ohmic contact layer serves to reduce a contact resistance between the first protrusion 1911 and the first semiconductor layer 140 disposed in the first through hole 151.
  • the method of manufacturing the thin film transistor 100 further includes a step S108.
  • Step S108 forming a second ohmic contact layer disposed between the second through hole 152 and the first semiconductor layer 140.
  • the second ohmic contact layer serves to reduce a contact resistance between the second protrusion 1921 and the first semiconductor layer 140 disposed in the second through hole 152.
  • the thin film transistor 100 prepared by the above method for fabricating a thin film transistor includes two semiconductor layers of a first semiconductor layer 140 and a second semiconductor layer 160, and the first semiconductor layer 140 and the second semiconductor layer 160 are two layers.
  • the semiconductor layers are all connected to the source 170 and the drain 180, and the first semiconductor layer 140 functions as a semiconductor layer while also serving as a gate of the second semiconductor layer 160.
  • the thin film transistor 100 operates, assuming that the current in the first semiconductor layer 140 is the first current Ion1 and the circuit in the second semiconductor layer 160 is the second current Ion2, the thin film transistor 100 is turned on.
  • the state current is the sum of the first current Ion1 and the second current Ion2.
  • the thin film transistor of the present invention can effectively increase the on-state current of the thin film transistor, and therefore, the thin film transistor 100 has a faster switching speed.

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  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管及薄膜晶体管的制备方法，薄膜晶体管包括：基板（110）；依次层叠设置在该基板（110）的表面上的栅极（120）、栅极绝缘层（130）、第一半导体层（140）、蚀刻阻挡层（150）以及第二半导体层（160）；以及源极（170）和漏极（180），源极（170）及漏极（180）分别覆盖在第二半导体层（160）的两端，蚀刻阻挡层（150）上分别对应源极（170）和漏极（180）设有第一贯孔（151）和第二贯孔（152），源极（170）通过第一贯孔（151）与第一半导体层（140）相连，漏极（180）通过第二贯孔（152）与第一半导体层（140）相连。该薄膜晶体管能够有效增加薄膜晶体管的开态电流，且具有较快的开关速度。

Description

薄膜晶体管及薄膜晶体管的制备方法
本发明要求2014年12月30日递交的发明名称为“薄膜晶体管及薄膜晶体管的制备方法”的申请号201410853629.0的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其涉及一种薄膜晶体管及薄膜晶体管的制备方法。
背景技术
薄膜晶体管(thin film transistor，TFT)作为一种开关元件被广泛地应用在液晶显示装置等电子装置中。薄膜晶体管由于可以应用在高分辨率(high pixels per inch，high PPI)的显示设备上而得到广泛地关注。对于薄膜晶体管而言，高的开态电流可以增加所述晶体管的开关速度。为了增加所述薄膜晶体管的开态电流，通常的做法是增加薄膜晶体管中沟道的宽度或者是减小沟道的长度。然而，增大薄膜晶体管中沟道的宽度会降低液晶显示装置的开口率；减小薄膜晶体管的沟道的长度会引起短沟道效应。综上所述，现有技术中薄膜晶体管的开态电流较小，从而导致薄膜晶体管的开关速度较慢。
发明内容
本发明提供一种薄膜晶体管，所述薄膜晶体管具有较大的开态电流以及较快的开关速度。
所述薄膜晶体管包括：
基板；
依次层叠设置在所述基板的表面上的栅极、栅极绝缘层、第一半导体层、蚀刻阻挡层以及第二半导体层；
以及源极和漏极，所述源极及所述漏极分别覆盖在所述第二半导体的两端，所述蚀刻阻挡层上分别对应所述源极和漏极设有第一贯孔和第二贯孔，所 述源极通过所述第一贯孔与所述第一半导体层相连，所述漏极通过第二贯孔与所述第一半导体层相连。
其中，所述薄膜晶体管还包括第一导电部，所述第一导电部用于连接所述源极与所述第一导电层以及连接所述源极与所述第二半导体层，所述第一导电部包括第一凸出部及第一覆盖部，所述第一凸出部的一端与所述第一覆盖部相连，所述第一凸出部收容于所述第一贯孔内以使所述第一凸出部的另一端与所述第一半导体层相连，所述第一覆盖部设置于所述蚀刻阻挡层上，覆盖所述第一贯孔，且所述第一覆盖部与所述源极相连。
其中，所述薄膜晶体管还包括第二导电部，所述第二导电部用于连接所述漏极与所述第一半导体层以及连接所述漏极与所述第二半导体层，所述第二导电部包括第二凸出部及第二覆盖部，所述第二凸出部的一端与所述第二覆盖部的一端相连，所述第二凸出部收容于所述第二贯孔内以使所述第二凸出部的另一端与所述第一半导体层相连，所述第二覆盖部设置于所述蚀刻阻挡层上，覆盖所述第二贯孔，且所述第二覆盖部与所述漏极相连。
其中，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置于所述第一贯孔与所述第一半导体层之间。
其中，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置于所述第二贯孔与所述第一半导体层之间。
本发明还提供一种薄膜晶体管的制备方法，所述薄膜晶体管的制备方法制备得到的薄膜晶体管具有较大的开态电流以及较快的开关速度。
相较于现有技术，在本实施方式的所述薄膜晶体管中，所述薄膜晶体管包括第一半导体层和第二半导体层这两层半导体层，且所述第一半导体层及所述第二半导体这两层半导体层均与源极及漏极相连，所述第一半导体层充当半导体层的同时也作为所述第二半导体层的栅极。当所述薄膜晶体管工作时，假设所述第一半导体层中的电流为第一电流，所述第二半导体层中的电路为第二电流，则所述薄膜晶体管的开态电流为所述第一电流与所述第二电流的和。本发明的薄膜晶体管能够有效增加所述薄膜晶体管的开态电流，因此，所述薄膜晶体管具有较快的开关速度。
所述薄膜晶体管的制备方法包括：
提供基板；
在所述基板的表面依次层叠设置栅极、栅极绝缘层、第一半导体层、蚀刻阻挡层及第二半导体层；
覆盖在所述第二半导体层且对应所述第二半导体层两端分别形成源极和漏极；
在所述蚀刻阻挡层上分别对应所述源极和漏极形成第一贯孔和第二贯孔，以使所述源极通过所述第一贯孔与所述第一半导体层相连，所述漏极通过所述第二贯孔与所述第一半导体层相连。
其中，所述薄膜晶体管的制备方法还包括：
形成第一导电部，所述第一导电部包括第一凸出部及第一覆盖部，所述第一凸出部的一端与所述第一覆盖部相连，所述第一凸出部收容于所述第一贯孔内以使所述第一凸出部的另一端与所述第一半导体层相连，所述第一覆盖部设置于所述蚀刻阻挡层上，覆盖所述第一贯孔，且所述第一覆盖部与所述源极相连。
其中，所述薄膜晶体管的制备方法还包括：
形成第二导电部，所述第二导电部包括第二凸出部及第二覆盖部，所述第二凸出部的一端与所述第二覆盖部的一端相连，所述第二凸出部收容于所述第二贯孔内以使所述第二凸出部的另一端与所述第一半导体层相连，所述第二覆盖部设置于所述蚀刻阻挡层上，覆盖所述第二贯孔，且所述第二覆盖部与所述漏极相连。
其中，所述薄膜晶体管的制备方法还包括：
形成第一欧姆接触层，所述第一欧姆接触层设置于所述第一贯孔与所述第一半导体层之间。
其中，所述薄膜晶体管的制备方法还包括：
形成第二欧姆接触层，所述第二欧姆接触层设置于所述第二贯孔与所述第一半导体层之间。
相较于现有技术，在本发明薄膜晶体管的制备方法制备出来的薄膜晶体管中，所述薄膜晶体管包括第一半导体层和第二半导体层这两层半导体层，且所述第一半导体层及所述第二半导体这两层半导体层均与源极及漏极相连，所述 第一半导体层充当半导体层的同时也作为所述第二半导体层的栅极。当所述薄膜晶体管工作时，假设所述第一半导体层中的电流为第一电流，所述第二半导体层中的电路为第二电流，则所述薄膜晶体管的开态电流为所述第一电流与所述第二电流的和。本发明的薄膜晶体管能够有效增加所述薄膜晶体管的开态电流，因此，所述薄膜晶体管具有较快的开关速度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。
图2为本发明一较佳实施方式的薄膜晶体管的制备方法的流程图。
图3至图7为本发明一较佳实施方式的薄膜晶体管的各个制备流程中对应的薄膜晶体管的剖面图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。所述薄膜晶体管100包括基板110，依次层叠设置在所述基板110的表面上的栅极120、栅极绝缘层130、第一半导体层140、蚀刻阻挡层150以及第二半导体层160。所述薄膜晶体管100还包括源极170和漏极180，所述源极170及所述漏极180分别覆盖在所述第二半导体160的两端。所述蚀刻阻挡层150上分别对应所述源极170和所述漏极180设有第一贯孔(via hole)151和第二贯孔152，所述源极170通过所述第一贯孔151与所述第一半导体层140相连，所述漏极180通过所述第二贯孔152与所述第一半导体层140相连。
在本实施方式中，所述薄膜晶体管100为底栅极(bottom gate)薄膜晶体管。在本实施方式中，所述基板110为一玻璃基板。可以理解地，在其他实施中，所述基板110并不局限于为玻璃基板，所述基板110也可以为一塑料基板。所述基板110包括第一表面a及与所述第一表面a相对的第二表面b。在本实施方式中，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160依次层叠设置于所述基板100的所述第一表面a上。可以理解地，在其他实施方式中，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160依次层叠设置于所述基板100的所述第二表面b上。
在一实施方式中，所述薄膜晶体管100还包括缓冲层(图未示)。所述缓冲层设置于所述基板110的所述第一表面a上，此时，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160通过所述缓冲层层叠设置于所述基板110的所述第一表面a上。所述缓冲层用于缓冲所述基板110在制备所述薄膜晶体管100的过程中受到的应力，以避免所述基板110的损坏或者破裂。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。可以理解地，在其他实施方式中，所述缓冲层也可设置在所述基板110的所述第二表面b上，此时，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160通过所述缓冲层层叠设置于所述基板110的所述第二表面b上。
所述栅极120设置于所述基板110的所述第一表面a的中部，所述栅极120可以通过如下方式形成。在所述基板110的所述第一表面a上形成第一金属层，图案化所述第一金属层，以在所述基板110的所述第一表面a的中部形成所述栅极120。所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
所述栅极绝缘层130覆盖在所述栅极120上及未覆盖所述栅极120的第一表面a上。所述栅极绝缘层130的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
所述第一半导体层140设置于所述栅极绝缘层130的中部。所述蚀刻阻挡 层150设置于所述栅极绝缘层130上以及所述栅极绝缘层130上。所述蚀刻阻挡层150用于防止在形成所述薄膜晶体管100的过程中对所述蚀刻阻挡层150覆盖的第一半导体层140以及栅极绝缘层130等各层的损坏。所述蚀刻阻挡层150设置有所述第一贯孔151及所述第二贯孔152，所述第一贯孔151及所述第二贯孔152分别对应所述第一半导体层140的两端设置。
所述第二半导体层160设置于所述蚀刻阻挡层150的中部，且所述第二半导体层160对应所述第一贯孔151及所述第二贯孔152之间的位置设置。换句话说，所述第二半导体层160设置于所述蚀刻阻挡层150的中部，且所述第二半导体层160未覆盖所述第一贯孔151及所述第二贯孔152。
所述源极170及所述漏极180分别设置于所述第二半导体层160的两端，且所述源极170通过所述第一贯孔151与所述第一半导体层140相连，所述漏极180通过所述第二贯孔152与所述第一半导体层140相连。
所述薄膜晶体管100还包括第一导电部191，所述第一导电部191用于连接所述源极170与所述第一半导体层140以及连接所述源极170与所述第二半导体层160。所述第一导电部191包括第一凸出部1911及第一覆盖部1912。所述第一凸出部1911的一端与所述第一覆盖部1912相连，所述第一凸出部1911收容于所述第一贯孔151内以使所述第一凸出部1911的另一端与所述第一半导体层140相连。所述第一覆盖部1912设置于所述蚀刻阻挡层150上，覆盖所述第一贯孔151，且所述第一覆盖部1912与所述源极180相连。所述薄膜晶体管100还包括第二导电部192，所述第二导电部192用于连接所述漏极180与所述第一半导体层140以及连接所述漏极180与所述第二半导体层160。所述第二导电部192包括第二凸出部1921及第二覆盖部1922。所述第二凸出部1921的一端与所述第二覆盖部1922的一端相连，所述第二凸出部1921收容于所述第二贯孔152内以使所述第二凸出部1921的另一端与所述第一半导体层140相连。所述第二覆盖部1922设置于所述蚀刻阻挡层150上，覆盖所述第二贯孔152，且所述第二覆盖部1922与所述漏极180相连。
在一实施方式中，所述薄膜就晶体管100还包括第一欧姆接触层(图未示)，所述第一欧姆接触层设置于所述第一贯孔151与所述第一半导体层140之间。所述第一欧姆接触层用于减小设置在所述第一贯孔151内的所述第一凸 出部1911与所述第一半导体层140之间的接触电阻。
在一实施方式中，所述薄膜晶体管100还包括第二欧姆接触层(图未示)，所述第二欧姆接触层设置于所述第二贯孔152与所述第一半导体层140之间。所述第二欧姆接触层用于减小设置在所述第二贯孔152内的所述第二凸出部1921与所述第一半导体层140之间的接触电阻。
在本实施方式的所述薄膜晶体管100中，所述薄膜晶体管100包括第一半导体层140和第二半导体层160这两层半导体层，且所述第一半导体层140及所述第二半导体层160这两层半导体层均与源极170及漏极180相连，所述第一半导体层140充当半导体层的同时也作为所述第二半导体层160的栅极。当所述薄膜晶体管100工作时，假设所述第一半导体层140中的电流为第一电流Ion1，所述第二半导体层160中的电路为第二电流Ion2，则所述薄膜晶体管100的开态电流为所述第一电流Ion1与所述第二电流Ion2的和。本发明的薄膜晶体管能够有效增加所述薄膜晶体管的开态电流，因此，所述薄膜晶体管100具有较快的开关速度。
下面结合图1对本发明薄膜晶体管100的制备方法详细介绍如下。请一并参阅图2，图2为本发明一较佳实施方式的薄膜晶体管的制备方法的流程图。所述薄膜晶体管100的制备方法包括但不仅限于以下步骤。
步骤S101，提供基板110。在本实施方式中，所述基板110为一玻璃基板。可以理解地，在其他实施方式中，所述基板110并不局限于为玻璃基板，所述基板110也可以为一塑料基板。请参阅图3，所述基板110包括第一表面a及与所述第一表面a相对的第二表面b。
步骤S102，在所述基板110的表面上依次层叠设置栅极120、栅极绝缘层130、第一半导体层140、蚀刻阻挡层150及第二半导体层160。请一并参阅图4，在本实施方式中，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160依次层叠设置于所述基板100的所述第一表面a上。可以理解地，在其他实施方式中，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160依次层叠设置于所述基板100的所述第二表面b上。
具体地，所述栅极120设置于所述基板110的所述第一表面a的中部，所 述栅极120可以通过如下方式形成。在所述基板110的所述第一表面a上形成第一金属层，图案化所述第一金属层，以在所述基板110的所述第一表面a的中部形成所述栅极120。所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
所述栅极绝缘层130覆盖在所述栅极120上及未覆盖所述栅极120的第一表面a上。所述栅极绝缘层130的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
所述第一半导体层140设置于所述栅极绝缘层130的中部。所述蚀刻阻挡层150设置于所述栅极绝缘层130上以及所述栅极绝缘层130上。所述蚀刻阻挡层150用于防止在形成所述薄膜晶体管100的过程中对所述蚀刻阻挡层150覆盖的第一半导体层140以及栅极绝缘层130等各层的损坏。所述蚀刻阻挡层150设置有所述第一贯孔151及所述第二贯孔152，所述第一贯孔151及所述第二贯孔152分别对应所述第一半导体层140的两端设置。
所述第二半导体层160设置于所述蚀刻阻挡层150的中部，且所述第二半导体层160对应所述第一贯孔151及所述第二贯孔152之间的位置设置。换句话说，所述第二半导体层160设置于所述蚀刻阻挡层150的中部，且所述第二半导体层160未覆盖所述第一贯孔151及所述第二贯孔152。
在一实施方式中，所述薄膜晶体管100的制备方法在所述步骤S101及所述步骤S102之间还包括步骤I。
步骤I，在所述基板110的表面上形成缓冲层(图未示)，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160通过所述缓冲层依次层叠设置于所述基板110的表面上。在本实施方式中，在所述基板110的第一表面a上形成缓冲层，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160通过所述缓冲层依次层叠设置于所述基板110的第一表面a上。在其他实施方式中，在所述基板110的第二表面b上形成缓冲层，所述栅极120、所述栅极绝缘层130、所述第一半导体层140、所述蚀刻阻挡层150及所述第二半导体层160通过所述缓冲层依次层叠设置于所述基板110的所述第二表面b上。所述缓冲层用于缓冲所述基板110在制备所述薄膜晶体管100的过 程中受到的应力，以避免所述基板110的损坏或者破裂。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
步骤S103，覆盖在所述第二半导体层160上且对应所述第二半导体层160的两端分别形成源极170和漏极180。请一并参阅图5，所述源极170及所属漏极180可以通过如下方式形成。首先在所述第二半导体层160上形成第二金属层，图案化所述第二金属层，保留所述第二半导体层160两端的第二金属层，以形成对应所述第二半导体层160的两端的源极170和漏极180。所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。可以理解地，所述第二金属层的材质可以与所述第一金属层的材质相同，也可以与所述第一金属层的材质不同。
步骤S104，在所述蚀刻阻挡层150上分别对应所述源极170和所述漏极180形成第一贯孔151和第二贯孔152，以使所述源极170通过所述第一贯孔151与所述第一半导体层140相连，所述漏极180通过所述第二贯孔152与所述第一半导体层140相连。
所述薄膜晶体管100的制备方法还包括步骤S105，请一并参阅图6。
步骤S105：形成第一导电部191，所述第一导电部191包括第一凸出部1911及第一覆盖部1912，所述第一凸出部1911的一端与所述第一覆盖部1912相连，所述第一凸出部1911收容于所述第一贯孔151内以使所述第一凸出部1911的另一端与所述第一半导体层140相连，所述第一覆盖部1912设置于所述蚀刻阻挡层150上，覆盖所述第一贯孔151，且所述第一覆盖部1912与所述源极170相连。
所述薄膜晶体管100的制备方法还包括步骤S106，请一并参阅图7。
步骤S106，形成第二导电部192，所述第二导电部192包括第二凸出部1921及第二覆盖部1922，所述第二凸出部1921的一端与所述第二覆盖部1922的一端相连，所述第二凸出部1921收容于所述第二贯孔152内以使所述第二凸出部1921的另一端与所述第一半导体层140相连，所述第二覆盖部1922设置于所述蚀刻阻挡层150上，覆盖所述第二贯孔152，且所述第二覆盖部1922与所述漏极180相连。
所述薄膜晶体管100的制备方法还包括步骤S107。
步骤S107，形成第一欧姆接触层，所述第一欧姆接触层设置于所述第一贯孔151与所述第一半导体层140之间。所述第一欧姆接触层用于减小设置在所述第一贯孔151内的所述第一凸出部1911与所述第一半导体层140之间的接触电阻。
所述薄膜晶体管100的制备方法还包括步骤S108。
步骤S108，形成第二欧姆接触层，所述第二欧姆接触层设置于所述第二贯孔152与所述第一半导体层140之间。所述第二欧姆接触层用于减小设置在所述第二贯孔152内的所述第二凸出部1921与所述第一半导体层140之间的接触电阻。
采用上述薄膜晶体管的制备方法制备出来的薄膜晶体管100包括第一半导体层140和第二半导体层160这两层半导体层，且所述第一半导体层140及所述第二半导体层160这两层半导体层均与源极170及漏极180相连，所述第一半导体层140充当半导体层的同时也作为所述第二半导体层160的栅极。当所述薄膜晶体管100工作时，假设所述第一半导体层140中的电流为第一电流Ion1，所述第二半导体层160中的电路为第二电流Ion2，则所述薄膜晶体管100的开态电流为所述第一电流Ion1与所述第二电流Ion2的和。本发明的薄膜晶体管能够有效增加所述薄膜晶体管的开态电流，因此，所述薄膜晶体管100具有较快的开关速度。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    基板；
    依次层叠设置在所述基板的表面上的栅极、栅极绝缘层、第一半导体层、蚀刻阻挡层以及第二半导体层；
    以及源极和漏极，所述源极及所述漏极分别覆盖在所述第二半导体的两端，所述蚀刻阻挡层上分别对应所述源极和漏极设有第一贯孔和第二贯孔，所述源极通过所述第一贯孔与所述第一半导体层相连，所述漏极通过第二贯孔与所述第一半导体层相连。
  2. 如权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括第一导电部，所述第一导电部用于连接所述源极与所述第一导电层以及连接所述源极与所述第二半导体层，所述第一导电部包括第一凸出部及第一覆盖部，所述第一凸出部的一端与所述第一覆盖部相连，所述第一凸出部收容于所述第一贯孔内以使所述第一凸出部的另一端与所述第一半导体层相连，所述第一覆盖部设置于所述蚀刻阻挡层上，覆盖所述第一贯孔，且所述第一覆盖部与所述源极相连。
  3. 如权利要求2所述的薄膜晶体管，其中，所述薄膜晶体管还包括第二导电部，所述第二导电部用于连接所述漏极与所述第一半导体层以及连接所述漏极与所述第二半导体层，所述第二导电部包括第二凸出部及第二覆盖部，所述第二凸出部的一端与所述第二覆盖部的一端相连，所述第二凸出部收容于所述第二贯孔内以使所述第二凸出部的另一端与所述第一半导体层相连，所述第二覆盖部设置于所述蚀刻阻挡层上，覆盖所述第二贯孔，且所述第二覆盖部与所述漏极相连。
  4. 如权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置于所述第一贯孔与所述第一半导体层之 间。
  5. 如权利要求4所述的薄膜晶体管，其中，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置于所述第二贯孔与所述第一半导体层之间。
  6. 一种薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法包括：
    提供基板；
    在所述基板的表面依次层叠设置栅极、栅极绝缘层、第一半导体层、蚀刻阻挡层及第二半导体层；
    覆盖在所述第二半导体层且对应所述第二半导体层两端分别形成源极和漏极；
    在所述蚀刻阻挡层上分别对应所述源极和漏极形成第一贯孔和第二贯孔，以使所述源极通过所述第一贯孔与所述第一半导体层相连，所述漏极通过所述第二贯孔与所述第一半导体层相连。
  7. 如权利要求6所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括：
    形成第一导电部，所述第一导电部包括第一凸出部及第一覆盖部，所述第一凸出部的一端与所述第一覆盖部相连，所述第一凸出部收容于所述第一贯孔内以使所述第一凸出部的另一端与所述第一半导体层相连，所述第一覆盖部设置于所述蚀刻阻挡层上，覆盖所述第一贯孔，且所述第一覆盖部与所述源极相连。
  8. 如权利要求7所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括：
    形成第二导电部，所述第二导电部包括第二凸出部及第二覆盖部，所述第二凸出部的一端与所述第二覆盖部的一端相连，所述第二凸出部收容于所述第二贯孔内以使所述第二凸出部的另一端与所述第一半导体层相连，所述第二覆 盖部设置于所述蚀刻阻挡层上，覆盖所述第二贯孔，且所述第二覆盖部与所述漏极相连。
  9. 如权利要求6所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括：
    形成第一欧姆接触层，所述第一欧姆接触层设置于所述第一贯孔与所述第一半导体层之间。
  10. 如权利要求9所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括：
    形成第二欧姆接触层，所述第二欧姆接触层设置于所述第二贯孔与所述第一半导体层之间。
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