WO2016090674A1 - 薄膜晶体管 - Google Patents

薄膜晶体管 Download PDF

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Publication number
WO2016090674A1
WO2016090674A1 PCT/CN2014/094555 CN2014094555W WO2016090674A1 WO 2016090674 A1 WO2016090674 A1 WO 2016090674A1 CN 2014094555 W CN2014094555 W CN 2014094555W WO 2016090674 A1 WO2016090674 A1 WO 2016090674A1
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Prior art keywords
hole
layer
thin film
film transistor
semiconductor layer
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PCT/CN2014/094555
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English (en)
French (fr)
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石龙强
曾志远
张合静
胡宇彤
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深圳市华星光电技术有限公司
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Priority to US14/416,767 priority Critical patent/US9960283B2/en
Publication of WO2016090674A1 publication Critical patent/WO2016090674A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of manufacturing thin film transistors, and more particularly to a thin film transistor having a large on-state current.
  • a thin film transistor is widely used as a switching element in an electronic device such as a liquid crystal display device.
  • a double gate thin film transistor has been widely concerned because it can be applied to a high pixel per inch (high PPI) display device.
  • high PPI pixel per inch
  • a high on-state current can increase the switching speed of the dual gate transistor.
  • increasing the width of the channel in the double gate thin film transistor lowers the aperture ratio of the liquid crystal display device; reducing the length of the channel of the double gate thin film transistor causes a short channel effect.
  • the on-state current of the double gate thin film transistor in the prior art is small, resulting in a slow switching speed of the double gate thin film transistor.
  • the present invention provides a thin film transistor, thereby increasing an on-state current of a thin film transistor and increasing a switching speed of the thin film transistor.
  • the invention provides a thin film transistor, the thin film transistor comprising:
  • the first gate, the first gate insulating layer, the semiconductor layer, the etch barrier layer and the second gate are disposed on the surface of the substrate, wherein the semiconductor layer has a thickness of 200 nm to 2000 nm;
  • the etch barrier layer is provided with a first through hole and a second through hole, and the first through hole and the second through hole respectively are disposed corresponding to the semiconductor layer;
  • a source and a drain wherein the source and the drain respectively connect the semiconductor layer through the first through hole and the second through hole.
  • the thin film transistor further includes a passivation layer, the passivation layer is stacked on the second gate, and the passivation layer is provided with a third through hole and a fourth through hole, and the third The through hole communicates with the first through hole, the fourth through hole communicates with the second through hole, and the source passes through the third through hole and the first through hole to connect the semiconductor layer, The drain is connected to the semiconductor layer through the fourth through hole and the second through hole.
  • the thin film transistor further includes a first ohmic contact layer disposed between the source and the semiconductor layer, the source being connected by the first ohmic contact layer Semiconductor layer.
  • the thin film transistor further includes a second ohmic contact layer disposed between the drain and the semiconductor layer, the drain being connected by the second ohmic contact layer Semiconductor layer.
  • the lateral dimension of the semiconductor layer is greater than a lateral dimension of the first gate and greater than a lateral dimension of the second gate.
  • the thickness of the semiconductor layer is set to 200 nm to 2000 nm, a semiconductor layer of such a thickness can form two current channels in the semiconductor layer.
  • the on-state current of the thin film transistor is the sum of the currents in the two current channels. Therefore, the thin film transistor has a high on-state current, which increases the switching speed of the thin film transistor.
  • the present invention provides a thin film transistor including:
  • a first gate a first gate insulating layer, at least two semiconductor layers, an etch barrier layer and a second gate layer disposed on the surface of the substrate;
  • the etch barrier layer is provided with a first through hole and a second through hole, and the first through hole and the second through hole respectively are disposed corresponding to the semiconductor layer;
  • a source and a drain wherein the source and the drain respectively connect the semiconductor layer through the first through hole and the second through hole.
  • the thin film transistor further includes a passivation layer, the Dunhua layer is stacked on the second gate, and the passivation layer is provided with a third through hole and a fourth through hole, the third through a hole communicating with the first through hole, the fourth through hole communicating with the second through hole, the source passing through the third through hole and the first through hole connecting the semiconductor layer, A drain is connected to the semiconductor layer through the fourth through hole and the second through hole.
  • the thin film transistor further includes a first ohmic contact layer disposed between the source and the semiconductor layer, the source being connected by the first ohmic contact layer Semiconductor layer.
  • the thin film transistor further includes a second ohmic contact layer disposed between the drain and the semiconductor layer, the drain being connected by the second ohmic contact layer Semiconductor layer.
  • the lateral dimension of the semiconductor layer is greater than a lateral dimension of the first gate and greater than a lateral dimension of the second gate.
  • the thin film transistor of the present invention since at least two semiconductor layers are included in the thin film transistor of the present invention, at least two current channels can be formed in the thin film transistor.
  • the on-state current in the thin film transistor is the sum of the currents in all the current channels, and therefore, the thin film transistor has a higher on-state current, which improves the switching speed of the thin film transistor.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic view showing a current flow direction in a semiconductor layer of the thin film transistor of FIG. 1.
  • FIG 3 is a cross-sectional structural view of a thin film transistor according to another preferred embodiment of the present invention.
  • FIG. 4 is a schematic view showing a current flow direction in a semiconductor layer of the thin film transistor of FIG.
  • FIG. 1 is a cross-sectional structural diagram of a thin film transistor according to a preferred embodiment of the present invention.
  • the thin film transistor (TFT) 100 includes a substrate 110, a first gate 120 stacked on a surface of the substrate 110, a first gate insulating layer 130, a semiconductor layer 140, and an etching stop layer (etching stop layer) 150 and the second gate 160.
  • the semiconductor layer 140 has a thickness of 200 nm to 2000 nm.
  • the etch stop layer 150 is provided with a first through hole 151 and a second through hole 152.
  • the first through hole 151 and the second through hole 152 are respectively disposed corresponding to the semiconductor layer 140.
  • the thin film transistor 100 further includes a source 181 and a drain 182.
  • the source 181 and the drain 182 are connected to the semiconductor layer 140 through the first through hole 151 and the second through hole 152, respectively. .
  • the thin film transistor 100 further includes a buffer layer (not shown).
  • the buffer layer is used to buffer stress received during fabrication of other structures of the thin film transistor 100 on the substrate 110 to avoid damage or cracking of the substrate 110.
  • the first gate 120, the first gate insulating layer 130, the semiconductor layer 140, the etching stop layer 150, and the second gate 160 pass the buffer. Layers are stacked on the substrate 110.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the substrate 110 may be a glass substrate, or may be a plastic substrate or an insulating substrate.
  • the first gate 120 is disposed at a middle portion of a surface of the substrate 110.
  • the material of the first gate 120 is metal or a metal alloy. In one embodiment, the material of the first gate 120 is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the first gate 120 can be formed by the following steps. First, an entire metal layer is formed on the surface of the substrate 110. For convenience of description, an entire metal layer formed on the surface of the substrate 110 is named as a first metal layer, and the first metal layer pattern is The first gate electrode 120 disposed in the middle of the substrate 110 of the present embodiment is formed.
  • the first gate insulating layer 130 covers the first gate 120 and the substrate 110.
  • the material of the first gate insulating layer 130 is selected from silicon oxide, silicon nitride layer, silicon oxynitride layer and One of its combinations.
  • the semiconductor layer 140 is disposed on a surface of the first gate insulating layer 130 away from the first gate 120, and the semiconductor layer 140 is electrically connected between a source 181 and a drain 182 of the thin film transistor 100. Or disconnected channels.
  • the etch stop layer 150 covers the semiconductor layer 140.
  • the second gate 160 is disposed at a middle portion of the surface of the etch barrier layer 150 away from the semiconductor layer 140.
  • the material of the second gate 160 is a metal or a metal alloy, and the material of the second gate 160 is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof. In one embodiment, the material of the second gate 160 is the same as the material of the first gate 120. In other embodiments, the material of the second gate 160 is different from the material of the first gate 120.
  • the thin film transistor 100 further includes a passive layer 170.
  • the passivation layer 170 is disposed on the second gate 160, and the passivation layer 170 is provided with a third through hole 171 and a fourth through hole 172.
  • the third through hole 171 communicates with the first through hole 151
  • the fourth through hole 172 communicates with the second through hole 152 .
  • the source electrode 181 is connected to the semiconductor layer 140 through the third through hole 171 and the first through hole 151, and the drain 182 passes through the fourth through hole 172 and the second through hole.
  • 152 is connected to the semiconductor layer 140.
  • the source electrode 181 and the drain electrode 182 are respectively disposed corresponding to both ends of the semiconductor layer 140.
  • the source 181 and the drain 182 may be formed of a transparent conductive material. Specifically, a transparent conductive material is formed on the surface of the passivation layer 170 away from the second gate 160, and then the source 181 and the drain 182 are patterned.
  • the source 181 and the drain 182 may be metal or a metal alloy, or the transparent conductive material may comprise one or any combination of indium tin oxide, indium zinc oxide, indium oxide or zinc oxide.
  • the thin film transistor 100 further includes a first ohmic contact layer (not shown).
  • the first ohmic contact layer is disposed between the source electrode 181 and the semiconductor layer 140, and the source electrode 181 is connected to the semiconductor layer 140 through the first ohmic contact layer.
  • the first ohmic contact layer serves to reduce contact resistance between the source 181 and the semiconductor layer 140.
  • the thin film transistor 100 further includes a second ohmic contact layer (not shown).
  • the second ohmic contact layer is disposed between the drain 182 and the semiconductor layer 140, and the drain 182 is connected to the semiconductor layer 140 through the second ohmic contact layer.
  • the second ohmic contact layer serves to reduce contact resistance between the drain 182 and the semiconductor layer 140.
  • the lateral dimension of the semiconductor layer 140 is greater than the lateral dimension of the first gate 120 and greater than The lateral dimension of the second gate 160.
  • the lateral direction refers to the first gate 120, the first gate insulating layer 130, the semiconductor layer 140, the etch stop layer 150, and the second gate 160.
  • the stacking direction is perpendicular to the direction.
  • FIG. 2 is a schematic diagram of current flow in the semiconductor layer of the thin film transistor of FIG.
  • the semiconductor layer 140 of such a thickness can form two current channels in the semiconductor layer 140.
  • the two current channels are named first current channel 1 and second current channel 2, respectively.
  • the first current channel 1 is adjacent to the first gate insulating layer 130
  • the second current channel 2 is adjacent to the etch barrier layer 150.
  • the direction of the current in the first current channel 1 and the second current channel 2 flows from the source 181 to the drain 182.
  • the on-state current of the thin film transistor 100 is the sum of the current in the first current channel 1 and the current in the second current channel 2. Therefore, the thin film transistor 100 has a high on-state current, which increases the switching speed of the thin film transistor 100.
  • FIG. 3 is a cross-sectional structural diagram of a thin film transistor according to another preferred embodiment of the present invention.
  • the thin film transistor 200 includes a substrate 210 , a first gate 220 stacked on the surface of the substrate 210 , a first gate insulating layer 230 , at least two semiconductor layers 240 , an etch barrier layer 250 , and a second gate 260 .
  • the etch stop layer 250 is provided with a first through hole 251 and a second through hole 252.
  • the first through hole 251 and the second through hole 252 are respectively disposed corresponding to the semiconductor layer 240.
  • the thin film transistor 200 further includes a source 281 and a drain 282.
  • the source 281 and the drain 282 are connected to the semiconductor layer 240 through the first through hole 251 and the second through hole 252, respectively. .
  • the thin film transistor 200 further includes a buffer layer (not shown).
  • the buffer layer serves to buffer stresses encountered during fabrication of other structures of the thin film transistor 200 on the substrate 210 to avoid damage or cracking of the substrate 210.
  • the first gate 220, the first gate insulating layer 230, the semiconductor layer 240, the etch stop layer 250, and the second gate 260 are stacked on the buffer layer.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the substrate 210 may be a glass substrate, or may be a plastic substrate or an insulating substrate.
  • the first gate 220 is disposed at a middle portion of a surface of the substrate 210.
  • the material of the first gate 220 is metal or a metal alloy. In an embodiment, the material of the first gate 220 is selected from the group consisting of One of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the first gate 220 can be formed by the following steps. First, an entire metal layer is formed on the surface of the substrate 210. For convenience of description, an entire metal layer formed on the surface of the substrate 210 is named as a first metal layer, and the first metal layer is Patterning is performed to form the first gate 220 of the present embodiment disposed in the middle of the substrate 210.
  • the first gate insulating layer 230 covers the first gate 220 and the substrate 210.
  • the material of the first gate insulating layer 230 is selected from silicon oxide, silicon nitride layer, silicon oxynitride layer and One of its combinations.
  • the semiconductor layer 240 is disposed on a surface of the first gate insulating layer 230 away from the first gate 220, and the semiconductor layer 240 is electrically connected between a source 281 and a drain 282 of the thin film transistor 200. Or disconnected channels.
  • the etch stop layer 250 overlies the semiconductor layer 240.
  • the material of each layer of the semiconductor layer 240 may be the same or different.
  • the semiconductor layer 240 is described as an example of two layers.
  • the two layers of the semiconductor layers 240 are named as the first semiconductor layer 241 and the second semiconductor layer 242, respectively.
  • the second semiconductor layer 242 and the first semiconductor layer 241 are sequentially stacked on the first gate insulating layer 230.
  • the first semiconductor layer 241 is disposed on a surface of the first gate insulating layer 230 away from the first gate 220, and the second semiconductor layer 242 is disposed adjacent to the etch barrier layer 250.
  • the second gate 260 is disposed at a middle portion of the surface of the etch barrier layer 250 away from the semiconductor layer 240.
  • the material of the second gate 260 is metal or alloy, and the material of the second gate 260 is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the material of the second gate 260 is the same as the material of the first gate 220. In other embodiments, the material of the second gate 260 is different from the material of the first gate 220.
  • the thin film transistor 200 further includes a passivation layer 270.
  • the passivation layer 270 is disposed on the second gate 260, and the passivation layer 270 is provided with a third through hole 271 and a fourth through hole 272.
  • the third through hole 271 communicates with the first through hole 251
  • the fourth through hole 272 communicates with the second through hole 252 .
  • the source 282 is connected to the semiconductor layer 240 through the third through hole 271 and the first through hole 251, and the drain 282 passes through the fourth through hole 272 and the second through hole. 252 is connected to the semiconductor layer 240.
  • the source 281 and the drain 282 are respectively disposed corresponding to both ends of the semiconductor layer 240.
  • Place The material of the source 281 and the drain 282 may be a metal or a metal alloy, or in an embodiment, the source 281 and the drain 282 may be formed of a transparent conductive material. Specifically, the formation of the source 281 and the drain 282 is described by taking the material of the source 281 and the drain 282 as a transparent conductive material, and the passivation layer 270 is away from the A surface of the second gate 260 is formed with a transparent conductive material, and then the source 281 and the drain 282 are patterned.
  • the transparent conductive material may comprise one or any combination of indium tin oxide, indium zinc oxide, indium oxide or zinc oxide.
  • the thin film transistor 200 further includes a first ohmic contact layer (not shown).
  • the first ohmic contact layer is disposed between the source 281 and the semiconductor layer 240, and the source 281 is connected to the semiconductor layer 240 through the first ohmic contact layer.
  • the first ohmic contact layer serves to reduce contact resistance between the source 281 and the semiconductor layer 240.
  • the thin film transistor 200 further includes a second ohmic contact layer (not shown).
  • the second ohmic contact layer is disposed between the drain 282 and the semiconductor layer 240, and the drain 282 is connected to the semiconductor layer 240 through the second ohmic contact layer.
  • the second ohmic contact layer serves to reduce contact resistance between the drain 282 and the semiconductor layer 240.
  • the lateral dimension of the semiconductor layer 240 is greater than the lateral dimension of the first gate 220 and greater than the lateral dimension of the second gate 260.
  • the lateral direction refers to the first gate 220, the first gate insulating layer 230, the semiconductor layer 240, the etch stop layer 250, and the second gate 260.
  • the stacking direction is perpendicular to the direction.
  • FIG. 4 is a schematic diagram of current flow in the semiconductor layer of the thin film transistor of FIG.
  • a current channel is formed in each of the first semiconductor layer 241 and the second semiconductor layer 242.
  • the current channel formed in the first semiconductor layer 241 is named as the third current channel 3
  • the current channel formed in the second semiconductor layer 242 is named as the fourth current channel 4.
  • the direction of the current in the third current channel 3 and the fourth current channel 4 flows from the source 281 to the drain 282.
  • the on-state current of the thin film transistor 200 is the sum of the current in the third current channel 3 and the current in the fourth current channel 4. Therefore, the thin film transistor 200 has a high on-state current, which increases the switching speed of the thin film transistor 200.
  • the number of the semiconductor layers 240 is not limited to two, and may be plural.

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Abstract

一种薄膜晶体管（100），所述薄膜晶体管（100）包括：基板（110）；层叠设置在所述基板（110）表面的第一栅极（120）、第一栅极绝缘层（130）、半导体层（140）、蚀刻阻挡层（150）及第二栅极（160），其中，所述半导体层（140）的厚度为200nm～2000nm；所述蚀刻阻挡层（150）设置有第一贯孔（151）及第二贯孔（152），所述第一贯孔（151）及所述第二贯孔（152）分别对应所述半导体层（140）设置；源极（181）及漏极（182），所述源极（181）及所述漏极（182）分别穿过所述第一贯孔（151）及所述第二贯孔（152）连接所述半导体层（140）。所述薄膜晶体管（100）具有较高的开态电流，以及开关速度。

Description

薄膜晶体管
本发明要求2014年12月9日递交的发明名称为“薄膜晶体管”的申请号201410748282.3的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及薄膜晶体管的制造领域，尤其涉及一种具有较大开态电流的薄膜晶体管。
背景技术
薄膜晶体管(thin film transistor，TFT)作为一种开关元件被广泛地应用在液晶显示装置等电子装置中。双栅极薄膜晶体管作为薄膜晶体管的一种特定的结构，由于可以应用在高分辨率(high pixels per inch，high PPI)的显示设备上而得到广泛地关注。对于双栅极薄膜晶体管而言，高的开态电流可以增加所述双栅极晶体管的开关速度。为了增加所述双栅极薄膜晶体管的开态电流，通常的做法是增加双栅极薄膜晶体管中沟道的宽度或者是减小沟道的长度。然而，增大双栅极薄膜晶体管中沟道的宽度会降低液晶显示装置的开口率；减小双栅极薄膜晶体管的沟道的长度会引起短沟道效应。综上所述，现有技术中双栅极薄膜晶体管的开态电流较小，从而导致双栅极薄膜晶体管的开关速度较慢。
发明内容
本发明提供一种薄膜晶体管，从而提高薄膜晶体管的开态电流，提升所述薄膜晶体管的开关速度。
一方面，本发明提供了一种薄膜晶体管，所述薄膜晶体管包括：
基板；
层叠设置在所述基板表面的第一栅极、第一栅极绝缘层、半导体层、蚀刻阻挡层及第二栅极，其中，所述半导体层的厚度为200nm～2000nm；
所述蚀刻阻挡层设置有第一贯孔及第二贯孔，所述第一贯孔及所述第二贯孔分别对应所述半导体层设置；
源极及漏极，所述源极及所述漏极分别穿过所述第一贯孔及所述第二贯孔连接所述半导体层。
其中，所述薄膜晶体管还包括钝化层，所述钝化层层叠设置于所述第二栅极上，所述钝化层上设有第三贯孔及第四贯孔，所述第三贯孔连通所述第一贯孔，所述第四贯孔连通所述第二贯孔，所述源极穿过所述第三贯孔及所述第一贯孔连接所述半导体层，所述漏极穿过所述第四贯孔及所述第二贯孔连接所述半导体层。
其中，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置于所述源极与所述半导体层之间，所述源极通过所述第一欧姆接触层连接所述半导体层。
其中，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置于所述漏极与所述半导体层之间，所述漏极通过所述第二欧姆接触层连接所述半导体层。
其中，所述半导体层的横向尺寸大于所述第一栅极的横向尺寸且大于所述第二栅极的横向尺寸。
相较于现有技术，由于把所述半导体层的厚度设置为200nm～2000nm，此种厚度的半导体层可以在所述半导体层中形成两个电流沟道。所述薄膜晶体管的开态电流为两个电流沟道中的电流之和。因此，所述薄膜晶体管具有较高的开态电流，提升了所述薄膜晶体管的开关速度。
另一方面，本发明提供了一种薄膜晶体管，所述薄膜晶体管包括：
基板；
层叠设置于所述基板表面的第一栅极、第一栅极绝缘层、至少两层半导体层、蚀刻阻挡层及第二栅极；
所述蚀刻阻挡层设置有第一贯孔及第二贯孔，所述第一贯孔及所述第二贯孔分别对应所述半导体层设置；
源极及漏极，所述源极及所述漏极分别穿过所述第一贯孔及所述第二贯孔连接所述半导体层。
其中，所述薄膜晶体管还包括钝化层，所述敦化层层叠设置于所述第二栅极上，所述钝化层上设有第三贯孔及第四贯孔，所述第三贯孔连通所述第一贯孔，所述第四贯孔连通所述第二贯孔，所述源极穿过所述第三贯孔及所述第一贯孔连接所述半导体层，所述漏极穿过所述第四贯孔及所述第二贯孔连接所述半导体层。
其中，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置于所述源极与所述半导体层之间，所述源极通过所述第一欧姆接触层连接所述半导体层。
其中，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置于所述漏极与所述半导体层之间，所述漏极通过所述第二欧姆接触层连接所述半导体层。
其中，所述半导体层的横向尺寸大于所述第一栅极的横向尺寸且大于所述第二栅极的横向尺寸。
相较于现有技术，由于本发明薄膜晶体管中包括至少两个半导体层，因此，所述薄膜晶体管中能够形成至少两个电流沟道。所述薄膜晶体管中的开态电流为所有的电流沟道中的电流之和，因此，所述薄膜晶体管具有较高的开态电流，提升了所述薄膜晶体管的开关速度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。
图2为图1中的薄膜晶体管的半导体层中的电流流向示意图。
图3为本发明另一较佳实施方式的薄膜晶体管的剖面结构示意图。
图4为图3中的薄膜晶体管的半导体层中的电流流向示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。所述薄膜晶体管(thin film transistor，TFT)100包括基板110、层叠设置在所述基板110表面的第一栅极120、第一栅极绝缘层130、半导体层140、蚀刻阻挡层(etching stop layer)150及第二栅极160。其中，所述半导体层140的厚度为200nm～2000nm。所述蚀刻阻挡层150设有第一贯孔151及第二贯孔152，所述第一贯孔151及所述第二贯孔152分别对应所述半导体层140设置。所述薄膜晶体管100还包括源极181及漏极182，所述源极181及所述漏极182分别穿过所述第一贯孔151及所述第二贯孔152连接所述半导体层140。
在其他实施方式中，所述薄膜晶体管100还包括一缓冲层(图未示)。所述缓冲层用于缓冲在所述基板110上制作所述薄膜晶体管100的其他结构的过程中受到的应力，以避免所述基板110的损坏或者破裂。此时，所述第一栅极120、所述第一栅极绝缘层130、所述半导体层140、所述蚀刻阻挡层(etching stop layer)150及所述第二栅极160通过所述缓冲层层叠设置于所述基板110上。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
所述基板110可以为玻璃基板，也可以为塑料基板或者是绝缘基板。
所述第一栅极120设置于所述基板110的表面的中部。所述第一栅极120的材质为金属或者金属合金，在一实施方式中，所述第一栅极120的材质选自铜、钨、铬、铝及其组合的其中之一。所述第一栅极120可由如下步骤形成。首先，在所述基板110的表面形成一整层金属层，为方便描述，在所述基板110的表面上形成的一整层金属层命名为第一金属层，将所述第一金属层图案化以形成本实施方式的设置在所述基板110中部的第一栅极120。
所述第一栅极绝缘层130覆盖在所述第一栅极120及所述基板110上，所述第一栅极绝缘层130的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
所述半导体层140设置于所述第一栅极绝缘层130远离所述第一栅极120的表面，所述半导体层140为所述薄膜晶体管100的源极181和漏极182之间导通或者断开的通道。所述蚀刻阻挡层150覆盖所述半导体层140上。
所述第二栅极160设置于所述蚀刻阻挡层150远离所述半导体层140的表面的中部。所述第二栅极160的材质为金属或者金属合金，所述第二栅极160的材质选自铜、钨、铬、铝及其组合的其中之一。在一实施方式中，所述第二栅极160的材质与所述第一栅极120的材质相同。在其他实施方式中，所述第二栅极160的材质与所述第一栅极120的材质不同。
所述薄膜晶体管100还包括钝化层(passive layer)170。所述钝化层170设置于所述第二栅极160上，所述钝化层170上设有第三贯孔171及第四贯孔172。所述第三贯孔171连通所述第一贯孔151，所述第四贯孔172连通所述第二贯孔152。所述源极181穿过所述第三贯孔171及所述第一贯孔151连接所述半导体层140，所述漏极182穿过所述第四贯孔172及所述第二贯孔152连接所述半导体层140。
所述源极181及所述漏极182分别对应所述半导体层140的两端设置。在一实施方式中，所述源极181及所述漏极182可以为透明导电材料形成的。具体地，在所述钝化层170远离所述第二栅极160的表面形成一层透明的导电材料，然后图案化定义出所述源极181及所述漏极182。所述源极181及所述漏极182的可以为金属或者金属合金，或者所述透明导电材料可以包含铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
所述薄膜晶体管100还包括第一欧姆接触层(图未示)。所述第一欧姆接触层设置于所述源极181及所述半导体层140之间，所述源极181通过所述第一欧姆接触层连接所述半导体层140。所述第一欧姆接触层用于减小所述源极181与所述半导体层140之间的接触电阻。
所述薄膜晶体管100还包括第二欧姆接触层(图未示)。所述第二欧姆接触层设置于所述漏极182与所述半导体层140之间，所述漏极182通过所述第二欧姆接触层连接所述半导体层140。所述第二欧姆接触层用于减小所述漏极182与所述半导体层140之间的接触电阻。
所述半导体层140的横向尺寸大于所述第一栅极120的横向尺寸，且大于 所述第二栅极160的横向尺寸。在本实施方式中，所述横向是指与所述第一栅极120、所述第一栅极绝缘层130、所述半导体层140、所述蚀刻阻挡层150及所述第二栅极160的堆叠方向垂直的方向。
请一并参阅图2，图2为图1中的薄膜晶体管的半导体层中的电流流向示意图。在本实施方式中，由于把所述半导体层140的厚度设置为200nm～2000nm，此种厚度的半导体层140可以在所述半导体层140中形成两个电流沟道。两个电流沟道分别命名为第一电流沟道①及第二电流沟道②。所述第一电流沟道①邻近所述第一栅极绝缘层130，所述第二电流沟道②邻近所述蚀刻阻挡层150。所述第一电流沟道①及所述第二电流沟道②中的电流的方向均为由所述源极181流向所述漏极182。所述薄膜晶体管100的开态电流为所述第一电流沟道①中的电流与所述第二电流沟道②中的电流之和。因此，所述薄膜晶体管100具有较高的开态电流，提升了所述薄膜晶体管100的开关速度。
请参阅图3，图3为本发明另一较佳实施方式的薄膜晶体管的剖面结构示意图。所述薄膜晶体管200包括基板210、层叠设置于所述基板210表面的第一栅极220、第一栅极绝缘层230、至少两层半导体层240、蚀刻阻挡层250及第二栅极260。所述蚀刻阻挡层250设置有第一贯孔251及第二贯孔252，所述第一贯孔251及所述第二贯孔252分别对应所述半导体层240设置。所述薄膜晶体管200还包括源极281和漏极282，所述源极281及所述漏极282分别穿过所述第一贯孔251及所述第二贯孔252连接所述半导体层240。
在其他实施方式中，所述薄膜晶体管200还包括一缓冲层(图未示)。所述缓冲层用于缓冲在所述基板210上制作所述薄膜晶体管200的其他结构的过程中受到的应力，以避免所述基板210的损坏或者破裂。此时，所述第一栅极220、所述第一栅极绝缘层230、所述半导体层240、所述蚀刻阻挡层250及所述第二栅极260通过所述缓冲层层叠设置于所述基板210上。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
所述基板210可以为玻璃基板，也可以为塑料基板或者是绝缘基板。
所述第一栅极220设置于所述基板210的表面的中部。所述第一栅极220的材质为金属或者金属合金，在一实施方式中，所述第一栅极220的材质选自 铜、钨、铬、铝及其组合的其中之一。所述第一栅极220可由以下步骤形成。首先，在所述基板210的表面形成一整层的金属层，为方便描述，在所述基板210的表面上形成的一整层金属层命名为第一金属层，将所述第一金属层图案化以形成本实施方式的设置在所述基板210中部的第一栅极220。
所述第一栅极绝缘层230覆盖在所述第一栅极220及所述基板210上，所述第一栅极绝缘层230的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
所述半导体层240设置于所述第一栅极绝缘层230远离所述第一栅极220的表面，所述半导体层240为所述薄膜晶体管200的源极281和漏极282之间导通或者断开的通道。所述蚀刻阻挡层250覆盖在所述半导体层240上。各层半导体层240的材料可以相同，也可以不同。
在本实施方式中，以所述半导体层240为两层为例进行介绍。为了方便描述，两层所述半导体层240分别命名为第一半导体层241及第二半导体层242。所述第二半导体层242及所述第一半导体层241依次层叠设置于所述第一栅极绝缘层230上。换句话说，所述第一半导体层241设置于所述第一栅极绝缘层230远离所述第一栅极220的表面，所述第二半导体层242邻近所述蚀刻阻挡层250设置。
所述第二栅极260设置于所述蚀刻阻挡层250远离所述半导体层240的表面的中部。所述第二栅极260的材质为金属或者合金，所述第二栅极260的材质选自铜、钨、铬、铝及其组合的其中之一。在一实施方式中，所述第二栅极260的材质与所述第一栅极220的材质相同。在其他实施方式中，所述第二栅极260的材质与所述第一栅极220的材质不同。
所述薄膜晶体管200还包括钝化层270。所述钝化层270设置于所述第二栅极260上，所述钝化层270上设有第三贯孔271及第四贯孔272。所述第三贯孔271连通所述第一贯孔251，所述第四贯孔272连通所述第二贯孔252。所述源极282穿过所述第三贯孔271及所述第一贯孔251连接所述半导体层240，所述漏极282穿过所述第四贯孔272及所述第二贯孔252连接所述半导体层240。
所述源极281及所述漏极282分别对应所述半导体层240的两端设置。所 述源极281及所述漏极282的材料可以为金属或者金属合金，或者在一实施方式中，所述源极281及所述漏极282可以为透明的导电材料形成的。具体地，以所述源极281及所述漏极282的材料为透明导电材料为例对所述源极281及所述漏极282的形成进行描述，在所述钝化层270远离所述第二栅极260的表面形成一层透明的导电材料，然后图案化定义出所述源极281及所述漏极282。所述透明导电材料可以包含铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
所述薄膜晶体管200还包括第一欧姆接触层(图未示)。所述第一欧姆接触层设置于所述源极281及所述半导体层240之间，所述源极281通过所述第一欧姆接触层连接所述半导体层240。所述第一欧姆接触层用于减小所述源极281与所述半导体层240之间的接触电阻。
所述薄膜晶体管200还包括第二欧姆接触层(图未示)。所述第二欧姆接触层设置于所述漏极282与所述半导体层240之间，所述漏极282通过所述第二欧姆接触层连接所述半导体层240。所述第二欧姆接触层用于减小所述漏极282与所述半导体层240之间的接触电阻。
所述半导体层240的横向尺寸大于所述第一栅极220的横向尺寸，且大于所述第二栅极260的横向尺寸。在本实施方式中，所述横向是指与所述第一栅极220、所述第一栅极绝缘层230、所述半导体层240、所述蚀刻阻挡层250及所述第二栅极260的堆叠方向垂直的方向。
请一并参阅图4，图4为图3中的薄膜晶体管的半导体层中的电流流向示意图。所述第一半导体层241及所述第二半导体层242中分别形成一个电流沟道。所述第一半导体层241中形成的电流沟道命名为第三电流沟道③，所述第二半导体层242中形成的电流沟道命名为第四电流沟道④。所述第三电流沟道③及所述第四电流沟道④中的电流的方向均为由所述源极281流向所述漏极282。所述薄膜晶体管200的开态电流为所述第三电流沟道③中的电流与所述第四电流沟道④中的电流之和。因此，所述薄膜晶体管200具有较高的开态电流，提升了所述薄膜晶体管200的开关速度。
可以理解地，在其他实施方式中，所述半导体层240的数目并不局限于为两个，也可以为多个。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管，其特征在于，所述薄膜晶体管包括：
    基板；
    层叠设置在所述基板表面的第一栅极、第一栅极绝缘层、半导体层、蚀刻阻挡层及第二栅极，其中，所述半导体层的厚度为200nm～2000nm；
    所述蚀刻阻挡层设置有第一贯孔及第二贯孔，所述第一贯孔及所述第二贯孔分别对应所述半导体层设置；
    源极及漏极，所述源极及所述漏极分别穿过所述第一贯孔及所述第二贯孔连接所述半导体层。
  2. 如权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括钝化层，所述钝化层层叠设置于所述第二栅极上，所述钝化层上设有第三贯孔及第四贯孔，所述第三贯孔连通所述第一贯孔，所述第四贯孔连通所述第二贯孔，所述源极穿过所述第三贯孔及所述第一贯孔连接所述半导体层，所述漏极穿过所述第四贯孔及所述第二贯孔连接所述半导体层。
  3. 如权利要求2所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置于所述源极与所述半导体层之间，所述源极通过所述第一欧姆接触层连接所述半导体层。
  4. 如权利要求3所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置于所述漏极与所述半导体层之间，所述漏极通过所述第二欧姆接触层连接所述半导体层。
  5. 如权利要求1所述的薄膜晶体管，其特征在于，所述半导体层的横向尺寸大于所述第一栅极的横向尺寸且大于所述第二栅极的横向尺寸。
  6. 一种薄膜晶体管，其特征在于，所述薄膜晶体管包括：
    基板；
    层叠设置于所述基板表面的第一栅极、第一栅极绝缘层、至少两层半导体层、蚀刻阻挡层及第二栅极；
    所述蚀刻阻挡层设置有第一贯孔及第二贯孔，所述第一贯孔及所述第二贯孔分别对应所述半导体层设置；
    源极及漏极，所述源极及所述漏极分别穿过所述第一贯孔及所述第二贯孔连接所述半导体层。
  7. 如权利要求6所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括钝化层，所述敦化层层叠设置于所述第二栅极上，所述钝化层上设有第三贯孔及第四贯孔，所述第三贯孔连通所述第一贯孔，所述第四贯孔连通所述第二贯孔，所述源极穿过所述第三贯孔及所述第一贯孔连接所述半导体层，所述漏极穿过所述第四贯孔及所述第二贯孔连接所述半导体层。
  8. 如权利要求7所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置于所述源极与所述半导体层之间，所述源极通过所述第一欧姆接触层连接所述半导体层。
  9. 如权利要求8所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置于所述漏极与所述半导体层之间，所述漏极通过所述第二欧姆接触层连接所述半导体层。
  10. 如权利要求6所述的薄膜晶体管，其特征在于，所述半导体层的横向尺寸大于所述第一栅极的横向尺寸且大于所述第二栅极的横向尺寸。
PCT/CN2014/094555 2014-12-09 2014-12-22 薄膜晶体管 WO2016090674A1 (zh)

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