WO2016106795A1 - 用于液晶显示装置的goa电路 - Google Patents

用于液晶显示装置的goa电路 Download PDF

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Publication number
WO2016106795A1
WO2016106795A1 PCT/CN2015/070263 CN2015070263W WO2016106795A1 WO 2016106795 A1 WO2016106795 A1 WO 2016106795A1 CN 2015070263 W CN2015070263 W CN 2015070263W WO 2016106795 A1 WO2016106795 A1 WO 2016106795A1
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Prior art keywords
signal
circuit
goa
liquid crystal
crystal display
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English (en)
French (fr)
Inventor
肖军城
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/417,978 priority Critical patent/US9678593B2/en
Publication of WO2016106795A1 publication Critical patent/WO2016106795A1/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

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  • the present invention relates to the field of liquid crystal display technology, and more particularly to a OLED (Completary Metal Oxide Semiconductor) based on LTPS (Gate Driver On Array) for use in a liquid crystal display device. Circuit.
  • OLED Organic Metal Oxide Semiconductor
  • LTPS Gate Driver On Array
  • touch panel has been widely used in smart phones, tablet/e-books, notebook computers, POS/KIOSK, game consoles, ATM machines, and the like. Touch screens will grow rapidly in the coming years, especially in mobile phones, tablets, portable multimedia players (PMP/MP3), personal navigation devices and other applications. At the same time, touch panels are expected to achieve breakthroughs and growth in large-size screen applications, such as All-In-One computers.
  • the reporting rate is an important indicator of touch technology. It is generally set at a specific value (60) or more to meet the technical requirements.
  • the scanning format determines its reporting point. The rate, which directly affects the sensitivity of the touch, is limited by the time limit of the frame rate and the gate scan driving form.
  • the scanning electrode (Tx) is divided into two types, one is a blanking time after the scanning of the display screen is used for the driving electrode scanning of the touch, so that for 60 Hz
  • the available scanning time is generally less than 4ms.
  • the other is the gap output between the output gate signals during the line scan process, and in order to avoid the interference of the data signal to the drive electrode signals, it needs to be in the flat section of the data, so that for high resolution products
  • the single signal width of the drive electrode is less than 2 us, and the time is small, which is difficult to implement.
  • touch technology it is necessary to consider touch technology to match the normal display drive, which is very large for touch technology. Scanning limit, it is difficult to achieve 120Hz, even higher frequency scanning form, the reporting rate will be more low.
  • the design of GOA is to make the gate scan drive signal circuit on the array substrate by using the existing thin film transistor liquid crystal display array (Array) process.
  • Array thin film transistor liquid crystal display array
  • a technique for driving a gate progressive scan Considering the problem of panel power consumption, the industry almost uses CMOS circuit design for the LTPS process.
  • This patent proposes a CMOS gate drive circuit based on LTPS.
  • the scanning form of the touch is improved, and the reporting rate of the touch panel (TP) is increased, thereby improving the touch.
  • the sensitivity of the control panel is improved.
  • the present invention provides a GOA circuit for a liquid crystal display device, the liquid crystal display device including a plurality of scan lines, the GOA circuit including a plurality of cascaded GOA units, wherein the Nth stage GOA unit controls The Nth stage scan line is charged, wherein the Nth stage GOA unit includes a signal transmission circuit, an inverting amplifier circuit, a signal reset circuit, and an inverting logic circuit.
  • the signal transmission circuit is configured to receive a reverse scan signal, a forward scan signal, and a (N-1)th stage gate signal point and an (N+1)th level gate signal point.
  • the inverting amplifier circuit is connected to the signal transmission circuit, the first clock signal, and the (N)th stage gate signal point.
  • the signal reset circuit is coupled to the inverting amplifier circuit and connected to the high constant voltage source and receives the reset signal.
  • the inverting logic circuit is configured to connect the signal reset circuit, the inverting amplifier circuit, the (N)th stage gate signal point, and the Nth stage scan line.
  • the GOA circuit scans forward from the first level GOA unit to the Xth level GOA unit, and when the GOA circuit accepts the touch message, enters a The touch point scanning program enters a second screen scanning program when the reset signal goes low.
  • the touch point scanning process starts when the forward scan signal is high. Turning to a low potential, the reverse scan signal will change from a low potential to a high potential, and when the reset signal becomes a low potential, in the touch point scanning program, the liquid crystal display device performs A location confirmation procedure for the touch message.
  • the second screen scanning program includes scanning from the Mth level GOA unit to the (X+2)th level GOA unit in which the GOA circuit is reversed, where M is greater than or equal to X+2 .
  • the signal transmission circuit includes a first transmission gate and a second transmission gate.
  • the first transmission gate receives the reverse scan signal
  • the second control terminal receives the forward scan signal, and the input end thereof is connected to the (N-1)th level gate signal point .
  • the first transmission terminal receives the forward scan signal
  • the second control terminal receives the reverse scan signal, and the input end thereof is connected to the (N+1)th level gate signal point
  • the output end is connected to the output end of the first transmission gate.
  • the signal reset circuit includes a first transistor having an output coupled to the output of the second inverting amplifier, a control terminal receiving a reset signal, and an input coupled to the high constant voltage source.
  • the pull-up control circuit includes:
  • the inverting logic circuit includes a second inverter, a NAND gate, a third inverter, a fourth inverter, and a fifth inverter.
  • the second inverter has an input end connected to an output end of the first transistor, and an output end connected to the (N)th stage gate level signal point.
  • the NAND gate has a first input connected to an output of the second inverter and the (N)th stage gate signal point, and a second input receiving a second clock signal.
  • the third inverter has an input end connected to the output end of the NAND gate.
  • the fourth inverter has an input end connected to an output end of the third inverter.
  • the fifth inverter has an input end connected to an output end of the fourth inverter, and an output end connected to the Nth-level scan line.
  • the first clock signal and the second clock signal are mutually inverted signals.
  • the inverting amplifier circuit includes a first inverting amplifier, a first inverter, and a second inverting amplifier.
  • a first inverting amplifier having a first input coupled to an output of the second pass gate.
  • the first inverter has an output connected to the second input of the first inverting amplifier, and an input of the first clock signal.
  • a second inverting amplifier having an output connected to an output of the first first inverting amplifier, a first input connected to an output of the second transmission gate, and a second input receiving a first clock signal
  • the third input terminal and the third input terminal of the first inverting amplifier are connected in common to the (N)th stage gate signal point.
  • the first to second transmission gates are CMOS.
  • the present invention provides a GOA circuit for a liquid crystal display device, the liquid crystal display device including a plurality of scan lines, the GOA circuit including a plurality of cascaded GOA units, wherein the Nth stage GOA unit controls The Nth stage scan line is charged, wherein the Nth stage GOA unit includes a forward and backward scan determination circuit, a signal transmission circuit, an inverting amplifier circuit, a signal reset circuit, and an inverting logic circuit.
  • the forward/reverse scan determining circuit is configured to receive a reverse scan signal, a forward scan signal, a touch point normal phase scan signal, and a touch point reverse scan signal.
  • the signal transmission circuit is configured to receive the reverse scan signal, the forward scan signal, and the (N-1)th stage gate signal point and the (N+1)th level gate signal point.
  • the inverting amplifier circuit is connected to the signal transmission circuit, the first clock signal, and the (N)th stage gate signal point.
  • the signal reset circuit is coupled to the inverting amplifier circuit and connected to the high constant voltage source and receives the reset signal.
  • the inverting logic circuit is configured to connect the signal reset circuit, the inverting amplifier circuit, the (N)th stage gate signal point, and the Nth stage scan line.
  • the GOA circuit scans forward from the first level GOA unit to the Xth level GOA unit, and when the GOA circuit accepts the touch message, enters a
  • the touch point scanning program enters a second screen scanning process when the forward scanning signal changes from a low potential to a high potential and the reverse scanning signal changes from a high potential to a low potential.
  • the touch point scanning process starts when the forward scan signal changes from a high potential to a low potential, and the reverse scan signal changes from a low potential to a high potential, ending at the The forward scan signal goes high again and the reverse scan signal goes low again.
  • the liquid crystal display device performs a position confirmation procedure of the touch message.
  • the second screen scanning program includes the GOA circuit scanning forward from the X+2th GOA unit to the Mth level GOA unit, where M is greater than or equal to X+2.
  • the inverting amplifier circuit includes a first inverting amplifier, a first inverter, and a second inverting amplifier.
  • a first inverting amplifier having a first input coupled to an output of the second pass gate.
  • the first inverter has an output connected to the second input of the first inverting amplifier, and an input of the first clock signal.
  • a second inverting amplifier having an output connected to an output of the first first inverting amplifier, a first input connected to an output of the second transmission gate, and a second input receiving a second clock signal a third input end thereof and a third input end of the first inverting amplifier are commonly connected to the (N)th level gate Level signal point.
  • the signal reset circuit includes a first transistor having an output coupled to the output of the second inverting amplifier, a control terminal receiving a reset signal, and an input coupled to the high constant voltage source.
  • the pull-up control circuit includes:
  • the inverting logic circuit includes a second inverter, a NAND gate, a third inverter, a fourth inverter, and a fifth inverter.
  • the second inverter has an input end connected to an output end of the first transistor, and an output end connected to the (N)th stage gate level signal point.
  • the NAND gate has a first input connected to an output of the second inverter and the (N)th stage gate signal point, and a second input receiving a second clock signal.
  • the third inverter has an input end connected to the output end of the NAND gate.
  • the fourth inverter has an input end connected to an output end of the third inverter.
  • the fifth inverter has an input end connected to an output end of the fourth inverter, and an output end connected to the Nth-level scan line.
  • the first clock signal and the second clock signal are mutually inverted signals.
  • the signal transmission circuit includes a first transmission gate and a second transmission gate.
  • the first transmission gate receives the reverse scan signal
  • the second control terminal receives the forward scan signal, and the input end thereof is connected to the (N-1)th level gate signal point .
  • the first transmission terminal receives the forward scan signal
  • the second control terminal receives the reverse scan signal, and the input end thereof is connected to the (N+1)th level gate signal point
  • the output end is connected to the output end of the first transmission gate.
  • the forward and backward scan determination circuit includes a third transmission gate and a fourth transmission gate.
  • the third transmission gate has a first control end that receives the reverse scan signal, a second control end that receives the forward scan signal, and an input end that receives the touch point reverse scan signal.
  • the first transmission terminal receives the forward scan signal, the second control end receives the reverse scan signal, and the input end receives the touch point reverse scan signal, and the output end thereof Connecting the output of the first transmission gate.
  • the first to fourth transmission gates are CMOS.
  • the LTPS-based CMOS GOA circuit design combined with the scanning method of the touch point realizes the demand of the high-reporting point rate of the touch point and increases the sensitivity of the touch point.
  • the GOA circuit of the display area can be stopped at any position of the circuit, and then the touch point is scanned and touched. At the end of the dot scan, the GOA circuit starts to continue scanning from the next point of the circuit, and then after the end of the output of the GOA circuit, the second TP scan is continued, and the 120 Hz effect of the TP is achieved within a frame range.
  • FIG. 1 is a circuit diagram of a GOA of a first preferred embodiment of the present invention.
  • FIG. 2 is a waveform diagram of the GOA circuit of FIG. 1 in actual operation.
  • FIG. 3 is a schematic diagram of a GOA circuit of FIG. 1 in a liquid crystal display device.
  • FIG. 4 is a schematic view showing the waveform of the liquid crystal display device of FIG. 3 in actual operation.
  • Figure 5 is a circuit diagram of a GOA of a second preferred embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the GOA circuit of FIG. 5 in a liquid crystal display device.
  • FIG. 7 is a schematic diagram showing the waveform of the liquid crystal display device of FIG. 5 in actual operation.
  • the present invention provides a GOA circuit for a liquid crystal display device, the liquid crystal display device comprising a plurality of scan lines, the GOA circuit comprising a plurality of cascaded GOA units (100), wherein the Nth stage GOA unit (100) Controlling charging of the Nth-order scan line (G(N)), wherein the N-th stage GOA unit (G(N)) includes a signal transmission circuit (500), an inverting amplifier circuit (600), and a signal reset circuit (700) And the inverting logic circuit (800).
  • the inverting amplifier circuit (600) connects the signal transmission circuit (500), the first clock signal (CK), and the (N)th stage gate signal point (Q(N)).
  • the signal reset circuit (700) is connected to the inverting amplifier circuit (600), and is connected to a high constant voltage source (VGH) and receives a reset signal (RESET).
  • the inverting logic circuit (800) is configured to connect the signal reset circuit 700, the inverting amplifier circuit (600), the (N)th stage gate signal point (Q(N)), and The Nth-order scan line (G(N)).
  • the signal transmission circuit (500) includes a first transmission gate (11) and a second transmission gate (12).
  • the first transmission gate (11) has a first control end receiving the reverse scan signal (D2U), and a second control end receiving the forward scan signal (U2D), the input end of which is connected to the first N-1) level gate level signal point (Q(N-1)).
  • the second transmission gate (12) has a first control terminal receiving the forward scan signal (U2D), a second control terminal receiving the reverse scan signal (D2U), and an input terminal connected to the first ( N+1) level gate level signal point (Q(N+1)) whose output is connected to the output of the first transmission gate (11).
  • the first transmission gate (11) and the second transmission gate (12) may be CMOS, and the first control end thereof is a gate of a PMOS (P-channel metal-Oxide-semiconductor) in the CMOS, and the second control terminal is A gate of an NMOS (N-channel metal-Oxide-semiconductor) in CMOS.
  • the input of CMOS is the source of PMOS and NMOS (Sourcfe electrode), and the output of CMOS is the drain of PMOS and NMOS.
  • the inverting amplifier circuit (600) includes a first inverting amplifier (19), a first inverter (18), and a second inverting amplifier (20).
  • a first inverting amplifier (19) has a first input connected to an output of the second transmission gate (12).
  • the first inverter (18) has an output connected to the second input of the first inverting amplifier (18) and an input receiving the first clock signal (XCK).
  • a second inverting amplifier (20) having an output connected to an output of the first first inverting amplifier (18), a first input connected to an output of the second transmission gate (12), The second input terminal receives the first clock signal (XCK), and the third input end and the third input end of the first inverting amplifier (18) are commonly connected to the (N)th stage gate level signal point (Q(N)) .
  • the signal reset circuit (700) includes a first transistor (13) having an output connected to an output of the second inverting amplifier (20), a control terminal receiving a reset signal (RESET), and an input terminal connected thereto.
  • the first switch (13) may be an NMOS or a PMOS, the output end of which is a drain, and the input end thereof is a source Its control terminal is the gate.
  • the inverting logic circuit (800) includes a second inverter (14), a NAND gate (21), a third inverter (15), a fourth inverter (16), and a fifth inverter ( 17).
  • the second inverter (14) has an input connected to an output end of the first transistor (13) and an output connected to the (N)th stage gate signal point (Q(N)).
  • the NAND gate (32) has a first input connected to an output of the second inverter (14) and the (N)th gate signal point (Q(N)), and a second The input receives the second clock signal (CK).
  • the third inverter (15) has an input end connected to an output end of the NAND gate (21).
  • the fourth inverter (16) has an input end connected to an output end of the third inverter (15).
  • the fifth inverter (17) has an input end connected to an output end of the fourth inverter (16), and an output end connected to the Nth-order scan line (G(N)).
  • the first clock signal (XCK) and the second clock signal (CK) are mutually inverted signals.
  • the CMOS GOA driver circuit of the present invention is constructed by a transfer gate, an inverter, a NAND gate, and an inverting amplifier.
  • FIG. 2 is a waveform diagram of the GOA circuit of FIG. 1 in actual operation.
  • the second clock signals CK1_L, CK2_R, CK3_L, CK4_R
  • the high constant voltage source (VGH) and the low constant voltage source (VGL) are used to provide high and low potentials in the GOA circuit.
  • the reverse scan signal (D2U) and the forward scan signal (U2D) are used to control the forward and reverse scan of the circuit.
  • the start pulse (STV) is used to turn on the scan action.
  • the four GOA units (100) sequentially generate four scan lines (G1, G2, G3, G4) respectively connected. Group signal.
  • FIG. 3 is a schematic diagram of a GOA circuit of FIG. 1 in a liquid crystal display device.
  • 4 is a schematic view showing the waveform of the liquid crystal display device of FIG. 3 in actual operation.
  • the GOA circuit will scan positively from the first level GOA unit to the third level GOA unit (100) when the GOA circuit accepts the touch message. Entering a touch point scanning program, when the reset signal (RESET) goes low, enters a second screen scanning procedure.
  • RESET reset signal
  • the touch point scanning program starts when the forward scan signal (U2D) changes from a high potential to a low potential, and the reverse scan signal (D2U) changes from a low potential to a high potential, ending at the When the reset signal (RES ET) becomes a low potential, in the touch point scanning program, the liquid crystal display device performs the touch A location confirmation procedure for the message.
  • the second screen scanning program includes scanning from the Mth stage GOA unit to the 5th stage GOA unit (100) in which the GOA circuit is reversed. In other words, in the preferred embodiment, when the local one screen scanning program is scanning to the third level GOA unit (100), the touch message is received, and then the liquid crystal display device performs the position confirmation.
  • the program is used to confirm the position of the touch point, and then the second screen scanning process is executed, and the last level (Mth level) GOA unit (100) is reverse scand to the fifth level GOA unit (100), level 4
  • the level GOA unit (100) does not perform scanning. Complete scanning of all GOA units (100).
  • FIG. 5 is a circuit diagram of a GOA of a second preferred embodiment of the present invention.
  • the preferred embodiment differs from the first preferred embodiment in that the GOA unit (100) further includes a forward and backward scan determination circuit (900).
  • the forward/reverse scan judging circuit (900) is configured to receive the reverse scan signal (D2U), the forward scan signal (U2D), the touch point normal phase scan signal (TPC_F), and the touch point reverse scan Signal (TPC_R).
  • the forward and backward scan determination circuit (900) includes a third transmission gate (21) and a fourth transmission gate (22).
  • the third transmission gate (21) has a first control terminal receiving the reverse scan signal (D2U), a second control terminal receiving the forward scan signal (U2D), and an input terminal receiving the positive phase Scan signal (TPC_F).
  • a fourth transmission gate (22) the first control end thereof receives the forward scan signal, the second control end thereof receives the reverse scan signal, and the input end thereof receives the touch point reverse scan signal (TPC_R) The output end is connected to the output end of the first transmission gate (11).
  • the GOA circuit needs to perform touch point forward and backward scan signal (TCP_F, TCP_R) control, and the front and back scan judgment circuit (900) needs to be independently introduced to start the second screen scanning process.
  • FIG. 6 is a schematic diagram of the GOA circuit of FIG. 5 in a liquid crystal display device.
  • FIG. 7 is a schematic diagram showing the waveform of the liquid crystal display device of FIG. 5 in actual operation.
  • the second screen scanning procedure in the preferred embodiment is forward rather than reverse.
  • the GOA circuit will scan positively from the level 1 GOA unit (100) to the level 3 GOA unit (100) when the GOA circuit accepts the touch
  • a touch point scanning program is entered, and when the forward scan signal (U2D) changes from a low level to a high level and the reverse scan signal (D2U) changes from a high level to a low level, The second screen scanning program.
  • the touch point scanning program starts when the forward scan signal (U2D) changes from a high potential to a low potential, and the reverse scan signal (D2U) changes from a low potential to a high potential, ending at the Forward scan signal U2D) goes high again and the reverse scan signal (D2U) goes low again.
  • the liquid crystal display device performs a position confirmation process of the touch message.
  • the GOA circuit will scan positively from the 5th stage GOA unit to the Mth stage GOA unit (100), and the 4th stage GOA unit (100) will not perform scanning.
  • the GOA circuit is divided into three GOA circuit modules (200, 300, and 400) that are scanned by the first screen scanning program and displayed in the third by scanning to the panel.
  • Level 1 of the GOA unit (100) pauses, starts scanning of the touch point, and then scans the drive electrodes.
  • TCP starts to activate the 5th stage GOA unit (100), and starts the second screen scanning process of the GOA circuit.
  • the GOA circuit module (300) scans and scans to the end. This architecture is suitable for both forward and reverse scanning processes.

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Abstract

一种用于液晶显示装置的阵列基板行扫描驱动（GOA）电路，该液晶显示装置包括多条扫描线，该GOA电路包括级联的多个GOA单元（100）。第N级GOA单元（100）控制对显示区域第N级扫描线充电，该第N级GOA单元（100）包括信号传输电路（500）、倒相放大器电路（600）、信号重置电路（700）及倒相逻辑电路（800）。执行一第一屏幕扫描程序时，该GOA电路会正向的从该第1级GOA单元（100）扫描至该第X级GOA单元（100），当该GOA电路接受该触控讯息时，进入一触控点扫描程序，当该重置信号变为低电位时，进入一第二屏幕扫描程序。该电路通过改善触控的扫描形式，增加触控面板(TP)的报点率，从而改善触控面板的灵敏度。

Description

用于液晶显示装置的GOA电路 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种基于LTPS(Low-Temperature Poly-Si)的CMOS(Complementary Metal Oxide Semiconductor)用于液晶显示装置的GOA(Gate Driver On Array，阵列基板行扫描驱动)电路。
背景技术
触摸屏(Touch Panel)已能广泛应用于智能手机、平板电脑/电子书、笔记本电脑、POS/KIOSK、游戏机、ATM机等领域。未来几年触摸屏将快速成长，尤其是应用在手机、平板电脑、可携式多媒体播放器(PMP/MP3)、个人导航装置与其它应用等。同时，触控面板在大尺寸屏幕的应用上将有望实现突破与成长，如All-In-One计算机等。
从出货量来看，全球有2/3的触摸屏应用于手机，是最主要的应用领域，尤其是，随着成本市场竞争的白热化和高品质的需求，内嵌式(In Cell Touch)电容式技术应运而生，但是对于触控技术来讲，报点率是触控技术的一个重要指标，一般会设定在一个特定的值(60)以上才能符合技术要求，扫描形式决定其报点率，进而直接影响到触控的灵敏度，而触控的扫描形式受限于帧率(Frame Rate)的时间限制和栅极扫描驱动形式。
通常对于触控技术来讲，驱动电极(Tx)的扫描的形式分为两种，一种是在显示画面扫描完之后的空白时间(Blanking time)用于触控的驱动电极扫描，这样对于60Hz的显示装置来讲，可用扫描时间一般不足4ms，
另一种是在行扫描过程中，输出的栅极信号之间的空隙输出，同时为了避免数据(Data)信号对驱动电极信号的干扰，需要在数据的平段区，这样对于高分辨率产品来讲，可用的时间极端，驱动电极的单个信号宽度不足2us，时间较小，很难实现，尤其是需要考虑触控技术来配合正常的显示驱动，这样对触控技术来讲有很大的扫描限制，很难实现120Hz，甚至更高频率的扫描形式这样报点率将较 低。
对于中小尺寸的显示装置，尤其是LTPS产品，均采用GOA的设计，就是利用现有薄膜晶体管液晶显示器数组(Array)制程将栅极(Gate)行扫描驱动信号电路制作在数组基板上，实现对栅极逐行扫描的驱动方式的一项技术。而考虑到面板功耗的问题，业界对于LTPS制程几乎采用CMOS的电路设计。
本篇专利提出了一种基于LTPS的CMOS栅极驱动电路，通过对电路的架构和扫描的形式，来改善触控的扫描形式，增加(触控面板(TP)的报点率，从而改善触控面板的灵敏度。
对发明的公开
技术问题
本发明的目的在于提供一种基于LTPS的CMOS的用于液晶显示装置GOA电路。
问题的解决方案
技术解决方案
为实现上述目的，本发明提供一种用于液晶显示装置的GOA电路，所述液晶显示装置包括多条扫描线，所述GOA电路包含级联的多个GOA单元，其中第N级GOA单元控制对第N级扫描线充电，其中该第N级GOA单元包括信号传输电路、倒相放大器电路、信号重置电路及倒相逻辑电路。
所述信号传输电路，用以接收反向扫描信号、正向扫描信号以及连接第(N-1)级栅级信号点、第(N+1)级栅级信号点。
所述倒相放大器电路，连接所述信号传输电路、第一时钟信号以及第(N)级栅级信号点。所述信号重置电路，连接所述倒相放大器电路，并连接高恒压源以及接收重置信号。所述倒相逻辑电路，用以连接所述信号重置电路、所述倒相放大器电路、所述第(N)级栅级信号点及所述第N级扫描线。
执行一第一屏幕扫描程序时，所述GOA电路会正向的从所述第1级GOA单元扫描至所述第X级GOA单元，当所述GOA电路接受所述触控讯息时，进入一触控点扫描程序，当所述重置信号变为低电位时，进入一第二屏幕扫描程序。
在一实施例中，所述触控点扫描程序开始于所述所述正向扫描信号会由高电位 变为低电位，所述反向扫描信号会由低电位变为高电位，结束于所述重置信号变为低电位时，在所述触控点扫描程序中，所述液晶显示装置进行所述触控讯息的一位置确认程序。在一实施例中，所述第二屏幕扫描程序包括所述GOA电路会反向的从所述第M级GOA单元扫描至第(X+2)级GOA单元，其中M大于或等于X+2。
在一实施例中，所述信号传输电路包括第一传输门及第二传输门。所述第一传输门，其第一控制端接收所述反向扫描信号，其第二控制端接收所述正向扫描信号，其输入端连接所述第(N-1)级栅级信号点。所述第二传输门，其第一控制端接收所述正向扫描信号，其第二控制端接收所述反向扫描信号，其输入端连接所述第(N+1)级栅级信号点，其输出端连接所述第一传输门的输出端。
在一实施例中，所述信号重置电路包括第一晶体管，其输出端连接所述第二倒相放大器的输出端，其控制端接收重置信号，其输入端连接高恒压源。在一实施例中，所述上拉控制电路包括：
在一实施例中，所述倒相逻辑电路包括第二倒相器、与非门、第三倒相器、第四倒相器及第五倒相器。所述第二倒相器，其输入端连接所述第一晶体管的输出端，其输出端连接所述第(N)级栅级信号点。所述与非门，其第一输入端连接所述第二倒相器的输出端及所述第(N)级栅级信号点，其第二输入端接收第二时钟信号。所述第三倒相器，其输入端连接所述与非门的输出端。所述第四倒相器，其输入端连接所述第三倒相器的输出端。所述第五倒相器，其输入端连接所述第四倒相器的输出端，其输出端连接所述第N级扫描线。
在一实施例中，所述第一时钟信号与所述第二时钟信号互为反相信号。
在一实施例中，所述倒相放大器电路包括第一倒相放大器、第一倒相器及第二倒相放大器。第一倒相放大器，其第一输入端连接所述第二传输门的输出端。第一倒相器，其输出端连接所述第一倒相放大器的第二输入端，其输入端接收第一时钟信号。第二倒相放大器，其输出端连接所述第一第一倒相放大器的输出端，其第一输入端连接所述第二传输门的输出端，其第二输入端接收第一时钟信号，其第三输入端及所述第一倒相放大器的第三输入端共同连接第(N)级栅级信号点。
在一实施例中，所述第一至第二传输门是CMOS。
为实现上述目的，本发明提供一种用于液晶显示装置的GOA电路，所述液晶显示装置包括多条扫描线，所述GOA电路包含级联的多个GOA单元，其中第N级GOA单元控制对第N级扫描线充电，其中该第N级GOA单元包括正反扫描判断电路、信号传输电路、倒相放大器电路、信号重置电路及倒相逻辑电路。
所述正反扫描判断电路，用以接收反向扫描信号、正向扫描信号、触控点正相扫描信号及触控点反向扫描信号。所述信号传输电路，用以接收所述反向扫描信号、所述正向扫描信号以及连接所述第(N-1)级栅级信号点、第(N+1)级栅级信号点。所述倒相放大器电路，连接所述信号传输电路、第一时钟信号以及第(N)级栅级信号点。所述信号重置电路，连接所述倒相放大器电路，并连接高恒压源以及接收重置信号。所述倒相逻辑电路，用以连接所述信号重置电路、所述倒相放大器电路、所述第(N)级栅级信号点及所述第N级扫描线。
执行一第一屏幕扫描程序时，所述GOA电路会正向的从所述第1级GOA单元扫描至所述第X级GOA单元，当所述GOA电路接受所述触控讯息时，进入一触控点扫描程序，当所述正向扫描信号由低电位变为高电位以及所述反向扫描信号由高电位变为低电位时，进入一第二屏幕扫描程序。
在一实施例中，所述触控点扫描程序开始于所述所述正向扫描信号会由高电位变为低电位，所述反向扫描信号会由低电位变为高电位，结束于所述正向扫描信号再变为高电位以及所述反向扫描信号再变为低电位，在所述触控点扫描程序中，所述液晶显示装置进行所述触控讯息的一位置确认程序。
在一实施例中，所述第二屏幕扫描程序包括所述GOA电路会正向的从所述第X+2级GOA单元扫描至第M级GOA单元，其中M大于或等于X+2。
在一实施例中，所述倒相放大器电路包括第一倒相放大器、第一倒相器及第二倒相放大器。第一倒相放大器，其第一输入端连接所述第二传输门的输出端。第一倒相器，其输出端连接所述第一倒相放大器的第二输入端，其输入端接收第一时钟信号。第二倒相放大器，其输出端连接所述第一第一倒相放大器的输出端，其第一输入端连接所述第二传输门的输出端，其第二输入端接收第二时钟信号，其第三输入端及所述第一倒相放大器的第三输入端共同连接第(N)级栅 级信号点。
在一实施例中，所述信号重置电路包括第一晶体管，其输出端连接所述第二倒相放大器的输出端，其控制端接收重置信号，其输入端连接高恒压源。在一实施例中，所述上拉控制电路包括：
在一实施例中，所述倒相逻辑电路包括第二倒相器、与非门、第三倒相器、第四倒相器及第五倒相器。所述第二倒相器，其输入端连接所述第一晶体管的输出端，其输出端连接所述第(N)级栅级信号点。所述与非门，其第一输入端连接所述第二倒相器的输出端及所述第(N)级栅级信号点，其第二输入端接收第二时钟信号。所述第三倒相器，其输入端连接所述与非门的输出端。所述第四倒相器，其输入端连接所述第三倒相器的输出端。所述第五倒相器，其输入端连接所述第四倒相器的输出端，其输出端连接所述第N级扫描线。
在一实施例中，所述第一时钟信号与所述第二时钟信号互为反相信号。
在一实施例中，所述信号传输电路包括第一传输门及第二传输门。所述第一传输门，其第一控制端接收所述反向扫描信号，其第二控制端接收所述正向扫描信号，其输入端连接所述第(N-1)级栅级信号点。所述第二传输门，其第一控制端接收所述正向扫描信号，其第二控制端接收所述反向扫描信号，其输入端连接所述第(N+1)级栅级信号点，其输出端连接所述第一传输门的输出端。
在一实施例中，所述正反扫描判断电路包括第三传输门及第四传输门。所述第三传输门，其第一控制端接收所述反向扫描信号，其第二控制端接收所述正向扫描信号，其输入端接收所述触控点反向扫描信号。所述第四传输门，其第一控制端接收所述正向扫描信号，其第二控制端接收所述反向扫描信号，其输入端接收所述触控点反向扫描信号，其输出端连接所述第一传输门的输出端。
在一实施例中，所述第一至第四传输门是CMOS。
发明的有益效果
有益效果
通过本发明的上述技术方案，产生的有益技术效果在于：
1.基于LTPS的CMOS GOA电路设计结合触控点的扫描方式，实现触控点的高报点率的需求，增加触控点的灵敏度。
2.通过区域扫描，来实现触控点的多次扫描，达到120Hz甚至更高的扫描频率，可以将显示区的GOA电路在电路的任意某一位置停止输出，接着触控点扫描，触控点扫描结束，GOA电路开始从停止的点开始下一级电路的继续扫描，然后在GOA电路输出后部分结束之后，继续第二次的TP扫描，在一帧范围之内实现TP的120Hz效果。
3.通过对电路架构的修正减轻电子工程(Eelectronic Engineering)端的限制和压力，节省IC(Integrated Chip)的控制成本，达到面板成本的降低，通时通过CMOS的电路设计来结合触控点的显示，可以有效的降低功耗，增强电路的性能
对附图的简要说明
附图说明
图1为本发明的第一优选实施例的GOA的电路示意图。
图2为图1中的GOA电路在实际操作时的波形示意图。
图3为图1的GOA电路在液晶显示装置的示意图。
图4为图3的液晶显示装置在实际操作时的波形示意图。
图5为本发明的第二优选实施例的GOA的电路示意图。
图6为图5的GOA电路在液晶显示装置的示意图。
图7为图5的液晶显示装置在实际操作时的波形示意图。
实施该发明的最佳实施例
本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
图1为本发明的第一优选实施例的GOA的电路示意图。本发明提供一种用于液晶显示装置的GOA电路，所述液晶显示装置包括多条扫描线，所述GOA电路包含级联的多个GOA单元(100)，其中第N级GOA单元(100)控制对第N级扫描线(G(N))充电，其中该第N级GOA单元(G(N))包括信号传输电路(500)、倒相放大器电路(600)、信号重置电路(700)及倒相逻辑电路(800)。所述信号传输电路(500)，用 以接收反向扫描信号(D2U)、正向扫描信号(U2D)以及连接第(N-1)级栅级信号点(Q(N-1))、第(N+1)级栅级信号点(Q(N+1))。所述倒相放大器电路(600)，连接所述信号传输电路(500)、第一时钟信号(CK)以及第(N)级栅级信号点(Q(N))。所述信号重置电路(700)，连接所述倒相放大器电路(600)，并连接高恒压源(VGH)以及接收重置信号(RESET)。所述倒相逻辑电路(800)，用以连接所述信号重置电路700、所述倒相放大器电路(600)、所述第(N)级栅级信号点(Q(N))及所述第N级扫描线(G(N))。
所述信号传输电路(500)包括第一传输门(11)及第二传输门(12)。所述第一传输门(11)，其第一控制端接收所述反向扫描信号(D2U)，其第二控制端接收所述正向扫描信号(U2D)，其输入端连接所述第(N-1)级栅级信号点(Q(N-1))。所述第二传输门(12)，其第一控制端接收所述正向扫描信号(U2D)，其第二控制端接收所述反向扫描信号(D2U)，其输入端连接所述第(N+1)级栅级信号点(Q(N+1))，其输出端连接所述第一传输门(11)的输出端。
所述第一传输门(11)及第二传输门(12)可以是CMOS，其第一控制端就是CMOS中的PMOS(P-channel metal-Oxide-semiconductor)的栅极，第二控制端就是CMOS中的NMOS(N-channel metal-Oxide-semiconductor)的栅极(Gate electrode)。CMOS的输入端就是PMOS与NMOS的源极(Sourcfe electrode)，CMOS的输出端就是PMOS与NMOS的漏极(Drain electrode)。
所述倒相放大器电路(600)包括第一倒相放大器(19)、第一倒相器(18)及第二倒相放大器(20)。第一倒相放大器(19)，其第一输入端连接所述第二传输门(12)的输出端。第一倒相器(18)，其输出端连接所述第一倒相放大器(18)的第二输入端，其输入端接收第一时钟信号(XCK)。第二倒相放大器(20)，其输出端连接所述第一第一倒相放大器(18)的输出端，其第一输入端连接所述第二传输门(12)的输出端，其第二输入端接收第一时钟信号(XCK)，其第三输入端及所述第一倒相放大器(18)的第三输入端共同连接第(N)级栅级信号点(Q(N))。
所述信号重置电路(700)包括第一晶体管(13)，其输出端连接所述第二倒相放大器(20)的输出端，其控制端接收重置信号(RESET)，其输入端连接高恒压源(VGH)。所述第一开关(13)可以是NMOS或PMOS，其输出端是漏极，其输入端是源极 ，其控制端是栅极。
所述倒相逻辑电路(800)包括第二倒相器(14)、与非门(21)、第三倒相器(15)、第四倒相器(16)及第五倒相器(17)。所述第二倒相器(14)，其输入端连接所述第一晶体管(13)的输出端，其输出端连接所述第(N)级栅级信号点(Q(N))。所述与非门(32)，其第一输入端连接所述第二倒相器(14)的输出端及所述第(N)级栅级信号点(Q(N))，其第二输入端接收第二时钟信号(CK)。所述第三倒相器(15)，其输入端连接所述与非门(21)的输出端。所述第四倒相器(16)，其输入端连接所述第三倒相器(15)的输出端。所述第五倒相器(17)，其输入端连接所述第四倒相器(16)的输出端，其输出端连接所述第N级扫描线(G(N))。所述第一时钟信号(XCK)与所述第二时钟信号(CK)互为反相信号。
在本优选实施例中，通过传输门、倒相器、与非门、倒相放大器构成了本发明的CMOS GOA驱动电路。
图2为图1中的GOA电路在实际操作时的波形示意图。举例来说，当有四个所述第二时钟信号(CK1_L，CK2_R，CK3_L，CK4_R)，分别用于控制4个所述GOA单元(100)。所述高恒压源(VGH)及所述低恒压源(VGL)用于提供GOA电路中的高低电位。反向扫描信号(D2U)及正向扫描信号(U2D)用于负责电路的正反相扫描控制。启动脉冲(STV)用于开启扫描动作。依据所述四个所述第二时钟信号(CK1_L，CK2_R，CK3_L，CK4_R)，四个所述GOA单元(100)依序对分别连接的四条扫描线(G1，G2，G3，G4)产生四组信号。
参考图3及图4。图3为图1的GOA电路在液晶显示装置的示意图。图4为图3的液晶显示装置在实际操作时的波形示意图。执行一第一屏幕扫描程序时，所述GOA电路会正向的从所述第1级GOA单元扫描至所述第3级GOA单元(100)，当所述GOA电路接受所述触控讯息时，进入一触控点扫描程序，当所述重置信号(RESET)变为低电位时，进入一第二屏幕扫描程序。
所述触控点扫描程序开始于所述所述正向扫描信号(U2D)会由高电位变为低电位，所述反向扫描信号(D2U)会由低电位变为高电位，结束于所述重置信号(RES ET)变为低电位时，在所述触控点扫描程序中，所述液晶显示装置进行所述触控 讯息的一位置确认程序。所述第二屏幕扫描程序包括所述GOA电路会反向的从所述第M级GOA单元扫描至第5级GOA单元(100)。换句话说，本优选实施例中，当地一屏幕扫描程序正向扫描至所述第3级GOA单元(100)时，接收到所述触控讯息，接着所述液晶显示装置执行所述位置确认程序用以确认触控点的位置，接着执行所述第二屏幕扫描程序，由最后一级(第M级)GOA单元(100)反向扫描至第5级GOA单元(100)，第4级级GOA单元(100)不执行扫描。完成所有GOA单元(100)的扫描。
图5为本发明的第二优选实施例的GOA的电路示意图。本优选实施例与第一优选实施例的区别在于：所述GOA单元(100)进一步包括一正反扫描判断电路(900)。所述正反扫描判断电路(900)用以接收所述反向扫描信号(D2U)、所述正向扫描信号(U2D)、触控点正相扫描信号(TPC_F)及触控点反向扫描信号(TPC_R)。
所述正反扫描判断电路(900)包括第三传输门(21)及第四传输门(22)。所述第三传输门(21)，其第一控制端接收所述反向扫描信号(D2U)，其第二控制端接收所述正向扫描信号(U2D)，其输入端接收所述正相扫描信号(TPC_F)。第四传输门(22)，其第一控制端接收所述正向扫描信号，其第二控制端接收所述反向扫描信号，其输入端接收所述触控点反向扫描信号(TPC_R)，其输出端连接所述第一传输门(11)的输出端。
所述GOA电路需要做触控点正反向扫描信号(TCP_F，TCP_R)控制，需要独立引入所述正反扫描判断电路(900)来启动第二屏幕扫描程序。
参考图6及图7。图6为图5的GOA电路在液晶显示装置的示意图。图7为图5的液晶显示装置在实际操作时的波形示意图。
与第一优选实施例的区别在于：本优选实施例中第二屏幕扫描程序是正向而非反向。执行一第一屏幕扫描程序时，所述GOA电路会正向的从所述第1级GOA单元(100)扫描至所述第3级GOA单元(100)，当所述GOA电路接受所述触控讯息时，进入一触控点扫描程序，当所述正向扫描信号(U2D)由低电位变为高电位以及所述反向扫描信号(D2U)由高电位变为低电位时，进入一第二屏幕扫描程序。
所述触控点扫描程序开始于所述所述正向扫描信号(U2D)会由高电位变为低电位，所述反向扫描信号(D2U)会由低电位变为高电位，结束于所述正向扫描信号( U2D)再变为高电位以及所述反向扫描信号(D2U)再变为低电位，在所述触控点扫描程序中，所述液晶显示装置进行所述触控讯息的一位置确认程序。
在所述第二屏幕扫描程序中，所述GOA电路会正向的从所述第5级GOA单元扫描至第M级GOA单元(100)，第4级GOA单元(100)不执行扫描。完成所有GOA单元(100)的扫描。在本优选实施例中，此GOA电路分成三个GOA电路模块(200、300和400)，所述GOA电路模块(200)是由第一屏幕扫描程序负责扫描，通过扫描至面板显示在第3级GOA单元(100)那一级停顿，开始触控点的扫描，接着扫描驱动电极，完毕之后，TCP开始启动第5级GOA单元(100)，开始GOA电路的第二屏幕扫描程序对所述GOA电路模块(300)进行扫描，一直扫描到结束，此架构同时适用于正向和反响扫描的过程。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种用于液晶显示装置的GOA电路，所述液晶显示装置包括多条扫描线，所述GOA电路包含级联的M个GOA单元，其中第N级GO A单元控制对第N级扫描线充电，所述GOA电路用于执行第一屏幕扫描程序与第二屏幕扫描程序以侦测一触控讯息，其特征在于，该第N级GOA单元包括：
    信号传输电路，用以接收反向扫描信号、正向扫描信号以及连接第(N-1)级栅级信号点、第(N+1)级栅级信号点；
    倒相放大器电路，连接所述信号传输电路、第一时钟信号以及第(N)级栅级信号点；
    信号重置电路，连接所述倒相放大器电路，并连接高恒压源以及接收重置信号；
    倒相逻辑电路，用以连接所述信号重置电路、所述倒相放大器电路、所述第(N)级栅级信号点及所述第N级扫描线，
    其中，执行所述第一屏幕扫描程序时，所述GOA电路会正向的从所述第1级GOA单元扫描至所述第X级GOA单元，当所述GOA电路接受所述触控讯息时，进入一触控点扫描程序，当所述重置信号变为低电位时，进入所述第二屏幕扫描程序。
  2. 如权利要求1所述的用于液晶显示装置的GOA电路，其中所述触控点扫描程序开始于所述所述正向扫描信号会由高电位变为低电位，所述反向扫描信号会由低电位变为高电位，结束于所述重置信号变为低电位时，在所述触控点扫描程序中，所述液晶显示装置进行所述触控讯息的一位置确认程序。
  3. 如权利要求1所述的用于液晶显示装置的GOA电路，其中所述第二屏幕扫描程序包括所述GOA电路会反向的从所述第M级GOA单元扫描至第(X+2)级GOA单元，其中M大于或等于X+2。
  4. 如权利要求1所述的用于液晶显示装置的GOA电路，其中所述倒相放大器电路包括：
    第一倒相放大器，其第一输入端连接所述第二传输门的输出端；
    第一倒相器，其输出端连接所述第一倒相放大器的第二输入端，其输入端接收第一时钟信号；
    第二倒相放大器，其输出端连接所述第一第一倒相放大器的输出端，其第一输入端连接所述第二传输门的输出端，其第二输入端接收第一时钟信号，其第三输入端及所述第一倒相放大器的第三输入端共同连接第(N)级栅级信号点。
  5. 如权利要求1所述的用于液晶显示装置的GOA电路，其中所述信号重置电路包括：
    第一晶体管，其输出端连接所述第二倒相放大器的输出端，其控制端接收重置信号，其输入端连接高恒压源。
  6. 如权利要求1所述的用于液晶显示装置的GOA电路，其中所述倒相逻辑电路包括：
    第二倒相器，其输入端连接所述第一晶体管的输出端，其输出端连接所述第(N)级栅级信号点；
    与非门，其第一输入端连接所述第二倒相器的输出端及所述第(N)级栅级信号点，其第二输入端接收第二时钟信号；
    第三倒相器，其输入端连接所述与非门的输出端；
    第四倒相器，其输入端连接所述第三倒相器的输出端；
    第五倒相器，其输入端连接所述第四倒相器的输出端，其输出端连接所述第N级扫描线。
  7. 如权利要求1所述的用于液晶显示装置的GOA电路，其中所述第一时钟信号与所述第二时钟信号互为反相信号。
  8. 如权利要求1所述的用于液晶显示装置的GOA电路，其中所述信号传输电路包括：
    第一传输门，其第一控制端接收所述反向扫描信号，其第二控制端接收所述正向扫描信号，其输入端连接所述第(N-1)级栅级信号点；
    第二传输门，其第一控制端接收所述正向扫描信号，其第二控制端接收所述反向扫描信号，其输入端连接所述第(N+1)级栅级信号点，其输出端连接所述第一传输门的输出端。
  9. 如权利要求4所述的用于液晶显示装置的GOA电路，其中所述第一至第二传输门是CMOS(Complementary Metal-Oxide Semiconductor)。
  10. 一种用于液晶显示装置的GOA电路，所述液晶显示装置包括多条扫描线，所述GOA电路包含级联的M个GOA单元，其中第N级GO A单元控制对第N级扫描线充电，所述GOA电路用于执行第一屏幕扫描程序与第二屏幕扫描程序以侦测一触控讯息，M大于(N+1)，其中该第N级GOA单元包括：
    正反扫描判断电路，用以接收反向扫描信号、正向扫描信号、触控点正相扫描信号及触控点反向扫描信号；
    信号传输电路，用以接收所述反向扫描信号、所述正向扫描信号以及连接所述第(N-1)级栅级信号点、第(N+1)级栅级信号点；
    倒相放大器电路，连接所述信号传输电路、第一时钟信号以及第(N)级栅级信号点；
    信号重置电路，连接所述倒相放大器电路，并连接高恒压源以及接收重置信号；
    倒相逻辑电路，用以连接所述信号重置电路、所述倒相放大器电路、所述第(N)级栅级信号点及所述第N级扫描线，
    其中，执行所述第一屏幕扫描程序时，所述GOA电路会正向的从所述第1级GOA单元扫描至所述第X级GOA单元，当所述GOA电路接受所述触控讯息时，进入一触控点扫描程序，当所述正向扫描信号由低电位变为高电位以及所述反向扫描信号由高电位变为低电位时，进入所述一第二屏幕扫描程序。
  11. 如权利要求9所述的用于液晶显示装置的GOA电路，其中所述触控点扫描程序开始于所述所述正向扫描信号会由高电位变为低电 位，所述反向扫描信号会由低电位变为高电位，结束于所述正向扫描信号再变为高电位以及所述反向扫描信号再变为低电位，在所述触控点扫描程序中，所述液晶显示装置进行所述触控讯息的一位置确认程序。
  12. 如权利要求9所述的用于液晶显示装置的GOA电路，其中所述第二屏幕扫描程序包括所述GOA电路会正向的从所述第X+2级GOA单元扫描至第M级GOA单元，其中M大于或等于X+2。
  13. 如权利要求9所述的用于液晶显示装置的GOA电路，其中所述倒相放大器电路包括：
    第一倒相放大器，其第一输入端连接所述第二传输门的输出端；
    第一倒相器，其输出端连接所述第一倒相放大器的第二输入端，其输入端接收第一时钟信号；
    第二倒相放大器，其输出端连接所述第一第一倒相放大器的输出端，其第一输入端连接所述第二传输门的输出端，其第二输入端接收第一时钟信号，其第三输入端及所述第一倒相放大器的第三输入端共同连接第(N)级栅级信号点。
  14. 如权利要求9所述的用于液晶显示装置的GOA电路，其中所述信号重置电路包括：
    第一晶体管，其输出端连接所述第二倒相放大器的输出端，其控制端接收重置信号，其输入端连接高恒压源；
  15. 如权利要求9所述的用于液晶显示装置的GOA电路，其中所述倒相逻辑电路包括：
    第二倒相器，其输入端连接所述第一晶体管的输出端，其输出端连接所述第(N)级栅级信号点；
    与非门，其第一输入端连接所述第二倒相器的输出端及所述第(N)级栅级信号点，其第二输入端接收第二时钟信号；
    第三倒相器，其输入端连接所述与非门的输出端；
    第四倒相器，其输入端连接所述第三倒相器的输出端；
    第五倒相器，其输入端连接所述第四倒相器的输出端，其输出端连接所述第N级扫描线。
  16. 如权利要求9所述的用于液晶显示装置的GOA电路，其中所述第一时钟信号与所述第二时钟信号互为反相信号。
  17. 如权利要求9所述的用于液晶显示装置的GOA电路，其中所述信号传输电路包括：
    第一传输门，其第一控制端接收所述反向扫描信号，其第二控制端接收所述正向扫描信号，其输入端接收所述触控点正相扫描信号；
    第二传输门，其第一控制端接收所述正向扫描信号，其第二控制端接收所述反向扫描信号，其输入端接收触控点反相扫描信号，其输出端连接所述第三传输门的输出端共同连接第(N-1)级栅级信号点。
  18. 如权利要求17所述的用于液晶显示装置的GOA电路，其中所述正反扫描判断电路包括：
    第三传输门，其第一控制端接收所述反向扫描信号，其第二控制端接收所述正向扫描信号，其输入端接收所述触控点正相扫描信号；
    第四传输门，其第一控制端接收所述正向扫描信号，其第二控制端接收所述反向扫描信号，其输入端接收触控点反向扫描信号，其输出端连接所述第一传输门的输出端。
  19. 如权利要求17-18其中任一项所述的用于液晶显示装置的GOA电路，其中所述第一至第四传输门是CMOS。
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