WO2016098296A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2016098296A1
WO2016098296A1 PCT/JP2015/005974 JP2015005974W WO2016098296A1 WO 2016098296 A1 WO2016098296 A1 WO 2016098296A1 JP 2015005974 W JP2015005974 W JP 2015005974W WO 2016098296 A1 WO2016098296 A1 WO 2016098296A1
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WO
WIPO (PCT)
Prior art keywords
wiring board
semiconductor element
semiconductor device
mounting
semiconductor
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PCT/JP2015/005974
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French (fr)
Japanese (ja)
Inventor
典子 狩野
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凸版印刷株式会社
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Publication of WO2016098296A1 publication Critical patent/WO2016098296A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a resin-encapsulated semiconductor device and a manufacturing method thereof.
  • an interposer substrate for mounting a semiconductor element and a printed wiring board that generically refers to a printed circuit board for mounting an electronic component including the semiconductor element are required to have high density and high-speed response.
  • electronic devices are required to be miniaturized, thinned, multi-pinned, and high heat dissipation on the premise of high reliability.
  • a liquid epoxy resin composition is used to fill and seal the gap between the semiconductor element and the wiring board (hereinafter referred to as “gap”).
  • the epoxy resin composition is cured, the entire semiconductor element is sealed with the epoxy resin composition again.
  • this method has a problem that it takes a very long time to complete the filling because the liquid epoxy resin composition is filled in the gap between the semiconductor element and the wiring board by utilizing the capillary phenomenon.
  • the entire semiconductor element is sealed with the epoxy resin composition after the step of filling the gap with the liquid epoxy resin composition, a plurality of steps are required, and there is a problem that productivity is lowered.
  • Patent Document 1 in order to solve the above problem, by approaching the compounding of the inorganic filler contained in the sealing resin composition, the mold sealing on the back surface of the semiconductor element and the wiring substrate and the semiconductor element are disclosed. A method of manufacturing a semiconductor device that enables simultaneous filling of both gaps is disclosed.
  • Patent Document 2 discloses a method of increasing the mechanical strength of a circuit board and preventing moisture absorption from the outside by forming a metal barrier groove in the circuit board.
  • FIG. 1 is an end view of a cut portion of a conventional resin-encapsulated semiconductor device described in Patent Document 1.
  • FIG. 1 is an end view of a cut portion of a conventional resin-encapsulated semiconductor device described in Patent Document 1.
  • Patent Document 1 When the imposing wiring board is separated and separated into pieces by using the method of Patent Document 1, the outer periphery of the substrate is completely exposed as shown in FIG. There is a problem that moisture permeates into the apparatus and interface peeling of the package substrate occurs. Further, the method described in Patent Document 2 has a problem that the number of external terminals and the layout of components are limited because the metal barrier groove is formed in the semiconductor device substrate.
  • a method of manufacturing a semiconductor device includes a step of mounting one or more semiconductor elements in each of a plurality of semiconductor element mounting regions on a wiring board, and a dicing line before or after mounting the semiconductor elements. After the step of forming a groove in the wiring board and mounting of the semiconductor element, the mounting surface of the semiconductor element on the wiring board, the groove, and the semiconductor element are collectively sealed with mold resin, and then along the dicing line, from the groove And a step of dicing the semiconductor device by dicing with a narrow cutting width.
  • a semiconductor device includes a wiring substrate having a core layer and a wiring layer provided on at least one surface of the core layer and including a laminate of one or more conductor layers and one or more insulating layers. And a semiconductor element mounted on the wiring layer, a mounting surface of the semiconductor element on the wiring board, and a mold resin formed to cover the semiconductor element.
  • the mold resin is formed so as to surround at least a part of the side surface of the conductor layer provided on the outermost surface on the mounting surface side of the wiring board.
  • a resin-encapsulated semiconductor device with improved reliability and a method for manufacturing the same can be realized.
  • FIG. 1 is a cutaway end view of a conventional resin-encapsulated semiconductor device.
  • FIG. 2 is a cross-sectional end view of the semiconductor device according to the embodiment.
  • FIG. 3 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment.
  • FIG. 4 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment.
  • FIG. 5 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment.
  • FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment.
  • FIG. 2 is an end view of a cut portion of the semiconductor device according to the embodiment
  • FIGS. 3 to 6 are diagrams showing manufacturing steps of the semiconductor device according to the embodiment.
  • the semiconductor device manufacturing method shown in FIG. 3 to FIG. 6 is a method in which a plurality of semiconductor elements are provided on a single wiring board and the semiconductor device is separated into pieces after forming a mold resin. In the wiring board, a boundary portion between a pair of adjacent semiconductor element mounting regions is shown enlarged.
  • a multilayer wiring board 3 is used as the wiring board.
  • the multilayer wiring board 3 is provided with a plurality of semiconductor element mounting regions arranged in a matrix in order to improve the productivity of the semiconductor device.
  • the lamination method is a method of laminating the conductor layer 9 and the insulating layer 11 on both surfaces of the core layer 4 or a method of laminating the conductor layer 9 and the insulating layer 11 on one side of the support and the like and finally separating from the support. Either may be sufficient.
  • the material of the core layer 4 is desirably the same as or lower than the moisture absorption rate of the insulating layer 11 so as not to affect the moisture absorption of the wiring layer.
  • the moisture absorption rate of the material constituting the core layer 4 is generally 0.2% or less.
  • glass can be preferably used, and in particular, borosilicate glass can be more preferably used.
  • Through holes and vias 10 are formed by laser processing or the like for the purpose of measuring conduction between layers.
  • the material for the insulating layer 11 include, but are not limited to, materials such as resin, glass, glass epoxy, polyimide, ceramic, and metal.
  • the material of the conductor layer 9 is a conductive metal capable of forming a circuit, and examples thereof include Cu, Al, Ni, and Au, but are not limited thereto.
  • the conductor layer 9 is formed by electroplating or a chemical plating method.
  • the thickness of the conductor layer 9 is, for example, 1 to 20 ⁇ m, and the circuit is formed by, for example, a technique such as photolithography.
  • the semiconductor element 1 is disposed in each of the semiconductor element mounting regions on the multilayer wiring board 3, and the semiconductor element electrode 5a is mounted on the substrate electrode 5b of the multilayer wiring board 3 in a face-down manner.
  • a flip chip mounting portion (hereinafter referred to as “mounting portion”) is formed.
  • the mounting portion on the multilayer wiring board 3 is reflowed to form bumps 5.
  • the substrate electrode 5b include Sn / Ag / Cu, Sn / Pb, Sn / Ag, Su / Cu, Su / Sb, Su / Zn, and Su / Bi, but are not limited thereto.
  • the shape of the substrate electrode 5b may be a protruding electrode, the surface may be subjected to plating or pre-solder treatment, or may be subjected to organic coating treatment such as OSP. Further, in order to connect the semiconductor element electrode 5a and the substrate electrode 5b in a short time, pressurization with heating or vibration may be applied by local reflow.
  • the semiconductor element electrode 5a and the substrate electrode 5b are not arranged in corresponding areas on the semiconductor element 1 and the multilayer wiring board 3, respectively, but on the peripheral four sides of the semiconductor element 1 and on the multilayer wiring board 3, respectively. Peripherals may be arranged in the corresponding regions.
  • the gap 12 of the mounting part is cleaned. This is intended to remove flux residual components. Therefore, it is not always necessary to clean the gap 12 when a flux that does not require cleaning is used or when a flux is not used.
  • passive components may be mounted on the multilayer wiring board 3.
  • the passive element electrode 6 is formed on the electrode on the multilayer wiring board 3 by using plating, printing, vapor deposition or the like (see FIG. 2).
  • a multilayer ceramic capacitor or the like may be mounted on the formed passive element electrode 6 using a component mounting device.
  • the type, size, and number of electrodes of the passive component are not limited.
  • the material of the passive element electrode 6 is preferably composed mainly of solder, for example, Sn / Ag / Cu, Sn / Pb, Su / Ag, Su / Cu, Su / Sb, Su / Zn, Su, Examples include Bi, but are not limited thereto.
  • the shape of the passive element electrode 6 may be a protruding electrode, the surface may be subjected to plating or pre-solder treatment, or may be subjected to organic coating treatment such as OSP.
  • the passive element electrode 6 and the passive component may be joined by reflow.
  • the resin composition may be filled before the molding step as necessary.
  • the resin composition used is mainly a liquid epoxy resin composition system, but a phenol resin, a polyimide resin, a silicone resin resin, or the like may be used.
  • the multilayer wiring board 3 on which the mounting portion is formed is placed on a heated dispenser stage, and the temperature is raised to enhance the fluidity of the liquid epoxy resin composition. About the temperature rising temperature, you may select the recommended conditions where the performance of the resin composition to be used is exhibited most.
  • the liquid epoxy resin composition is applied to any one side of the flip chip mounting part and left on the stage until filling is completed. Thereafter, the flip-chip mounting portion where the resin filling is completed is moved to a temperature atmosphere in which the resin can be cured, and the resin is completely cured, thereby forming an underfill.
  • optimum conditions are adopted for the curing time and the curing temperature.
  • E. Groove fabrication ( Figure 5) A dicing tape (not shown) is attached to the multilayer wiring board 3 on which the semiconductor element 1 is mounted, and a groove 7 is formed in the multilayer wiring board 3 along the center of the individualized dicing line 14 as shown in FIG. To do. There is no problem in the step of forming the groove 7 even before the semiconductor element 1 is mounted.
  • a method by blade dicing, laser dicing, or a combination of both may be used.
  • the method for forming the groove 7 is not limited to this.
  • the width of the groove 7 formed on the multilayer wiring board 3 is made larger than the dicing width (cutting width) at the time of separation.
  • the depth of the groove 7 is preferably a sufficient depth to reach the core layer 4. After forming the groove 7, the multilayer wiring board 3 is deaerated in a vacuum oven.
  • the mold resin 2 contains a curing agent, a catalyst, and an inorganic filler for optimizing mechanical strength, linear expansion coefficient, thermal conductivity, and the like. Is preferred.
  • a curing agent for optimizing mechanical strength, linear expansion coefficient, thermal conductivity, and the like. Is preferred.
  • the semiconductor device that has been filled with the resin is transferred to a temperature atmosphere in which the resin can be cured, and after the resin is completely cured, dicing is performed along the individualized dicing line 14 as shown in FIG. A resin-encapsulated semiconductor device 8 is obtained.
  • the dicing width (cutting width) at the time of singulation is made smaller than the width of the groove 7.
  • the resin-encapsulated semiconductor device 8 after singulation has a semiconductor element as shown in FIG. A part of the wiring layer on the mounting side and a part of the core layer 4 are cut out, and a step due to the groove 7 is formed in the outer peripheral portion of the multilayer wiring board 3.
  • the boundary surface between the mold resin 2 and the multilayer wiring board 3 becomes complicated, so that it is possible to prevent moisture from entering from the side surface of the wiring layer and to generate cracks. Can be reduced.
  • the external terminal 13 is provided on the other main surface of the multilayer wiring board 3 that is not connected to the semiconductor element 1.
  • the external terminal 13 is electrically connected to the semiconductor element 1 through wiring inside the multilayer wiring board 3.
  • a BGA Ball Grid Array
  • the material of the external terminals 13 include solder materials such as Sn / Ag / Cu, Sn / Pb, Su / Ag, Su / Cu, Su / Sb, Su / Zn, Su, and Bi.
  • the external terminals 13 are formed on the multilayer wiring board 3 using ball mounting, plating, printing, vapor deposition, or the like.
  • the surface of the external terminal 13 may have a protruding electrode, plating or pre-solder technique, or may be subjected to an organic coating treatment such as OSP.
  • the semiconductor device is connected to an external substrate or the like via the external terminal 13.
  • the groove 7 reaching the core layer 4 is formed in advance along the individualized dicing lines that divide the mounting area on the multilayer wiring board 3, and the semiconductor Resin sealing is performed so as to fill the groove 7 when the element 1 is molded.
  • the entire outer peripheral surface of the wiring layer portion located on the semiconductor element 1 mounting side from the core layer 4 is covered with the mold resin 2.
  • the example in which the groove 7 is formed after the semiconductor element 1 is mounted on the multilayer wiring board 3 has been described.
  • the semiconductor element 1 is formed after the groove 7 is formed in advance before the semiconductor element 1 is mounted.
  • mold resin formation and dicing may be performed.
  • the mold resin can be formed so as to surround the side surface of the wiring layer on the semiconductor element mounting side in the multilayer wiring board 3, and from the outer peripheral surface of the multilayer wiring board 3 to the inside of the semiconductor device. It is possible to suppress the intrusion of moisture and the occurrence of cracks.
  • the groove 7 is formed at a depth reaching the core layer 4 from the surface of the multilayer wiring board 3.
  • the groove 7 may be formed at a depth not reaching the core layer 4.
  • the mold resin 2 can be formed so as to surround at least a part of the side surface of the insulating layer 11 in the outermost layer on the semiconductor element mounting side in the multilayer wiring board 3. It is possible to suppress the intrusion of moisture from the side surface surrounded by the mold resin and the generation of cracks.
  • the groove 7 is formed to a depth reaching the core layer 4 as in this embodiment. More preferably.
  • a multilayer wiring board 3 as shown in FIG. 3 was produced.
  • the core layer 4 of the multilayer wiring board 3 was made of non-alkali glass having a 6-inch size and a thickness of 500 ⁇ m.
  • a multilayer wiring substrate 3 was produced in which a conductor layer 9 mainly composed of 5 ⁇ m Ni / Cu and an insulating layer 11 were laminated on both surfaces of the core layer 4.
  • vacuum lamination was used for the lamination of the insulating layer 11.
  • ABF-GX-T31 manufactured by Ajinomoto Fine Techno Co., Ltd.
  • the thickness of the insulating layer 11 on the conductor layer 9 was 6 ⁇ m.
  • Via processing to the insulating layer 11 was performed using a UV-YAG laser.
  • the conductor layer 9 was formed by sputtering to deposit Cu on the thin film formed by sputtering.
  • the layers between the conductor layers 6 were electrically connected by vias 10.
  • the via 10 was designed to electrically connect a plurality of layers by plating or the like.
  • the total thickness of the multilayer wiring board was about 0.57 mm.
  • the semiconductor element 1 was mounted on the obtained multilayer wiring board (50 ⁇ 50 mm square shape).
  • the semiconductor element electrode 5a is formed by forming a tin silver plating layer on the tip of a Cu post.
  • the semiconductor element electrode 5a may be made of a material such as Au.
  • the semiconductor element electrode 5a arranged in the same area with respect to the substrate electrode 5b arranged in the area was positioned and mounted using a mounting device in a face-down manner.
  • the electrodes 5a and 5b intended for connection are arranged in the area, but the same applies to a peripheral arrangement such as arranged around the side of the semiconductor element 1. The effect of.
  • the multilayer wiring board 3 on which the semiconductor element 1 is mounted is reflowed to complete the bonding.
  • the material of the formed bump 5 include Sn / Ag / Cu, Sn / Pb, Sn / Ag, Su / Cu, Su / Sb, Su / Zn, and Su / Bi.
  • a method of applying pressure with heating or applying vibration by local reflow may be performed. . When joining by local reflow, the reflow of the whole multilayer wiring board 3 is unnecessary.
  • the multilayer wiring substrate 3 was subjected to surface activation treatment with plasma so that the mold resin 2 filled thereafter was uniformly sealed in the gap 12 between the semiconductor element 1 and the multilayer wiring substrate 3.
  • the multilayer wiring board 3 was affixed to a dicing tape, and a groove 7 was formed along the center of the dicing line of each substrate with a NBC-Z series (manufactured by Disco) blade having a blade thickness of 0.3 mm. The depth of the groove was 0.28 mm. The groove 7 was formed so as to reach the glass of the core layer 4. After forming the groove 7, the multilayer wiring board 3 was deaerated in a vacuum oven. Thereafter, the semiconductor device mounting surface side of the multilayer wiring board 3 was collectively sealed with a resin by a low-pressure transfer molding method. In a state where the sealing was completed, the resin was sealed using an oven to form a resin batch sealing type semiconductor device 8.
  • a batch-sealed semiconductor device is affixed to a dicing tape, separated into pieces along a dicing line 14 using a blade having a blade thickness of 0.15 mm, and the outer peripheral portion of the upper surface of the flip chip in FIG. 2 is sealed. Obtained.
  • Test method The semiconductor device according to this example and the conventional semiconductor device in which the groove 7 is not formed are divided into two groups of 10 pieces, stored under JEDEC-Level 3 conditions (temperature 30 ° C./humidity 60% / 192 h), and reflowed after moisture absorption. Went.
  • the peak temperature of the reflow process was 260 ° C./20 sec, and this process was repeated three times.
  • the present invention can be used as a sealing structure between a semiconductor element and a semiconductor device substrate in manufacturing a semiconductor device.

Abstract

Provided is a method for manufacturing a resin-sealed semiconductor device having improved reliability. This semiconductor device manufacturing method is provided with: a step for respectively mounting one or more semiconductor elements on a plurality of semiconductor element mounting regions on a wiring board; a step for forming, before or after mounting the semiconductor elements, grooves in the wiring board, said grooves being formed along dicing lines; and a step for dividing into semiconductor devices by, after the semiconductor elements are mounted, batch-sealing the semiconductor element-mounted surface of the wiring board, the grooves, and the semiconductor elements using a mold resin, then, by performing, along the dicing line, dicing with a cutting width that is smaller than that of the grooves.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、樹脂封止型の半導体装置及びその製造方法に関する。 The present invention relates to a resin-encapsulated semiconductor device and a manufacturing method thereof.
　近年、高度情報化時代を迎え、情報通信技術が急速に発達し、それに伴って各種半導体素子の高密度化が図られている。そのため、半導体装置において、半導体素子を実装するためのインターポーザ基板や、半導体素子を含む電子部品を実装するためのプリント基板を総称するプリント配線板には、高密度化及び高速対応が要求されている。一方、電子機器には、高信頼性を前提に小型化・薄型化・多ピン化、高放熱化が要求されるため、これらをバランスよく併存させることが必要となる。 In recent years, with the advent of advanced information era, information communication technology has been rapidly developed, and accordingly, various semiconductor elements have been increased in density. Therefore, in a semiconductor device, an interposer substrate for mounting a semiconductor element and a printed wiring board that generically refers to a printed circuit board for mounting an electronic component including the semiconductor element are required to have high density and high-speed response. . On the other hand, electronic devices are required to be miniaturized, thinned, multi-pinned, and high heat dissipation on the premise of high reliability.
　従来は、リードフレームに半導体素子を搭載し、樹脂で封止した半導体装置が主流であったが、近年では急速に発展する電子機器の要求から、パッケージの形態が極めて多様化している。パッケージの形態として、例えば、フェイスダウン型や積層型、フリップチップ型、ウェハーレベル型などが挙げられる。 Conventionally, a semiconductor device in which a semiconductor element is mounted on a lead frame and sealed with a resin has been mainstream. However, in recent years, the form of packages has been extremely diversified due to the demand for electronic devices that are rapidly developing. Examples of the package form include a face-down type, a laminated type, a flip chip type, and a wafer level type.
　フリップチップ実装型では、半導体素子の信頼性を向上させるため、まず、半導体素子と配線基板との空隙部（以下、「ギャップ」という）に液状のエポキシ樹脂組成物を用いて充填封止を行い、エポキシ樹脂組成物を硬化させた後で、再度エポキシ樹脂組成物を用いて半導体素子全体について樹脂封止を行うことが一般的である。 In the flip chip mounting type, in order to improve the reliability of the semiconductor element, first, a liquid epoxy resin composition is used to fill and seal the gap between the semiconductor element and the wiring board (hereinafter referred to as “gap”). In general, after the epoxy resin composition is cured, the entire semiconductor element is sealed with the epoxy resin composition again.
　しかしながら、この方法は毛細管現象を利用して半導体素子と配線基板のギャップに液状のエポキシ樹脂組成物を充填することから、充填完了までに非常に長い時間を要するという問題がある。また、ギャップに液状のエポキシ樹脂組成物を充填する工程の後に半導体素子全体をエポキシ樹脂組成物で封止するため、複数の工程が必要となり、生産性が低下するといった問題がある。 However, this method has a problem that it takes a very long time to complete the filling because the liquid epoxy resin composition is filled in the gap between the semiconductor element and the wiring board by utilizing the capillary phenomenon. In addition, since the entire semiconductor element is sealed with the epoxy resin composition after the step of filling the gap with the liquid epoxy resin composition, a plurality of steps are required, and there is a problem that productivity is lowered.
　特許文献１には、上記の問題を解決するために、封止用樹脂組成物に含有される無機質充填材の配合にアプローチすることにより、半導体素子の背面のモールド封止及び配線基板と半導体素子との間隙の双方への同時充填を可能とする半導体装置の製造方法が開示されている。 In Patent Document 1, in order to solve the above problem, by approaching the compounding of the inorganic filler contained in the sealing resin composition, the mold sealing on the back surface of the semiconductor element and the wiring substrate and the semiconductor element are disclosed. A method of manufacturing a semiconductor device that enables simultaneous filling of both gaps is disclosed.
　また、特許文献２には、回路基板内に金属バリア溝を形成することで、回路基板の機械的強度を上げ、外部からの吸湿を防ぐ方法が開示されている。 Also, Patent Document 2 discloses a method of increasing the mechanical strength of a circuit board and preventing moisture absorption from the outside by forming a metal barrier groove in the circuit board.
特開２００８－２１４４２８号公報JP 2008-214428 A 特開２００６－３１３８０２号公報JP 2006-313802 A
　図１は、特許文献１に記載される、従来の樹脂封止型半導体装置の切断部端面図である。 FIG. 1 is an end view of a cut portion of a conventional resin-encapsulated semiconductor device described in Patent Document 1. FIG.
　上記特許文献１の方法を用いて、面付けされた配線基板を分離して個片化すると、図１に示すように、基板の外周が完全に露出する状態となるため、この外周からの半導体装置への水分の浸入やパッケージ基板の界面剥離などが生じるという課題がある。また、特許文献２に記載される方法では、半導体装置基板内に金属バリア溝が形成されるために、外部端子の数や部品のレイアウトに制限が生じてしまうという課題がある。 When the imposing wiring board is separated and separated into pieces by using the method of Patent Document 1, the outer periphery of the substrate is completely exposed as shown in FIG. There is a problem that moisture permeates into the apparatus and interface peeling of the package substrate occurs. Further, the method described in Patent Document 2 has a problem that the number of external terminals and the layout of components are limited because the metal barrier groove is formed in the semiconductor device substrate.
　本発明は、信頼性を向上させた樹脂封止型の半導体装置及びその製造方法を提供することを目的とする。 It is an object of the present invention to provide a resin-encapsulated semiconductor device with improved reliability and a method for manufacturing the same.
　本発明に係る半導体装置の製造方法は、配線基板上の複数の半導体素子実装領域のそれぞれに１個以上の半導体素子を実装する工程と、半導体素子の実装前または実装後に、ダイシングラインに沿って配線基板に溝を形成する工程と、半導体素子の実装後に、配線基板における半導体素子の実装面と、溝と、半導体素子とをモールド樹脂で一括封止した後、ダイシングラインに沿って、溝より狭い裁断幅でダイシングを行うことにより半導体装置を個片化する工程とを備える。 A method of manufacturing a semiconductor device according to the present invention includes a step of mounting one or more semiconductor elements in each of a plurality of semiconductor element mounting regions on a wiring board, and a dicing line before or after mounting the semiconductor elements. After the step of forming a groove in the wiring board and mounting of the semiconductor element, the mounting surface of the semiconductor element on the wiring board, the groove, and the semiconductor element are collectively sealed with mold resin, and then along the dicing line, from the groove And a step of dicing the semiconductor device by dicing with a narrow cutting width.
　また、本発明に係る半導体装置は、コア層と、コア層の少なくとも一方面に設けられ、１層以上の導体層及び１層以上の絶縁層の積層体からなる配線層とを有する配線基板と、配線層上に実装された半導体素子と、配線基板における半導体素子の実装面と、半導体素子とを覆うように形成されたモールド樹脂とを備える。モールド樹脂は、配線基板における実装面側の最表面に設けられた導体層の側面の少なくとも一部を取り囲むように形成される。 In addition, a semiconductor device according to the present invention includes a wiring substrate having a core layer and a wiring layer provided on at least one surface of the core layer and including a laminate of one or more conductor layers and one or more insulating layers. And a semiconductor element mounted on the wiring layer, a mounting surface of the semiconductor element on the wiring board, and a mold resin formed to cover the semiconductor element. The mold resin is formed so as to surround at least a part of the side surface of the conductor layer provided on the outermost surface on the mounting surface side of the wiring board.
　本発明によれば、信頼性を向上させた樹脂封止型の半導体装置及びその製造方法を実現できる。 According to the present invention, a resin-encapsulated semiconductor device with improved reliability and a method for manufacturing the same can be realized.
図１は、従来の樹脂封止型半導体装置の切断部端面図である。FIG. 1 is a cutaway end view of a conventional resin-encapsulated semiconductor device. 図２は、実施形態に係る半導体装置の切断部端面図である。FIG. 2 is a cross-sectional end view of the semiconductor device according to the embodiment. 図３は、実施形態に係る半導体装置の製造方法を説明する図である。FIG. 3 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment. 図４は、実施形態に係る半導体装置の製造方法を説明する図である。FIG. 4 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment. 図５は、実施形態に係る半導体装置の製造方法を説明する図である。FIG. 5 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment. 図６は、実施形態に係る半導体装置の製造方法を説明する図である。FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment.
　以下、本発明の実施形態に係る半導体装置の製造方法を説明する。 Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.
　図２は、実施形態に係る半導体装置の切断部端面図であり、図３～図６は、実施形態に係る半導体装置の製造工程を示す図である。図３～図６に示す半導体装置の製造方法は、１枚の配線基板上に複数の半導体素子を多面付けし、モールド樹脂形成の後に、半導体装置を個片化するものであり、各図では、配線基板のうち、隣接する一対の半導体素子実装領域の境界部分を拡大して示している。 FIG. 2 is an end view of a cut portion of the semiconductor device according to the embodiment, and FIGS. 3 to 6 are diagrams showing manufacturing steps of the semiconductor device according to the embodiment. The semiconductor device manufacturing method shown in FIG. 3 to FIG. 6 is a method in which a plurality of semiconductor elements are provided on a single wiring board and the semiconductor device is separated into pieces after forming a mold resin. In the wiring board, a boundary portion between a pair of adjacent semiconductor element mounting regions is shown enlarged.
Ａ．多層配線基板の作製（図３）
　図３に示すように、本実施形態では、配線基板として、多層配線基板３が用いられる。多層配線基板３には、半導体装置の生産性を向上させるために、複数の半導体素子実装領域がマトリックス状に並べて設けられている。積層方式は、コア層４の両面に導体層９及び絶縁層１１を積層する方式や、支持体などの片側に導体層９及び絶縁層１１を積層し、最終的に支持体から分離する方式のいずれであってもよい。コア層４の材質は、配線層の吸湿に影響を与えないようにするため、絶縁層１１の吸湿率と同程度かそれ以下の材質であることが望まれる。尚、一般的には、コア層４を構成する材質の吸湿率は、０．２％以下が目安である。コア層４としては、例えばガラスを好適に利用でき、特に、ホウ珪酸ガラスをより好適に利用できる。層間の導通を計る目的でスルーホールやビア１０をレーザ加工などによって形成する。絶縁層１１の材質は樹脂、ガラス、ガラスエポキシ、ポリイミド、セラミック、金属などの材料が挙げられるがこれに限定されるものではない。導体層９の材質は、回路形成が可能な導体性のある金属であり、例えば、Ｃｕ、Ａｌ、Ｎｉ、Ａｕなどが挙げられるがこれに限定されるものではない。導体層９は、電気めっきや化学的なめっき方法により形成される。導体層９の厚さは例えば、１～２０μｍであり、回路形成は、例えば、フォトリソグラフィーなどの手法がとられる。 A. Fabrication of multilayer wiring board (Figure 3)
As shown in FIG. 3, in the present embodiment, a multilayer wiring board 3 is used as the wiring board. The multilayer wiring board 3 is provided with a plurality of semiconductor element mounting regions arranged in a matrix in order to improve the productivity of the semiconductor device. The lamination method is a method of laminating the conductor layer 9 and the insulating layer 11 on both surfaces of the core layer 4 or a method of laminating the conductor layer 9 and the insulating layer 11 on one side of the support and the like and finally separating from the support. Either may be sufficient. The material of the core layer 4 is desirably the same as or lower than the moisture absorption rate of the insulating layer 11 so as not to affect the moisture absorption of the wiring layer. In general, the moisture absorption rate of the material constituting the core layer 4 is generally 0.2% or less. As the core layer 4, for example, glass can be preferably used, and in particular, borosilicate glass can be more preferably used. Through holes and vias 10 are formed by laser processing or the like for the purpose of measuring conduction between layers. Examples of the material for the insulating layer 11 include, but are not limited to, materials such as resin, glass, glass epoxy, polyimide, ceramic, and metal. The material of the conductor layer 9 is a conductive metal capable of forming a circuit, and examples thereof include Cu, Al, Ni, and Au, but are not limited thereto. The conductor layer 9 is formed by electroplating or a chemical plating method. The thickness of the conductor layer 9 is, for example, 1 to 20 μm, and the circuit is formed by, for example, a technique such as photolithography.
Ｂ．半導体素子の搭載（図４）
　図３に示すように、多層配線基板３上の半導体素子実装領域のそれぞれに半導体素子１を配置し、多層配線基板３の基板電極５ｂに対して半導体素子電極５ａをフェイスダウン方式で搭載し、フリップチップ実装部（以下、「実装部」という）を形成する。 B. Mounting of semiconductor elements (Fig. 4)
As shown in FIG. 3, the semiconductor element 1 is disposed in each of the semiconductor element mounting regions on the multilayer wiring board 3, and the semiconductor element electrode 5a is mounted on the substrate electrode 5b of the multilayer wiring board 3 in a face-down manner. A flip chip mounting portion (hereinafter referred to as “mounting portion”) is formed.
　次に、図４に示すように、多層配線基板３上の実装部をリフローにかけバンプ５を形成する。基板電極５ｂは、Ｓｎ／Ａｇ／Ｃｕ、Ｓｎ／Ｐｂ、Ｓｎ／Ａｇ、Ｓｕ／Ｃｕ、Ｓｕ／Ｓｂ、Ｓｕ／Ｚｎ、Ｓｕ／Ｂｉなどが挙げられるが、これに限定されるものではない。基板電極５ｂの形状は、突起電極であってもよく、表面にめっきやプレソルダーの処理が施されていてもよく、ＯＳＰなどの有機被膜処理が施されていてもよい。また、半導体素子電極５ａと基板電極５ｂを短時間で接続するために、ローカルリフローで加熱とともに加圧したり、振動を与えたりしてもよい。また、半導体素子電極５ａ及び基板電極５ｂは、それぞれ半導体素子１上及び多層配線基板３上の対応する領域にエリア配置されるのではなく、それぞれ半導体素子１の周辺部四辺及び多層配線基板３上の対応する領域にペリフェラル配置されてもよい。 Next, as shown in FIG. 4, the mounting portion on the multilayer wiring board 3 is reflowed to form bumps 5. Examples of the substrate electrode 5b include Sn / Ag / Cu, Sn / Pb, Sn / Ag, Su / Cu, Su / Sb, Su / Zn, and Su / Bi, but are not limited thereto. The shape of the substrate electrode 5b may be a protruding electrode, the surface may be subjected to plating or pre-solder treatment, or may be subjected to organic coating treatment such as OSP. Further, in order to connect the semiconductor element electrode 5a and the substrate electrode 5b in a short time, pressurization with heating or vibration may be applied by local reflow. Further, the semiconductor element electrode 5a and the substrate electrode 5b are not arranged in corresponding areas on the semiconductor element 1 and the multilayer wiring board 3, respectively, but on the peripheral four sides of the semiconductor element 1 and on the multilayer wiring board 3, respectively. Peripherals may be arranged in the corresponding regions.
　次に、実装部のギャップ１２の洗浄を行う。これは、フラックス残留成分の除去を目的とするものである。したがって、洗浄不要のフラックスを使用する場合、またはフラックスを使用しない場合などは、必ずしもギャップ１２を洗浄する必要はない。 Next, the gap 12 of the mounting part is cleaned. This is intended to remove flux residual components. Therefore, it is not always necessary to clean the gap 12 when a flux that does not require cleaning is used or when a flux is not used.
Ｃ．受動部品の搭載
　また、本発明に係る半導体装置においては、多層配線基板３上に受動部品を搭載してもよい。この場合、多層配線基板３上の電極にめっき、印刷法や蒸着法などを用いて、受動素子電極６を形成しておく（図２参照）。形成された受動素子電極６の上に部品搭載装置を用いて、積層セラミックコンデンサなどを搭載してもよい。受動部品の種類、大きさ、電極の数は、限定されない。また、受動素子電極６の材質は、はんだを主材とすることが望ましく、例えば、Ｓｎ／Ａｇ／Ｃｕ、Ｓｎ／Ｐｂ、Ｓｕ／Ａｇ、Ｓｕ／Ｃｕ、Ｓｕ／Ｓｂ、Ｓｕ／Ｚｎ、Ｓｕ、Ｂｉなどが挙げられるがこれに限定されるものではない。受動素子電極６の形状は、突起電極であってもよく、表面にめっきやプレソルダーの処理が施されていてもよく、ＯＳＰなどの有機被膜処理が施されていてもよい。受動素子電極６と受動部品との接合はリフローにより行ってもよい。 C. Mounting Passive Components In the semiconductor device according to the present invention, passive components may be mounted on the multilayer wiring board 3. In this case, the passive element electrode 6 is formed on the electrode on the multilayer wiring board 3 by using plating, printing, vapor deposition or the like (see FIG. 2). A multilayer ceramic capacitor or the like may be mounted on the formed passive element electrode 6 using a component mounting device. The type, size, and number of electrodes of the passive component are not limited. The material of the passive element electrode 6 is preferably composed mainly of solder, for example, Sn / Ag / Cu, Sn / Pb, Su / Ag, Su / Cu, Su / Sb, Su / Zn, Su, Examples include Bi, but are not limited thereto. The shape of the passive element electrode 6 may be a protruding electrode, the surface may be subjected to plating or pre-solder treatment, or may be subjected to organic coating treatment such as OSP. The passive element electrode 6 and the passive component may be joined by reflow.
Ｄ．樹脂組成物の充填
　本発明に係る半導体装置においては、必要に応じてモールド工程の前に樹脂組成物の充填を行ってもよい。使用する樹脂組成物は、液状エポキシ樹脂組成物系が主流であるが、フェノール樹脂、ポリイミド樹脂、シリコーン樹脂系の樹脂などを用いてもよい。 D. Filling of Resin Composition In the semiconductor device according to the present invention, the resin composition may be filled before the molding step as necessary. The resin composition used is mainly a liquid epoxy resin composition system, but a phenol resin, a polyimide resin, a silicone resin resin, or the like may be used.
　実装部を形成した多層配線基板３を加熱したディスペンサステージに配置し、液状エポキシ樹脂組成物の流動性を高めるため昇温する。昇温温度については、使用される樹脂組成物の性能がもっとも発揮される推奨条件を選択してよい。次に、液状エポキシ樹脂組成物をフリップチップ実装部の任意の一辺に塗布し、充填の完了までステージ上に放置する。その後、樹脂充填が完了したフリップチップ実装部を樹脂硬化が可能な温度雰囲気に移して、樹脂を完全に硬化させることにより、アンダーフィルが形成される。使用する樹脂組成物によって、硬化時間及び硬化温度は最適な条件を採用する。 The multilayer wiring board 3 on which the mounting portion is formed is placed on a heated dispenser stage, and the temperature is raised to enhance the fluidity of the liquid epoxy resin composition. About the temperature rising temperature, you may select the recommended conditions where the performance of the resin composition to be used is exhibited most. Next, the liquid epoxy resin composition is applied to any one side of the flip chip mounting part and left on the stage until filling is completed. Thereafter, the flip-chip mounting portion where the resin filling is completed is moved to a temperature atmosphere in which the resin can be cured, and the resin is completely cured, thereby forming an underfill. Depending on the resin composition used, optimum conditions are adopted for the curing time and the curing temperature.
Ｅ．溝の作製（図５）
　半導体素子１が搭載された多層配線基板３にダイシングテープ（図示せず）を貼り付け、図５に示すように、個片化ダイシングライン１４の中心に沿って多層配線基板３に溝７を形成する。溝７の形成工程は、半導体素子１を搭載する前であっても問題ない。溝７の形成については、ブレードダイシングによる方法やレーザーダイシング、または、その両方を組み合わせてもよい。溝７の形成方法はこれに限られるものではない。また、多層配線基板３上に形成される溝７の幅は、個片化時のダイシング幅（裁断幅）より大きくする。また、溝７の深さは、コア層４に到達する十分な深さであることが好ましい。溝７を形成した後、多層配線基板３を真空オーブンで脱気する。 E. Groove fabrication (Figure 5)
A dicing tape (not shown) is attached to the multilayer wiring board 3 on which the semiconductor element 1 is mounted, and a groove 7 is formed in the multilayer wiring board 3 along the center of the individualized dicing line 14 as shown in FIG. To do. There is no problem in the step of forming the groove 7 even before the semiconductor element 1 is mounted. For the formation of the groove 7, a method by blade dicing, laser dicing, or a combination of both may be used. The method for forming the groove 7 is not limited to this. Further, the width of the groove 7 formed on the multilayer wiring board 3 is made larger than the dicing width (cutting width) at the time of separation. Further, the depth of the groove 7 is preferably a sufficient depth to reach the core layer 4. After forming the groove 7, the multilayer wiring board 3 is deaerated in a vacuum oven.
Ｆ．モールド工程について（図６）
　多層配線基板３における半導体素子実装側の面と、半導体素子１の外面全体と、半導体素子１と多層配線基板３とのギャップ１２と、多層配線基板３上に形成された溝７とを、低圧トランスファ成形法により、一括で樹脂封止する。これにより、半導体素子搭載面がコア層４とモールド樹脂２によって閉鎖される構造が出来上がる。封止するモールド樹脂２として、エポキシ樹脂組成物、ポリウレタン樹脂、シリコーン樹脂、ポリエステル樹脂、オキセタン樹脂、マレイミド樹脂のいずれかの樹脂、またはこれらの樹脂の２種類以上が混合された樹脂にフィラーとしてシリカ、酸化チタン、酸化アルミニウム、酸化マグネシウム、または酸化亜鉛などを加えた材料が用いられる。また、モールド樹脂２は、基本成分となる樹脂のほかに、硬化剤、触媒、さらには機械的強度、線膨張係数、熱伝導率などを最適化するための無機充填材が配合されていることが好ましい。これにより、半導体装置をＰＷＢ（Ｐｒｉｎｔｅｄ　Ｗｉｒｉｎｇ　Ｂｏａｒｄ）などに２次実装する際の熱によって発生する材料間の応力が緩和され、基板内への水分の浸入の防止や半導体素子１をストレスから保護する効果が得られる。 F. About the molding process (Figure 6)
The surface of the multilayer wiring board 3 on the semiconductor element mounting side, the entire outer surface of the semiconductor element 1, the gap 12 between the semiconductor element 1 and the multilayer wiring board 3, and the groove 7 formed on the multilayer wiring board 3 are Resin sealing is performed at once by transfer molding. Thereby, a structure in which the semiconductor element mounting surface is closed by the core layer 4 and the mold resin 2 is completed. As mold resin 2 to be sealed, epoxy resin composition, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, or a mixture of two or more of these resins with silica as filler In addition, a material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used. In addition to the basic resin, the mold resin 2 contains a curing agent, a catalyst, and an inorganic filler for optimizing mechanical strength, linear expansion coefficient, thermal conductivity, and the like. Is preferred. As a result, stress between materials generated by heat when the semiconductor device is secondarily mounted on a PWB (Printed Wiring Board) or the like is relieved to prevent moisture from entering the substrate and protect the semiconductor element 1 from stress. An effect is obtained.
　最後に、樹脂の充填が完了した半導体装置を樹脂硬化可能な温度雰囲気に移して、樹脂を完全に硬化させた後、個片化ダイシングライン１４に沿ってダイシングを行うことにより、図２に示した樹脂封止型半導体装置８を得る。上述したように、個片化時のダイシング幅（裁断幅）は、溝７の幅より小さくする。 Finally, the semiconductor device that has been filled with the resin is transferred to a temperature atmosphere in which the resin can be cured, and after the resin is completely cured, dicing is performed along the individualized dicing line 14 as shown in FIG. A resin-encapsulated semiconductor device 8 is obtained. As described above, the dicing width (cutting width) at the time of singulation is made smaller than the width of the groove 7.
　モールド樹脂２の形成前に予め個片化時のダイシング幅より幅広の溝７を形成することによって、個片化後の樹脂封止型半導体装置８においては、図２に示すように、半導体素子実装側の配線層の一部とコア層４の一部とが切り欠かれた状態となり、多層配線基板３の外周部に溝７に由来する段差が形成される。この段差をモールド樹脂２で埋め込むことによって、モールド樹脂２と多層配線基板３との境界面が複雑化するため、配線層の側面からの水分の侵入を防ぐことが可能となると共に、クラックの発生を低減できる。 By forming grooves 7 wider than the dicing width at the time of singulation before forming the mold resin 2, the resin-encapsulated semiconductor device 8 after singulation has a semiconductor element as shown in FIG. A part of the wiring layer on the mounting side and a part of the core layer 4 are cut out, and a step due to the groove 7 is formed in the outer peripheral portion of the multilayer wiring board 3. By embedding this step with the mold resin 2, the boundary surface between the mold resin 2 and the multilayer wiring board 3 becomes complicated, so that it is possible to prevent moisture from entering from the side surface of the wiring layer and to generate cracks. Can be reduced.
Ｇ．外部端子について
　外部端子１３は、多層配線基板３の半導体素子１を接続していない他方の主面に設けられる。外部端子１３は、多層配線基板３内部の配線を介して、半導体素子１と電気的に接続されている。外部端子１３としては、はんだ材料からなるボール形状の端子をグリッド状に配列したＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）が多く用いられる。外部端子１３の材質は、Ｓｎ／Ａｇ／Ｃｕ、Ｓｎ／Ｐｂ、Ｓｕ／Ａｇ、Ｓｕ／Ｃｕ、Ｓｕ／Ｓｂ、Ｓｕ／Ｚｎ、Ｓｕ、Ｂｉなどのはんだ材料などが挙げられる。外部端子１３は、多層配線基板３上にボール搭載、めっき、印刷法や蒸着法などを用いて形成される。外部端子１３の表面は、突起電極、めっきやプレソルダーの手法がとられていてもよく、ＯＳＰなどの有機被膜処理が施されていてもよい。この外部端子１３を介して、半導体装置は外部の基板などに接続される。 G. External Terminal The external terminal 13 is provided on the other main surface of the multilayer wiring board 3 that is not connected to the semiconductor element 1. The external terminal 13 is electrically connected to the semiconductor element 1 through wiring inside the multilayer wiring board 3. As the external terminal 13, a BGA (Ball Grid Array) in which ball-shaped terminals made of a solder material are arranged in a grid is often used. Examples of the material of the external terminals 13 include solder materials such as Sn / Ag / Cu, Sn / Pb, Su / Ag, Su / Cu, Su / Sb, Su / Zn, Su, and Bi. The external terminals 13 are formed on the multilayer wiring board 3 using ball mounting, plating, printing, vapor deposition, or the like. The surface of the external terminal 13 may have a protruding electrode, plating or pre-solder technique, or may be subjected to an organic coating treatment such as OSP. The semiconductor device is connected to an external substrate or the like via the external terminal 13.
　以上説明したように、本実施形態に係る半導体装置の製造方法では、多層配線基板３上の実装領域を区画する個片化ダイシングラインに沿ってコア層４に達する溝７を予め形成し、半導体素子１のモールディング時に溝７を埋め込むように樹脂封止する。これにより、コア層４より半導体素子１搭載側に位置する配線層部分の外周面全体がモールド樹脂２によって覆われる。この結果、多層配線基板３の外周面から半導体装置内部への水分の侵入を抑制できると共に、クラック等が発生することを抑制できる。したがって、本発明によれば、生産性を低下させることなく、信頼性の高い半導体装置の製造方法を実現できる。 As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the groove 7 reaching the core layer 4 is formed in advance along the individualized dicing lines that divide the mounting area on the multilayer wiring board 3, and the semiconductor Resin sealing is performed so as to fill the groove 7 when the element 1 is molded. As a result, the entire outer peripheral surface of the wiring layer portion located on the semiconductor element 1 mounting side from the core layer 4 is covered with the mold resin 2. As a result, it is possible to suppress the intrusion of moisture from the outer peripheral surface of the multilayer wiring board 3 into the semiconductor device and to suppress the occurrence of cracks and the like. Therefore, according to the present invention, a highly reliable manufacturing method of a semiconductor device can be realized without reducing productivity.
　尚、本実施形態では、多層配線基板３に半導体素子１を実装した後に、溝７を形成する例を説明したが、半導体素子１の実装前に予め溝７を形成してから半導体素子１を実装し、その後、モールド樹脂形成及びダイシングを行ってもよい。この場合でも、本実施形態と同様に、多層配線基板３における半導体素子実装側の配線層の側面を取り囲むようにモールド樹脂を形成することができ、多層配線基板３の外周面から半導体装置内部への水分の侵入と、クラックの発生とを抑制することが可能となる。 In this embodiment, the example in which the groove 7 is formed after the semiconductor element 1 is mounted on the multilayer wiring board 3 has been described. However, the semiconductor element 1 is formed after the groove 7 is formed in advance before the semiconductor element 1 is mounted. After mounting, mold resin formation and dicing may be performed. Even in this case, as in the present embodiment, the mold resin can be formed so as to surround the side surface of the wiring layer on the semiconductor element mounting side in the multilayer wiring board 3, and from the outer peripheral surface of the multilayer wiring board 3 to the inside of the semiconductor device. It is possible to suppress the intrusion of moisture and the occurrence of cracks.
　また、本実施形態では、多層配線基板３の表面からコア層４に達する深さに溝７を形成する例を説明したが、コア層４に達しない深さに溝７を形成してもよい。この場合でも、モールド樹脂２で溝７を埋め込むことによって、多層配線基板３における半導体素子実装側の最表層にある絶縁層１１の側面の少なくとも一部を取り囲むようにモールド樹脂２を形成することができ、モールド樹脂で囲まれた側面部分からの水分の浸入と、クラックの発生とを抑制することができる。ただし、半導体素子実装側の配線層の側面からの水分の侵入とクラックの発生とをより効果的に抑制するため、本実施形態のように、コア層４に達する深さにまで溝７を形成することがより好ましい。 In the present embodiment, the groove 7 is formed at a depth reaching the core layer 4 from the surface of the multilayer wiring board 3. However, the groove 7 may be formed at a depth not reaching the core layer 4. . Even in this case, by embedding the groove 7 with the mold resin 2, the mold resin 2 can be formed so as to surround at least a part of the side surface of the insulating layer 11 in the outermost layer on the semiconductor element mounting side in the multilayer wiring board 3. It is possible to suppress the intrusion of moisture from the side surface surrounded by the mold resin and the generation of cracks. However, in order to more effectively suppress the intrusion of moisture from the side surface of the wiring layer on the semiconductor element mounting side and the generation of cracks, the groove 7 is formed to a depth reaching the core layer 4 as in this embodiment. More preferably.
　以下、本発明のより詳細な実施例を説明するが、本発明はこの実施例に限定されるものではない。 Hereinafter, more detailed examples of the present invention will be described, but the present invention is not limited to these examples.
　まず、図３に示されるような多層配線基板３を作製した。多層配線基板３のコア層４には、６インチサイズ、厚さ５００μｍの無アルカリガラスを用いた。コア層４の両面それぞれに、５μｍのＮｉ／Ｃｕを主とする導体層９と、絶縁層１１とを３層ずつ積層した多層配線基板３を作製した。絶縁層１１の積層は、真空ラミネートを用いた。絶縁層を形成する絶縁樹脂には、ＡＢＦ－ＧＸ－Ｔ３１（味の素ファインテクノ株式会社製）を用いた。絶縁層１１の導体層９上の厚さは６μｍとした。絶縁層１１へのビア加工は、ＵＶ－ＹＡＧレーザを用いて行った。導体層９はスパッタにて薄膜形成されたものに電解めっきなどでＣｕを析出させる方法をとった。それぞれの導体層６の層間は、ビア１０で電気的に接続した。ビア１０は、めっきなどによって、複数層間を電気的に接続するように設計した。多層配線基板の総厚は０．５７ｍｍ程度となった。 First, a multilayer wiring board 3 as shown in FIG. 3 was produced. The core layer 4 of the multilayer wiring board 3 was made of non-alkali glass having a 6-inch size and a thickness of 500 μm. A multilayer wiring substrate 3 was produced in which a conductor layer 9 mainly composed of 5 μm Ni / Cu and an insulating layer 11 were laminated on both surfaces of the core layer 4. For the lamination of the insulating layer 11, vacuum lamination was used. ABF-GX-T31 (manufactured by Ajinomoto Fine Techno Co., Ltd.) was used as the insulating resin for forming the insulating layer. The thickness of the insulating layer 11 on the conductor layer 9 was 6 μm. Via processing to the insulating layer 11 was performed using a UV-YAG laser. The conductor layer 9 was formed by sputtering to deposit Cu on the thin film formed by sputtering. The layers between the conductor layers 6 were electrically connected by vias 10. The via 10 was designed to electrically connect a plurality of layers by plating or the like. The total thickness of the multilayer wiring board was about 0.57 mm.
　次に、得られた多層配線基板（５０×５０ｍｍの正方形状）に半導体素子１を搭載した。半導体素子１には、２０×２０ｍｍの正方形状のものを用いた。半導体素子電極５ａは、Ｃｕポストの先端に錫銀めっき層を形成したものからなる。また、半導体素子電極５ａは、Ａｕなどの材質でもよい。エリア配置された基板電極５ｂに対して同一のエリア配置された半導体素子電極５ａをフェイスダウン方式で搭載装置を使用して位置決め搭載した。尚、発明の実施の形態では、接続を目的とした電極５ａ、５ｂがエリア配置されているものとしたが、半導体素子１の辺の周辺に配置されているようなペリフェラル配置をとるものでも同様の効果を得られる。 Next, the semiconductor element 1 was mounted on the obtained multilayer wiring board (50 × 50 mm square shape). As the semiconductor element 1, a square shape of 20 × 20 mm was used. The semiconductor element electrode 5a is formed by forming a tin silver plating layer on the tip of a Cu post. The semiconductor element electrode 5a may be made of a material such as Au. The semiconductor element electrode 5a arranged in the same area with respect to the substrate electrode 5b arranged in the area was positioned and mounted using a mounting device in a face-down manner. In the embodiment of the present invention, the electrodes 5a and 5b intended for connection are arranged in the area, but the same applies to a peripheral arrangement such as arranged around the side of the semiconductor element 1. The effect of.
　半導体素子１を搭載した多層配線基板３をリフローにかけ接合を完了する。形成されたバンプ５の材質の例としては、Ｓｎ／Ａｇ／Ｃｕ、Ｓｎ／Ｐｂ、Ｓｎ／Ａｇ、Ｓｕ／Ｃｕ、Ｓｕ／Ｓｂ、Ｓｕ／Ｚｎ、Ｓｕ／Ｂｉなどが挙げられる。尚、任意でバンプ５が形成された半導体素子１と多層配線基板３を短時間で接続するために、ローカルリフローで加熱と共に加圧を行ったり、振動を加えたりする方法を実施してもよい。ローカルリフローで接合する場合は、多層配線基板３全体のリフローは不要である。 The multilayer wiring board 3 on which the semiconductor element 1 is mounted is reflowed to complete the bonding. Examples of the material of the formed bump 5 include Sn / Ag / Cu, Sn / Pb, Sn / Ag, Su / Cu, Su / Sb, Su / Zn, and Su / Bi. In addition, in order to connect the semiconductor element 1 on which the bumps 5 are arbitrarily formed and the multilayer wiring board 3 in a short time, a method of applying pressure with heating or applying vibration by local reflow may be performed. . When joining by local reflow, the reflow of the whole multilayer wiring board 3 is unnecessary.
　多層配線基板３には、その後充填されるモールド樹脂２が均一に半導体素子１と多層配線基板３との間のギャップ１２に均一に封止されるよう、プラズマによる表面活性処理を行った。 The multilayer wiring substrate 3 was subjected to surface activation treatment with plasma so that the mold resin 2 filled thereafter was uniformly sealed in the gap 12 between the semiconductor element 1 and the multilayer wiring substrate 3.
（溝の作製）
　ダイシングテープに多層配線基板３を貼り付け、ＮＢＣ－Ｚシリーズ（ディスコ社製）ブレード厚み０．３ｍｍのブレードで個々の基板のダイシングラインの中心に沿って溝７を形成した。溝の深さは、０．２８ｍｍとした。溝７は、コア層４のガラスに到達するように形成した。溝７を形成した後、多層配線基板３を真空オーブンで脱気した。その後、多層配線基板３の半導体装置搭載面側を低圧トランスファーモールド法にて樹脂で一括封止した。封止が完了した状態でオーブンを用いて硬化させ樹脂一括封止型半導体装置８を形成した。 (Fabrication)
The multilayer wiring board 3 was affixed to a dicing tape, and a groove 7 was formed along the center of the dicing line of each substrate with a NBC-Z series (manufactured by Disco) blade having a blade thickness of 0.3 mm. The depth of the groove was 0.28 mm. The groove 7 was formed so as to reach the glass of the core layer 4. After forming the groove 7, the multilayer wiring board 3 was deaerated in a vacuum oven. Thereafter, the semiconductor device mounting surface side of the multilayer wiring board 3 was collectively sealed with a resin by a low-pressure transfer molding method. In a state where the sealing was completed, the resin was sealed using an oven to form a resin batch sealing type semiconductor device 8.
（ダイシングによる個片化）
　一括封止型半導体装置をダイシングテープに貼り付け、ブレード厚み０．１５ｍｍのブレードを用いてダイシングライン１４にそって個片化し、図２のフリップチップ上面の外周部が封止された半導体装置を得た。 (Individualization by dicing)
A batch-sealed semiconductor device is affixed to a dicing tape, separated into pieces along a dicing line 14 using a blade having a blade thickness of 0.15 mm, and the outer peripheral portion of the upper surface of the flip chip in FIG. 2 is sealed. Obtained.
（試験方法）
　本実施例に係る半導体装置と、溝７を形成しない従来の半導体装置を１０個ずつ２群に分け、ＪＥＤＥＣ－Ｌｅｖｅｌ３の条件（温度３０℃／湿度６０％／１９２ｈ）で保存し、吸湿後にリフローを行った。リフロー処理のピーク温度は２６０℃／２０ｓｅｃとし、この処理を３回繰り返した。 (Test method)
The semiconductor device according to this example and the conventional semiconductor device in which the groove 7 is not formed are divided into two groups of 10 pieces, stored under JEDEC-Level 3 conditions (temperature 30 ° C./humidity 60% / 192 h), and reflowed after moisture absorption. Went. The peak temperature of the reflow process was 260 ° C./20 sec, and this process was repeated three times.
（試験結果）
　結果、本発明の半導体装置において導通不良は０／１０個、従来の半導体装置では、３／１０個の不良が発生した。 (Test results)
As a result, 0/10 defects in conduction occurred in the semiconductor device of the present invention, and 3/10 defects occurred in the conventional semiconductor device.
（故障解析）
　故障サンプルの断面研磨を実施したところ、バンプクラック及び半導体素子とバンプとの界面での剥離が生じていることが観察された。 (Failure analysis)
When the cross section of the failed sample was polished, it was observed that bump cracks and peeling at the interface between the semiconductor element and the bump occurred.
　よって、半導体装置搭載面側の外周部に溝を設け複雑化することによって、水分の浸入を抑制できることが確認された。 Therefore, it was confirmed that the intrusion of moisture can be suppressed by providing a groove in the outer peripheral portion on the semiconductor device mounting surface side and making it complicated.
　本発明は、半導体装置を製造するにあたり、半導体素子と半導体装置基板の封止構造として利用可能である。 The present invention can be used as a sealing structure between a semiconductor element and a semiconductor device substrate in manufacturing a semiconductor device.
１　　半導体素子
２　　モールド樹脂
３　　多層配線基板
４　　コア層
５　　バンプ
５ａ　半導体素子電極
５ｂ　基板電極
６　　受動素子電極
７　　溝
８　　樹脂封止型半導体装置
９　　導体層
１０　ビア
１１　絶縁層
１２　ギャップ
１３　外部端子
１４　個片化ダイシングライン DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Mold resin 3 Multilayer wiring board 4 Core layer 5 Bump 5a Semiconductor element electrode 5b Substrate electrode 6 Passive element electrode 7 Groove 8 Resin sealing type semiconductor device 9 Conductor layer 10 Via 11 Insulating layer 12 Gap 13 External terminal 14 pieces One-sided dicing line

Claims (5)

  1. 　半導体装置の製造方法であって、
    　配線基板上の複数の半導体素子実装領域のそれぞれに１個以上の半導体素子を実装する工程と、
    　前記半導体素子の実装前または実装後に、ダイシングラインに沿って前記配線基板に溝を形成する工程と、
    　前記半導体素子の実装後に、前記配線基板における前記半導体素子の実装面と、前記溝と、前記半導体素子とをモールド樹脂で一括封止した後、前記ダイシングラインに沿って、前記溝より狭い裁断幅でダイシングを行うことにより前記半導体装置を個片化する工程とを備える、半導体装置の製造方法。     A method for manufacturing a semiconductor device, comprising:
    Mounting one or more semiconductor elements in each of a plurality of semiconductor element mounting regions on the wiring board;
    Forming a groove in the wiring board along a dicing line before or after mounting the semiconductor element;
    After the semiconductor element is mounted, the semiconductor element mounting surface, the groove, and the semiconductor element on the wiring board are collectively sealed with a mold resin, and then the cutting width is narrower than the groove along the dicing line. And a step of dicing the semiconductor device into individual pieces.
  2. 　前記配線基板は、コア層と、前記コア層の少なくとも一方面に設けられ、１層以上の導体層及び１層以上の絶縁層の積層体からなる配線層とを有し、
    　前記配線基板に溝を形成する工程において、前記配線基板の表面から前記コア層にまで達する深さで前記溝を形成することを特徴とする、請求項１に記載の半導体装置の製造方法。     The wiring board includes a core layer and a wiring layer provided on at least one surface of the core layer and including a laminate of one or more conductor layers and one or more insulating layers,
    2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming a groove in the wiring substrate, the groove is formed to a depth reaching from the surface of the wiring substrate to the core layer.
  3. 　前記コア層を構成する材料の吸湿率が、前記絶縁層の吸湿率以下であることを特徴とする、請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2, wherein a moisture absorption rate of a material constituting the core layer is equal to or less than a moisture absorption rate of the insulating layer.
  4. 　半導体装置であって、
    　コア層と、前記コア層の少なくとも一方面に設けられ、１層以上の導体層及び１層以上の絶縁層の積層体からなる配線層とを有する配線基板と、
    　前記配線層上に実装された半導体素子と、
    　前記配線基板における前記半導体素子の実装面と、前記半導体素子とを覆うように形成されたモールド樹脂とを備え、
    　前記モールド樹脂は、前記配線基板における前記実装面側の最表面に設けられた前記導体層の側面の少なくとも一部を取り囲むように形成される、半導体装置。     A semiconductor device,
    A wiring board having a core layer and a wiring layer provided on at least one surface of the core layer and including a laminate of one or more conductor layers and one or more insulating layers;
    A semiconductor element mounted on the wiring layer;
    A mounting surface of the semiconductor element on the wiring board, and a mold resin formed to cover the semiconductor element,
    The mold resin is formed so as to surround at least a part of a side surface of the conductor layer provided on the outermost surface of the wiring board on the mounting surface side.
  5. 　前記モールド樹脂は、前記実装面側の前記配線層の側面全体と、前記コア層の前記実装面側の一部の側面とを取り囲むように形成される、請求項４に記載の半導体装置。 5. The semiconductor device according to claim 4, wherein the mold resin is formed so as to surround the entire side surface of the wiring layer on the mounting surface side and a part of the side surface of the core layer on the mounting surface side.
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