JP2014093406A - Wiring board with through electrode and manufacturing method of the same - Google Patents

Wiring board with through electrode and manufacturing method of the same Download PDF

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JP2014093406A
JP2014093406A JP2012242727A JP2012242727A JP2014093406A JP 2014093406 A JP2014093406 A JP 2014093406A JP 2012242727 A JP2012242727 A JP 2012242727A JP 2012242727 A JP2012242727 A JP 2012242727A JP 2014093406 A JP2014093406 A JP 2014093406A
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wiring board
electrode
hole
wiring
metal layer
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JP6056386B2 (en
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Tomohiro Yoshida
智洋 吉田
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Toppan Inc
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Toppan Printing Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To form a fine through electrode which is excellent in heat dissipation by using a glass base material.SOLUTION: A wiring board with a through electrode is constituted by using a glass base material mainly composed of SiO, comprises: a plurality of through holes 11 formed in the glass base material; a metal layer 13 with predetermined thickness formed on the surface of the glass base material 12 including the through holes; an insulation layer 14 formed on the surface of the metal layer and having predetermined thickness for preventing leak current from a through electrode 15; and the through electrode 15 consisting of a conductive material formed at parts of the through holes 11, is excellent in heat dissipation since the through holes 11 with comparatively large diameters can be formed in the glass base material 12, and the wiring board includes the metal layer 13 with excellent thermal conductivity and a fine through electrode can be attached to the wiring board by adjusting the thickness of the metal layer 13.

Description

本発明は、ガラス基材に貫通電極を設けたインターポーザとして使用可能な貫通電極付き配線基板及びその製造方法に関する。   The present invention relates to a wiring substrate with a through electrode that can be used as an interposer in which a through electrode is provided on a glass substrate, and a method for manufacturing the wiring substrate.

ウェハープロセス技術を用いて製造される各種のメモリー、CMOS(Complementary Metal Oxide Semiconductor;相補型金属酸化膜半導体)、CPU(Central Processing Unit;中央演算処理装置)等の半導体素子は、電気的接続用の端子を有している。   Semiconductor devices such as various memories manufactured using wafer process technology, CMOS (Complementary Metal Oxide Semiconductor), and CPU (Central Processing Unit) are used for electrical connection. It has a terminal.

この半導体素子の接続用端子のピッチと、半導体素子と電気的な接続を行うためのプリント配線基板側接続部のピッチとは、通常数倍から数十倍程度スケールが異なる。そのため、半導体素子とプリント配線基板とを電気的に接続しようとする場合、インターポーザと称するピッチ変換のための中継用基板(半導体素子実装用基板)が使用される。このインターポーザの一方の面には半導体素子を実装し、他方の面もしくは基板の周辺部でプリント配線基板との接続がとられる。   The pitch of the connection terminals of the semiconductor element and the pitch of the printed wiring board side connection portion for electrical connection with the semiconductor element usually differ in scale by several to several tens of times. Therefore, when electrically connecting a semiconductor element and a printed wiring board, a relay substrate (semiconductor element mounting substrate) for pitch conversion called an interposer is used. A semiconductor element is mounted on one surface of the interposer and connected to the printed wiring board on the other surface or the peripheral portion of the substrate.

プリント配線基板に半導体素子を実装するためのインターポーザとしては、従来の有機基板や有機ビルドアップ基板の他、近年はハイエンド向けのインターポーザとして、基板の材質にシリコンやガラスを用いたインターポーザの研究が活発に行われるようになり、大きな注目が集まっている。   As an interposer for mounting semiconductor elements on printed wiring boards, in addition to conventional organic substrates and organic buildup substrates, research on interposers using silicon or glass as the substrate material has recently been active as a high-end interposer. Has attracted a great deal of attention.

基材としてシリコンやガラスを用いたインターポーザでは、内部に貫通孔を形成し、その孔を導電性物質で充填するTSV(Through−Silicon Via)やTGV(Through−Glass Via)と呼ばれる技術を用いていることが特徴である。   An interposer using silicon or glass as a base material uses a technique called TSV (Through-Silicon Via) or TGV (Through-Glass Via) which forms a through-hole inside and fills the hole with a conductive material. It is a feature.

このような技術により形成される貫通電極は、インターポーザの表裏を最短距離で接続することで配線長が短縮され、信号伝送速度の高速化などに優れた電気特性が期待されている。また、内部に配線を形成する構造のため電子デバイスの小型化や高密度化にも有効な実装方法であるといえる。さらに、貫通電極を採用することで、多ピン並列接続が可能となり、LSI自体を高速化させる必要がなく、優れた電気特性が得られることから、低消費電力化が実現できると期待されている。   A through electrode formed by such a technique is expected to have excellent electrical characteristics such as shortening the wiring length by connecting the front and back of the interposer at the shortest distance, and increasing the signal transmission speed. Moreover, it can be said that it is an effective mounting method for downsizing and increasing the density of electronic devices because of the structure in which wiring is formed inside. Furthermore, it is expected that low power consumption can be realized by adopting through-electrodes because multi-pin parallel connection is possible, it is not necessary to speed up the LSI itself, and excellent electrical characteristics can be obtained. .

特に近年では、ガラスを基板の材質として用いたガラスインターポーザに大きな注目が集まっている。   Particularly in recent years, much attention has been focused on glass interposers using glass as a substrate material.

ガラスインターポーザの大きな関心の1つは、低コスト化の実現が挙げられる。それは、シリコンインターポーザがウエハー処理でしか製造できないのに対し、ガラスインターポーザは、大型パネルでの大量処理が可能であると考えられているためである。その結果、これまで高性能や最高級向けのインターポーザで大きな課題となっていたコストの問題を解決できる可能性が出てきた。   One of the major concerns of glass interposers is the realization of lower costs. This is because the silicon interposer can only be manufactured by wafer processing, whereas the glass interposer is considered to be capable of mass processing with a large panel. As a result, it has become possible to solve the cost problem that has been a major issue with high-performance and first-class interposers.

しかしながら、ガラスインターポーザを製造する場合、幾つかの克服すべき課題が存在する。   However, there are several challenges to overcome when manufacturing glass interposers.

その1つは加工性が挙げられる。材質がシリコンの場合、開口径10μmφ程度の微細な孔を加工する技術が既に確立されており、その孔の形状もほぼストレートな貫通孔を形成することができる。これに対して、ガラスは、シリコンと比較して加工性が劣るため、微細な孔をあけることが難しく、加工技術も未だ確立されていないのが現状である。   One of them is workability. When the material is silicon, a technique for processing a fine hole having an opening diameter of about 10 μmφ has already been established, and a through hole having a substantially straight shape can be formed. On the other hand, glass is inferior in workability compared with silicon, so it is difficult to make fine holes, and the processing technology has not been established yet.

もう1つの大きな課題は、基板の放熱性に問題がある。それは、ガラスの熱伝導率がシリコンに比べて低いため、熱が内部から逃げにくく信頼性の確保が難しい。   Another major problem is a problem with heat dissipation of the substrate. That is, since the thermal conductivity of glass is lower than that of silicon, it is difficult for heat to escape from the inside and it is difficult to ensure reliability.

そこで、以上のような課題を解決するために幾つかの技術が提案されている。   Therefore, several techniques have been proposed to solve the above problems.

その1つは、ガラス基板に安価で良好な貫通電極を簡便な工程を用いて形成する貫通電極付き配線基板の製造方法が提案されている(特許文献1)。   As one of them, a manufacturing method of a wiring substrate with a through electrode has been proposed in which an inexpensive and good through electrode is formed on a glass substrate using a simple process (Patent Document 1).

また、他の1つは、金属薄膜上に塗布したレジストに貫通電極に相当し、かつ金属薄膜に至る長さの複数の開口部を形成した後、各開口部の内壁に金属を円筒状にめっきした後、レジストを除去する。しかる後、各円筒状の金属間に溶融ガラスを流し込んで固化させた後、金属薄膜を除去することで、微細な貫通電極を形成する貫通電極付きガラスウエアの形成方法が提案されている(特許文献2)。   The other is that after forming a plurality of openings corresponding to the through electrodes in the resist coated on the metal thin film and reaching the metal thin film, the metal is cylindrically formed on the inner wall of each opening. After plating, the resist is removed. Thereafter, a method of forming glassware with through electrodes that forms fine through electrodes is proposed by pouring molten glass between the respective cylindrical metals and solidifying them, and then removing the metal thin film (patent) Reference 2).

特開2012−119611号公報JP 2012-119611 A 特開2011−119372号公報JP 2011-119372 A

第25回エレクトロニクス実装学会春季講演大会 10D−14「3次元実装用・高気密・貫通ビア付ガラスウェハ “SCHOTT HermeS”」25th Electronics Packaging Society Spring Meeting 10D-14 “Three-Dimensional Mounting, Highly Airtight, Glass Wafer with Through-via“ SCHOTT HermeS ””

しかしながら、特許文献1の方法は、ガラス基板の微細な貫通孔にも電極を形成できると記載されているが、貫通孔を微細化する方法については具体的な開示がなされていない。   However, although the method of Patent Document 1 describes that an electrode can be formed even in a fine through hole of a glass substrate, no specific disclosure has been made about a method of miniaturizing the through hole.

また、特許文献2の方法は、少なくとも微細な貫通電極の形成工程と溶融ガラスの流入工程とが必要となり、製造工程数が多くなること及び技術的な難易度が非常に高くなり、簡便な製造方法とは言い難い。   In addition, the method of Patent Document 2 requires at least a fine through electrode forming step and a molten glass inflow step, which increases the number of manufacturing steps and the technical difficulty level, and makes it easy to manufacture. It's hard to say how.

本発明は上記事情に鑑みてなされたもので、ガラス基材に任意の大きさの貫通孔を形成でき、かつ貫通孔を含むガラス基材面に金属層及び絶縁層の順序で施し、放熱性に優れた構成及び自在な径の貫通孔を形成し、信頼性の高い微細な貫通電極を有するインターポーザとして使用可能な貫通電極付き配線基板及びその製造方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and can form a through hole of an arbitrary size in a glass substrate, and is applied to the glass substrate surface including the through hole in the order of a metal layer and an insulating layer. It is an object of the present invention to provide a wiring substrate with a through electrode that can be used as an interposer having a highly reliable and fine through electrode by forming a through hole having an excellent configuration and a flexible diameter, and a method for manufacturing the wiring substrate.

上記課題を解決するために、請求項1に対応する発明は、SiOを主成分とするガラス基材を用いた配線基板において、前記ガラス基材に形成された複数の貫通孔と、この貫通孔を含むガラス基材の面に形成された所定厚さの金属層と、この金属層の面に形成され、後記する貫通電極からのリーク電流防止用の所定厚さを有する絶縁層と、前記貫通孔部分に形成された導電性物質からなる前記貫通電極とを備えたことを特徴とする貫通電極付き配線基板である。 In order to solve the above-mentioned problems, the invention corresponding to claim 1 is a wiring board using a glass base material mainly composed of SiO 2 , and a plurality of through holes formed in the glass base material and the through holes A metal layer having a predetermined thickness formed on the surface of the glass substrate including the holes, an insulating layer formed on the surface of the metal layer and having a predetermined thickness for preventing leakage current from a through electrode to be described later, A wiring substrate with a through electrode, comprising: the through electrode made of a conductive material formed in a through hole portion.

請求項2に対応する発明は、請求項1に対応する発明に記載の貫通電極付き配線基板において、前記金属層の熱伝導率は、10W・m−1・K−1〜400W・m−1・K−1の範囲内であることを特徴とする。 The invention corresponding to claim 2 is the wiring substrate with through electrodes according to the invention corresponding to claim 1, wherein the thermal conductivity of the metal layer is 10 W · m −1 · K −1 to 400 W · m −1. -It is within the range of K- 1 .

請求項3に対応する発明は、請求項1または請求項2に対応する発明に記載の貫通電極付き配線基板において、前記貫通電極の主材料は、Cu,Ag,Au,Ni,Pt,Pd,Ru,Feの何れか一種またはこれらの金属を含む合金の何れか一種であることを特徴とする。   The invention corresponding to claim 3 is the wiring substrate with a through electrode according to claim 1 or 2, wherein the main material of the through electrode is Cu, Ag, Au, Ni, Pt, Pd, It is characterized by being any one of Ru and Fe or any one of alloys containing these metals.

請求項4に対応する発明は、請求項1ないし請求項3の何れか一項に対応する発明に記載の貫通電極付き配線基板において、前記配線基板の片面または両面に取り付けられ、絶縁基材に貼り付けた導体層に所望の回路構成が形成され、かつ前記配線基板から露出される前記貫通電極に接続するための貫通電極を設けた配線板をさらに備えたことを特徴とする。   The invention corresponding to claim 4 is the wiring substrate with a through electrode according to any one of claims 1 to 3, wherein the wiring substrate is attached to one side or both sides of the wiring substrate, and The circuit board further includes a wiring board having a desired circuit configuration formed on the pasted conductor layer and provided with a through electrode for connection to the through electrode exposed from the wiring board.

請求項5に対応する発明は、請求項4に対応する発明に記載の貫通電極付き配線基板において、前記配線板の表面部に半導体素子を搭載してなることを特徴とする。   According to a fifth aspect of the present invention, in the wiring substrate with a through electrode according to the fourth aspect of the present invention, a semiconductor element is mounted on the surface portion of the wiring board.

請求項6に対応する発明は、SiOを主成分とするガラス基材を用いた配線基板の製造方法において、前記ガラス基材に複数の貫通孔を形成する孔形成工程と、この孔形成工程で形成された貫通孔を含む前記ガラス基材の面部に所定厚さの金属層を形成する工程と、この工程で形成された金属層の面部にリーク電流防止用の所定厚さの絶縁層を形成する工程と、前記貫通孔以外の部分にレジストを形成する工程と、前記貫通孔に導電性物質を充填、または埋め込んで貫通電極とする工程と、前記レジストを剥離する工程とを含むことを特徴とする貫通電極付き配線基板の製造方法である。 The invention corresponding to claim 6 is a method of manufacturing a wiring board using a glass base material mainly composed of SiO 2 , a hole forming step of forming a plurality of through holes in the glass base material, and the hole forming step A step of forming a metal layer having a predetermined thickness on the surface portion of the glass substrate including the through-hole formed in the step, and an insulating layer having a predetermined thickness for preventing leakage current on the surface portion of the metal layer formed in this step. Including a step of forming, a step of forming a resist in a portion other than the through hole, a step of filling or filling the through hole with a conductive substance to form a through electrode, and a step of peeling the resist. It is a manufacturing method of the wiring board with a penetration electrode characterized by it.

請求項7に対応する発明は、請求項6に対応する発明に記載の貫通電極付き配線基板の製造方法において、絶縁基板に導電性の回路配線を施した配線板を形成する工程と、この配線板の所定の位置に形成される貫通孔に導電性物質を充填、または埋め込んで貫通電極を形成する工程と、前記配線基板の片面または両面から露出する貫通電極に対して、前記配線板の貫通電極を位置決めして接続する工程とをさらに含むことを特徴とする。   The invention corresponding to claim 7 is a method of manufacturing a wiring substrate with through electrodes according to the invention corresponding to claim 6, wherein a step of forming a wiring board in which conductive circuit wiring is applied to an insulating substrate, and the wiring A step of forming a through electrode by filling or embedding a conductive material in a through hole formed at a predetermined position of the plate, and a through-hole of the wiring board with respect to the through-electrode exposed from one side or both sides of the wiring substrate And a step of positioning and connecting the electrodes.

本発明によれば、SiOを主成分とするガラス基材を用いた配線基板においては、加工性及び放熱性に優れた高機能で信頼性の高い貫通電極付き配線基板及びその製造方法を提供できる。 According to the present invention, in a wiring board using a glass base material mainly composed of SiO 2 , a highly functional and highly reliable wiring board with a through electrode excellent in workability and heat dissipation and a method for manufacturing the same are provided. it can.

すなわち、請求項1に係る発明によれば、貫通孔を含むガラス基材の面を所定厚さの金属層で覆うことにより、配線基板の内部に熱伝導性の高い物質を取り込むことができ、結果放熱性が強化された信頼性の高いインターポーザを実現できる。   That is, according to the invention according to claim 1, by covering the surface of the glass substrate including the through hole with a metal layer having a predetermined thickness, a substance having high thermal conductivity can be taken into the wiring board, As a result, a highly reliable interposer with enhanced heat dissipation can be realized.

その結果、ガラス基材に金属層などの熱伝導性の高い物質を含まない配線基板においては、チップ搭載部周辺に熱が留まり信頼性を低下させる恐れがあるが、熱伝導性の高い金属を放熱用の層として内部に配置することで、熱を分散させて逃がすという効果がある。特にこの金属層をインターポーザ外部に配置した放熱板などにサーマルビアなどを形成して接続させると、よりいっそうの高い放熱効果が期待できる。   As a result, in a wiring board that does not contain a highly thermally conductive substance such as a metal layer in the glass substrate, heat may remain in the periphery of the chip mounting part and reduce reliability. By disposing inside as a layer for heat dissipation, there is an effect that heat is dispersed and released. In particular, if a thermal via or the like is formed and connected to a heat radiating plate or the like in which this metal layer is disposed outside the interposer, an even higher heat radiating effect can be expected.

また、金属層の厚さを自在に制御することにより、微細な貫通電極を形成することが可能となる。   In addition, a fine through electrode can be formed by freely controlling the thickness of the metal layer.

一般に、SiOを主成分とするガラス基材への加工は非常に難しく、例えば既存の技術であるレーザー加工などで形成できるビア(孔)サイズは小さくてもせいぜい50〜60μm程度が限界であるといわれており、またこのサイズの場合にはビアの形状もストレートではなくテーパーになりやすい。 In general, it is very difficult to process a glass substrate containing SiO 2 as a main component. For example, even if the via (hole) size that can be formed by laser processing, which is an existing technology, is small, the limit is about 50-60 μm at most. Also, in this size, the via shape is not straight but is likely to be tapered.

しかし、請求項1に係る発明では、あらかじめガラス基材に容易に形成できる大きいサイズの貫通孔を開けた後、金属層の厚さを自在に調整制御することにより、開口径が50μmφ以下の貫通孔であっても容易に形成できる。例えば、ガラス基材に大きい径となる開口径100μmφの貫通孔を開けた後、この貫通孔を含むガラス基材の面に30μmの金属層を形成させることによって、最終的に開口径が40μmφを下回るような、既存技術では形成困難な微細な貫通電極を形成することが可能である。   However, in the invention according to claim 1, after opening a through-hole of a large size that can be easily formed in a glass substrate in advance, the thickness of the metal layer is freely adjusted and controlled, so that the opening diameter is 50 μmφ or less. Even a hole can be easily formed. For example, after opening a through hole having a large diameter of 100 μmφ in a glass substrate, a metal layer of 30 μm is formed on the surface of the glass substrate including the through hole, so that the final opening diameter is 40 μmφ. It is possible to form a fine through electrode that is difficult to form with existing technology.

請求項2に係る発明によれば、放熱用途の金属層の熱伝導率として、少なくとも10W・m−1・K−1〜400W・m−1・K−1の範囲内にある値とすることを特徴とする。一般に、ガラスであるフロートガラスの熱伝導率は1W・m−1・K−1程度であり、SiO純度が高い石英ガラスでも1.3W・m−1・K−1程度とガラスは熱伝導率が低い。 According to the invention of claim 2, as the thermal conductivity of the metal layer of the heat dissipating applications, it is a value that is at least 10 W · m in the range of -1 · K -1 ~400W · m -1 · K -1 It is characterized by. In general, the thermal conductivity of float glass, which is glass, is about 1 W · m −1 · K −1 , and even if quartz glass having a high SiO 2 purity is about 1.3 W · m −1 · K −1 , the glass is thermally conductive. The rate is low.

これに対して、金属の場合には、例えばアルミニウムでは200W・m−1・K−1程度、銅で380W・m−1・K−1程度とはるかに高い。金属の中では熱伝導率が低いチタンでも17W・m−1・K−1程度とガラス類の10倍以上の値を有しており、結果として放熱性は強化されることになる。 On the other hand, in the case of metal, for example, aluminum is about 200 W · m −1 · K −1 , and copper is about 380 W · m −1 · K −1, which is much higher. Among metals, titanium having a low thermal conductivity has a value of about 17 W · m −1 · K −1 and 10 times that of glass, and as a result, heat dissipation is enhanced.

請求項3に係る発明によれば、貫通電極の主材料がCu、Ag、Au、Ni、Pt、Pd、Ru、Feまたはこれらの金属を含む合金のいずれか一種とすれば、これら単体又は合金の物質はめっきにより容易に析出させることが可能であり、電気特性も優れている。中でも特に電気特性やコストの両面で優れているのは銅である。   According to the invention of claim 3, if the main material of the through electrode is Cu, Ag, Au, Ni, Pt, Pd, Ru, Fe, or an alloy containing these metals, these simple substances or alloys This material can be easily deposited by plating and has excellent electrical characteristics. Of these, copper is particularly excellent in terms of both electrical characteristics and cost.

また、請求項4及び5に係る発明によれば、貫通電極付き配線基板の表裏面に配線板を取り付けることにより、配線基板への半導体素子の搭載やプリント配線基板への実装が可能となるため、半導体装置として使用が可能となる。このとき、配線基板側の貫通電極と配線板側の貫通電極とを接続することにより、高速伝送特性など優れた電気特性を有する。また、内部に配線を形成させる構造により電子機器の小型化にも寄与する。   Further, according to the inventions according to claims 4 and 5, mounting the wiring board on the front and back surfaces of the wiring board with through electrodes enables mounting of the semiconductor element on the wiring board and mounting on the printed wiring board. It can be used as a semiconductor device. At this time, by connecting the through electrode on the wiring board side and the through electrode on the wiring board side, excellent electrical characteristics such as high-speed transmission characteristics are obtained. In addition, the structure in which wiring is formed inside contributes to miniaturization of electronic equipment.

さらに、請求項6及び7に係る発明によれば、配線基板の表裏面に当該配線基板とは別工程で形成された配線板を位置決めして重ね合わせた後、貫通電極どうしを接続することを特徴とする。別工程で形成された配線板は、絶縁基材に導電性の回路配線を施したものであって、例えば絶縁基材はポリイミド、導電性の回路配線には銅を用いることができる。前記配線板は単層だけでなく多層配線構造にすることも可能である。   Furthermore, according to the invention which concerns on Claim 6 and 7, after positioning and overlapping the wiring board formed in the process different from the said wiring board on the front and back of the wiring board, connecting the penetration electrodes to each other Features. The wiring board formed in a separate process is obtained by applying conductive circuit wiring to an insulating base. For example, polyimide can be used for the insulating base and copper can be used for the conductive circuit wiring. The wiring board can have a multilayer wiring structure as well as a single layer.

この製造方法によれば、ガラス基材の配線基板に一層ずつ配線層を形成するよりも、別工程であらかじめ作製しておいた配線板を重ね合わせる方法とすれば、工程の大幅な短縮が可能となる。   According to this manufacturing method, rather than forming wiring layers one by one on a glass-based wiring board, it is possible to significantly shorten the process by using a method in which wiring boards prepared in a separate process are stacked. It becomes.

本発明に係る貫通電極付き配線基板の一実施の形態を示す概略的な構成の断面図。BRIEF DESCRIPTION OF THE DRAWINGS Sectional drawing of the schematic structure which shows one Embodiment of the wiring board with a penetration electrode which concerns on this invention. 本発明に係る貫通電極付き配線基板の製造方法の一例を説明する図。The figure explaining an example of the manufacturing method of the wiring board with a penetration electrode concerning the present invention. 本発明に係る貫通電極付き配線基板の表裏面に重ね合わせるための配線板の概略的な構成の断面図。Sectional drawing of schematic structure of the wiring board for overlapping on the front and back of the wiring board with a penetration electrode concerning the present invention. 図3に示す配線板の製造方法の一例を説明する図。The figure explaining an example of the manufacturing method of the wiring board shown in FIG. 図1に示す貫通電極付き配線基板の表裏面に図3に示す配線板を重ね合わせた構成の断面図。Sectional drawing of the structure which piled up the wiring board shown in FIG. 3 on the front and back of the wiring board with a penetration electrode shown in FIG.

以下、本発明の実施の形態について、図面を参照しながら詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図1は本発明に係る貫通電極付き配線基板の一実施の形態を示す概略的な構成断面図である。   FIG. 1 is a schematic cross-sectional view showing an embodiment of a wiring board with a through electrode according to the present invention.

貫通電極付き配線基板10は、SiOを主成分とするガラスで構成され、厚さ方向に複数の貫通孔11aを形成されたガラス基材12と、貫通孔11aを含むガラス基材12の表面を覆うように、例えばスパッタ、蒸着などの物理的な方法あるいはめっきによる化学的な方法により所要の厚さに形成された金属筒状貫通孔11bを含む金属層13と、この金属層13の表面に所要の厚さに形成され、かつ金属筒状貫通孔11bに相当する部分にも同様に絶縁材で覆われた絶縁筒状貫通孔11cを含む絶縁層14と、絶縁筒状貫通孔11c内に導電性物質を充填することで形成される貫通電極15とで構成される。 The wiring substrate 10 with a through electrode is made of glass mainly composed of SiO 2 and has a glass base 12 having a plurality of through holes 11a formed in the thickness direction, and a surface of the glass base 12 including the through holes 11a. A metal layer 13 including a metal cylindrical through-hole 11b formed to have a required thickness by a physical method such as sputtering or vapor deposition, or a chemical method such as plating, and the surface of the metal layer 13 An insulating layer 14 including an insulating cylindrical through-hole 11c formed in a required thickness and covered with an insulating material also in a portion corresponding to the metal cylindrical through-hole 11b, and in the insulating cylindrical through-hole 11c And a through electrode 15 formed by filling a conductive material.

よって、配線基板の構造としては、ガラス基材12の面部に金属層13及び絶縁層14の順序で施した多層構造の貫通電極付き配線基板10となる。   Therefore, the wiring board structure is a wiring board 10 with a through electrode having a multilayer structure in which the metal layer 13 and the insulating layer 14 are applied to the surface of the glass substrate 12 in this order.

このような実施の形態によれば、貫通孔11aを含むガラス基材12の表面に所定厚さの金属層13を覆うことにより、配線基板10内部に熱伝導性の高い物質を取り込むことができ、結果として放熱性が強化された信頼性の高いインターポーザを実現することができる。   According to such an embodiment, by covering the surface of the glass substrate 12 including the through hole 11a with the metal layer 13 having a predetermined thickness, a substance having high thermal conductivity can be taken into the wiring board 10. As a result, a highly reliable interposer with enhanced heat dissipation can be realized.

また、金属層13の厚さを自在に制御できるので、微細な貫通電極15を容易に形成することができる。   In addition, since the thickness of the metal layer 13 can be freely controlled, the fine through electrode 15 can be easily formed.

次に、本発明に係る貫通電極付き配線基板の製造方法の一実施の形態について、図2を参照して説明する。   Next, an embodiment of a method for manufacturing a wiring substrate with through electrodes according to the present invention will be described with reference to FIG.

先ず、SiOを主成分とするガラス基材12を用意する(図2(a)参照)。 First, a glass substrate 12 whose main component is SiO 2 (see FIG. 2 (a)).

このガラス基材12の厚さ方向に所要の間隔をもって複数の貫通孔11a,…を形成する(図2(b)参照)。貫通孔11aを形成する方法は、レーザー、ドリル、ウェットエッチングなどにより貫通する方法が考えられるが、これらに限定されるものではない。   A plurality of through holes 11a,... Are formed in the thickness direction of the glass substrate 12 with a required interval (see FIG. 2B). A method of forming the through hole 11a may be a method of penetrating with a laser, a drill, wet etching, or the like, but is not limited thereto.

また、ガラス基材12はSiOを主成分とするガラスであれば特に限定されない。例えば、石英ガラス、ホウ珪酸ガラス、無アルカリガラスなどを用いることができる。 The glass substrate 12 is not particularly limited as long as glass composed mainly of SiO 2. For example, quartz glass, borosilicate glass, non-alkali glass, or the like can be used.

次に、複数の貫通孔11a,…を含むガラス基材12の表面に金属層13を形成する(図2(c)参照)。この金属層13を形成することで、貫通孔11aの壁部分には金属筒状貫通孔11bが形成される。   Next, the metal layer 13 is formed on the surface of the glass substrate 12 including the plurality of through holes 11a,... (See FIG. 2C). By forming this metal layer 13, a metal cylindrical through hole 11b is formed in the wall portion of the through hole 11a.

金属筒状貫通孔11bを含む金属層13を形成する手段は、スパッタや蒸着などの物理的な方法で形成することが可能であるが、めっきによる化学的な方法で形成するのが望ましい。めっきによる方法を用いた場合、高アスペクト比を有する孔に対して、物理的な方法よりも均一に孔内部への薄い皮膜形成が容易であり、また真空系の大型装置を使用する必要がないため、低コストで金属層13を形成することが可能である。なお、前記貫通孔11aに相当する壁面部分も薄い金属皮膜で形成され、金属筒状貫通孔11bとして形成される。   The means for forming the metal layer 13 including the metal cylindrical through-hole 11b can be formed by a physical method such as sputtering or vapor deposition, but is preferably formed by a chemical method by plating. When the plating method is used, it is easier to form a thin film inside the hole more uniformly than the physical method for holes having a high aspect ratio, and there is no need to use a large vacuum system. Therefore, the metal layer 13 can be formed at a low cost. The wall surface portion corresponding to the through hole 11a is also formed of a thin metal film, and is formed as a metal cylindrical through hole 11b.

貫通孔11aを含むガラス基材12の表面にめっきにて金属層13を形成する場合、無電解めっき法を用いることができる。例えば、ガラス基材12上に無電解めっきの触媒が担持可能な有機層などを一層形成させることで、無電解めっきが可能となる。ガラス基材12の主成分であるSiOに対して、シランカップリング剤などを使用することで、ガラス基材12表層のシラノール基との間にシロキサン結合を形成させることができ、有機層が形成できる。この有機層の官能基部分に触媒を担持させることができ、その結果として無電解めっきが可能となる。 When the metal layer 13 is formed by plating on the surface of the glass substrate 12 including the through holes 11a, an electroless plating method can be used. For example, electroless plating can be performed by forming one layer of an organic layer or the like that can carry an electroless plating catalyst on the glass substrate 12. By using a silane coupling agent or the like with respect to SiO 2 which is the main component of the glass substrate 12, a siloxane bond can be formed between the surface layer of the glass substrate 12 and the silanol group. Can be formed. A catalyst can be supported on the functional group portion of the organic layer, and as a result, electroless plating becomes possible.

金属層13は、熱伝導率が少なくとも10W・m−1・K−1以上であれば限定しないが、容易にめっきにより形成可能であり、かつ熱伝導性の高い金属を考えると、銅を用いることが望ましい。ちなみに、銅の熱伝導率は、380W・m−1・K−1程度である。 The metal layer 13 is not limited as long as the thermal conductivity is at least 10 W · m −1 · K −1 or more, but copper can be used when considering a metal that can be easily formed by plating and has high thermal conductivity. It is desirable. Incidentally, the thermal conductivity of copper is about 380 W · m −1 · K −1 .

従って、金属層13の熱伝導率としては、10W・m−1・K−1〜400W・m−1・K−1の範囲が望ましい。 Thus, the thermal conductivity of the metal layer 13, is preferably in the range of 10W · m -1 · K -1 ~400W · m -1 · K -1.

また、有機層を組成するシランカップリング剤の官能基部分には電子供与基を持っていることが望ましい。その理由は、電子供与基が無電解めっきの触媒となるパラジウムや白金などの金属のイオンと相互作用し、有機層上に選択的に金属イオンを吸着させることができるためである。シランカップリング剤の電子供与基としては、アミノ基やチオール基などが考えられるが、これらに限定されるものではない。   Further, it is desirable that the functional group portion of the silane coupling agent constituting the organic layer has an electron donating group. The reason is that the electron donating group interacts with metal ions such as palladium and platinum which serve as a catalyst for electroless plating, and the metal ions can be selectively adsorbed on the organic layer. The electron donating group of the silane coupling agent may be an amino group or a thiol group, but is not limited thereto.

また、有機層上に吸着される金属イオンは還元処理を施すことで金属となり、触媒としての利用が可能となる。このとき、次工程の無電解めっき液中の還元剤で金属イオンを還元することができる。   Moreover, the metal ion adsorbed on the organic layer becomes a metal by performing a reduction treatment, and can be used as a catalyst. At this time, metal ions can be reduced with a reducing agent in the electroless plating solution in the next step.

また、無電解めっき液中の還元剤で金属イオンを還元できない場合、無電解めっき工程の前に予め金属イオンを還元する必要がある。例えば、触媒としてパラジウムのイオンを吸着させる場合、無電解めっき液中の還元剤が次亜リン酸ナトリウムやジメチルアミンボランであれば還元できるが、ホルムアルデヒドの場合には還元できないため、事前にジメチルアミンボランなどにより還元を必要とする。使用できる還元剤は、次亜リン酸ナトリウム、ジメチルアミンボラン、ホルマリン、水素化ホウ素ナトリウム、ヒドラジンなどが挙げられるが、これらに限定されるものではない。   Moreover, when a metal ion cannot be reduced with the reducing agent in the electroless plating solution, it is necessary to reduce the metal ion in advance before the electroless plating step. For example, when palladium ions are adsorbed as a catalyst, it can be reduced if the reducing agent in the electroless plating solution is sodium hypophosphite or dimethylamine borane, but cannot be reduced in the case of formaldehyde. Reduction is required with borane. The reducing agent that can be used includes, but is not limited to, sodium hypophosphite, dimethylamine borane, formalin, sodium borohydride, hydrazine and the like.

ガラス基材12の表面に金属層13を形成する際、放熱及び貫通電極15の径を考慮し、所望とする厚さに制御する。例えば、無電解めっきを長時間行って所定の厚さを得る方法や無電解めっき又はスパッタなどにより薄い金属層13を形成させた後、これらをシード層として電解めっきにより金属層を厚付けする方法も考えられるが、これらの方法は限定しない。しかし、短時間で金属層13を厚くすることができる電解めっきを使用することが望ましい。   When forming the metal layer 13 on the surface of the glass substrate 12, the heat dissipation and the diameter of the through electrode 15 are taken into consideration and the thickness is controlled to a desired value. For example, a method of obtaining a predetermined thickness by performing electroless plating for a long time, or a method of forming a thin metal layer 13 by electroless plating or sputtering, and then thickening the metal layer by electrolytic plating using these as a seed layer However, these methods are not limited. However, it is desirable to use electrolytic plating that can thicken the metal layer 13 in a short time.

さらに、複数の金属筒状貫通孔11b,…を含む金属層13の表面に絶縁層14を形成する(図2(d)参照)。この絶縁層14を形成することで、金属筒状貫通孔11bの内壁部分には絶筒状貫通孔11cが形成される。   Further, an insulating layer 14 is formed on the surface of the metal layer 13 including the plurality of metal cylindrical through holes 11b,... (See FIG. 2D). By forming this insulating layer 14, a cylindrical through hole 11c is formed in the inner wall portion of the metal cylindrical through hole 11b.

以下、説明の便宜上,貫通孔11a,筒状金属貫通孔11b及び筒状絶縁貫通孔11cを含んで貫通孔11と総称する。   Hereinafter, for convenience of explanation, the through hole 11 is collectively referred to as including the through hole 11a, the cylindrical metal through hole 11b, and the cylindrical insulating through hole 11c.

貫通孔11である絶縁筒状貫通孔11cを含む絶縁層14を形成する手段としては、CVD法などが挙げられるが、特に限定するものではない。この絶縁層14は、金属層13と貫通電極15とを絶縁するために施すものである。   As a means for forming the insulating layer 14 including the insulating cylindrical through-hole 11c which is the through-hole 11, a CVD method or the like can be mentioned, but it is not particularly limited. The insulating layer 14 is provided to insulate the metal layer 13 and the through electrode 15 from each other.

絶縁層14の厚さは、貫通電極15からのリーク電流が流れなければ厚さは限定しないが、信頼性を考えると最低でも1μm程度に形成することが望ましい。   The thickness of the insulating layer 14 is not limited as long as a leak current from the through electrode 15 does not flow. However, considering the reliability, it is desirable to form the insulating layer 14 at least about 1 μm.

貫通孔11を含む絶縁層14を形成した後、貫通孔11以外の部分にフォトリソグラフィーによりレジスト16をパターニングした後、貫通孔11のみに導電性物質を充填(フィリング)して貫通電極15を形成する。このとき、貫通孔11の開口径より少し広くレジスト16をパターニングすることにより、貫通電極15上に部品取付け用導電パターンであるランドを同時に形成することが可能となる(図2(e)及び同図(f)参照)。   After forming the insulating layer 14 including the through hole 11, the resist 16 is patterned on the portion other than the through hole 11 by photolithography, and then only the through hole 11 is filled (filled) with the conductive material to form the through electrode 15. To do. At this time, by patterning the resist 16 slightly wider than the opening diameter of the through hole 11, it is possible to simultaneously form lands that are component mounting conductive patterns on the through electrode 15 (see FIG. 2E and FIG. 2). (Refer figure (f)).

このように予めランドを形成することにより、後記する配線板(配線層とも言う)を重ね合わせる工程でのアライメントが容易になる。また、フィリングする方法はめっきやスパッタ、導電性ペーストなどを使用する方法が挙げられるが、これらに限定しない。しかしながら、均一でボイドフリーな貫通電極15を形成するにはめっきを用いることが望ましい。   By forming the lands in advance in this way, alignment in the process of overlaying wiring boards (also referred to as wiring layers) to be described later becomes easy. Examples of the filling method include, but are not limited to, plating, sputtering, and a method using a conductive paste. However, it is desirable to use plating to form a uniform and void-free through electrode 15.

貫通孔11内部の絶縁層14上にめっきにてフィリングする場合、例示した方法と同様に無電解めっき法を用いることができる。その後、無電解めっきで貫通孔11を完全に埋める方法や無電解めっきで形成させた層をシード層として電解めっき法により貫通孔11を充填させる方法などにより貫通電極15を形成する。これらの方法は限定しないが、電解めっきを行うことにより短時間で容易に貫通電極15を形成することができる。   When filling the insulating layer 14 in the through hole 11 by plating, an electroless plating method can be used in the same manner as the exemplified method. Thereafter, the through electrode 15 is formed by a method of completely filling the through hole 11 by electroless plating or a method of filling the through hole 11 by an electrolytic plating method using a layer formed by electroless plating as a seed layer. Although these methods are not limited, the penetration electrode 15 can be easily formed in a short time by performing electroplating.

さらに、貫通電極15を形成した後、レジスト16を剥離することにより(図2(g)参照)、ガラス基材12上であっても微細な貫通電極15を形成できるとともに放熱性にも優れた配線基板10を作製することができる。   Furthermore, after the through electrode 15 is formed, the resist 16 is peeled off (see FIG. 2G), so that the fine through electrode 15 can be formed even on the glass substrate 12, and the heat dissipation is also excellent. The wiring board 10 can be manufactured.

次に、配線基板10に適用する配線板とその製造方法について、図3及び図4を参照して説明する。
図3は配線板20の一例を説明する概略的な断面図である。
Next, a wiring board applied to the wiring board 10 and a manufacturing method thereof will be described with reference to FIGS.
FIG. 3 is a schematic cross-sectional view illustrating an example of the wiring board 20.

配線板20は、配線基板10とは別工程により配線基板10の表面及び裏面に貼り合わせまたは重ね合わせることにより形成される層であって、絶縁基材21、この絶縁基材21の表面及び裏面に形成される回路配線22,23と、絶縁基材21の両面に跨って貫通形成される回路配線24と、絶縁基材21の裏面に形成される回路配線23を覆うように施される絶縁層25とを備えた構成である。   The wiring board 20 is a layer formed by bonding or overlapping the front and back surfaces of the wiring board 10 in a separate process from the wiring board 10, and includes an insulating base material 21, and the front and back surfaces of the insulating base material 21. Insulation applied so as to cover the circuit wirings 22 and 23 formed in the circuit board 24, the circuit wiring 24 formed through the both sides of the insulating base material 21, and the circuit wiring 23 formed on the back surface of the insulating base material 21 And a layer 25.

図4は配線板20を製造する方法を説明する図である
配線板20は、配線基板10とは別工程で形成する。配線板20を形成する手段としては、ビルドアップ法を用いて多層配線板として形成する。
FIG. 4 is a diagram for explaining a method of manufacturing the wiring board 20. The wiring board 20 is formed in a separate process from the wiring board 10. As a means for forming the wiring board 20, it is formed as a multilayer wiring board using a build-up method.

先ず、絶縁基材21に導体層22´が貼り合わせた基材を出発材料として(図4(a)参照)、導体層22´をエッチングすることにより回路配線22を形成する(図4(b)参照)。出発材料は限定しないが、例えば絶縁基材21にはポリイミド系の絶縁性樹脂、導体層22´には銅箔などを用いることができる。   First, using the base material in which the conductor layer 22 ′ is bonded to the insulating base material 21 as a starting material (see FIG. 4A), the circuit layer 22 is formed by etching the conductor layer 22 ′ (FIG. 4B). )reference). Although the starting material is not limited, for example, a polyimide-based insulating resin can be used for the insulating base material 21, and a copper foil or the like can be used for the conductor layer 22 '.

絶縁基材21上に回路配線22を形成した後、当該絶縁基材21の所定位置にレーザーなどによる加工により、所要数の貫通孔26を形成する(図4(c)参照)。   After the circuit wiring 22 is formed on the insulating base material 21, a required number of through holes 26 are formed at a predetermined position of the insulating base material 21 by processing with a laser or the like (see FIG. 4C).

引き続き、貫通孔26に対してめっきまたは導電性ペーストなどを充填した後、絶縁基材21の回路配線22とは反対側の面に導体層23´を形成する(図4(d)参照)。導体層23´の材料は限定しないが、コストや電気特性を考慮すると、銅であることが望ましい。   Subsequently, after the through hole 26 is filled with plating or conductive paste, a conductor layer 23 ′ is formed on the surface of the insulating base 21 opposite to the circuit wiring 22 (see FIG. 4D). The material of the conductor layer 23 'is not limited, but copper is desirable in consideration of cost and electrical characteristics.

しかる後、導体層23´をエッチングすることにより回路配線23を形成する(図4(e)参照)。   After that, the circuit wiring 23 is formed by etching the conductor layer 23 '(see FIG. 4E).

さらに、絶縁基材21の裏面側に回路配線23を覆うように絶縁層25を塗布またはラミネーションにより形成した後、レーザーなどにより貫通孔27を形成する(図4(f)及び同図(g)参照)。   Further, an insulating layer 25 is formed by coating or lamination so as to cover the circuit wiring 23 on the back surface side of the insulating base material 21, and then a through hole 27 is formed by a laser or the like (FIG. 4 (f) and FIG. 4 (g)). reference).

さらに、貫通孔27にはめっきまたは導電ペーストなどにより銅などを充填して回路配線24を形成することで、配線板20を作製することができる(図4(h)参照)。   Furthermore, the wiring board 20 can be produced by filling the through holes 27 with copper or the like by plating or conductive paste to form the circuit wiring 24 (see FIG. 4H).

多層の数は、前述した一連の工程を繰り返すことで何層でも自在に作製することが可能である。また、今回の図は配線基板10の表面の配線板20の製造方法について説明したが、配線基板10の裏面の配線板20についても同様の方法を用いて作製することができる。   Any number of layers can be freely produced by repeating the series of steps described above. Moreover, although this figure demonstrated the manufacturing method of the wiring board 20 of the surface of the wiring board 10, the wiring board 20 of the back surface of the wiring board 10 can also be produced using the same method.

そこで、別工程で作製した表裏面の配線板20と貫通電極付き配線基板10との位置合わせを行いながら、熱圧着などにより貼り合わせまたは重ね合わせることにより、図5に示すように配線基板10の表裏面に配線板20を備えた貫通電極付き配線基板30を作製することができる。   Therefore, while aligning the front and back wiring boards 20 produced in a separate process and the wiring substrate 10 with through electrodes, by bonding or superimposing them by thermocompression bonding or the like, as shown in FIG. A wiring substrate 30 with a through electrode having the wiring board 20 on the front and back surfaces can be produced.

このとき、配線基板10に表裏面に最も近い位置に貼り合わせまたは重ね合わせする配線板20の中の絶縁層(図5の絶縁層25)は、熱可塑性の樹脂などでできた接着層、例えばポリイミド系接着剤などを用いることで容易に接合することができる。この配線基板30に半導体素子を搭載させることによって、ガラスインターポーザとして使用することが可能となる。   At this time, the insulating layer (insulating layer 25 in FIG. 5) in the wiring board 20 to be bonded or superimposed on the wiring board 10 at the position closest to the front and back surfaces is an adhesive layer made of a thermoplastic resin, for example, It can be easily joined by using a polyimide-based adhesive or the like. By mounting a semiconductor element on the wiring board 30, it can be used as a glass interposer.

本発明に係る貫通電極付き配線基板の製造方法の実施例について説明する。   Examples of the method for manufacturing a wiring substrate with through electrodes according to the present invention will be described.

先ず、厚さ300μmの無アルカリガラスにレーザーにより開口径80μmφ、ピッチ250μmのスルーホールビア(貫通孔11)を形成した。このスルーホールビアを有するガラス基材12に対してアミノ基を有するシランカップリング剤APTESとトルエンの混合溶液(APTES:トルエン=1:9)に60℃で30min浸漬することで、ガラス基材12上に有機単分子膜を形成した。   First, through-hole vias (through-holes 11) having an opening diameter of 80 μmφ and a pitch of 250 μm were formed in a non-alkali glass having a thickness of 300 μm by a laser. The glass substrate 12 is immersed in a mixed solution of silane coupling agent APTES having an amino group APTES and toluene (APTES: toluene = 1: 9) at 60 ° C. for 30 minutes with respect to the glass substrate 12 having the through-hole via. An organic monomolecular film was formed thereon.

次に、前述のガラス基材12を0.2g/Lの塩化パラジウム水溶液に室温で10min浸漬し、触媒となるパラジウムイオンを有機膜中へ担持させる。さらに、触媒が付着したガラス基材12を0.1mol/Lのジメチルアミンボランを含む溶液に60℃で30sec浸漬し、パラジウムイオンの還元を行った。続いて、ガラス基材12上には還元したパラジウムを核として無電解銅めっきにより厚さ2μmの銅皮膜を均一に施した。この銅皮膜をシード層として、電解銅めっきにより銅を20μmの厚さまで成長させてなる金属層14を形成した。   Next, the glass substrate 12 described above is immersed in a 0.2 g / L palladium chloride aqueous solution at room temperature for 10 minutes to support palladium ions serving as a catalyst in the organic film. Further, the glass substrate 12 with the catalyst attached was immersed in a solution containing 0.1 mol / L dimethylamine borane at 60 ° C. for 30 seconds to reduce palladium ions. Subsequently, a copper film having a thickness of 2 μm was uniformly applied on the glass substrate 12 by electroless copper plating using reduced palladium as a nucleus. Using this copper film as a seed layer, a metal layer 14 was formed by growing copper to a thickness of 20 μm by electrolytic copper plating.

そして、厚付けした金属層13上にCVD法により、SiOを主成分とする2μm厚さの絶縁層14を施した。さらに、この絶縁層14上にドライフィルムレジストを形成し、フォトリソグラフィーよるパターニングを行い、36μm程度まで微細化されたスルーホールビアの径より大きい50μmのランド形成を見越したパターンを形成した。 Then, an insulating layer 14 having a thickness of 2 μm containing SiO 2 as a main component was applied on the thick metal layer 13 by a CVD method. Further, a dry film resist was formed on the insulating layer 14, and patterning was performed by photolithography to form a pattern in anticipation of land formation of 50 μm larger than the diameter of the through-hole via refined to about 36 μm.

ガラス基材12へのめっきと同様の方法により、シランカップリング剤を用いてレジストの無いスルーホールビアの内部のSiO上に有機膜と触媒を担持させ、無電解銅めっきによりスルーホール内部に均一な2μm程度の銅皮膜を形成させた。この銅皮膜をシード層として電解銅めっきによるビアフィリングを行い、径36μmφ、また50μmのランドを有する貫通電極15を形成した。 In the same manner as plating on the glass substrate 12, an organic film and a catalyst are supported on the SiO 2 inside the through hole via without a resist using a silane coupling agent, and the inside of the through hole is formed by electroless copper plating. A uniform copper film of about 2 μm was formed. Via filling by electrolytic copper plating was performed using this copper film as a seed layer, and a through electrode 15 having a land with a diameter of 36 μmφ and 50 μm was formed.

次に、配線板20の製造方法の実施例について説明する。   Next, an embodiment of a method for manufacturing the wiring board 20 will be described.

厚さ30μmのポリイミド絶縁基材21と例えば5μmの銅箔である導体層22´とを貼り合わされた基材の銅箔(導体層22´)をフォトエッチングにより回路形成を行い、回路配線22を形成した、その後、ポリイミド側からレーザーにより開口径40μmφ程度の貫通孔26を形成した。   A circuit is formed by photoetching a copper foil (conductor layer 22 ′) of a base material obtained by bonding a polyimide insulating base material 21 having a thickness of 30 μm and a conductor layer 22 ′, for example, a copper foil of 5 μm, and circuit wiring 22 is formed. Then, a through hole 26 having an opening diameter of about 40 μmφ was formed by laser from the polyimide side.

その後、貫通孔26を導電性ペーストで充填し、さらに無電解銅めっきにより5μmの厚さの導体層23´を形成した後、この導体層23´をフォトエッチングにより回路配線23を形成した。   Thereafter, the through hole 26 was filled with a conductive paste, and a conductor layer 23 ′ having a thickness of 5 μm was formed by electroless copper plating. Then, the circuit wiring 23 was formed by photoetching the conductor layer 23 ′.

さらに、熱可塑性ポリイミド接着剤をコーティングすることで絶縁層25を形成し、再び裏面からレーザーにて開口径40μmφの貫通孔27を加工した。そして、貫通孔27に導電性ペーストを充填し、同様の方法にて反対面の回路配線24を形成した。   Furthermore, the insulating layer 25 was formed by coating with a thermoplastic polyimide adhesive, and the through hole 27 having an opening diameter of 40 μmφ was processed again from the back surface with a laser. Then, the through hole 27 was filled with a conductive paste, and the circuit wiring 24 on the opposite surface was formed by the same method.

最後に貫通電極付き配線基板10と表裏面の配線板20との位置についてアライメントを行ないながら熱圧着により一括積層させることによって、ガラス基材とした径36μmφという微細な貫通電極15(回路配線24を含む)を有し、放熱性にも優れたガラスインターポーザとして使用可能な配線基板を作製することができた。   Finally, the fine through electrodes 15 (diameter 36 μmφ having a diameter of 36 μm) made of a glass substrate are obtained by laminating together by thermocompression while aligning the positions of the wiring substrate 10 with through electrodes and the wiring boards 20 on the front and back surfaces. And a wiring board usable as a glass interposer with excellent heat dissipation.

<比較例>
以下、本発明と先行技術文献との比較例について説明する。
<Comparative example>
Hereinafter, comparative examples of the present invention and prior art documents will be described.

表1は、本発明に係る貫通電極付き配線基板と前述する先行技術文献の項目に掲げる非特許文献1の貫通電極付きガラスウエハの仕様との比較を示す表である。

Figure 2014093406
Table 1 is a table showing a comparison between the specification of the wiring substrate with through electrodes according to the present invention and the specification of the glass wafer with through electrodes of Non-Patent Document 1 listed in the item of the prior art document described above.
Figure 2014093406

この比較結果から明らかなように、本発明においてはガラス基材に対する貫通孔の径が非特許文献1と比較して大きな径とすることにより加工性に優れたものとなり、かつガラス基材の表面に金属層13を内包することにより、配線基板30内部の熱伝導性が良くなり、放熱性に優れた貫通電極付き配線基板及びその製造方法を提供することができる。   As is apparent from this comparison result, in the present invention, the diameter of the through-hole with respect to the glass base material is larger than that of Non-Patent Document 1, so that the workability is excellent, and the surface of the glass base material By encapsulating the metal layer 13 in the wiring board, the thermal conductivity inside the wiring board 30 is improved, and a wiring board with a through electrode having excellent heat dissipation and a manufacturing method thereof can be provided.

よって、SiOを主成分とするガラス基材を用いた配線基板においては、加工性及び放熱性に優れた高機能で信頼性の高い貫通電極付き配線基板及びその製造方法を提供することができる。 Therefore, in a wiring board using a glass base material containing SiO 2 as a main component, it is possible to provide a highly functional and highly reliable wiring board with a through electrode excellent in workability and heat dissipation and a method for manufacturing the wiring board. .

本発明による製造方法を用いることにより、3次元実装における電子機器の高機能化、高速化に対応可能なインターポーザ基板の製造方法に利用して有用なものと期待できる。   By using the manufacturing method according to the present invention, it can be expected to be useful for a method of manufacturing an interposer substrate that can cope with higher functions and higher speeds of electronic devices in three-dimensional mounting.

なお、前記実施の形態は、一例として提示したものであり、発明の範囲を限定することは意図していない。前記各実施の形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施の形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   In addition, the said embodiment is shown as an example and is not intending limiting the range of invention. Each of the embodiments described above can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10…貫通電極付き配線基板、11(11a,11b,11c)…貫通孔、12…ガラス基材、13…金属層、14…絶縁層、15…貫通電極、16…レジスト、21…絶縁板、22´…導体層、22…回路配線,23´…導体層、23…回路配線、24…貫通電極、25…絶縁層、26,27…貫通孔。   DESCRIPTION OF SYMBOLS 10 ... Wiring board with a through-electrode, 11 (11a, 11b, 11c) ... Through-hole, 12 ... Glass base material, 13 ... Metal layer, 14 ... Insulating layer, 15 ... Through-electrode, 16 ... Resist, 21 ... Insulating plate, 22 '... conductor layer, 22 ... circuit wiring, 23' ... conductor layer, 23 ... circuit wiring, 24 ... through electrode, 25 ... insulating layer, 26, 27 ... through hole.

Claims (7)

SiOを主成分とするガラス基材を用いた配線基板において、
前記ガラス基材に形成された複数の貫通孔と、
この貫通孔を含むガラス基材の表面に形成された所定厚さの金属層と、
この金属層の表面に形成され、後記する貫通電極からのリーク電流防止用の所定厚さを有する絶縁層と、
前記貫通孔部分に形成された導電性物質からなる前記貫通電極と
を備えたことを特徴とする貫通電極付き配線基板。
In a wiring board using a glass substrate mainly composed of SiO 2 ,
A plurality of through holes formed in the glass substrate;
A metal layer having a predetermined thickness formed on the surface of the glass substrate including the through hole;
An insulating layer formed on the surface of the metal layer and having a predetermined thickness for preventing leakage current from a through electrode to be described later;
A wiring substrate with a through electrode, comprising: the through electrode made of a conductive material formed in the through hole portion.
前記金属層の熱伝導率は、10W・m−1・K−1〜400W・m−1・K−1の範囲内であることを特徴とする請求項1に記載の貫通電極付き配線基板。 The thermal conductivity of the metal layer, with a through hole electrode wiring board according to claim 1, characterized in that in the range of 10W · m -1 · K -1 ~400W · m -1 · K -1. 前記貫通電極の主材料は、Cu,Ag,Au,Ni,Pt,Pd,Ru,Feの何れか一種またはこれらの金属を含む合金の何れか一種であることを特徴とする請求項1または請求項2に記載の貫通電極付き配線基板。   The main material of the through electrode is any one of Cu, Ag, Au, Ni, Pt, Pd, Ru, Fe, or any one of alloys containing these metals. Item 3. A wiring board with through electrodes according to Item 2. 請求項1ないし請求項3の何れか一項に記載の貫通電極付き配線基板において、
前記配線基板の片面または両面に取り付けられ、絶縁基材に貼り付けた導体層に所望の回路構成が形成され、かつ前記配線基板から露出される前記貫通電極に接続するための貫通電極を設けた配線板を、さらに備えたことを特徴とする貫通電極付き配線基板。
In the wiring board with a penetration electrode according to any one of claims 1 to 3,
A desired circuit configuration is formed on a conductor layer attached to one or both sides of the wiring board and attached to an insulating base material, and a through electrode for connecting to the through electrode exposed from the wiring board is provided. A wiring board with a through electrode, further comprising a wiring board.
請求項4に記載の貫通電極付き配線基板において、
前記配線板の表面に半導体素子を搭載してなることを特徴とする貫通電極付き配線基板。
In the wiring board with a penetration electrode according to claim 4,
A wiring board with a through electrode, wherein a semiconductor element is mounted on the surface of the wiring board.
SiOを主成分とするガラス基材を用いた配線基板の製造方法において、
前記ガラス基材に複数の貫通孔を形成する孔形成工程と、
この孔形成工程で形成された貫通孔を含む前記ガラス基材の面部に所定厚さの金属層を形成する工程と、
この工程で形成された金属層の面部にリーク電流防止用の所定厚さの絶縁層を形成する工程と、
前記貫通孔以外の部分にレジストを形成する工程と、
前記貫通孔に導電性物質を充填、または埋め込んで貫通電極とする工程と、
前記レジストを剥離する工程と
を含むことを特徴とする貫通電極付き配線基板の製造方法。
In the manufacturing method of a wiring substrate using the glass substrate mainly composed of SiO 2,
A hole forming step of forming a plurality of through holes in the glass substrate;
A step of forming a metal layer having a predetermined thickness on the surface portion of the glass substrate including the through hole formed in the hole forming step;
Forming an insulating layer having a predetermined thickness for preventing leakage current on the surface of the metal layer formed in this step;
Forming a resist in a portion other than the through hole;
A step of filling or filling the through hole with a conductive material to form a through electrode;
And a step of peeling the resist. A method of manufacturing a wiring substrate with a through electrode.
請求項6に記載の貫通電極付き配線基板の製造方法において、
絶縁基材に導電性の回路配線を施した配線板を形成する工程と、
この配線板の所定の位置に形成される貫通孔に導電性物質を充填、または埋め込んで貫通電極を形成する工程と、
前記配線基板の片面または両面から露出する貫通電極に対して、前記配線板の貫通電極を位置決めして接続する工程とを、さらに含むことを特徴とする貫通電極付き配線基板の製造方法。
In the manufacturing method of the wiring board with a penetration electrode according to claim 6,
Forming a wiring board with conductive circuit wiring on an insulating substrate;
A step of forming a through electrode by filling or embedding a conductive substance in a through hole formed at a predetermined position of the wiring board;
A method of manufacturing a wiring board with through electrodes, further comprising the step of positioning and connecting the through electrodes of the wiring board to the through electrodes exposed from one or both sides of the wiring board.
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