WO2016093769A1 - Fil de cuivre (cu) revêtu destiné à des applications de connexion - Google Patents

Fil de cuivre (cu) revêtu destiné à des applications de connexion Download PDF

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Publication number
WO2016093769A1
WO2016093769A1 PCT/SG2015/000143 SG2015000143W WO2016093769A1 WO 2016093769 A1 WO2016093769 A1 WO 2016093769A1 SG 2015000143 W SG2015000143 W SG 2015000143W WO 2016093769 A1 WO2016093769 A1 WO 2016093769A1
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WIPO (PCT)
Prior art keywords
wire
core
coating layer
range
bonding
Prior art date
Application number
PCT/SG2015/000143
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English (en)
Inventor
Jin Zhi LIAO
Murali Sarangapani
Ping Ha Yeung
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Heraeus Materials Singapore Pte., Ltd.
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Publication date
Application filed by Heraeus Materials Singapore Pte., Ltd. filed Critical Heraeus Materials Singapore Pte., Ltd.
Publication of WO2016093769A1 publication Critical patent/WO2016093769A1/fr

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Definitions

  • the present invention relates to a wire which has an average diameter in the range of from 8 to 80 ⁇ , wherein the wire comprises at least a core with a surface, a first coating layer with a layer surface and a further coating layer, wherein A) the core comprises copper and elemental phosphorus; B) the first coating layer is composed of at least one element selected from the group comprising of palladium, platinum and silver, wherein the first coating layer is superimposed over the surface of the core; C) the further coating layer is superimposed over the layer surface of the first coating layer of core; wherein the further coating layer is composed of at least one element selected from silver and gold and wherein the composition of the further coating layer is different from the composition of the first coating layer; characterized in that at least one, two, three or all of the following conditions are met: Al) the ratio of the average grain size of the crystal grains in the core, measured in longitudinal direction, and the diameter of the wire is in the range of from 0.14 - 0.28 ( ⁇ / ⁇ ), and the relative standard deviation of the average grain size is less than
  • Bonding wires are used in the manufacture of semiconductor devices for electrically intercon- necting an integrated circuit and a printed circuit board during semiconductor device fabrication. Further, bonding wires are used in power electronic applications to electrically connect transistors, diodes and the like with pads or pins of the housing. While bonding wires were made from gold in the beginning, nowadays less expensive materials are used such as copper. While copper wire provides very good electrical and thermal conductivity, ball-bonding as well as wedge-bonding of copper wire has its challenges. Moreover, copper wires are susceptible to oxidation. With respect to wire geometry, most common are bonding wires of circular cross-section and bonding ribbons which have a more or less rectangular cross-section. Both types of wire geometries have their advantages making them useful for specific applications.
  • bonding ribbons have a larger contact area for a given cross-sectional area.
  • bending of the ribbons is limited and orientation of the ribbon must be observed when bonding in order to arrive at acceptable electrical contact between the ribbon and the element to which it is bonded.
  • bonding wires these are more flexible to bending.
  • bonding involves either welding and/or larger deformation of the wire in the bonding process, which can cause harm or even destroy the bonding pad and underlying electric structures of the element, which is bonded thereto.
  • copper is chosen because of high electric conductivity.
  • the coating layer palladium is a possible choice.
  • Another object of the invention is to provide a bonding wire which has good processing properties and which has no specific needs when interconnecting. Another object of the invention is to provide a bonding wire which has excellent electrical and thermal conductivity.
  • Another object of the invention is to provide a bonding wire which exhibits an improved reliability.
  • Another object of the invention is to provide a bonding wire which shows an improved bonda- bility with respect to a second bonding which is a stitch bonding, whilst the bonding performance for a first bonding which was a ball bonding is at least sufficient.
  • Another object of the invention is to provide a bonding wire which has improved resistance to corrosion and/or oxidation.
  • Another object of the invention is to provide a system for bonding an electronic device, which can be used with standard chip and bonding technology, which system shows reduced failure rate at least with respect to a second bonding.
  • Another object of the invention is to provide a method for manufacturing an inventive bonding wire, whereby the method basically shows no increase in manufacturing costs compared with known methods.
  • the wires of the present invention have been found to solve at least one of the objects men- tioned above. Further, a process for manufacturing these wires has been found which overcomes at least one of the challenges of manufacturing wires. Further, electric devices comprising the wires of the invention were found to be more reliable, both at the interface between the wire according to the invention and other electrical elements, e.g., the printed circuit board, the pad/pin etc., as well at interfaces within the electric devices, where bonding wires are connect- ed to other electric or electronic parts thus constituting the electric device.
  • a first aspect of the invention is a wire, comprising of at least a core with a surface, a first coating layer with a layer surface and a further coating layer, wherein A) the core comprises copper and elemental phosphorus;
  • the first coating layer is composed of at least one element selected from the group comprising of palladium, platinum and silver,
  • first coating layer is superimposed over the surface of the core
  • the further coating layer is superimposed over the layer surface of the first coating layer of core; wherein the further coating layer is composed of at least one element selected from silver and gold and
  • composition of the further coating layer is different from the composition of the first coating layer
  • the wire has an average diameter in the range of from 8 to 80 ⁇ ;
  • the ratio of the average grain size of the crystal grains in the core, measured in longitudinal direction, and the diameter of the wire is in the range of from 0.14 to 0.28 ( ⁇ / ⁇ ), more preferred in the range of from 0.17 to 0.24, or in the range from 0.17 to 0.20, and the relative standard deviation (RSD) of the average grain size is less than 0.9; or
  • the degree of recrystalhzation of the crystal grains in the core, measured in longitudinal direction, is in the range of from 50 to 95 %, more preferred in the range offrom 80 to 90%; or
  • the fraction of twin boundaries, measured in longitudinal direction, is in the range of from 2 to 25 %, more preferred in the range of from 15 to 20 %; or
  • A4) 18 to 42 % of the grains of the wire are oriented in ⁇ 100> direction and 27 to 38 % of the grains of the wire are oriented in ⁇ 111> direction, each % with respect to the total number of crystals with orientation parallel to the drawing direction of the wire. Yet more preferred are 35 to 42 % of the grains of the wire are oriented in ⁇ 100> direction and 30 to 38 % of the grains of the wire are oriented in ⁇ 111> direction. Grains of the wire are oriented in the specified direction if the direction of the crystal grains deviates less than from -15° to +15°, whereby drawing direction of the wire was used as reference orientation.
  • the ⁇ 100> and ⁇ 111> texture percentages were calculated by counting the number of crystals with ⁇ 100> and the number of crystals with ⁇ 111> orientation. These numbers were divided by the sum of both ⁇ 100> and ⁇ 111>, since usually no crystal grains with orientation ⁇ 010> were identified.
  • the wire is preferably a bonding wire for bonding in microelectronics.
  • the wire is preferably a one-piece object. Numerous shapes are known and appear useful for wires of the present invention. Preferred shapes are - in cross-sectional view - round, ellipsoid and rectangular shapes.
  • RSD standard deviation(x) /arithmetic mean (x).
  • a "twin boundary" in the context of the present invention separates the two crystals grains or a domain with sheared lattice within a grain in the wire core, where, a 60° rotation about ⁇ 111> plane of orientation between the neighboring crystallographic domains or grains.
  • Recrystallization in the context of the present invention describes a modification of the crystals' arrangement in the copper wire during annealing. In this stage of annealing, new strain- free grains nucleate and grow to replace those deformed grains by residual stresses.
  • the degree of recrystallization refers to the amount of recrystallized grains with respect to the total number of grains.
  • first item e.g. a copper core
  • second item e.g. a coating layer
  • “Superimposed” characterizes, that further items, such as an intermediate layer, can - but no need to be arranged between the first and the second item.
  • the second item is at least partially superimposed over the first item, e.g. for at least 30 %, 50 %, 70 % or for at least 90 %, each with respect to the total surface of the first item. Most preferably, the second item is completely superimposed over the first item.
  • intermediate layer in the context of this invention refers to a region of the wire between the copper core and the coating layer. In this region, a combination of materials of both, the core and the coating layer, is present.
  • thickness in the context of this invention is used to define the size of a layer in perpendicular direction to the longitudinal axis of the copper core, which layer is at least partially superimposed over the surface of copper core.
  • bonding wire comprises all shapes of cross-sections and all usual wire diameters, though bonding wires with circular cross-section and thin diameters are preferred.
  • Such thin wires mostly, but not necessarily have a cross-sectional view essentially in the shape of a circle.
  • a cross-sectional view in the present context refers to a view of a cut through the wire, wherein the plane of the cut is perpendicular to the longitudinal extension of the wire.
  • the cross-sectional view can be found at any position on the longitudinal extension of the wire.
  • a "longest path” through the wire in a cross-section is the longest chord which can be laid through the cross-section of the wire within the plane of the cross-sectional view.
  • a "shortest path” through the wire in a cross-section is the longest chord perpendicular to the longest path within the plane of the cross-sectional view defined above.
  • the longest path and the shortest path become indistinguishable and share the same value.
  • the term "diameter” is the arithmetic mean of all geometric diameters of any plane and in any direction, wherein all planes are perpendicular to the longitudinal extension of the wire.
  • the core of the wire in the present context is defined as a homogenous region of bulk material. Since any bulk material always has a surface region which might exhibit different properties to some extent, the properties of the core of the wire are understood as properties of the homogeneous region of bulk material.
  • the surface of the bulk material region can differ in terms of morphology, composition (e.g. oxygen content) and other features.
  • the surface can be an outer surface of the inventive wire in preferred embodiments.
  • the surface of the wire core can be an interface region between the wire core and a coating layer superimposed on the wire core.
  • a preferred embodiment of the invention is a wire as described above, wherein at least one, two or all of the following conditions is met:
  • the amount of copper in core is at least 99.95 wt.%; or in the range of from 99.98 to 99.95 wt.%, or in the range of from 99.98 to 99.99 wt.%; usually, the amount of copper in the core is not more than 99.995 wt.%.
  • a copper content as defined in this section allows for using common supplies of copper material for wire bonding without exceedingly high costs due to high purity specifications.
  • the amount of elemental phosphorus in core is in the range of from 20 to 300 ppm, yet more preferred in the range of from 20 to 100 ppm, or from 40 to 80 ppm, each based on the total weight of the core; or
  • the amount of elemental silver in core is in the range of from 2 to 250 ppm, yet more preferred in the range of from 2 to 50 ppm, or in the range of from 2 to 15 ppm,
  • the core of the wire of the invention comprises in total in the range of from 0 to 100 ppm, preferably less than 30 ppm, of further components.
  • the low amount of these further components ensures a good reproducibility of the wire properties.
  • the further components often also referred as "inevitable impurities" are minor amounts of chemical elements and/or compounds which originate from impurities present in the raw materials used or from the manufacturing process which produced the wire. Examples of such further components are: i, Mn, Pt, Cr, Ca, La, Al, B, Zr, Ti, Fe.
  • Further components present in the core are usually not added separately. The presence of the further components originates from impurities present in one or more of components a), b) and c).
  • the core of the wire of the invention comprises less than the following amounts of further components:
  • a further preferred embodiment of the invention is a wire, wherein the first coating layer has a thickness in the range of from 40 nm to less than 0.5 ⁇ , preferably in the range of from 40nm to 200nm, or in the range of from 40 nm to 80 nm.
  • the first coating layer is composed of palladium
  • a further embodiment of the in- vention has first a coating layer which has a thickness of less than 0.5 ⁇ . Yet more preferred, further coating layer has a thickness of less than 0.05 ⁇ .
  • a sufficiently thin further coating layer causes only little changes to most properties of the overall wire. However, some properties are remarkably improved, in particular regarding the bonding process.
  • the palladium content of the layer is at least 50 wt.%, more preferably at least 95 wt.%, each wt.% based on the total weight of the first coating layer.
  • the coating layer consists of pure palladium. Pure palladium usually has less than 1 wt.% of further components, with regard to the total amount of palladium in the first coating layer.
  • the further compo- nents present in the first coating layer are noble metals.
  • the further coating layer of the wire has a thickness in the range of from 1.0 nm to less than 50 mn, preferably in the range of from 1.0 nm to 40 mn, or from 1.0 nm to 25 nm.
  • the core of the wire has a content of silver or gold in the range of 5 ppm to 10000 ppm, preferably in the range of 5 ppm to 1000 ppm, yet more preferred in the range of 200 ppm to 250 ppm. It was observed that the presence of at least small amounts of silver improves the mechanical properties, e.g. awards some softness to the wire.
  • the content of the at least one element in the further coating layer on the wire is at least 50 wt.%, more preferably at least 95 wt.%, each based on the total amount wt.% of the further coating layer.
  • the further coating layer consists of pure gold or pure silver. Pure gold usually has less than 1 wt.% of further components, with regard to the total amount of gold in the further coating layer.
  • a second aspect of the invention is a method for manufacturing a wire, comprising at least the steps of
  • composition of the further coating layer is different from the composition of the first coating layer
  • step iv. drawing the coated core precursor obtained from step iv. to a final diameter of 8-80 ⁇ ;
  • the wire (1) has an average diameter in the range of from 8 to 80 ⁇ ,
  • the ratio of the average grain size of the crystal grains in the core, measured in longitudinal direction, and the diameter of the wire is in the range of from 0.14 - 0.28 ( ⁇ / ⁇ ), more preferred in the range of from 0.17 to 0.24, or in the range from 0.17 to 0.20, and the relative standard deviation RSD of the average grain size is less than 0.9; or
  • the degree of recrystallization of the crystal grains in the core, measured in longitudinal direction, is in the range of from 50 to 95 %%, more preferred in the range of from 80 to 90%; or
  • the fraction of twin boundaries, measured in longitudinal direction, is in the range of from 2 to 25 %, more preferred in the range of from 15 to 20 %; or
  • 18 to 42 % of the grains of the wire are oriented in ⁇ 100> direction and 27 to 38 % of the grains of the wire are oriented in ⁇ 111> direction, each % with respect to the total number of crystals with orientation parallel to the drawing direction of the wire (1). Yet more preferred are 35 to 42 % of the grains of the wire are oriented in ⁇ 100> direction and 30 to 38 % of the grains of the wire are oriented in ⁇ 111> direction. Grains of the wire are oriented in the specified direction if the direction of the crystal grains deviates less than from -15° to +15°, whereby drawing direction of the wire was used as reference orientation.
  • the ⁇ 100> and ⁇ 1 11> texture percentages were calculated by counting the number of crystals with ⁇ 100> and the number of crystals with ⁇ 111> orientation. These numbers were divided by the sum of both ⁇ 100> and ⁇ 1 11>, since usually no crystal grains with orientation ⁇ 010> were identified.
  • a precursor item as in step i. can be obtained by doping copper with an amount of elemental phosphorus, optionally by doping with further elements. Doping can be realized by producing a melt of said components and copper and cooling the melt to form a homogeneous piece of copper based precursor item.
  • the annealing of the product in step vi. of the method is performed at a temperature of at least 400 °C, preferably of at least 430 °C, or of at least 540 °C.
  • Higher annealing temperatures can provide for higher values for the elongation of the wire.
  • a third aspect of the invention is a method for connecting an electrical device, comprising the steps of
  • step II bonding the wire provided in step I. to a first bond pad of the device by either ball bonding or wedge bonding;
  • step III bonding the wire of step I. which is bonded to a first bond pad to a second bond pad of the device by wedge bonding;
  • step III. is performed without the use of a forming gas
  • step II. is performed in presence of an inert gas or fonning gas.
  • the wire is bonded in step II. by ball bonding and in step III. by wedge bonding.
  • Wires according to the third aspect of the invention or to the embodiment thereto have excellent properties with respect to oxidation effects. Even better protection against oxidation of the copper core is achieved by complete encapsulation of the core with thin gold over palladium coating layers are present in combination with a certain amount of silver and/or phosphorous in the core material.
  • the resulting properties allow for processing the wire by purging forming gas and hence lead to clean, axi-symmetrical free air ball form.
  • Forming gas is known in the art as a mixture of an inert gas like nitrogen with hydrogen, wherein the hydrogen content may provide for reduction reactions of oxidized wire material. In the sense of the invention, omit- ting of forming gas means that no reactive compounds like hydrogen is used. Nevertheless, use of an inert gas like nitrogen can still be advantageous.
  • a fourth aspect of the invention is a method for manufacturing a wire according to the invention, comprising the steps;
  • step b drawing the precursor
  • the manufacturing method is generally known in the art. It is pointed out that the coating layer might be applied by any known or suitable method like mechanical coating, electrolytic plating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD) and more.
  • the coating can be done before or after the drawing of the wire, which may be dependent on properties of the respective coating and coating method. In particular, the coating might be performed at an intermediate step, with a drawing of the wire or precursor occurring before as well as after the coating step.
  • annealing is performed in a controlled way as known in the art in order to achieve a softening of the wire and/or optimizing the crystal structure of the wire according to the respective demands.
  • the annealing is done dynamically while the wire is moved through an annealing oven and wound onto a spool after having left the oven.
  • a fifth aspect of the invention is an electrical device comprising a first and a second bonding pad, and a wire according to the first aspect of the invention or an embodiment thereto, or a wire obtained by a method according the second aspect of the invention or one of the embodi- ments thereto, wherein the wire is connected to at least one of the bonding pads using ball- wedge bonding.
  • An electric device in the present context includes electronic devices. Electronic devices are those which comprise semiconducting elements.
  • An embodiment of the fifth aspect is an electrical device, wherein the wire is connected to both pads by ball-wedge bonding.
  • a sixth aspect of the invention is a system for bonding an electronic device, comprising a first bond pad, a second bond pad and a wire according to the invention, wherein the wire is con- nected to at least one of the bonding pads by means of stitch-bonding.
  • This combination of an inventive wire in a system is preferred due to the fact that the wire has especially beneficial properties with respect to stitch bonding.
  • the process window for the at least one stitch bond to a gold bond pad has a value of at least 10450 mA*g for a wire which has a diameter of 18 ⁇ .
  • a process window area for bonding wires is known in the art and is widely used to compare different wires. In principle, it is the product of a bonding window of an ultrasonic energy used in the bonding and a bonding window of a force used in the bonding, wherein the resulting bond has to meet certain pull test specifications, e.g. a pull force of 2.5 grams, no non-stick on lead etc..
  • the actual value of the process window area of a given wire further depends on the wire diameter as well as the bond pad material.
  • the scope an inventive system is not limited to wires of this diameter and bond pads made of gold, but names this data only for definition purpose. DESCRIPTION OF THE FIGURES
  • Figure 2 shows a cross sectional view of wire 1.
  • a copper core 2 is in the middle of the cross sectional view.
  • the copper core 2 is encompassed by a palladium coating layer 3.
  • the palladium coating layer 3 is . encompassed by a thin gold coating layer 41.
  • On the limit of copper wire 2 a surface 15 of the copper core is located.
  • On the limit of palladium coating 3, a surface 42 of the palladium coating is located.
  • On a line L through the centre 23 of wire 1 the diameter of copper core 2 is shown as the end to end distance between the intersections of line L with the surface 15.
  • the diameter of wire 1 is the end-to-end distance between the intersections of line L through the centre 23 and the outer limit of wire 1.
  • thickness of coating layer 3 and 41 are depicted.
  • Figure 3 shows a process for manufacturing a wire according to the invention.
  • Figure 4 depicts an electric device 10 comprising two elements 11 and a wire 1.
  • the wire 1 electrically connects the two elements 11.
  • the dashed lines mean further connections or circuitry which connects the elements 11 with external wiring of a packaging device surrounding the elements 11.
  • the elements 11 can comprise bond pads, lead fingers, integrated circuits, LEDs or the like.
  • Figure 5 depicts an annealing curve of a 0.7 mil wire. Pieces of this wire were annealed at different annealing temperatures. The value of elongation in %, based on the length of the wire before annealing, was recorded as a function of annealing temperature. Region A denotes start- ing of recrystallization; region B denotes stalling of grain growth; region C denotes starting of over annealing.
  • Figure 6 depicts four items: item (a) is an inverse pole figure map. This map illustrates orientation of the grains to certain plane by the color contrast defined by color key, whereby angles are determined in longitudinal direction of the wire core.
  • the copper wire is expected to be oriented to three main plane of direction [1 11], [101], [100].
  • Low-angle grain boundaries (LAGBs) have angles in the range of from 2° ⁇ ⁇ ⁇ 10°
  • High-angle grain boundaries have angles in the range of from 10° ⁇ ⁇ .
  • Twin boundaries (TBs) are present when ⁇ l l l> is > 60°.
  • Item (b) is a grain boundary map. This map illustrates the presence of grain boundaries. Boundaries in grey lines are low-angle grain boundaries and boundaries in light grey lines are twin boundaries. Dark grey lines represent high-angle grain boundaries.
  • Item (c) is an inverse pole figure. This figure illustrates orientation of the grains to certain plane as dots, more the number of dots, more the grains are highly oriented to the plane of direction, whereby angles are determined in longitudinal direction of the wire core.
  • the copper wire is expected to be oriented mainly by the three plane of direction ⁇ 11 1>, ⁇ 101>, ⁇ 100>.
  • Item (d) is a color key of a 0.7mil finished Cu wire. Color key defines the color for each plane of orientation (the three main direction ⁇ 111>, ⁇ 101>, ⁇ 100> which and to be reflected by each grain color and its orientation in the cross-sectioned wire core along the longitudinal di- rection.
  • Figure 7 shows a chart reflecting the grain size distribution of a 0-7 mil Cu wire.
  • Figure 8 consists of three items.
  • Item (a) is a recrystaUization map. Dark areas represent re- crystallized grains, light areas are sub-structured and deformed crystal grains. Black lines are boundaries between crystal grains.
  • Item (b) is recrystaUization a chart providing quantitative data on fractions of a 0.7mil finished Cu wire. "Finished" means that the final wire was drawn and annealed. Measurements were recorded in respect of the wire longitudinal direction. According to the chart, about 85 % of the crystal grains investigated by the measurement were recrystallized and about 15 % of the crystal grains were sub-structured. About 1 % of the crystal grains was defonned.
  • Defonned crystal grains describe a situation usually found in an un-annealed drawn wire (without high temperature annealing), in which highly oriented crystals are present along the defonnation direction (wire axis). Some "deformed" crystal grains may remain after annealing.
  • Figure 9 consists of 2 items.
  • Item (a) is a grain boundary map ⁇ see figure 6 (a)).
  • Item (b) is chart showing the mis-orientation angle distribution of a 0,7mil finished (final wire drawn and annealed) Cu wire. According to the chart, the degree of mis-orientation is for most angles between 1 and 3 %. The mis-orientation is 20 % for an angle of 2° and about 16 % for an angle of 60°. Measurements were recorded in respect of the wire longitudinal direction.
  • the invention is further exemplified by examples. These examples serve for exemplary elucidation of the invention and are not intended to limit the scope of the invention or the claims in any way.
  • ⁇ 111> texture percentages were calculated by measurement of the percentage of crystals with ⁇ 100> and ⁇ 111> orientation parallel to the reference orientation. Commonly ⁇ 010> component was absent. Grain sizes were analyzed defining the crystallographic orientation between neighboring grid points of greater than a minimum, herein 10°, to determine the position of grain boundaries. The EBSD software calculated the area of each grain and converted it to equivalent circle diameter, which is defined as "crystal grain size". All the grains along the longitudinal direction of the wire within a length of ⁇ 100 ⁇ were counted to determine mean and standard deviation of the crystal grain size.
  • Twin boundaries also called ⁇ 3 CSL twin boundaries
  • the twin boundary was described by a 60° rotation about ⁇ 111> plane of orientation between the neighboring crystallographic domains.
  • the degree of recrystallization of the annealed wire was also measured using the EBSD soft- ware.
  • the software measured the maximum mis-orientation between any two points in a grain and then weights the grain according to the mis-orientation value.
  • the average mis-orientation was defined as ⁇ . This was a pixel-based measurement that computed the average of the mis- orientation between a given point/pixel and its first nearest neighbor points. The number of points depends on the step size, which was less than 1/5 of the average crystal grain size.
  • the wire micro-structure was classified into three types: 1) deformed, 2) sub-structured and 3) recrystallized grain.
  • the grain When there were no sub-grains and the average mis-orientation within the grain was > 2°, the grain was defined as deformed.
  • the average mis-orientation was ⁇ 2°, and the mis-orientation between every sub-grain was > 2°, the grain- structure was defined as sub-structure.
  • rest of the wire grain structure was defined as recrystallized grain.
  • the deformed regions were strongly mis-oriented.
  • the recrystallized regions were strain f ee, and the majority revealed high angle recrystallization boundaries.
  • Copper of 4N purity was used to prepare the alloys and was melted in a vacuum induction furnace. Phosphorus was added into the melt using Cu-0.5wt%P master alloy (composition of Cu- 0.5 wt%P alloy: 99.5 wt.% Cu and 0.5 wt.% P). The melt was held for few minutes to allow a thorough dissolution. The alloy was continuously cast into 2 to 25mm rods at slow speed. No significant loss in dopant addition was observed. These rods were wire drawn at room temperature (25°C). Tungsten carbide die was used to draw heavy wire and a diamond die was used for further reduction. It was drawn in two stages at a drawing speed of 15m s or less. The die reduction ratio was around 14 to 18% for thick wires and 4 to 12% for thin size. During cold drawing, the wires were lubricated.
  • the thin wires with a diameter of 6 to 15mil were in-line degreased, palladium electroplated and then gold electroplated, finally washed and spooled for finishing wire drawing.
  • the wire speed was maintained at 5 to 25m/min., voltage applied was between IV and 8V and the current applied was from 0.05 to 5 A.
  • the pH of palladium plating bath was maintained between 7 to 10 and gold plating was maintained at pH in the range from 4 to 6.
  • the plating was processed at 40 to 60°C.
  • the electroplated wires were drawn to final size 0.5 to 2mil. Finally, the drawn wires were strand annealed, spooled on clean anodized (plated) aluminum spools, vacuum packed and stored.
  • the ratio of the average grain size of the crystal grains in the core and the diameter of the wire was in the range of 0.14 to 0.28 and with standard deviation of ⁇ 0.9. This was achieved by annealing the wire in the temperature range of 470 to 520°C (example: see Figure 5 for a 0.7 mil wire). The average crystal grain size ratio in the outer range of the above mentioned values was achieved by annealing the wire in the range of 420 to 470°C. 3. Ball-wedge Bonding Parameter Definition
  • Wires were bonded using a KNS-iConn bonder. Bonding of a wire to a plated surface was performed at 20°C. First the free air ball was formed by electric flame off firing for varying cur- rent in the range 3 to 5V. Further, the free air ball was bonded to bond pad on the ICs (integrated chips). Most of the bond pads were metallized with the composition Al-0.5Cu (99.5 wt.% Al and 0.5 wt.% Cu). Some bond pads were metallized with gold surface. After forming a first ball bond between the wire and the bond pad, the wire was stitched (wedged) with its second end to the substrate lead fingers wherein the bonding was applied to the gold finger surface in BGA substrate, silver finger surface in lead frame.
  • Some lead finger surface was plated with palladium or nickel, too.
  • the distance of the bonds between the two ends of the wire was in the range of from 5 mm to 20 mm. This distance was selected in order to assure the angle of 45° between the wire and the substrate in wedge.
  • ul- trasonic sound of a frequency in the range of 60 - 140 kHz was applied to the bond tool for 40 to 500 milliseconds.
  • the bonded wires were observed in LEO- 1450 VP scanning electron microscope (SEM) for good looping, first bond neck area, second bond heel and stitch, tool mark, etc. 4.
  • the electric flame off (EFO) current and time defines the specification of the FAB.
  • EFO electric flame off
  • the tip of the fractured Cu wire melts and form axi-symmetrical spherical FAB, further stitch the wire on lead frame such that FAB stand on air. This mode of bonding was referred to as cherry pits.
  • the procedures are described in the NS Process User Guide for Free Air Ball (Kulicke & Soffa Industries Inc, Fort Washington, PA, USA, 2002, 31 May 2009).
  • the FAB diameter was measured using optical microscope at 200X to 500X magnification in micron scale. Morphology of the FAB was observed using scanning electron microscope (SEM). 5. Process window area
  • Measurements of ball-bonding process window area were done by standard procedure.
  • the test wires were bonded using a KNS-iConn bonder tool (Kulicke & Soffa Industries Inc, Fort Washington, PA, USA).
  • the definition of a 2 nd bond process window area for bonding wires was known in the art and was widely used to compare different wires. In principle, it is the product of scrub amplitude and force used in the bonding, wherein the resulting bond has to meet certain pull test specifications, e.g. a pull force of 2.5 grams, no non-stick on lead etc..
  • the actual value of the 2 nd bond process window area of a given wire further depends on the wire diameter as well as the lead finger plated material.
  • the four corners of the process window were derived by overcoming the two main failure modes:
  • a typical ICP analysis of sample 1 and a comparative sample wires are provided in the Table.1.
  • Samplel core material is doped with "P".
  • Predicted thickness of Au flash of the wire is close to about 3nm.
  • Predicted thickness of Pd coating of the wire is about 63nm.
  • the inventive wire samplel revealed wide 2 nd bond window of 10450mA*g which is quite high (Table.l) compared to bare 4N Cu of about 8100mA*g.
  • a competitor wire with composition close to samplel has also showed wide 2 nd bond window (comparative sample).
  • Table 1 ICP analysis and second bond process window of 0.7mil wires
  • the wire grain morphol- ogy and size were calculated.
  • the CSL ⁇ 3 boundaries also referred to as: twin boundaries
  • the crystal grain size has a normal distribution ( Figure 7).
  • the average crystal grain size is around 3.49 ⁇ , and the standard deviation is around 3.05 ⁇ .
  • Ratio of the average grain size of the crystal grains in the core and the diameter of the wire is in the range of 0.14 - 0.28, preferably 0.17 - 0.24, and wherein the relative standard deviation RSD is less than 0.9. (see Figure 7, measured in the longitudinal direction).
  • Example2
  • FIG 8 A typical recrystallization map of samplel drawn and annealed wire is shown in Figure 8, measured in the longitudinal direction.
  • the recrystallization fraction of the crystal grains in the core is more than 50 % ( Figure 8b).
  • a wire (1) comprising of at least a core (2) with a surface (21), a first coating layer (3) with a layer surface (31) and a further coating layer (4), wherein
  • the core (2) comprises copper and elemental phosphorus
  • the first coating layer (3) is composed of at least one element selected from the group comprising of palladium, platinum and silver,
  • first coating layer (3) is superimposed over the surface (21) of the core (2);
  • the further coating layer (4) is composed of at least one element selected from silver and gold and
  • composition of the further coating layer (4) is different from the composition of the first coating layer (3);
  • wire (1) has an average diameter in the range of from 8 to 80 ⁇ ; characterized in that at least one, two, three or all of the following conditions are met:
  • Al the ratio of the average grain size of the crystal grains in the core, measured in longitudinal direction, and the diameter of the wire is in the range of from 0.14 - 0.28 ( ⁇ / ⁇ ), and
  • the relative standard deviation of the average grain size is less than 0.9; or A2) the degree of recrystallization of the crystal grains in the core, measured in longitudinal direction, is in the range of from 50 to 95 %; or
  • the fraction of twin boundaries, measured in longitudinal direction, is in the range of from 2 to 25 %;
  • the amount of copper in core (2) is at least 99.95 wt.%;
  • the amount of elemental phosphorus in core (2) is in the range of from 20 to 300 ppm, each based on the total weight of the core (2); or
  • the amount of elemental silver in core (2) is in the range of from 2 to 250 pm;
  • a method for manufacturing a wire (1) comprising at least the steps of
  • step iv. further coating with at least one element selected from silver and gold on the first coating layer (3) of the core precursor (2a) obtained in step iii.; whereby the composition of the further coating layer (4) is different from the composition of the first coating layer (3), whereby a further coating layer (4) is formed;
  • step iv. drawing the coated core precursor obtained from step iv. to a final diameter of 8-80 ⁇ ;
  • the wire (1) is obtained, wherein the wire (1) has an average diameter in the range of from 8 to 80 ⁇ ,
  • the ratio of the average grain size of the crystal grains in the core, measured in longitudinal direction, and the diameter of the wire is in the range of from 0.14 - 0.28 ( ⁇ / ⁇ ) and the standard deviation RSD of the average grain size is less than 0.9; or
  • the degree of recrystallization of the crystal grains in the core, measured in longitudinal direction, is in the range of from 50 to 95 %;
  • the fraction of twin boundaries, measured in longitudinal direction, is in the range of from 2 to 25 %;
  • step III. is performed without the use of a forming gas; and wherein step II. is performed in presence of an inert gas or forming gas.
  • An electrical device (10) comprising a first and a second bonding pad (11, 11), and a wire (1) according to any one of embodiments I) to IV), or a wire obtained by a method according to any one of embodiments V) to VI), wherein the wire (1) is connected to at least one of the bonding pads (11, 1 1) using ball-wedge bonding.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un fil et un procédé de fabrication, le fil comprenant au moins un noyau comprenant du cuivre (2) et du phosphore élémentaire ; une première couche de revêtement (3) composée d'au moins un élément choisi dans le groupe comprenant du palladium, du platine et de l'argent ; une couche de revêtement supplémentaire (41) composée d'au moins un élément choisi parmi l'argent et l'or ; au moins une des conditions suivantes étant satisfaite : A1) le rapport de la dimension moyenne des grains des grains cristallins dans le noyau et le diamètre du fil se situe dans la plage allant de 0,14 à 0,28 et le coefficient de variation CV de la dimension moyenne des grains est inférieur à 0,9 ; ou A2) le degré de recristallisation des grains cristallins dans le noyau est dans la plage de 50 à 95 % ; ou A3) la fraction des limites jumelées est dans la plage de 2 à 25 % ; ou A4) de 18 à 42 % des grains du fil sont orientés dans la direction <100> et de 27 à 38 % des grains du fil sont orientés dans la direction <111>.
PCT/SG2015/000143 2014-12-11 2015-12-11 Fil de cuivre (cu) revêtu destiné à des applications de connexion WO2016093769A1 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170250000A1 (en) * 2014-12-05 2017-08-31 Furukawa Electric Co., Ltd. Aluminum alloy wire rod, aluminum alloy stranded wire, covered wire and wire harness, and method of manufacturing aluminum alloy wire rod
WO2020101566A1 (fr) * 2018-11-16 2020-05-22 Heraeus Deutschland GmbH & Co. KG Fil enrobé
WO2022081080A1 (fr) * 2020-10-15 2022-04-21 Heraeus Materials Singapore Pte. Ltd. Fil revêtu
TWI818531B (zh) * 2021-05-05 2023-10-11 新加坡商新加坡賀利氏材料私人有限公司 塗佈圓線及其製造程序
WO2024058211A1 (fr) * 2022-09-16 2024-03-21 田中電子工業株式会社 Fil de liaison en cuivre, procédé de fabrication de fil de liaison en cuivre et dispositif à semi-conducteur

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2461358A1 (fr) * 2009-07-30 2012-06-06 Nippon Steel Materials Co., Ltd. Fil de connexion pour semi-conducteur
CN103219312A (zh) * 2013-03-01 2013-07-24 溧阳市虹翔机械制造有限公司 一种镀钯镀金的双镀层键合铜丝
SG191711A1 (en) * 2011-12-21 2013-08-30 Tanaka Electronics Ind Pd-coated copper ball bonding wire
WO2014137287A1 (fr) * 2013-03-05 2014-09-12 Heraeus Materials Singapore Pte. Ltd. Fil de cuivre revêtu de palladium destiné à des applications de collage

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201430977A (zh) * 2013-01-23 2014-08-01 Heraeus Materials Tech Gmbh 用於接合應用的經塗覆線材
EP2927955A1 (fr) * 2013-02-15 2015-10-07 Heraeus Materials Singapore Pte. Ltd. Fil de connexion en cuivre et méthode de sa production
SG2013016399A (en) * 2013-03-05 2014-10-30 Heraeus Materials Singapore Pte Ltd Coated copper wire for bonding applications

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2461358A1 (fr) * 2009-07-30 2012-06-06 Nippon Steel Materials Co., Ltd. Fil de connexion pour semi-conducteur
SG191711A1 (en) * 2011-12-21 2013-08-30 Tanaka Electronics Ind Pd-coated copper ball bonding wire
CN103219312A (zh) * 2013-03-01 2013-07-24 溧阳市虹翔机械制造有限公司 一种镀钯镀金的双镀层键合铜丝
WO2014137287A1 (fr) * 2013-03-05 2014-09-12 Heraeus Materials Singapore Pte. Ltd. Fil de cuivre revêtu de palladium destiné à des applications de collage

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170250000A1 (en) * 2014-12-05 2017-08-31 Furukawa Electric Co., Ltd. Aluminum alloy wire rod, aluminum alloy stranded wire, covered wire and wire harness, and method of manufacturing aluminum alloy wire rod
US10096394B2 (en) * 2014-12-05 2018-10-09 Furukawa Electric Co., Ltd. Aluminum alloy wire rod, aluminum alloy stranded wire, covered wire and wire harness, and method of manufacturing aluminum alloy wire rod
WO2020101566A1 (fr) * 2018-11-16 2020-05-22 Heraeus Deutschland GmbH & Co. KG Fil enrobé
WO2022081080A1 (fr) * 2020-10-15 2022-04-21 Heraeus Materials Singapore Pte. Ltd. Fil revêtu
US12084784B2 (en) 2020-10-15 2024-09-10 Heraeus Materials Singapore Pte. Ltd. Coated wire
TWI818531B (zh) * 2021-05-05 2023-10-11 新加坡商新加坡賀利氏材料私人有限公司 塗佈圓線及其製造程序
WO2024058211A1 (fr) * 2022-09-16 2024-03-21 田中電子工業株式会社 Fil de liaison en cuivre, procédé de fabrication de fil de liaison en cuivre et dispositif à semi-conducteur

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