WO2016092791A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

Info

Publication number
WO2016092791A1
WO2016092791A1 PCT/JP2015/006035 JP2015006035W WO2016092791A1 WO 2016092791 A1 WO2016092791 A1 WO 2016092791A1 JP 2015006035 W JP2015006035 W JP 2015006035W WO 2016092791 A1 WO2016092791 A1 WO 2016092791A1
Authority
WO
WIPO (PCT)
Prior art keywords
solder
oxide film
metal
semiconductor chip
thin film
Prior art date
Application number
PCT/JP2015/006035
Other languages
English (en)
Japanese (ja)
Inventor
英二 林
小林　渉
野村　英司
和輝 神田
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2015223330A external-priority patent/JP6578900B2/ja
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to US15/508,506 priority Critical patent/US10147671B2/en
Priority to DE112015005561.4T priority patent/DE112015005561B4/de
Priority to CN201580066323.3A priority patent/CN107004662B/zh
Publication of WO2016092791A1 publication Critical patent/WO2016092791A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/84001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8412—Aligning
    • H01L2224/84136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • a first conductive member is disposed on one surface side of a semiconductor chip via a metal member, an electrode formed on one surface and the metal member are connected by a first solder, and the metal member and the first conductive member are The present invention relates to a semiconductor device connected by a second solder and a manufacturing method thereof.
  • a first conductive member (second metal plate) is disposed on one surface side of a semiconductor chip (semiconductor element) via a metal member (block body), and an electrode formed on one surface; 2.
  • a semiconductor device is known in which a metal member is connected by a first solder and a metal member and a first conductive member are connected by a second solder.
  • the second conductive member (first metal plate) is disposed on the back surface side opposite to the one surface of the semiconductor chip, and the electrode formed on the back surface and the second conductive member are connected by the third solder.
  • the semiconductor chip is sealed with a sealing resin body (mold resin), and the surface of each conductive member opposite to the semiconductor chip is a heat radiating surface exposed from the sealing resin body.
  • the semiconductor device has a double-sided heat dissipation structure that can radiate the heat of the semiconductor chip to both sides.
  • the first solder disposed between the semiconductor chip and the metal member wets the surface of the metal member during reflow. There is a risk of spreading and flowing into the second solder side.
  • the second solder disposed between the metal member and the first conductive member may spread out on the surface of the metal member during reflow and flow into the first solder side.
  • the thermal stress becomes larger than the acute angle. For example, if the second solder flows into the first solder side and the amount of the first solder increases, there is a possibility that cracks may occur in the electrode due to thermal stress.
  • the semiconductor device having the above-described double-sided heat dissipation structure it is necessary to manage the distance between the heat dissipation surfaces in order to dispose the coolers on both sides. For this reason, in order to absorb the variation in the height of each component in the thickness direction of the semiconductor chip, reflow is performed with a larger amount of the second solder. Therefore, at the time of reflow, there is a possibility that the second solder wets and spreads the surface of the metal member and flows into the first solder side. That is, the angle formed between the first solder and the electrode on one surface may be an obtuse angle.
  • a semiconductor device in a first aspect of the present disclosure, includes a semiconductor chip having an electrode on one surface, a first conductive member disposed on one surface side of the semiconductor chip, a base material formed using a metal material, A coating formed on the surface of the base material, and a metal member interposed between the semiconductor chip and the first conductive member, and disposed between the electrode of the semiconductor chip and the metal member, A first solder that connects the electrode and the metal member; and a second solder that is disposed between the metal member and the first conductive member and connects the metal member and the first conductive member.
  • the film includes a metal thin film formed on the surface of the base material and an uneven oxide film that is an oxide of the same metal as the main component metal of the metal thin film and has a continuous surface.
  • the concavo-convex oxide film is formed on at least a part of a connecting region connecting a first connection region to which the first solder is connected and a second connection region to which the second solder is connected, on the surface of the metal member. It is arrange
  • the uneven oxide film is provided on the metal thin film in the connecting region, the uneven oxide film is formed in comparison with the structure in which the uneven oxide film is not provided, that is, the structure in which the surface of the metal thin film is exposed.
  • the wettability with respect to the solder of the provided part can be made low.
  • the surface of the concavo-convex oxide film has a continuous concavo-convex shape, that is, a roughened surface, the wettability with respect to solder can be reduced as compared with a flat surface.
  • the uneven oxide film may be a laser light irradiation film on the surface of the metal thin film.
  • the surface of the metal thin film is melted and evaporated (vaporized).
  • the metal thin film which melted and vaporized is vapor-deposited in the part irradiated with the laser beam, and its peripheral part.
  • a semiconductor chip having an electrode on one surface, a first conductive member disposed on one surface side of the semiconductor chip, a base material formed using a metal material, and the base material A metal member interposed between the semiconductor chip and the first conductive member, and disposed between the electrode of the semiconductor chip and the metal member, and the electrode and A first solder that connects a metal member; and a second solder that is disposed between the metal member and the first conductive member and connects the metal member and the first conductive member.
  • a method for manufacturing a semiconductor device comprising: Preparing a base material on which a metal thin film is formed, irradiating a surface of the metal thin film with pulsed laser light, and a first connection region to which the first solder is connected among the surfaces of the metal member; Forming the concavo-convex oxide film in at least a part of a connection region connecting the second connection region to which the second solder is connected; and after forming the concavo-convex oxide film, the first solder and the electrode of the semiconductor chip The metal member is connected, and the metal member and the first conductive member are connected by the second solder.
  • a concavo-convex oxide film having a continuous rugged surface can be formed by laser light irradiation. Accordingly, it is possible to suppress one of the first solder and the second solder from spreading on the surface of the metal member and flowing into the other. For example, the wetting and spreading of the second solder can be stopped with an uneven oxide film, and the second solder can be prevented from flowing into the first solder side.
  • FIG. 1 is a plan view showing a schematic configuration of the semiconductor device according to the first embodiment.
  • FIG. 2 is a sectional view taken along line II-II in FIG. 3 is an enlarged cross-sectional view of a region III indicated by a broken line in FIG.
  • FIG. 4 is a plan view showing a method for forming an uneven oxide film
  • FIG. 5 is an enlarged plan view of region V in FIG.
  • FIG. 6 is a cross-sectional view immediately before reflow of the second solder
  • FIG. 7 is a cross-sectional view showing the second solder during reflow
  • FIG. 1 is a plan view showing a schematic configuration of the semiconductor device according to the first embodiment.
  • FIG. 2 is a sectional view taken along line II-II in FIG. 3 is an enlarged cross-sectional view of a region III indicated by a broken line in FIG.
  • FIG. 4 is a plan view showing a method for forming an uneven oxide film
  • FIG. 5 is an enlarged plan view of
  • FIG. 8 is a cross-sectional view showing a first modification
  • FIG. 9 is a diagram showing the results of Example 1
  • FIG. 10 is a diagram showing the results of Example 2
  • FIG. 11 is a diagram showing the results of Example 3
  • FIG. 12 is a diagram showing the results of Example 4
  • FIG. 13 is a diagram showing the results of Example 5
  • FIG. 14 is a diagram showing the results of Example 6
  • FIG. 15 is a cross-sectional view illustrating a schematic configuration of the terminal and the uneven oxide film in the semiconductor device according to the second embodiment
  • FIG. 16 is a cross-sectional view showing a second modification of the terminal and the uneven oxide film
  • FIG. 17 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the third embodiment.
  • FIG. 15 is a cross-sectional view illustrating a schematic configuration of the terminal and the uneven oxide film in the semiconductor device according to the second embodiment
  • FIG. 16 is a cross-sectional view showing a second modification of the terminal
  • FIG. 18 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the fourth embodiment.
  • FIG. 19 is a cross-sectional view showing a third modification of the terminal and the uneven oxide film
  • FIG. 20 is a cross-sectional view showing a fourth modification of the terminal and the uneven oxide film
  • FIG. 21 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the fifth embodiment.
  • FIG. 22 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the sixth embodiment.
  • FIG. 23 is a plan view showing a schematic configuration of the semiconductor device according to the seventh embodiment.
  • FIG. 24 is a plan view in which the sealing resin body is omitted in the semiconductor device, FIG.
  • FIG. 25 is a plan view showing the formation range of the uneven oxide film in the first heat sink
  • FIG. 26 is a plan view showing the formation range of the uneven oxide film in the second heat sink and the main terminal
  • 27 is a cross-sectional view taken along line XXVII-XXVII in FIG.
  • a thickness direction of a semiconductor chip to be described later is indicated as a Z direction, and one direction orthogonal to the Z direction is indicated as an X direction.
  • a direction perpendicular to both the Z direction and the X direction is referred to as a Y direction.
  • the shape along the XY plane defined by the X direction and the Y direction is a planar shape.
  • the semiconductor device 10 includes a semiconductor chip 11, a sealing resin body 15, a terminal 18, a first heat sink 23, and a second heat sink 27. Furthermore, the semiconductor device 10 includes a signal terminal 16 and main terminals 25 and 28 as external connection terminals.
  • a semiconductor device 10 is known as a so-called 1 in 1 package constituting one of six arms constituting a three-phase inverter, and is incorporated in, for example, an inverter circuit of a vehicle.
  • the semiconductor chip 11 is formed by forming a power transistor such as an insulated gate bipolar transistor (IGBT) on a semiconductor substrate such as silicon.
  • a power transistor such as an insulated gate bipolar transistor (IGBT)
  • a semiconductor substrate such as silicon.
  • IGBT insulated gate bipolar transistor
  • FWD commutation diode
  • RC Reverse Conducting
  • the IGBT and FWD have a so-called vertical structure so that a current flows in the Z direction, and the semiconductor chip 11 has electrodes on the one surface 11a and the back surface 11b opposite to the one surface 11a in the Z direction.
  • An emitter electrode 12 is formed on the one surface 11a.
  • the emitter electrode 12 corresponds to “one surface electrode”.
  • the emitter electrode 12 also serves as an FWD anode electrode.
  • the emitter electrode 12 is exposed from the protective film 13 disposed on the one surface 11a in order to protect the IGBT and FWD.
  • the protective film 13 includes, for example, polyimide. Further, not only the emitter electrode 12 but also a pad (not shown) is exposed from the protective film 13. This pad includes a gate electrode pad and the like.
  • the collector electrode 14 is formed on the entire back surface 11b.
  • the collector electrode 14 corresponds to a “back electrode”.
  • the collector electrode 14 also serves as an FWD cathode electrode.
  • the sealing resin body 15 is made of, for example, an epoxy resin.
  • the sealing resin body 15 has a substantially rectangular plane shape, and includes a surface 15a orthogonal to the Z direction, a back surface 15b opposite to the surface 15a, and a side surface 15c that connects the surface 15a and the back surface 15b. Yes.
  • the one surface 15a and the back surface 15b are flat surfaces, for example.
  • the signal terminal 16 is electrically connected to the pad of the semiconductor chip 11 through a bonding wire (not shown). As shown in FIG. 1, the signal terminal 16 extends in the Y direction and protrudes from one of the side surfaces 15 c of the sealing resin body 15.
  • a terminal 18 is connected to the emitter electrode 12 of the semiconductor chip 11 via a first solder 17.
  • fluxless solder is used as the first solder 17.
  • the terminal 18 corresponds to a “metal member”.
  • the terminal 18 is interposed between the semiconductor chip 11 and the first heat sink 23. Since the terminal 18 is located in the middle of the heat conduction and electric conduction path between the semiconductor chip 11 and the first heat sink 23, the terminal 18 is mainly formed using a metal material in order to ensure heat conductivity and electric conductivity. . As shown in FIG. 3, the terminal 18 has a base material 19a made of a metal material and a coating 19b formed on the surface of the base material 19a. In this embodiment, Cu is adopted as the material of the base material 19a.
  • the terminal 18 has a substantially prismatic shape, more specifically, a substantially quadrangular prism shape (in other words, a substantially rectangular parallelepiped shape).
  • the terminal 18 has, as its surface, a first facing surface 18a facing the first heat sink 23, a second facing surface 18b facing the semiconductor chip 11, and a side surface 18c connecting both facing surfaces 18a and 18b. ing.
  • the first opposing surface 18a and the second opposing surface 18b are also referred to as a substantially quadrangular prism bottom surface.
  • the direction orthogonal to the first facing surface 18a and the second facing surface 18b of the terminal 18, that is, the thickness direction of the terminal 18 is substantially parallel to the Z direction.
  • substantially the entire surface of the second facing surface 18b of the surface of the terminal 18 is a first connection region 18d to which the first solder 17 is connected.
  • a second connection region 18e is a second connection region 18e to which a second solder 22 described later is connected.
  • the side surface 18c serves as a connection region 18f that connects the first connection region 18d and the second connection region 18e.
  • the film 19b is a metal thin film 20 formed on the surface of the base material 19a, and an oxide of the same metal as the main component metal constituting the metal thin film 20, and the uneven oxide film 21 whose surface continuously forms unevenness ,have.
  • the metal thin film 20 is a film containing metal as a constituent material.
  • the metal thin film 20 of this embodiment has Ni as a main component.
  • the metal thin film 20 is formed by, for example, plating or vapor deposition.
  • the metal thin film 20 is formed on the surface of the base material 19a by, for example, electroless Ni plating.
  • the metal thin film 20 contains P (phosphorus) in addition to Ni as a main component.
  • the metal thin film 20 is formed on the entire surface of the base material 19a.
  • a concave portion 20a is formed in the surface of the metal thin film 20 at the portion forming the side surface 18c of the terminal 18, as shown in FIG.
  • the recess 20a is formed by irradiation with pulsed laser light.
  • one recess 20a is formed for each pulse.
  • the recess 20a corresponds to a laser beam spot.
  • adjacent recesses 20a are connected in the scanning direction of the laser beam.
  • the width of each recess 20a is 5 ⁇ m to 300 ⁇ m.
  • the depth of the recess 20a is 0.5 ⁇ m to 5 ⁇ m.
  • the depth of the concave portion 20a is shallower than 0.5 ⁇ m, the surface of the metal thin film 20 is not sufficiently melted and deposited by laser light irradiation, and the uneven oxide film 21 described later is difficult to be formed.
  • the depth of the recess 20a is deeper than 5 ⁇ m, the surface of the metal thin film 20 is likely to be melted and scattered, and the surface formation by melting and scattering becomes more dominant than the vapor deposition, and the uneven oxide film 21 is hardly formed.
  • the uneven oxide film 21 is formed on the metal thin film 20.
  • the metal thin film 20 is formed on the surface forming the side surface 18 c of the terminal 18.
  • the uneven oxide film 21 is formed over the entire circumference of the four side surfaces 18 c of the terminal 18.
  • the concavo-convex oxide film 21 is formed on the entire side surface 18c, that is, the entire side surface 18c. Therefore, the uneven oxide film 21 is formed in the connecting region 18f.
  • the uneven oxide film 21 is formed by oxidizing the metal constituting the metal thin film 20 by irradiating the metal thin film 20 with laser light. That is, the uneven oxide film 21 is an oxide film formed on the surface of the metal thin film 20 by oxidizing the surface layer of the metal thin film 20. For this reason, it can be said that a part of the metal thin film 20 provides the uneven oxide film 21.
  • the main component of the uneven oxide film 21 is an oxide of Ni which is the main component of the metal thin film 20.
  • the average film thickness of the uneven oxide film 21 is 10 nm to several hundred nm.
  • the uneven oxide film 21 is formed following the unevenness on the surface of the metal thin film 20 having the recess 20a. Further, irregularities are formed at a pitch finer than the width of the recess 20a. That is, very fine irregularities are formed.
  • the plurality of convex portions 21a (columnar bodies) are formed at a fine pitch.
  • the average width of the convex portions 21a is 1 nm to 300 nm
  • the average interval between the convex portions 21a is 1 nm to 300 nm.
  • a first heat sink 23 is connected to the first facing surface 18 a of the terminal 18 via a second solder 22.
  • fluxless solder is used as the second solder 22.
  • the first heat sink 23 corresponds to a “first conductive member”.
  • the first solder 17 and the second solder 22 are also referred to as solders 17 and 22.
  • the first heat sink 23 functions to dissipate heat generated by the semiconductor chip 11 to the outside of the semiconductor device 10 and to electrically relay the semiconductor chip 11 and a main terminal 25 described later.
  • a first heat sink 23 is formed using a material that is more excellent in thermal conductivity than the second solder 22.
  • a metal material excellent in thermal conductivity and electrical conductivity such as Cu, Cu alloy, Al alloy, etc. can be employed. In this embodiment, it is formed using Cu.
  • the facing surface 23 a facing the terminal 18 is covered with the sealing resin body 15.
  • the surface opposite to the facing surface 23 a is a heat radiating surface 23 b exposed from the one surface 15 a of the sealing resin body 15.
  • the heat radiating surface 23b is substantially flush with the surface 15a.
  • the side surface 23c that connects the facing surface 23a and the heat dissipation surface 23b is also covered with the sealing resin body 15.
  • a groove 24 is formed on the facing surface 23a of the first heat sink 23 so as to surround the terminal 18 in a projected view from the Z direction.
  • the annular groove 24 is provided to absorb (store) excess second solder 22 that overflows from a region where the first heat sink 23 and the terminal 18 face each other during reflow.
  • the second solder 22 is disposed in the groove 24 and in a region surrounded by the groove 24 in a projection view from the Z direction.
  • a main terminal 25 is connected to the first heat sink 23.
  • the main terminal 25 is electrically connected to the emitter electrode 12 of the semiconductor chip 11 via the terminal 18 and the first heat sink 23.
  • the main terminal 25 extends from the first heat sink 23 in the Y direction and in the direction opposite to the signal terminal 16. And the main terminal 25 protrudes outside from the surface opposite to the surface from which the signal terminal 16 protrudes among the side surfaces 15c of the sealing resin body 15.
  • the main terminal 25 may be formed integrally with the first heat sink 23 as a part of the lead frame, or a separate main terminal 25 may be connected to the first heat sink 23.
  • a second heat sink 27 is connected to the collector electrode 14 of the semiconductor chip 11 via a third solder 26.
  • the second heat sink 27 corresponds to a “second conductive member”.
  • the second heat sink 27 also has a function of radiating heat generated by the semiconductor chip 11 to the outside of the semiconductor device 10 and a function of electrically relaying the semiconductor chip 11 and a main terminal 28 described later. Fulfill.
  • the second heat sink 27 is formed using Cu.
  • the facing surface 27 a facing the semiconductor chip 11 is covered with the sealing resin body 15.
  • the surface opposite to the facing surface 27 a is a heat radiating surface 27 b exposed from the back surface 15 b of the sealing resin body 15.
  • the heat radiating surface 27b is substantially flush with the back surface 15b.
  • the side surface 27c that connects the facing surface 27a and the heat radiating surface 27b is also covered with the sealing resin body 15.
  • a main terminal 28 is connected to the second heat sink 27.
  • the main terminal 28 is electrically connected to the collector electrode 14 of the semiconductor chip 11 via the second heat sink 27.
  • the main terminal 28 extends from the second heat sink 27 in the Y direction and in the same direction as the main terminal 25. And the main terminal 28 protrudes outside from the same surface as the surface from which the main terminal 25 protrudes among the side surfaces 15c of the sealing resin body 15.
  • the main terminal 28 may be formed integrally with the second heat sink 27 as a part of the lead frame, or a separate main terminal 28 may be connected to the second heat sink 27.
  • each element constituting the semiconductor device 10 is prepared. That is, the semiconductor chip 11, the signal terminal 16, the terminal 18, the first heat sink 23, the main terminal 25, the second heat sink 27, and the main terminal 28 are prepared. Of these preparation steps, a preparation step for the terminal 18 will be described. As shown below, the preparation process of the terminal 18 is also referred to as an irradiation process because it irradiates laser light. Moreover, in order to form the membrane
  • the terminal 18 having the base material 19a and the metal thin film 20 of the film 19b is prepared.
  • the metal thin film 20 is formed on the entire surface of the base material 19a by electroless Ni plating.
  • a target value of the thickness of the metal thin film 20 is, for example, about 10 ⁇ m.
  • the surface of the metal thin film 20 on the side surface 18c of the terminal 18 is irradiated with pulsed laser light to melt and evaporate the surface of the metal thin film 20.
  • Pulsed laser light energy density is large 100 J / cm 2 or less than 0 J / cm 2, the pulse width is adjusted to be equal to or less than 1 ⁇ seconds.
  • a YAG laser, a YVO 4 laser, a fiber laser, or the like can be employed.
  • the energy density may be 1 J / cm 2 or more.
  • the metal thin film 20 can be processed even at about 5 J / cm 2 as will be described later.
  • the energy density is also referred to as pulse fluence.
  • the laser beam is sequentially irradiated to a plurality of positions on the side surface 18c.
  • the laser light source may be moved, or the terminal 18 may be moved.
  • the laser beam may be scanned by rotating the mirror. That is, the laser beam may be sequentially irradiated to a plurality of positions on the side surface 18c by scanning the laser beam.
  • the irradiation angle of the laser beam with respect to the irradiation surface is not particularly limited.
  • the side surface 18c of the terminal 18 is irradiated with laser light from a direction orthogonal to the side surface 18c.
  • the side surface 18c orthogonal to the X direction is scanned with the laser light in the Y direction, and the laser light is sequentially irradiated to a plurality of positions on the straight line.
  • the laser beam is scanned in the X direction, and the laser beam is sequentially irradiated to a plurality of positions on the straight line.
  • the irradiation region of the laser beam is shifted in the Z direction. That is, the laser beam is scanned in the Z direction.
  • scanning is performed in the Y direction, and laser light is irradiated from one end to the other end.
  • the laser light is irradiated to almost the entire side surface 18c. That is, a laser beam is irradiated to a lattice point having a predetermined pitch in the YZ coordinates.
  • the laser beam is scanned in the Y direction so that adjacent laser beam spots (irradiation range by one pulse) partially overlap in the Y direction. Further, the laser light is scanned in the Z direction so that adjacent laser light spots partially overlap in the Z direction.
  • the side surface 18c orthogonal to the Y direction Thereby, the uneven oxide film 21 can be formed on almost the entire side surface 18c.
  • FIG. 4 shows a state in which laser light is irradiated up to the middle of the side surface 18c.
  • the average thickness of the metal thin film 20 on the side surface 18c is thinner than the average thickness of the metal thin film 20 on the first facing surface 18a and the second facing surface 18b that are not irradiated with laser light.
  • the molten metal thin film 20 is solidified. Specifically, the metal thin film 20 that has been melted and vaporized is deposited on a portion irradiated with the laser light and its peripheral portion. As described above, by depositing the metal thin film 20 which has been melted and vaporized, the concavo-convex oxide film 21 having concavities and convexities is formed on the surface of the metal thin film 20. As described above, the coating 19b including the uneven oxide film 21 in addition to the metal thin film 20 is formed on the base material 19a, and the preparation of the terminal 18 is completed.
  • the laser light is scanned in the Y direction so that the laser light spots partially overlap in the Y direction, for example, and the laser light is scanned in the Z direction so that the spots partially overlap in the Z direction. Therefore, the plurality of recesses 20a formed corresponding to the laser beam spots are continuous in the Y direction and also in the Z direction. Thereby, as shown in FIG. 5, the laser irradiation trace (concave part 20a) of the side surface 18c becomes a scale shape.
  • the present inventors have conducted extensive studies, the irradiation of the laser beam, the energy density large and 150 J / cm 2 than 100 J / cm 2, when a 300 J / cm 2, uneven oxide film 21 is not formed . Further, the uneven oxide film 21 was not formed even when continuous oscillation laser light was irradiated instead of pulse oscillation.
  • the semiconductor chip 11 is disposed on the facing surface 27a of the second heat sink 27 via the third solder 26 (for example, solder foil).
  • the terminal 18 in which the solders 17 and 22 are arranged in advance on both sides as the incoming solder is arranged so that the first solder 17 is on the semiconductor chip 11 side.
  • the second solder 22 is arranged in a large amount with a margin in order to absorb variations in height tolerance in the semiconductor device 10.
  • the solder 17, 22, and 26 are reflowed (1st reflow), whereby the semiconductor chip 11 and the second heat sink 27 are connected via the third solder 26, and the semiconductor chip 11 and the terminal 18 are connected.
  • the second solder 22 does not have the first heat sink 23 to be connected yet, and thus has a shape that rises with the center of the first facing surface 18a of the terminal 18 as a vertex due to surface tension.
  • the signal terminal 16 and the pad of the semiconductor chip 11 are connected by a bonding wire.
  • the first heat sink 23 is arranged on the pedestal 29 with the opposing surface 23a facing upward, and the connection body integrated by 1st reflow is connected so that the terminal 18 faces downward.
  • One heat sink 23 is disposed on the facing surface 23a.
  • reflow (2nd reflow) is performed with the first heat sink 23 facing down.
  • a load is applied to the structure so that the height of the semiconductor device 10 becomes a predetermined height.
  • the spacer 30 is interposed between the pedestal 29 and the opposing surface 27a of the second heat sink 27, and is brought into contact with both so that the height of the semiconductor device 10 becomes a predetermined height. That is, the base 29 and the spacer 30 function as a height adjusting member.
  • the second solder 22 between the terminal 18 and the first heat sink 23 is insufficient in the 2nd reflow. Therefore, a reliable connection can be made. Further, excessive second solder 22 is pushed out from between the terminal 18 and the first heat sink 23 by application of the load.
  • the concavo-convex oxide film 21 is formed on almost the entire side surface 18 c of the terminal 18. Therefore, the surplus second solder 22 does not wet and spread on the side surface 18 c of the terminal 18, but wets and spreads the facing surface 23 a of the first heat sink 23 and is accommodated in the groove 24.
  • the 1st reflow and 2nd reflow are reduced pressure reflow in a hydrogen atmosphere.
  • a natural oxide film on the metal surface unnecessary for soldering for example, a natural oxide film formed on the surfaces of the terminal 18, the first heat sink 23, and the second heat sink 27 can be removed by reduction. Therefore, a fluxless solder can be used as each of the solders 17, 22, and 26. Moreover, it can suppress that a void arises in solder 17,22,26 by pressure reduction. Since the uneven oxide film 21 is also reduced in thickness by reduction, the uneven oxide film 21 having a desired thickness is formed by laser light irradiation so that the uneven oxide film 21 remains even if reduced.
  • the sealing resin body 15 is then molded by the transfer molding method.
  • the sealing resin body 15 is formed so that the heat sinks 23 and 27 are completely covered. In this case, by cutting the molded sealing resin body 15 together with a part of the heat sinks 23 and 27, the heat radiation surfaces 23b and 27b of the heat sinks 23 and 27 are exposed.
  • the semiconductor device 10 can be obtained by removing unnecessary portions of the lead frame.
  • the uneven oxide film 21 is formed on the side surface 18 c of the surface of the terminal 18. That is, the uneven oxide film 21 is formed in the connecting region 18f that connects the first connection region 18d and the second connection region 18e.
  • the uneven oxide film 21 is provided in this manner, the wettability with respect to the solders 17 and 22 can be reduced as compared with the structure in which the uneven oxide film 21 is not provided, that is, the structure in which the surface of the metal thin film 20 is exposed.
  • the uneven oxide film 21 is provided, fine unevenness is formed on the surface of the terminal 18.
  • a contact area between a part of the solder 17 and 22 and the terminal 18 is reduced, and a part of the solder 17 and 22 becomes spherical due to surface tension. That is, the contact angle increases. Therefore, the wettability with respect to the solders 17 and 22 can be lowered in the portion where the uneven oxide film 21 is formed.
  • the uneven oxide film 21 is provided on the side surface 18 c of the terminal 18.
  • the side surface 18c is provided at a position farther from the emitter electrode 12 in the Z direction than the first connection region 18d. Further, the side surface 18c is provided at a position farther from the first heat sink 23 in the Z direction than the second connection region 18e. For this reason, with respect to the side surface 18c, it is not necessary to consider the capillary phenomenon regarding the wet spread of the solders 17 and 22. Therefore, it is possible to suppress the effect of the uneven oxide film 21 from being offset by the capillary phenomenon and weakening.
  • the contact area with the sealing resin body 15 increases. Furthermore, the sealing resin body 15 is entangled with the convex portion 21a of the uneven oxide film 21 to produce an anchor effect. Therefore, the adhesion between the terminal 18 and the sealing resin body 15 can be improved, and the peeling of the sealing resin body 15 can be suppressed.
  • the uneven oxide film 21 is provided on the entire side surface 18c of the terminal 18 .
  • the range of the uneven oxide film 21 formed on the side surface 18c is not limited to the above example.
  • the side surface 18c is a connecting region 18f. Therefore, when the uneven oxide film 21 is provided on at least a part of the side surface 18c, it is possible to prevent one of the first solder 17 and the second solder 22 from spreading toward the other.
  • the uneven oxide film 21 is provided over the entire circumference of the side surface 18c. In any of the four side surfaces 18c, it is possible to prevent one of the first solder 17 and the second solder 22 from spreading toward the other.
  • the uneven oxide film 21 may be provided only in a part of the side surface 18c of the terminal 18 from the end portion on the first facing surface 18a side.
  • the longer the length of the uneven oxide film 21 in the Z direction, that is, the wider the width the higher the effect of suppressing one of the first solder 17 and the second solder 22 from flowing into the other during reflow. It is done. Therefore, preferably, as described above, the uneven oxide film 21 is provided on the entire side surface 18c.
  • Example 1 The inventor has confirmed the relationship between the presence / absence of the uneven oxide film 21 and the formation range of the uneven oxide film 21 and solder wetting. The result is shown in FIG.
  • the semiconductor device 10 was formed by the above-described manufacturing method and evaluated.
  • the amount of the second solder 22 that does not cause wetting and spreading to the terminal 18 without the uneven oxide film 21 was taken as a reference amount, and a comparison was made between the reference amount and three times the reference amount.
  • the formation range of the uneven oxide film 21 on the side surface 18c is the entire surface, from the end on the first facing surface 18a side to 1/2 of the side surface 18c, and from the end on the first facing surface 18a side to 1/3 of the side surface 18c. Each of these was prepared and compared.
  • the uneven oxide film 21 formed by irradiating the metal thin film 20 formed by electroless Ni plating with laser light at an energy density of 12 J / cm 2 was used.
  • the second solder 22 wets and spreads to the side surface 18 c of the terminal 18 and flows into the first solder 17 side in three times the amount.
  • the second solder 22 does not spread to the terminal 18 even when the amount is three times.
  • the wettability with respect to the solders 17 and 22 can be reduced by providing the uneven oxide film 21 as compared with the configuration in which the surface of the metal thin film 20 is exposed.
  • the second solder 22 can be prevented from getting wet to the terminal 18 by providing the uneven oxide film 21 in at least a part of the range from the end portion on the first facing surface 18a side.
  • Example 2 The inventor confirmed the relationship between the presence or absence of the metal thin film 20, the type of the metal thin film 20, the presence or absence of the uneven oxide film 21, and the likelihood of occurrence of solder bridges. The result is shown in FIG. At that time, the semiconductor device 10 was formed by the above-described manufacturing method and evaluated. That is, when the uneven oxide film 21 was formed, the metal thin film 20 was irradiated with laser light at an energy density of 6 J / cm 2 and then soldered by reduced pressure reflow in a hydrogen atmosphere. About the metal thin film 20, what was formed by electro Ni plating and what was formed by electroless Ni plating were evaluated, respectively.
  • the material tolerance Typ indicates a state in which the thickness of each element constituting the semiconductor device 10, that is, the semiconductor chip 11, the terminal 18, the first heat sink 23, and the second heat sink 27 is set as the target value of the material tolerance.
  • the material tolerance max simulates the overflow of the second solder 22 when the thickness of each of the semiconductor chip 11, the terminal 18, the first heat sink 23, and the second heat sink 27 is set to the maximum value (upper limit value) of the material tolerance. Therefore, the number of the solder foils for forming the second solder 22 is 1.5. Then, it was confirmed whether or not the second solder 22 spreads on the side surface 18c of the terminal 18 to form a bridge with the first solder 17.
  • the bridge occurred in 5 times out of 172 even with the material tolerance Typ. Further, in the case of the material tolerance max, bridging occurred twice in two times. In the case where the metal thin film 20 was formed by electric Ni plating and the concavo-convex oxide film 21 was not provided, the material tolerance Typ did not cause bridging even once in 226 times. However, in the case of the material tolerance max, bridging occurred twice in two times. In the case where the metal thin film 20 was formed by electric Ni plating and the concavo-convex oxide film 21 was present, no bridging occurred once in 24 times with the material tolerance Typ. However, in the case of the material tolerance max, bridging occurred in 4 out of 4 times.
  • the material tolerance Typ did not cause bridging even once. However, in the case of the material tolerance max, bridging occurred in 6 out of 6 times. In the case where the metal thin film 20 is formed by electroless Ni plating and the concavo-convex oxide film 21 is present, no bridging occurs once in 4 times with the material tolerance Typ, and once in 12 times even when the material tolerance is max. No bridging.
  • the metal thin film 20 formed by electroless Ni plating is irradiated with laser light to form the concavo-convex oxide film 21, it is effective in suppressing the occurrence of bridges, that is, in reducing the wettability with respect to the solders 17 and 22. It became clear.
  • Example 3 The inventor has confirmed the relationship between energy density and solder wetting. The result is shown in FIG. At that time, the semiconductor device 10 was formed by the above-described manufacturing method and evaluated. Further, the entire side surface 18c of the terminal 18 was irradiated with laser light. Further, as the second solder 22, SnCuNiP with a Ni ball and having a thickness of 0.1 mm was used.
  • the wettability with respect to the solders 17 and 22 can be reduced by irradiation with a laser beam having a lower energy.
  • the energy is higher than that of electroless Ni plating, but the wettability with respect to the solders 17 and 22 is lowered by irradiation with laser light having energy lower than 100 J / cm 2. It became clear that we could do it.
  • Example 4 The inventor has confirmed the relationship between the energy density and the thickness of the uneven oxide film 21.
  • the result is shown in FIG. In FIG. 12, the metal thin film 20 formed by electroless Ni plating is shown by a solid line, and the metal thin film 20 formed by electric Ni plating is shown by a broken line.
  • the film thickness of the uneven oxide film 21 was measured by Auger electron spectroscopy.
  • the oxide film thickness decreases when the energy density of the irradiated laser beam is low, and the oxide film thickness increases when the energy density is high. Became clear. Specifically, 4J / cm 2 with an oxide film thickness of about 11 nm, the oxide film thickness at 10J / cm 2 was about 108 nm.
  • oxide film thickness 2J / cm 2 is about 5 nm
  • oxide film thickness at 10J / cm 2 was about 60 nm.
  • the metal thin film 20 formed by electroless Ni plating is thicker than the metal thin film 20 formed by electric Ni plating. It became clear that This is because the melting point of the metal thin film 20 (Ni-P) formed by electroless Ni plating is about 800 degrees depending on the P content, but the metal thin film 20 (Ni ) Of about 1450 degrees. Since the metal thin film 20 formed by electroless Ni plating has a lower melting point, it is considered that the metal oxide film 21 is melted and evaporated by a low energy laser beam and the thickness of the uneven oxide film 21 is increased.
  • the oxide film thickness after laser light irradiation was about 62 nm.
  • the oxide film thickness after 2nd reflow was about 33 nm. That is, by performing reflow in a reducing atmosphere, the oxide film for about 30 nm was reduced. In other words, about half of the uneven oxide film 21 was reduced. However, when the wettability with respect to the solders 17 and 22 was confirmed, the solders 17 and 22 did not spread even after laser light irradiation and after 2nd reflow.
  • the thickness of the uneven oxide film 21 is reduced by reflow in a reducing atmosphere.
  • the uneven oxide film 21 on the metal thin film 20 formed by electric Ni plating similarly reduces the oxide film thickness in a reducing atmosphere.
  • Example 2-5 From the results shown in Example 2-5 (FIGS. 10-13), in the case of the metal thin film 20 formed by electric Ni plating, if the energy density is less than 12 J / cm 2 , the uneven oxide film 21 is formed. Since it is thin, it is considered that the uneven oxide film 21 having a film thickness sufficient to suppress the wetting and spreading of the solders 17 and 22 does not remain by reduction during reflow. Accordingly, when the metal thin film 20 mainly composed of a metal having a low melting point, such as the metal thin film 20 formed by electroless Ni plating, is used, the thickness of the uneven oxide film 21 is increased with low energy laser light. Can do.
  • Example 6 The present inventor evaluated the shear strength for each case where the substrate 19 alone was used, and each of the cases without the uneven oxide film and with the uneven oxide film. The result is shown in FIG. In FIG. 14, the presence of the uneven oxide film is indicated by a solid line, only the base material 19 is indicated by a broken line, and the absence of the uneven oxide film (with the metal thin film 20) is indicated by a dashed line.
  • the metal thin film 20 formed by electroless Ni plating was used both with and without the uneven oxide film. Further, the concavo-convex oxide film 21 was formed by irradiating laser light at 12 J / cm 2 .
  • the resin material formed on the terminal 18 is the same epoxy resin as that of the sealing resin body 15, and the shape of the resin is a cone having a lower surface diameter of 3.57 mm, an upper surface diameter of 2.85 mm, and a height of 3.13 mm. It was trapezoidal. Then, the welding strength of the resin to the terminal 18, that is, the shear strength was evaluated at a shear speed of 50 ⁇ m / second. In that case, the workpiece
  • times. The shear strength shown in FIG. 14 shows an average value of n 5.
  • the surface of the metal thin film 20 is oxidized to form an oxide film. That is, an Ni oxide film is formed.
  • the Ni oxide film is stable even at high temperatures, and the growth of the oxide film is slower than that of Cu. For this reason, as shown in FIG. 14, it is thought that the decrease in the shear strength with time is smaller than that of Cu.
  • the contact area is increased by the fine unevenness of the uneven oxide film 21 in addition to the effect obtained when the uneven oxide film 21 is not present. Therefore, as shown in FIG. 14, it is considered that the shear strength is high as compared with the case where the uneven oxide film 21 is not provided.
  • the contact area can be increased by the fine unevenness, and a strong connection structure can be formed between the sealing resin body 15 and the sealing resin body 15.
  • a stable connection structure can be maintained over a long period of time.
  • the example in which the uneven oxide film 21 is provided on the side surface 18c of the terminal 18 having a substantially quadrangular prism shape is shown.
  • the shape of the terminal 18 is not limited to the above example.
  • the terminal 18 has a convex portion 18g, and has a convex shape on the first facing surface 18a side.
  • the first facing surface 18a includes a second connection region 18e and an outer peripheral region 18h surrounding the second connection region 18e.
  • the outer peripheral region 18h is positioned farther from the first heat sink 23 than the second connection region 18e.
  • the side surface 18c is divided into two by having the convex part 18g.
  • the side surface 18c has a first divided surface 18ca that connects the second connection region 18e and the outer peripheral region 18h, and a second divided surface 18cb that connects the outer peripheral region 18h and the second opposing surface 18b.
  • An uneven oxide film 21 is formed on the two divided surfaces 18ca and 18cb.
  • the uneven oxide film 21 can be formed on the divided surfaces 18ca and 18cb by irradiating laser light from a direction orthogonal to the Z direction.
  • the terminal 18 has a frustum shape. That is, the side surface 18c is an inclined surface (tapered surface). A concavo-convex oxide film 21 is formed on the entire surface of the inclined side surface 18c. Also in this case, the uneven oxide film 21 can be formed by irradiating the laser beam from the direction orthogonal to the Z direction as indicated by the white arrow.
  • the uneven oxide film 21 may be provided in a part of the side surface 18c from the end on the second facing surface 18b side. Further, on the side surface 18c, the uneven oxide film 21 may be provided at a position away from both the first facing surface 18a and the second facing surface 18b. Further, on the side surface 18c, the uneven oxide films 21 may be provided in multiple stages. For example, a plurality of uneven oxide films 21 may be provided in parallel with each other in the Z direction.
  • the terminal 18 has, as the side surface 18c, a first side surface portion 18c1, which is a portion within a predetermined range from the end portion on the first facing surface 18a side, a first side surface portion 18c1, and a second facing surface 18b. 2nd side part 18c2 which is a part of between.
  • the second side surface portion 18c2 has an outwardly convex curved shape (so-called R shape), and the second side surface portion 18c2 also faces the semiconductor chip 11 when viewed from the Z direction.
  • the uneven oxide film 21 is formed only on the first side surface portion 18c1 of the side surface 18c, and is not formed on the second side surface portion 18c2.
  • the first solder 17 is connected to the second facing surface 18 b and the second side surface portion 18 c 2 in the surface of the terminal 18. That is, the first connection region 18d is configured by the second facing surface 18b and the second side surface portion 18c2. Moreover, the connection area
  • the base material 19 of the terminal 18 having the second side surface portion 18c2 is formed by pressing a metal block.
  • an R-shaped second side surface portion 18c2 is formed.
  • the second side surface portion 18c2 is disposed on the semiconductor chip 11 side in the Z direction.
  • the uneven oxide film 21 is not formed on the second side surface portion 18c2, but the uneven oxide film 21 is formed only on the first side surface portion 18c1.
  • the first solder 17 spreads on the second side surface portion 18c2 during reflow, and a good fillet can be formed.
  • a heat radiation path for transferring the heat generated by the semiconductor chip 11 to the terminal 18 can be widened as compared with the configuration in which the uneven oxide film 21 is provided on the second side surface portion 18c2.
  • the second side surface portion 18c2 is shown as a part of the side surface 18c, but can also be considered as a part of the second facing surface 18b.
  • the second opposing surface 18b has a central portion and an outwardly convex R portion that surrounds the central portion and connects the central portion and the side surface 18c.
  • the uneven oxide film 21 is formed on the side surface 18c of the terminal 18 .
  • the example of the concavo-convex oxide film 21 formed by the laser beam irradiation from the direction orthogonal to the Z direction is shown.
  • the present embodiment is characterized in that the uneven oxide film 21 is formed on at least one of the first facing surface 18a and the second facing surface 18b in the surface of the terminal 18.
  • the terminal 18 has the convex part 18g like the above-mentioned 2nd Embodiment (refer FIG. 15).
  • the first opposing surface 18a has a second connection region 18e and an outer peripheral region 18h, and the outer peripheral region 18h has a longer opposing distance to the first heat sink 23 in the Z direction than the second connection region 18e. It has become.
  • the uneven oxide film 21 is formed in the outer peripheral region 18h.
  • the facing area between the terminal 18 and the first heat sink 23 is narrow, the second solder 22 spreads out by capillary action. Therefore, when the uneven oxide film 21 is provided in the outer peripheral region 18h on the flat first opposing surface 18a, the effect of the uneven oxide film 21 is offset by the capillary phenomenon and weakened.
  • the protrusion 18g is provided in the terminal 18, the 2nd connection area
  • corrugated oxide film 21 was provided in the outer peripheral area
  • the convex terminal 18 when employed, it can be easily formed by pressing, so that the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • the uneven oxide film 21 is provided in the outer peripheral region 18h of the convex terminal 18 .
  • the shape of the terminal 18 is not limited to the above example.
  • the terminal 18 has a tapered outer peripheral region 18h (inclined surface) as the first opposing surface 18a, and the uneven oxide film 21 is formed in the outer peripheral region 18h. . Even with such a configuration, the same effect as that in the case where the uneven oxide film 21 is provided in the outer peripheral region 18 h can be obtained in the convex terminal 18.
  • the terminal 18 has a substantially quadrangular prism shape as in the first embodiment, and the uneven oxide film 21 is formed in the outer peripheral region 18h in the flat first facing surface 18a. ing.
  • the uneven oxide film 21 can be formed by irradiating laser light from the Z direction as indicated by the white arrow.
  • the uneven oxide film 21 may be provided in the outer peripheral region surrounding the first connection region 18d on the second opposing surface 18b. In this case, the same effect can be obtained. Further, the uneven oxide film 21 may be provided on both the first facing surface 18a and the second facing surface 18b.
  • the uneven oxide film 21 is provided on the side surface 18c while the uneven oxide film 21 is provided on at least one of the first opposing surface 18a and the second opposing surface 18b may be employed.
  • This embodiment is characterized in that, as shown in FIG. 21, in addition to the uneven oxide film 21 formed on the terminal 18, an uneven oxide film 31 formed on the first heat sink 23 is provided.
  • the uneven oxide film 31 is also formed under the same conditions as the uneven oxide film 21.
  • the first heat sink 23 has a base material formed using, for example, Cu, and a metal thin film mainly formed of Ni and formed on the surface of the base material, like the terminal 18. ing.
  • the uneven oxide film 31 is formed by irradiating the surface of the metal thin film with laser light.
  • the uneven oxide film 31 is formed around the area where the second solder 22 is connected on the facing surface 23 a of the first heat sink 23.
  • the groove 24 is formed in the facing surface 23 a, and the annular groove 24 and a portion inside the groove 24 serve as a connection region with the second solder 22. Therefore, the concavo-convex oxide film 31 is formed on the entire surface outside the groove 24. That is, the uneven oxide film 31 is formed adjacent to the groove 24. Accordingly, the second solder 22 can be retained in the connection region of the second solder 22 by the uneven oxide film 31. For example, even if the amount of the second solder 22 is large, the second solder 22 can be prevented from overflowing outside the groove 24.
  • the second solder 22 is formed by providing the uneven oxide film 31 adjacent to the groove 24 so as to surround the second solder 22. Overflow from the groove 24 to the outside can be suppressed. Further, the present invention can also be applied to the first heat sink 23 that does not have the groove 24. Also in this case, by providing the uneven oxide film 31 so as to surround the second solder 22, the second solder 22 can be retained in the region surrounded by the uneven oxide film 31.
  • the contact area with the sealing resin body 15 increases.
  • the sealing resin body 15 is entangled with the convex portions of the uneven oxide film 31 to produce an anchor effect. Accordingly, the adhesion between the first heat sink 23 and the sealing resin body 15 can be improved, and thereby the peeling of the sealing resin body 15 can be suppressed.
  • the uneven oxide film 32 formed on the second heat sink 27 is provided in addition to the uneven oxide film 21 formed on the terminal 18, the uneven oxide film 32 formed on the second heat sink 27 is provided.
  • the structure shown in the fifth embodiment is added with the uneven oxide film 32, and the semiconductor device 10 includes the uneven oxide films 21, 31, and 32. .
  • the uneven oxide film 32 is also formed under the same conditions as the uneven oxide film 21.
  • the second heat sink 27 has a base material formed using, for example, Cu, and a metal thin film mainly formed of Ni and formed on the surface of the base material, like the terminal 18. ing.
  • the uneven oxide film 32 is formed by irradiating the surface of the metal thin film with laser light.
  • the concavo-convex oxide film 32 is disposed in the periphery of the region to which the third solder 26 is connected on the facing surface 27 a of the second heat sink 27. Specifically, the concavo-convex oxide film 32 is formed on the entire surface outside the connection region of the third solder 26 so as to surround the region to which the third solder 26 is connected in the facing surface 27a. Therefore, the third solder 26 can be retained in the connection region of the third solder 26 by the uneven oxide film 32.
  • the second heat sink 27 can also be provided with a groove for absorbing excess solder. In this case, by providing the uneven oxide film 32 adjacent to the groove, the third solder 26 can be prevented from overflowing from the groove.
  • the contact area with the sealing resin body 15 increases.
  • the sealing resin body 15 is entangled with the convex portion of the uneven oxide film 32 to produce an anchor effect. Therefore, the adhesion between the second heat sink 27 and the sealing resin body 15 can be improved, and thereby the peeling of the sealing resin body 15 can be suppressed.
  • the semiconductor device 10 includes, as the semiconductor chip 11, two semiconductor chips 11 that constitute upper and lower arms for one phase of a three-phase inverter. Similarly, the semiconductor device 10 includes two sets of signal terminals 16 and two terminals 18. In addition, the semiconductor device 10 includes two first heat sinks 23 and two second heat sinks 27. Of the semiconductor chip 11, the signal terminal 16, the terminal 18, the first heat sink 23, and the second heat sink 27, H is given to the end of the reference sign for the upper arm components, and the end of the reference sign to the lower arm components. L is given to. Other emitter electrodes 12, collector electrodes 14, and solders 17, 22, and 26 are given the same reference numerals for the upper arm and the lower arm for convenience.
  • the semiconductor chips 11H and 11L have substantially the same planar shape, specifically, a substantially rectangular shape, and have substantially the same size and thickness.
  • the semiconductor chips 11H and 11L are arranged with the collector electrode 14 on the same side in the Z direction.
  • the semiconductor chips 11H and 11L are located at substantially the same height in the Z direction and are arranged side by side in the X direction.
  • the upper arm side signal terminal 16H is electrically connected to the pad of the semiconductor chip 11H via a wire 33.
  • the lower arm side signal terminal 16L is also electrically connected to the pad of the semiconductor chip 11L via the wire 33.
  • the signal terminals 16 ⁇ / b> H and 16 ⁇ / b> L are both extended in the Y direction and project outward from the same side surface of the sealing resin body 15.
  • the signal terminals 16H and 16L are arranged side by side in the X direction.
  • a first heat sink 23H on the upper arm side is disposed on the emitter electrode 12 side of the semiconductor chip 11H.
  • the first heat sink 23H is provided so as to enclose the semiconductor chip 11H in a projection view from the Z direction.
  • a terminal 18H on the upper arm side is interposed between the facing surface 23a of the first heat sink 23H and the emitter electrode 12 of the semiconductor chip 11H.
  • the first solder 17 connects the emitter electrode 12 of the semiconductor chip 11H and the terminal 18H.
  • a first heat sink 23L on the lower arm side is disposed on the emitter electrode 12 side of the semiconductor chip 11L.
  • the first heat sink 23L is provided so as to enclose the semiconductor chip 11L in a projection view from the Z direction.
  • a lower arm side terminal 18L is interposed between the facing surface 23a of the first heat sink 23L and the emitter electrode 12 of the semiconductor chip 11L.
  • the first solder 17 connects the emitter electrode 12 of the semiconductor chip 11L and the terminal 18L.
  • the terminals 18H and 18L have a common shape. As shown in FIG. 27, uneven oxide films 21 are respectively formed on the side surfaces 18c of the terminals 18H and 18L.
  • the first heat sinks 23H and 23L have a common shape, and the first heat sink 23H and the first heat sink 23L are arranged so as to be two-fold symmetrical.
  • the first heat sink 23 (23 ⁇ / b> H, 23 ⁇ / b> L) has a substantially plane L shape, and a main body 23 d connected to the corresponding terminal 18 via the second solder 22. And a joint portion 23e extending from the main body portion 23d.
  • a groove 24 is formed on the opposing surface 23 a of the main body 23 d of the first heat sink 23.
  • a surface opposite to the terminal 18 in the main body portion 23 d is a heat radiating surface 23 b of the first heat sink 23. As shown in FIG.
  • the heat radiating surface 23b of the first arm heat sink 23H on the upper arm side and the heat radiating surface 23b of the first heat sink 23L on the lower arm side are exposed from the one surface 15a of the sealing resin body 15.
  • the heat radiation surfaces 23b of the first heat sinks 23H and 23L are arranged in the X direction.
  • the joint portion 23e is provided thinner than the main body portion 23d so as to be covered with the sealing resin body 15.
  • the main body portion 23d and the joint portion 23e are flush with each other on the facing surface 23a side.
  • a groove 34 is also formed in the facing surface 23a of the joint portion 23e in the first heat sink 23.
  • the groove 34 is formed so as to surround a connection portion between the joint portion 23e and a connection target of the joint portion 23e.
  • the joint portion 23 e and a connection target of the joint portion 23 e for example, a joint portion 27 e described later, are connected by solder 35.
  • the solder 35 is reflowed at the same timing as the second solder 22.
  • the groove 34 is provided to absorb (store) excess solder 35 overflowing from a region where the joint portion 23e and the connection target of the joint portion 23e are opposed to each other.
  • the solder 35 is disposed in the groove 34 and in a region surrounded by the groove 34 in a projection view from the Z direction.
  • An uneven oxide film 31 is formed on the facing surface 23 a of the first heat sink 23. As shown by hatching in FIG. 25, the uneven oxide film 31 is formed in a region of the facing surface 23 a excluding the region within the groove 24 and the region surrounded by the groove 24 and the region within the groove 34 and the region surrounded by the groove 34. Has been. For this reason, the concavo-convex oxide film 31 can prevent the second solder 22 from overflowing from the groove 24. Further, the uneven oxide film 31 can prevent the solder 35 from overflowing from the groove 34. Moreover, the adhesiveness of the opposing surface 23a and the sealing resin body 15 can also be improved.
  • the joint 23e of the first heat sink 23H is connected to the joint 27e of the second heat sink 27L on the lower arm side via a solder 35, as shown in FIGS.
  • the joint portion 23e of the first heat sink 23L is connected to the extended portion 25a of the main terminal 25 via the solder 35, as shown in FIG.
  • the main terminal 25 is a separate member from the first heat sink 23. Since the main terminal 25 is connected to the low potential side of the DC power supply, it is also referred to as a low potential power supply terminal or an N terminal.
  • the main terminal 25 extends in the Y direction as shown in FIG. 25, and protrudes to the outside from the side opposite to the signal terminal 16 in the sealing resin body 15 as shown in FIG. 23.
  • the length in the X direction that is, the width of the extending portion 25 a is made narrower than the width of the other portion of the main terminal 25.
  • the extending portion 25a is disposed between the main body portions 23d of the first heat sinks 23H and 23L in the projection view from the Z direction.
  • a second heat sink 27H on the upper arm side is disposed on the collector electrode 14 side of the semiconductor chip 11H.
  • the second heat sink 27H is provided so as to enclose the semiconductor chip 11H in a projection view from the Z direction.
  • a third solder 26 is interposed between the facing surface 27a of the second heat sink 27H and the collector electrode 14 of the semiconductor chip 11H. The third solder 26 causes the second heat sink 27H and the collector electrode 14 of the semiconductor chip 11H to be connected. It is connected. Note that the heat radiation surface 27b of the second heat sink 27H is exposed from the back surface 15b of the sealing resin body 15.
  • a main terminal 28H is connected to the second heat sink 27H. Since the main terminal 28H is connected to the high potential side of the DC power supply, it is also referred to as a high potential power supply terminal or a P terminal.
  • the main terminal 28H may be formed integrally with the second heat sink 27H, or may be a member connected to a separate member from the second heat sink 27H. In the present embodiment, the main terminal 28H is formed integrally with the second heat sink 27H.
  • the main terminal 28H is thinner than the second heat sink 27H, and the main terminal 28H extends from one of the side surfaces of the second heat sink 27H in the Y direction, and is the same as the main terminal 25 (N terminal) as shown in FIG. It protrudes from the side surface to the outside of the sealing resin body 15.
  • the second heat sink 27L on the lower arm side is juxtaposed with the second heat sink 27H in the X direction.
  • the second heat sink 27L is disposed on the collector electrode 14 side of the semiconductor chip 11L, and is provided so as to include the semiconductor chip 11L in a projected view from the Z direction.
  • a third solder 26 is also interposed between the opposing surface 27a of the second heat sink 27L and the collector electrode 14 of the semiconductor chip 11L.
  • the third solder 26 causes the second heat sink 27L and the collector electrode 14 of the semiconductor chip 11L to be connected to each other. Is connected.
  • the heat dissipation surface 27b of the second heat sink 27L is also exposed from the back surface 15b of the sealing resin body 15.
  • the heat radiation surfaces 27b of the second heat sinks 27H and 27L are also arranged in the X direction.
  • a main terminal 28L is connected to the second heat sink 27L as shown in FIGS. Since the main terminal 28L is connected to the output line of the three-phase motor, it is also referred to as an output terminal or an O terminal.
  • the main terminal 28L may be formed integrally with the second heat sink 27L, or may be a member connected to a different member from the second heat sink 27L. In the present embodiment, the main terminal 28L is formed integrally with the second heat sink 27L.
  • the main terminal 28L is thinner than the second heat sink 27L, and the main terminal 28L extends in the Y direction from one of the side surfaces of the second heat sink 27L, and is the same as the main terminal 25 (N terminal) as shown in FIG. It protrudes from the side surface to the outside of the sealing resin body 15.
  • the protruding portions from the sealing resin body 15 in the main terminals 25, 28H, and 28L are substantially at the same position in the Z direction.
  • the main terminal 28H (P terminal), the main terminal 25 (N terminal), and the main terminal 28L (O terminal) are arranged in this order.
  • the second heat sink 27L on the lower arm side is connected to the collector electrode 14 of the semiconductor chip 11L via the third solder 26, as shown in FIGS. 24, 26, and 27. It has a portion 27d and a joint portion 27e extending from the main body portion 27d.
  • the joint portion 27e is thinner than the main body portion 27d.
  • the joint portion 27e is extended from a surface of the main body portion 27d facing the second heat sink 27H in the X direction so as to overlap the joint portion 23e of the first heat sink 23H in the projection view from the Z direction. ing.
  • the joint portion 27e is connected to the joint portion 23e via the solder 35, and thus has two bent portions and extends toward the first heat sink 23H.
  • An uneven oxide film 32 is formed on the opposing surface 27 a of the second heat sink 27. As shown by hatching in FIG. 26, the uneven oxide film 32 is formed so as to surround the connection region of the third solder 26 on the facing surface 27a. The uneven oxide film 32 is formed in a region excluding the connection region of the third solder 26 in the facing surface 27a. The uneven oxide film 32 is formed on the joint portion 27e up to the bent portion, that is, on a portion substantially flush with the opposing surface 27a of the main body portion 27d. The uneven oxide film 32 is also formed on part of the main terminals 28H and 28L connected to the main body 27d. A one-dot chain line shown in FIG. 26 indicates the position of the end 15 d of the sealing resin body 15.
  • the uneven oxide film 32 is integrally formed from the second heat sink 27 to a predetermined distance outside the end 15d of the main terminal 28 (28H, 28L).
  • the portion of the main terminal 28 where the uneven oxide film 32 is not formed is a connection portion with a bus bar (not shown).
  • the uneven oxide film 32 is also formed on the main terminal 25. Also in the main terminal 25, the uneven oxide film 32 is formed up to a predetermined distance outside the end 15d of the sealing resin body 15. The uneven oxide film 32 is formed except for a connection portion with the solder 35 in the extending portion 25a and a connection portion with a bus bar (not shown).
  • the semiconductor device 10 configured in this way is a so-called 2 in 1 package including two semiconductor chips 11H and 11L.
  • the heat of the semiconductor chips 11H and 11L can be dissipated to both the one surface 15a and the back surface 15b of the sealing resin body 15.
  • Each of the uneven oxide films 21, 31, and 32 is formed by laser light irradiation as described above.
  • symbol 36 is a through-hole formed in the main terminal 28H in order to position the lead frame containing the main terminal 28H.
  • the through hole 36 is formed outside the region of the uneven oxide film 32.
  • Reference numeral 37 denotes a through hole formed around the connecting portion between the second heat sink 27 and the main terminal 28 in order to suppress the peeling of the sealing resin body 15.
  • Reference numeral 38 is a through hole formed in the signal terminal 16 in order to suppress the peeling of the sealing resin body 15.
  • the semiconductor device 10 has been described as an example of a 1 in 1 package having one semiconductor chip 11 and a 2 in 1 package having two semiconductor chips 11.
  • the number of semiconductor chips 11 is not limited to the above example.
  • the present invention can be applied to a configuration having six semiconductor chips 11 constituting upper and lower arms for three phases.
  • the present invention can also be applied to a configuration in which they are formed on different chips.
  • the present invention can be applied to a configuration that does not include the sealing resin body 15.
  • the present invention can also be applied to a configuration that does not include these.
  • heat radiation surfaces 23b and 27 An example in which b) is exposed from the sealing resin body 15 is shown.
  • the present invention can also be applied to a configuration in which the surface opposite to the semiconductor chip 11 is not exposed from the sealing resin body 15.
  • the metal constituting the metal thin film 20 is not limited to Ni.
  • the uneven oxide films 21, 31, and 32 are not limited to Ni oxides.
  • the concavo-convex oxide films 21, 31, and 32 may be oxides of the same metal as the metal constituting the metal thin film 20.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

La présente invention porte sur un dispositif à semi-conducteur comprenant : une puce de semi-conducteur (11, 11H, 11L) comportant une électrode (12) sur une surface (11a) ; un premier élément conducteur (23, 23H, 23L) du côté de ladite surface de la puce de semi-conducteur ; un élément métallique (18, 18H, 18L), qui comprend un matériau de base (19a) et un film (19b) et est disposé entre la puce de semi-conducteur et le premier élément conducteur ; une première brasure (17) entre l'élément métallique et l'électrode de la puce de semi-conducteur ; et une seconde brasure (22) entre l'élément métallique et le premier élément conducteur. Le film comprend, sur la surface avant du matériau de base, un film mince métallique (20) et un film d'oxyde en retrait et en saillie (21, 31, 32). Le film d'oxyde en retrait et en saillie est disposé sur le film mince métallique dans une partie d'une zone de connexion (18f) qui connecte l'une à l'autre une première zone de connexion (18d) à laquelle est connectée la première brasure et une seconde zone de connexion (18e) à laquelle est connectée la seconde brasure, ladite partie étant une partie de la surface avant de l'élément métallique.
PCT/JP2015/006035 2014-12-10 2015-12-04 Dispositif à semi-conducteur et son procédé de fabrication WO2016092791A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/508,506 US10147671B2 (en) 2014-12-10 2015-12-04 Semiconductor device and method for manufacturing same
DE112015005561.4T DE112015005561B4 (de) 2014-12-10 2015-12-04 Halbleitervorrichtung und verfahren zu deren fertigung
CN201580066323.3A CN107004662B (zh) 2014-12-10 2015-12-04 半导体装置及其制造方法

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2014250186 2014-12-10
JP2014-250186 2014-12-10
JP2015099403 2015-05-14
JP2015-099403 2015-05-14
JP2015223330A JP6578900B2 (ja) 2014-12-10 2015-11-13 半導体装置及びその製造方法
JP2015-223330 2015-11-13

Publications (1)

Publication Number Publication Date
WO2016092791A1 true WO2016092791A1 (fr) 2016-06-16

Family

ID=56107016

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/006035 WO2016092791A1 (fr) 2014-12-10 2015-12-04 Dispositif à semi-conducteur et son procédé de fabrication

Country Status (2)

Country Link
DE (1) DE112015005561B4 (fr)
WO (1) WO2016092791A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017154289A1 (fr) * 2016-03-10 2017-09-14 株式会社デンソー Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
JP2018082012A (ja) * 2016-11-15 2018-05-24 トヨタ自動車株式会社 半導体装置
WO2018179023A1 (fr) * 2017-03-27 2018-10-04 三菱電機株式会社 Dispositif à semi-conducteur, dispositif de conversion de puissance et procédé de fabrication de dispositif à semi-conducteur
JP2019087669A (ja) * 2017-11-08 2019-06-06 トヨタ自動車株式会社 半導体装置
CN112805823A (zh) * 2018-10-02 2021-05-14 株式会社电装 半导体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003188318A (ja) * 2001-12-19 2003-07-04 Denso Corp 半導体装置及びその製造方法
JP2005136332A (ja) * 2003-10-31 2005-05-26 Toyota Motor Corp 半導体装置
JP2013247256A (ja) * 2012-05-28 2013-12-09 Hitachi Ltd 半導体装置およびその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6693350B2 (en) 1999-11-24 2004-02-17 Denso Corporation Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
JP4702196B2 (ja) 2005-09-12 2011-06-15 株式会社デンソー 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003188318A (ja) * 2001-12-19 2003-07-04 Denso Corp 半導体装置及びその製造方法
JP2005136332A (ja) * 2003-10-31 2005-05-26 Toyota Motor Corp 半導体装置
JP2013247256A (ja) * 2012-05-28 2013-12-09 Hitachi Ltd 半導体装置およびその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017154289A1 (fr) * 2016-03-10 2017-09-14 株式会社デンソー Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
JP2018082012A (ja) * 2016-11-15 2018-05-24 トヨタ自動車株式会社 半導体装置
WO2018179023A1 (fr) * 2017-03-27 2018-10-04 三菱電機株式会社 Dispositif à semi-conducteur, dispositif de conversion de puissance et procédé de fabrication de dispositif à semi-conducteur
JPWO2018179023A1 (ja) * 2017-03-27 2019-06-27 三菱電機株式会社 半導体装置、電力変換装置および半導体装置の製造方法
JP2019087669A (ja) * 2017-11-08 2019-06-06 トヨタ自動車株式会社 半導体装置
CN112805823A (zh) * 2018-10-02 2021-05-14 株式会社电装 半导体装置
CN112805823B (zh) * 2018-10-02 2024-04-09 株式会社电装 半导体装置

Also Published As

Publication number Publication date
DE112015005561T5 (de) 2017-08-24
DE112015005561B4 (de) 2022-05-05

Similar Documents

Publication Publication Date Title
JP6578900B2 (ja) 半導体装置及びその製造方法
CN109075147B (zh) 电子装置及其制造方法
CN108886027B (zh) 电子装置
WO2016092791A1 (fr) Dispositif à semi-conducteur et son procédé de fabrication
JP4775327B2 (ja) 半導体装置の製造方法
CN108604579B (zh) 电子装置及其制造方法
WO2017154289A1 (fr) Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
US10943859B2 (en) Semiconductor device
WO2018173511A1 (fr) Dispositif à semi-conducteurs
US11742256B2 (en) Semiconductor device
JP4765853B2 (ja) 半導体装置の製造方法
US9468993B2 (en) Method for producing semiconductor device
JP6008750B2 (ja) 半導体装置
WO2019187608A1 (fr) Dispositif à semi-conducteur
KR20180031502A (ko) 파워 모듈 및 그 제조 방법
JP6423147B2 (ja) 電力用半導体装置およびその製造方法
JP2017188528A (ja) 半導体装置
JP2021118350A (ja) 電子装置及び電子装置の製造方法
JP2020198388A (ja) 半導体装置およびその製造方法
JP2022185936A (ja) 半導体装置
JP7390826B2 (ja) 半導体装置および半導体装置の製造方法
JP5261851B2 (ja) 半導体装置の製造方法
CN113241325A (zh) 电子装置以及电子装置的制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15867385

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 15508506

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 112015005561

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15867385

Country of ref document: EP

Kind code of ref document: A1