WO2016090562A1 - 一种设置均衡装置的方法及均衡装置 - Google Patents

一种设置均衡装置的方法及均衡装置 Download PDF

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Publication number
WO2016090562A1
WO2016090562A1 PCT/CN2014/093411 CN2014093411W WO2016090562A1 WO 2016090562 A1 WO2016090562 A1 WO 2016090562A1 CN 2014093411 W CN2014093411 W CN 2014093411W WO 2016090562 A1 WO2016090562 A1 WO 2016090562A1
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Prior art keywords
value
taps
tap
equalization
adder
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PCT/CN2014/093411
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English (en)
French (fr)
Inventor
马雅男
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华为技术有限公司
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Priority to CN201480083864.2A priority Critical patent/CN107005307B/zh
Priority to PCT/CN2014/093411 priority patent/WO2016090562A1/zh
Publication of WO2016090562A1 publication Critical patent/WO2016090562A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission
    • H04B10/2507—Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
    • H04B10/2513—Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion due to chromatic dispersion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising

Definitions

  • the present invention relates to the field of communications, and in particular, to a method and an equalization apparatus for setting an equalization apparatus.
  • the optical domain dispersion compensation uses a dispersion compensation fiber or a dispersion compensation grating to compensate the dispersion of the optical signal during transmission.
  • the dispersion slope will result in incomplete dispersion compensation, which will result in different residual dispersion on different channels, and will also bring a large insertion loss, which requires an additional large number of fiber amplifiers, but with It will introduce spontaneous radiated noise and reduce the signal-to-noise ratio of the transmitted signal.
  • the dispersion compensation grating uses a small loss, but the spectral passband is small, and a compensation grating can only compensate one channel, which is costly.
  • the compensation range of the optical domain dispersion compensation is determined by the compensation device, cannot be dynamically changed, and lacks adaptive compensation capability.
  • the electric dispersion compensation technology can adaptively adjust the waveform of the received signal according to the link damage condition by sampling the received optical signal in the electric domain, software optimization and signal recovery, and recovering due to group velocity dispersion, polarization film dispersion and nonlinearity.
  • the signal is broadened and distorted to achieve signal equalization.
  • the electrical dispersion compensation module (or chip) can be directly integrated into the optical receiver, which is flexible in design and low in cost. The above characteristics make the electric dispersion compensation technology a key dispersion compensation technology.
  • FIG. 1 it is a schematic diagram of the structure of the FFE.
  • the FFE includes N serial delay units, N+1 taps, and a Adder.
  • N + 1 taps interval T b may be the symbol cycle T (symbol-spaced equalizer), T b may be a part of a symbol period (fractionally spaced equalizer).
  • the FFE linearly superimposes the current value and the past value of the received signal by the tap coefficient C n (i.e., the weight), and sends the generated sum as an output to the decider.
  • the response expression of the FFE is: Where h k is the equilibrium value of the Kth value received by the FFE, and x kn is the Knth value received by the FFE.
  • the FFE structure is simple and easy to implement. However, since the equalization interval of the FFE is fixed, the channel estimation interval cannot be changed, which may not effectively reduce the system error rate when the signal transmission channel changes.
  • the embodiment of the present application provides a method for setting an equalization device and an equalization device, which are used to solve the technical problem that the equalization interval of the equalization device cannot be automatically changed in the prior art.
  • an embodiment of the present application provides a method for setting an equalization apparatus, where the equalization apparatus includes an equalizer, a decider, and a processor, where the equalizer includes M-1 delay units connected in series, M taps, and An adder, wherein the input terminals of the equalizer are respectively connected to an input end of a first one of the M-1 delay units and an input end of the first one of the M taps, An output of each of the M-1 delay units is connected in one-to-one correspondence with M-1 taps of the M taps except the first tap, each of the M taps The tap multiplies the input value by the product of the tap coefficients into the input of the adder, the adder inputs the sum of the M products to the input of the decider, the method comprising:
  • the processor uses the t-th value of the K values and the tap coefficient of the i-th tap of the M taps When multiplied, the output value of the adder is used as an equalization value of the t-th value, and the tap coefficients C i of the M taps are determined according to an equalization algorithm; wherein t is any positive integer less than or equal to K , i is any positive integer less than or equal to M;
  • the processor determines an output value Y t,i of the adder when the tap coefficient is C i and the t-th value is multiplied by a tap coefficient of the i-th tap;
  • the processor determines an equalization evaluation parameter Z t,i when Y t,i is used as the equalization value of the t-th value;
  • the processor determines the Z t, 1 to Z t, the best equalization evaluation parameters M equalizing effect Z t, and it is determined that the t-th value obtained when multiplying the Z t taps tap number S t ;
  • the processor After determining the S 1 to S K , the processor determines that the tap number with the most repetition among the S 1 to S K is S;
  • the processor determines that the output value of the adder is multiplied by the tap coefficient of the Sth tap of the M taps The equilibrium value of the equilibrium value is described.
  • the method further includes:
  • the processor sets the tap coefficients of the M taps to C s when calculating the equalization value of the values to be equalized.
  • an embodiment of the present application provides a method for setting an equalization apparatus, where the equalization apparatus includes a feedforward equalizer, a feedback equalizer, a first adder, a decider, and a processor, wherein the feedforward equalizer Including M-1 series delay units, M taps and second adders, the input ends of the feedforward equalizer and the input of the first delay unit of the M-1 delay units and the M The input of the first tap of the taps is connected, the output of each of the M-1 delay units and the M-1 taps of the M taps other than the first tap Connected one by one, each of the M taps inputs a product of the input value and the tap coefficient into the input of the second adder, the second adder sums the products of M a value is input to an input end of the first adder; the feedback equalizer includes N-1 delay units connected in series, N taps, and a third adder, and the input ends of the feedback equalizer are respectively N-1 An input of the first delay unit in the delay unit and
  • the processor uses the t-th value of the K values and the tap coefficient of the i-th tap of the M taps Multiplying and multiplying the equalized value of the tjth value of the K values by the tap coefficient of the first tap of the N taps as the tth of the first adder values of equilibrium, is determined according to the equalization algorithm M taps of the tap coefficients C i, j N taps and the tap coefficients D i, j; where, i is less than or equal to any positive integer M, j Is any positive integer less than or equal to the set value L;
  • the processor determines that the tap coefficients of the M taps are C i,j , the tap coefficients of the N taps are D i,j , the t-th value and the tap coefficients of the i-th tap Multiplying, the equalized value of the tjth value is multiplied by the tap coefficient of the first tap of the N taps, and the output value Y t,i,j of the first adder;
  • the processor determines an equalization evaluation parameter Z t,i,j when Y t,i,j is used as the equalization value of the t-th value;
  • the processor determines that the equalization evaluation parameter with the best balance effect in Z t,1,1 to Z t,M,L is Z t , and determines that the M taps and the first part are obtained when Z t is acquired
  • the tap number i 1 of the tap of the t data multiplied and the data multiplied by the first one of the N taps are the equalized values of the tj 1 value;
  • the processor determines that the most occurrences of all the values of (i 1 , j 1 ) are (s, h);
  • the processor determines, when the equalization device equalizes the equalized value, multiplies the value to be equalized by the tap coefficient of the sth tap of the M taps, and the equalized value of the thth value
  • the output value of the first adder when the tap coefficients of the first tap of the N taps are multiplied is an equalization value of the value to be equalized.
  • the method further includes:
  • the processor sets the tap coefficients of the M taps to C s,h , and sets the tap coefficients of the N taps to D s,h .
  • an embodiment of the present application provides an equalization apparatus, where the equalization apparatus is respectively connected to an equalizer and a decider, where the equalizer includes M-1 delay units connected in series, M taps, and an adder, wherein The input of the equalizer is respectively connected to an input end of a first one of the M-1 delay units and an input end of the first one of the M taps, the M-1 delays An output of each delay unit in the unit is connected in one-to-one correspondence with M-1 taps of the M taps other than the first tap, and each of the M taps inputs an input value The multiplied product of the tap coefficients is input to the input of the adder, and the adder inputs the sum of the M products to the input of the decider, the equalization device comprising:
  • a first determining unit configured to: when the equalizer receives the training sequence including K values, the t-th value of the K values and the tap coefficient of the i-th tap of the M taps When multiplied, the output value of the adder is used as an equalization value of the t-th value, and the tap coefficients C i of the M taps are determined according to an equalization algorithm; wherein t is any positive integer less than or equal to K , i is any positive integer less than or equal to M;
  • a second determining unit configured to determine that the tap coefficient is C i , the output value Y t, i of the adder when the t-th value is multiplied by the tap coefficient of the i-th tap;
  • a third determining unit configured to determine an equalization evaluation parameter Z t,i when Y t,i is used as the equalization value of the t-th value
  • Fourth determining means for determining a Z t, 1 to the Z t, the best equalization parameters of evaluation of the Z M t equalizing effect, and it is determined that the t-th value obtained by multiplying the Z when the tap t Tap number S t ;
  • a fifth determining unit configured to determine, after determining S 1 to S K , that the tap number with the most repetition among the S 1 to S K is S;
  • a sixth determining unit configured to determine, when the equalization device uses the equalization device to equalize the equalized value, the output of the adder when the value to be equalized is multiplied by a tap coefficient of the Sth tap of the M taps The value is the equalization value of the value to be equalized.
  • the equalizing apparatus further includes:
  • a setting unit configured to set the tap coefficients of the M taps to C s when calculating the equalization value of the values to be equalized.
  • an embodiment of the present application provides an equalization apparatus, where the equalization apparatus is respectively connected to a feedforward equalizer, a feedback equalizer, a first adder, and a decider, wherein the feedforward equalizer includes an M-1.
  • the feedback equalizer includes N-1 delay units connected in series, N taps, and a third adder, and the input ends of the feedback equalizer are respectively associated with N-1 delay units An input of the first delay unit and a first one of the N taps The input ends of the heads are connected, and the output ends of each of the N-1 delay units are connected in one-to-one correspondence with the N-1 taps of the N taps except the first tap.
  • the equalization device includes:
  • a first determining unit configured to: when the equalizer receives the training sequence including K values, the t-th value of the K values and the tap coefficient of the i-th tap of the M taps Multiplying and multiplying the equalized value of the tjth value of the K values by the tap coefficient of the first tap of the N taps as the tth of the first adder values of equilibrium, is determined according to the equalization algorithm M taps of the tap coefficients C i, j N taps and the tap coefficients D i, j; where, i is less than or equal to any positive integer M, j Is any positive integer less than or equal to the set value L;
  • a second determining unit configured to determine that the tap coefficients of the M taps are C i,j , the tap coefficients of the N taps are D i,j , the t-th value and the ith tap And multiplying the tap coefficients, the equalization value of the tjth value and the tap coefficients of the first tap of the N taps, the output value Y t,i,j of the first adder;
  • a third determining unit configured to determine an equalization evaluation parameter Z t,i,j when Y t,i,j is used as the equalization value of the t-th value
  • a fourth determining unit configured to determine that the equalization evaluation parameter with the best balance effect in Z t,1,1 to Z t,M,L is Z t , and determines that the M taps are obtained when Z t is acquired
  • the tap number i 1 of the tap of the t-th data and the data multiplied by the first one of the N taps are equalization values of the tj 1 value;
  • a fifth determining unit configured to determine, after determining Z 1 to Z K , that the most frequently occurring value of all values of (i 1 , j 1 ) is (s, h);
  • a sixth determining unit configured to determine, when the equalization device uses the equalization device to equalize the equalized value, multiply the value of the to-be-equalized value by the tap coefficient of the s-th tap of the M taps, and balance the th-th value
  • the value of the first adder when the value is multiplied by the tap coefficient of the first tap of the N taps is an equalization value of the value to be equalized.
  • the equalizing apparatus further includes:
  • a setting unit configured to set the tap coefficients of the M taps to C s,h when calculating the equalization value of the values to be equalized, and set the tap coefficients of the N taps to D s,h .
  • an embodiment of the present application provides an equalization apparatus, where the equalization apparatus includes an equalizer and a decider, where the equalizer includes M-1 delay units connected in series, M taps, and an adder, where The input ends of the equalizer are respectively connected to the input end of the first one of the M-1 delay units and the input end of the first one of the M taps, wherein the M-1 delay units are The output of each delay unit is connected in one-to-one correspondence with the M-1 taps of the M taps except the first tap, and each of the M taps inputs the input value and the tap coefficient
  • the multiplied product is input to the input of the adder, and the adder inputs the sum of the M products to the input of the decider.
  • the equalization device further includes:
  • a storage unit configured to store an instruction, when the equalizer receives the training sequence including K values, the t-th value of the K values and the first of the M taps
  • the tap coefficients of the i taps are multiplied, the output value of the adder is used as an equalization value of the t-th value, and the tap coefficients C i of the M taps are determined according to an equalization algorithm; wherein t is less than or equal to Any positive integer of K, i being any positive integer less than or equal to M; determining that the tap coefficient is C i , the t-th value is multiplied by the tap coefficient of the i-th tap
  • the best-performing equalization evaluation parameter is Z t , and determines the tap number S t of the tap multipli
  • a processor for executing the instructions.
  • the storage unit further includes an instruction: when calculating an equalization value of the to-balanced value, setting a tap coefficient of the M taps For C s .
  • an embodiment of the present application provides an equalization apparatus, where the equalization apparatus includes a feedforward equalizer, a feedback equalizer, a first adder, and a decider, wherein the feedforward equalizer includes M-1 serial devices.
  • the equalization apparatus includes a feedforward equalizer, a feedback equalizer, a first adder, and a decider, wherein the feedforward equalizer includes M-1 serial devices.
  • each of the M taps inputs a product of the input value and the tap coefficient to the input of the second adder, and the second adder inputs the sum of the M products into the first An input of the adder;
  • the feedback equalizer includes N-1 delay units connected in series, N taps, and a third adder, the input of the feedback equalizer and the first of the N-1 delay units, respectively The input of the delay unit and the input of the first of the N taps Connected to the ingress, the output of each of the N-1 delay units and the N-1 taps of the N taps other than the first tap Correspondingly connected, each of the N taps inputs a product obtained by multiplying an input value by a tap coefficient into an input end of the third adder, and the third adder inputs a sum value of N products An input of the first adder, the first adder inputs a sum of an output value of the second adder and an output value of the third adder to an input end of the decider, The output of the determiner is connected to the input
  • a storage unit configured to store an instruction, when the equalizer receives the training sequence including K values, the t-th value of the K values and the first of the M taps
  • the t-th value of the equilibrium value determined according to the equalization algorithm M taps of the tap coefficients C i, j N taps and the tap coefficients D i, j, where, i is less than or equal to M Any positive integer, j is any positive integer less than or equal to the set value L; determining that the tap coefficients of the M taps are C i,j , and the tap coefficients of the N taps are D i,j , The first addition when the t-th value is multiplied by the tap coefficient of the i-th tap, and the equalization value of the tj-th value
  • a processor for executing the instructions.
  • the storage unit further includes an instruction: when calculating an equalization value of the to-balanced value, setting a tap coefficient of the M taps For C s,h , the tap coefficients of the N taps are set to D s,h .
  • the equalizer when the equalizer receives the training sequence including K values for the equalizer training, the equalizer performs equalization under the M equalization interval, that is, the value and the M values respectively.
  • the output value of the adder (or the decider) is multiplied by each tap in the tap as the equalization value of the value, and after obtaining the M equalization values of the value, the respective equalization evaluation parameters when the M equalization values are obtained are compared, ie The better equalization interval for the value can be determined.
  • K preferred equalization intervals can be obtained, and the highest frequency among the K preferred equalization intervals is counted.
  • the equalization interval can be used as a formal equalization interval when the equalization device equalizes the input signal. Since the training sequence will be transmitted every time the signal transmission channel changes, the equalization interval of the equalization device can be re-determined for the changed channel, and the channel estimation interval can be adaptively adjusted, which can effectively reduce the error rate.
  • Figure 1 is a schematic structural view of an FFE
  • FIG. 2 is a schematic flowchart of a method for setting an equalization apparatus in Embodiment 1 of the present application;
  • FIG. 3 is a schematic diagram of an equalization interval movement of an equalizer in Embodiment 1 of the present application.
  • Embodiment 4 is a schematic structural diagram of an equalization apparatus in Embodiment 2 of the present application.
  • FIG. 5 is a schematic structural diagram of a feedback equalizer according to Embodiment 2 of the present application.
  • FIG. 6 is a schematic flowchart of a method for setting an equalization device according to Embodiment 2 of the present application.
  • FIG. 7 is a schematic diagram of an equalization interval movement of a feedforward equalizer and a feedback equalizer in Embodiment 2 of the present application;
  • FIG. 8 is a schematic block diagram showing the structure of an equalization apparatus in Embodiment 3 of the present application.
  • FIG. 9 is a schematic block diagram showing the structure of an equalization apparatus in Embodiment 4 of the present application.
  • FIG. 10 is a schematic block diagram showing the structure of an equalization apparatus according to Embodiment 5 of the present application.
  • FIG. 11 is a schematic block diagram showing the structure of an equalization apparatus in Embodiment 6 of the present application.
  • the embodiment of the present application provides a method for setting an equalization device, where the equalization device includes an equalizer, a decider, and a processor, and the equalizer includes M-1 a delay unit, M taps, and an adder in series, wherein an input of the equalizer and an input of a first one of the M-1 delay units and a first one of the M taps The inputs of the taps are connected, and the output of each of the M-1 delay units is connected in one-to-one correspondence with the M-1 taps of the M taps other than the first tap.
  • the method includes, when the equalizer receives a training sequence including K values, the processor uses a t-th value of the K values and an i-th tap of the M taps The output value of the adder when the tap coefficients are multiplied As the equalization value of the t-th value, the tap coefficients C i of the M taps are determined according to an equalization algorithm; wherein t is any positive integer less than or equal to K, and i is any less than or equal to M a positive integer; the processor determines an output value Y t,i of the adder when the tap coefficient is C i , the t-th value is multiplied by a tap coefficient of the i-th tap; The processor determines an equalization evaluation parameter Z t,i when Y t,i is used as the equalization value of
  • the equalizer receives the training including the K values.
  • each value is equalized in M kinds of equalization intervals, that is, the output value of the adder (or the decider) is multiplied by each of the M taps respectively.
  • the equilibrium value of the value after obtaining the M equalization values of the value, and comparing the respective equalization evaluation parameters of the M equalization values, the better equalization interval for the value can be determined, for each value in the training sequence.
  • K better equalization intervals can be obtained, and the equilibrium interval with the highest frequency appearing in the K preferred equalization intervals can be calculated, which can be used as the formal equalization interval when the equalization device equalizes the input signal. Since the training sequence will be transmitted every time the signal transmission channel changes, the equalization interval of the equalization device can be re-determined for the changed channel, and the channel estimation interval can be adaptively adjusted, which can effectively reduce the error rate.
  • the method for setting an equalization apparatus can be applied to the equalization apparatus shown in FIG. 1.
  • the equalization apparatus includes an equalizer and a decider, and the equalizer includes M-1 delay units connected in series, M taps, and an addition. And processor.
  • M-1 delay units adjacent unit delay time interval T the same as T b, T b may be adjacent to the value of the training sequence in the time interval may be less than T
  • T the following embodiment of the present application B to T
  • the method provided in the embodiment of the present application is introduced by taking T as an example.
  • the input of the equalizer is respectively connected to the input of the first delay unit of the M-1 delay units and the input of the first tap of the M taps, and each delay unit of the M-1 delay units
  • the output end is connected one-to-one with the M-1 taps of the M taps except the first tap, and each of the M taps multiplies the input value by the tap coefficient and the product of the adder is input to the adder.
  • the adder inputs the sum of the M products to the input of the decider.
  • the role of the arbiter is to compare the equilibrium value of the value to be equalized with the reference value, so as to balance the value of the value.
  • the equalization device will receive the training sequence, and the decider can obtain the true value of each value in the training sequence, so the equalization value can be subtracted from the real value (or other operations), and then Measure how close the equilibrium value is to the true value.
  • X t is located in the buffer of the first delay unit, and the output value of the adder at this time Y 2 may be the equalizer value of X t, X t is the balancing interval [X t + 1, X t , X t-1, X t-2, X t-3 ... X t- (M-2 ) ].
  • X t is sequentially located in the buffer of the second delay unit to the buffer of the M-1th delay unit, in each A time can be used to find an equilibrium value of X t .
  • the prior art X t equalization section is fixed to one of the above interval of N equalizers.
  • Embodiment 2 is a schematic flowchart of a method for setting an equalizer provided in Embodiment 1, and the process includes the following steps:
  • Step 101 When the training sequence including K values is received at the input end of the equalizer, the processor multiplies the t-th value of the K values by the tap coefficient of the i-th tap of the M taps. The output value is used as the equalization value of the t-th value, and the tap coefficients C i of the M taps are determined according to the equalization algorithm; wherein t is any positive integer less than or equal to K, and i is any positive less than or equal to M Integer.
  • the t-th value is any one of the training numbers, and the t-th value may have M kinds of equalization intervals, under the i-th equalization interval of the M equalization intervals (ie, the t-th value)
  • the tap coefficient of each of the M taps in the equalization interval is calculated according to the equalization adaptive algorithm.
  • C i (c 1,i ,c 1,i ,c 2,i ,c 3,i ...c M,i )
  • C i is the t-th value that can be made under the i-th equalization interval
  • the method for determining the C i according to the equalization algorithm may refer to the related technical solutions in the prior art.
  • Step 102 The processor determines an output value Y t,i of the adder when the tap coefficient is C i and the t-th value is multiplied by the tap coefficient of the i-th tap.
  • step 102 under the i-th equalization interval of the t-th value, when the tap coefficient C i is determined, the output value of the adder That is, the optimal equilibrium value of the t-th value in the i-th equilibrium interval.
  • Step 103 The processor determines an equalization evaluation parameter Z t,i when Y t,i is used as the equalization value of the t-th value.
  • the equilibrium evaluation parameter Z t,i can be determined according to the true value of Y t,i and the t-th value , and Y t,i is used as the equilibrium value of the t-th value.
  • the equalization evaluation parameter may specifically be an error value between a data equalization value and a data real value generated by the decision circuit, or may be a bit error rate after data equalization, or may be a data equalization value and a data reality.
  • the statistical minimum mean square error value of the value wherein the mean square error value refers to the square root of the mean of the sum of the squared error values of all the data in the training sequence, and the minimum mean square error value refers to the equilibrium interval The minimum value of the mean square error value.
  • Step 104 the processor determines the Z t, 1 to Z t, the best equalization evaluation parameters M equalizing effect Z t, and it is determined that the t-th value obtained when multiplying the Z t taps tap number S t .
  • steps 101-103 are performed for each equalization interval of the t-th value, and then M equalization values of the t-th value are obtained, and correspondingly, M equalization evaluation parameters are respectively, respectively, Z t,1 To Z t,M , from which the equilibrium evaluation parameter with the best balance effect is determined, that is, Z t , and the equilibrium interval corresponding to Z t is the equilibrium interval with the best balance effect among all possible equalization intervals of the t-th value.
  • the position of the t-th value in the equalization interval is recorded, that is, the tap number S t of the tap multiplied by the t-th value when Z t is obtained.
  • Step 105 After determining the S 1 to S K , the processor determines that the tap number with the most repetition among S 1 to S K is S.
  • steps 101-104 are performed for each of the k values of the training sequence, the preferred equalization interval of each value is determined, and the equilibrium interval with the highest frequency among all the M equalization intervals is counted. , that is: determine the number of taps with the most repetitions among S 1 to S K , denoted as S, and the equilibrium interval with the highest frequency is [X t+1-s, X ts, X t-1-s, ... X t-(Ms) ], where X t is the data to be equalized.
  • the tap number refers to the tap being the first tap of the M taps, for example, the number of the first tap is "1", and the number of the M tap is "M".
  • Step 106 When equalizing the equalized value by the equalization device, the processor determines that the output value of the adder is multiplied by the tap coefficient of the Sth tap of the M taps, and the output value of the adder is an equalized value of the value to be equalized.
  • the equalization device performs formal dispersion equalization on the transmission signal, it is determined that the equalization interval with the highest frequency of occurrence determined in step 105 is determined [X t+1-s, X ts, X t-1-s, ...X T-(Ms) ] is the equalization interval of the data to be equalized Xt , that is, the value of the adder is multiplied by the tap coefficient of the Sth tap of the M taps, and the output value of the adder is the equalized value of the value to be equalized.
  • the equalizer when the equalizer receives the training sequence including K values for the equalizer training, the equalizer performs equalization under the M equalization interval, that is, respectively, the value and the M taps.
  • the output value of the adder (or the decider) is used as the equalization value of the value when each tap is multiplied, and after obtaining the M equalization values of the value, the respective equalization evaluation parameters of the M equalization values are compared. Determining the better equalization interval for the value, after performing the above operations for each value in the training sequence, K better equalization intervals can be obtained, and the highest frequency equilibrium among the K better equalization intervals is calculated.
  • the interval is a formal equalization interval when the equalization device equalizes the input signal. Since the training sequence will be transmitted every time the signal transmission channel changes, the equalization interval of the equalization device can be re-determined for the changed channel, and the channel estimation interval can be adaptively adjusted, which can effectively reduce the error rate.
  • steps 101-103 are performed for each equalization interval of each of the K values, and then step 104 is performed to determine the optimal equalization evaluation of the value. Parameters, then after performing step 104 on all K values, steps 105-106 are performed.
  • the foregoing technical solution in the embodiment of the present application may be performed by using a data flow manner, and the optimal equalization value and the average balance value of each of the K data are calculated in each value interval of the data to be equalized. Evaluate the parameters, then switch to the next value interval, calculate the equilibrium value and the equilibrium evaluation parameters of each data in the value interval, until the above operations are performed for the M equalization intervals, and then compare the statistics of each data. It is better to take the value range and count the best value interval with the highest frequency.
  • the method for setting the equalization device further includes the step 107: when calculating the equalization value of the value to be equalized, the processor sets the tap coefficients of the M taps to C s .
  • C s is the tap coefficient obtained when the value of i in step 101 is S.
  • step 107 When the step 107 is executed, the following two implementation manners may be specifically included:
  • the initial value of the tap coefficients of the M taps is set to C s , and then in the process of equalizing the transmission signal, the tap coefficients are dynamically adjusted according to the feedback value embodying the equalization effect, and the specific implementation manner can refer to the existing implementation manner.
  • a technical solution for dynamically adjusting the tap coefficients in the technology is provided.
  • the tap coefficients of the first set of taps are set to C s , and the tap coefficients are kept unchanged during the equalization of the transmitted signals until the equalizer performs the next training, and the new tap coefficients are re-determined.
  • step 106 and step 107 may be performed simultaneously, or step 106 may be performed first, or step 107 may be performed first.
  • Embodiment 1 of the present application is further applicable to a decision feedback equalization structure with a feedforward equalizer and a feedback equalizer.
  • the equalization interval of the feedforward equalizer is set by using the above.
  • the equalization interval of the feedback equalizer is fixed to a certain equalization interval.
  • the processor may be an integrated chip or may be composed of several independent chips, each of which is responsible for executing different instructions.
  • the transmitter transmits a signal containing the training sequence
  • the feedforward equalizer receives the training sequence and trains to adjust the equalization interval and the tap coefficients.
  • the feedforward equalizer training data x to t in the sequence is the training data to be equalized
  • the equalized data is first to be located at x t feedforward equalizer taps first position, in which the balanced area
  • the iteration is repeated according to the equalization algorithm, the tap coefficient C 1 is determined, and the equilibrium evaluation parameter Z t,1 is calculated.
  • the equalization interval is adjusted such that the data to be equalized x t is located at the second tap position of the feedforward equalizer, and then the tap coefficient C 2 and the equalization evaluation parameter Z t, 2 under the equalization interval are determined.
  • the tap coefficient C 5 and the equalization evaluation parameter Z t,5 are determined .
  • the equilibrium evaluation parameter with the best balance effect is determined as Z t, 2 . Therefore, the better equilibrium interval for determining the t-th value is x t and The output value of the adder when the second tap is multiplied is used as the value interval in the case of the equalization value of x t .
  • the embodiment of the present application provides a method for setting an equalizer, and the method is applied to the equalization device shown in FIG. 4, where the equalization device includes a feedforward equalizer, a feedback equalizer, and a first adder.
  • the feedforward equalizer comprises M-1 series delay units, M taps and a second adder, the input of the feedforward equalizer and the first of the M-1 delay units respectively The input end of each delay unit and the input end of the first one of the M taps, the output end of each of the M-1 delay units and the M of the M taps except the first tap -1 taps are connected one by one, and each of the M taps inputs the product of the input value and the tap coefficient to the input of the second adder, and the second adder inputs the sum of the M products The input of the first adder; see FIG.
  • the feedback equalizer includes N-1 delay units connected in series, N taps and a third adder, and the input ends of the feedback equalizer are respectively associated with N-1 delay units Input of the first delay unit and N taps A first tap input terminal, N-1 th extension
  • the output of each delay unit in the late unit is connected in one-to-one correspondence with the N-1 taps of the N taps except the first tap, and each of the N taps has an input value and a tap coefficient.
  • the multiplied product is input to the input of the third adder, and the third adder inputs the sum of the N products to the input of the first adder, the first adder outputs the output of the second adder and the third adder
  • the sum of the output values is input to the input of the decider, and the output of the decider is coupled to the input of the feedback equalizer.
  • the role of the feedforward equalizer is the same as that of the feedforward equalizer in FIG. 1, and the function of the feedback equalizer is to input the equalization value of the input data that has been obtained before, and feedback.
  • the tap coefficients of the taps of the equalizer are multiplied, and then the superimposed result is added to the equalization value generated by the feedforward equalizer as an equalization value for the current data to be equalized. Therefore, in the equalization structure shown in FIG. 4, the final equalization value of the data to be equalized is related to the input data before and after the data to be equalized (processed by the feedforward equalizer), and also to the equilibrium value of the data before the data to be equalized. (Processed by the feedback equalizer).
  • the first adder, the second adder, and the third adder may be combined into one adder, and the inputs of the first adder and the second adder are used as inputs of the combined adder.
  • the output of the combined adder is used as an input to the decider, and the embodiment of the present application is intended to protect this variant.
  • FIG. 6 is a schematic flowchart of a method for setting an equalization apparatus according to Embodiment 2 of the present application, where the process includes the following steps:
  • Step 201 When receiving the training sequence including K values at the input end of the equalizer, the processor multiplies the t-th value of the K values by the tap coefficient of the i-th tap of the M taps and K When the equalized value of the tjth value in the numerical value is multiplied by the tap coefficient of the first tap of the N taps, the output value of the first adder is used as the equalized value of the tth value, and M taps are determined according to the equalization algorithm.
  • the equalization device shown in FIG. 4 balances the t-th value X t among the k values of the training sequence, according to the continuous M values including X t in the training sequence (by feedforward) The equalizer process) and the equalization value of X t based on the equalization values of the N consecutive values before X t (processed by the feedback equalizer). Since the continuous M values multiplied by the M taps in the feedforward equalizer can have M values (X t is multiplied by different taps for each value).
  • the continuous N values multiplied by N taps in the feedback equalizer may have t-1 values.
  • the number of values is limited to the set value L, that is, the feedback equalizer has L kinds of equalization intervals, wherein the first equalization interval is [Y t-1 , Yt t-2 , Y t-3 ..Y tN ]
  • the value is multiplied by the tap coefficients of the N taps of the feedback equalizer and the N products are added as the input of the first adder.
  • the feedforward equalizer has M equalization intervals
  • the feedback equalizer consists of N kinds of equalization intervals
  • the entire equalization device has M*L kinds of equalization structures.
  • step 201 for any one of the M*L kinds of equalization structures of Xt , the tap coefficients of the feedforward equalizer and the coefficients of the feedback equalizer under the equalization structure are obtained according to the equalization adaptive algorithm. That is, multiplying the t-th value of the K values by the tap coefficient of the i-th tap of the M taps and the equal-value of the tj-th value of the K values and the first tap of the N taps the tap coefficients are multiplied output value of the first adder as the equilibrium value of the t-th value, determined according to the equalization algorithm M taps of the tap coefficients C i, j N taps and tap coefficients D i, j, wherein , C i,j represents the set of the tap coefficients of each of the M taps of the feedforward equalizer after the adaptive equalization is achieved in the current equalization structure, and D i,j represents the reaching of the current equalization structure.
  • Step 202 The processor determines that the tap coefficients of the M taps are C i,j , the tap coefficients of the N taps are D i,j , the t values are multiplied by the tap coefficients of the i th taps, and the tj values are The output value Y t,i,j of the first adder when the equalization value is multiplied by the tap coefficient of the first tap of the N taps.
  • Step 203 The processor determines an equalization evaluation parameter Z t,i,j when Y t,i,j is used as the equalization value of the t-th value.
  • the equalization evaluation parameter Z t,i,j when Y t,i,j is used as the equilibrium value of the t-th value is determined to measure the equalization effect of the equalization structure, and the definition of the equilibrium evaluation parameter in the embodiment 2 is determined. Reference may be made to the definition of the equalization evaluation parameter in Embodiment 1.
  • Step 204 The processor determines that the equalization evaluation parameter with the best balance effect in Z t,1,1 to Z t,M,L is Z t , and determines the M data and the t data in the Z t when the Z t is obtained. multiplying taps tap number i 1 and N taps and a tap in the first data multiplied by a first value tj 1 equalized values.
  • t is the X-averaging effect best unbalanced structure, namely: M i 1 taps first tap data and the t-th multiplication, N taps of a tap of the first equalized tj 1 values with The time-sharing equilibrium structure.
  • Step 205 After determining the Z 1 to Z K , the processor determines that the most frequently occurring value of all the values of (i 1 , j 1 ) is (s, h).
  • a better equalization structure of a value is represented by the feature array (i 1 , j 1 ).
  • K better equalizations can be obtained.
  • Structure the best equilibrium structure with the highest frequency is counted, that is, it is determined that the most frequent occurrences of (i 1 , j 1 ) are (s, h), and the feature array (s, h) is characterized.
  • the equilibrium structure is the highest frequency equilibrium structure.
  • Step 206 When equalizing the equalized value by the equalization device, the processor determines that the value to be equalized is multiplied by the tap coefficient of the sth tap of the M taps, the equalized value of the thth value, and the first of the N taps When the tap coefficients of one tap are multiplied, the output value of the first adder is an equalized value of the value to be equalized.
  • the equalizing device determines the highest frequency equalizing structure occurs using the procedure determined out of 205 treated as equalized data X t equalizer that equalizes the structure, i.e., determines to be equalized values and the M
  • the tap coefficients of the sth tap in the tap are multiplied, and the equalization value of the th th value is multiplied by the tap coefficient of the first tap of the N taps, the output value of the first adder is an equalized value of the value to be equalized .
  • the equalizer receives the training sequence including K values.
  • each value is equalized under the M*L kind of equalization structure, that is, the value is multiplied by each of the M taps and the tjth value of the K values is respectively
  • the equalization value is multiplied by the tap coefficient of the first tap of the N taps
  • the output value of the first adder is used as the equalization value of the t-th value
  • the comparison obtains M*
  • the equalization evaluation parameters can be used to determine the better equalization structure for the value.
  • K better equilibrium structures can be obtained.
  • the highest frequency equalization structure appears in the K preferred equalization structures, which can be used as a formal equalization structure when the equalization device equalizes the input signal. Since the training sequence will be transmitted every time the signal transmission channel changes, the equalization structure of the equalization device can be re-determined for the changed channel, and the channel estimation interval can be adaptively adjusted, which can effectively reduce the error rate.
  • the technical solution in the second embodiment can also be performed in a bit-by-bit manner, or all signals in the training sequence can be processed in an equalization structure, that is, by means of data flow, Let me give an example.
  • step 206 the following steps are further included:
  • Step 207 When calculating the equalization value of the value to be equalized, the processor sets the tap coefficients of the M taps to C s,h , and sets the tap coefficients of the N taps to D s,h .
  • C s,h is the tap coefficient of the feedforward equalizer obtained when the value of i in step 201 is S and j is h
  • D s,h is the value of i in step 201, S, j.
  • the tap coefficient of the feedback equalizer obtained when the value is h.
  • step 207 When the step 207 is executed, the following two implementation manners may be specifically included:
  • the initial values of the tap coefficients of the M taps are set to C s,h
  • the initial values of the tap coefficients of the N taps are set to D s,h
  • the process of equalizing the transmitted signals is performed.
  • the tap coefficients of the taps of the feedforward equalizer and the feedback equalizer are dynamically adjusted according to the feedback value embodying the equalization effect. For the specific implementation manner, reference may be made to the technical solution for dynamically adjusting the tap coefficients in the prior art.
  • the initial value of the tap coefficients of the M taps is set to C s,h
  • the initial values of the tap coefficients of the N taps are set to D s,h , in the process of equalizing the transmitted signals. , so that the tap coefficient remains unchanged until the equalizer performs the next training, and then the new tap coefficient is re-determined.
  • step 206 and step 207 may be performed simultaneously, or step 206 may be performed first, or step 207 may be performed first.
  • the processor may be an integrated chip or may be composed of several independent chips, each of which is responsible for executing different instructions.
  • the process of determining the equilibrium evaluation parameter Z t of the t-th value of the K values will be described below with reference to FIG. It may be exemplified that the feedforward equalizer has 5 taps, the feedback equalizer has 3 taps, and the set value L is equal to 6 as an example, and the manner of changing the equalization structure of the equalizer in a traversal manner is described in detail.
  • the equalization interval of the feedforward equalizer is set to the A 1 equalization interval (that is, X t is multiplied by the first tap of the M taps), and under the A 1 equalization interval, the equalization of the feedback equalizer is performed.
  • the interval is set to the B 1 equalization interval (ie, Y t-1 is multiplied by the first one of the N taps), and the tap coefficient of the tap of the feedforward equalizer at this time is determined to be C 1,1 .
  • the tap coefficient of the tap of the feedback equalizer is D 1,1
  • the equalization evaluation parameter is Z 1,1, .
  • the first value range is set to the A 2 value range (X t is multiplied by the second one of the M taps), and the second value range is set to the B 1 value range to determine
  • the first tap coefficient is C 2,1
  • the second tap coefficient is D 2,1
  • the equilibrium evaluation parameter is Z 2,1 .
  • the second range is set to values of B 6
  • the range determines that the first tap coefficient is C 5,6
  • the second tap coefficient is D 5,6
  • the equilibrium evaluation parameter is Z 5,6 .
  • the equilibrium evaluation parameter with the best balance effect is selected, which is Z t .
  • the embodiment of the present application further provides an equalization device 300 for implementing the method described in FIG. 2 and its embodiments.
  • the equalization device 300 is coupled to the equalizer and the decider.
  • the equalizer includes M-1 delay units connected in series, M taps and an adder, wherein the input ends of the equalizer are respectively input to the input end of the first delay unit of the M-1 delay units and the M taps The input ends of the first taps are connected, and the output ends of each of the M-1 delay units are connected in one-to-one correspondence with the M-1 taps of the M taps except the first tap, M Each tap of each tap inputs the product of the input value and the tap coefficient to the input of the adder, and the adder inputs the sum of the M products to the input of the decider.
  • the equalization device 300 includes:
  • the first determining unit 301 is configured to: when the equalizer receives the training sequence including K values, the multiplier when the t-th value of the K values is multiplied by the tap coefficient of the i-th tap of the M taps The output value is used as the equalization value of the t-th value, and the tap coefficients C i of the M taps are determined according to the equalization algorithm; wherein t is any positive integer less than or equal to K, and i is any positive less than or equal to M Integer
  • the second determining unit 302 is configured to determine an output value Y t,i of the adder when the tap coefficient is C i and the t-th value is multiplied by the tap coefficient of the ith tap;
  • a third determining unit 303 configured to determine an equalization evaluation parameter Z t,i when Y t,i is used as the equalization value of the t-th value
  • the fourth determining unit 304 is configured to determine that the equalization evaluation parameter with the best balance effect in Z t, 1 to Z t, M is Z t , and determine the tap of the t-th value when the Z t is obtained.
  • Tap number S t is configured to determine that the equalization evaluation parameter with the best balance effect in Z t, 1 to Z t, M is Z t , and determine the tap of the t-th value when the Z t is obtained.
  • the fifth determining unit 305 is configured to determine, after determining S 1 to S K , that the tap number with the highest number of repetitions among S 1 to S K is S;
  • the sixth determining unit 306 is configured to: when the equalization device is used to equalize the equalized value, determine that the output value of the adder is multiplied by the tap coefficient of the Sth tap of the M taps, and the output value of the adder is an equalized value value.
  • the equalization device 300 further includes:
  • the setting unit 307 is configured to set the tap coefficients of the M taps to C s when calculating the equalization value of the values to be equalized.
  • the equalization device in this embodiment and the method for setting the equalization device in Embodiment 1 are based on two aspects under the same inventive concept.
  • the implementation process of the method has been described in detail above, so that those skilled in the art can
  • the foregoing description clearly understands the structure and implementation process of the equalization apparatus in this embodiment. For the sake of brevity of the description, details are not described herein again.
  • the embodiment of the present application further provides an equalization device 400 for implementing the method described in FIG. 6 and its embodiments.
  • Equalization device 400 is coupled to the feed forward equalizer, the feedback equalizer, the first adder, and the decider, respectively.
  • the feedforward equalizer comprises M-1 series delay units, M taps and a second adder, and the input end of the feedforward equalizer and the input end of the first delay unit of the M-1 delay units respectively And the input end of the first tap of the M taps is connected, and the output end of each of the M-1 delay units and the M-1 taps of the M taps except the first tap are one by one Correspondingly connected, each of the M taps inputs the product of the input value and the tap coefficient into the input of the second adder, and the second adder inputs the sum of the M products into the input of the first adder.
  • the feedback equalizer includes N-1 delay units connected in series, N taps, and a third adder, and the input ends of the feedback equalizer are respectively input to the first delay unit of the N-1 delay units and the N
  • the input of the first tap of the taps is connected, and the output of each of the N-1 delay units is in one-to-one correspondence with the N-1 taps of the N taps other than the first tap Connection, each of the N taps multiplies the input value by the tap coefficient
  • the third adder inputs the sum of the N products to the input of the first adder, and the first adder sums the output value of the second adder and the output value of the third adder
  • the value is input to the input of the decider, and the output of the decider is coupled to the input of the feedback equalizer.
  • the equalization device 400 includes:
  • the first determining unit 401 is configured to multiply the t-th value of the K values by the tap coefficient of the ith tap of the M taps and K when the equalizer receives the training sequence including the K values
  • the equalized value of the tjth value in the numerical value is multiplied by the tap coefficient of the first tap of the N taps
  • the output value of the first adder is used as the equalized value of the tth value
  • M taps are determined according to the equalization algorithm.
  • the second determining unit 402 is configured to determine that the tap coefficients of the M taps are C i,j , the tap coefficients of the N taps are D i,j , and the t-th value is multiplied by the tap coefficients of the i-th tap, The output value of the first adder Y t,i,j when the equalized value of the tj values is multiplied by the tap coefficient of the first tap of the N taps;
  • a third determining unit 403, configured to determine an equalization evaluation parameter Z t,i,j when Y t,i,j is used as the equalization value of the t-th value;
  • the fourth determining unit 404 is configured to determine that the equalization evaluation parameter with the best balance effect in Z t,1,1 to Z t,M,L is Z t , and determine that the M taps are obtained in the Z t t multiplication data taps and tap number i 1 data multiplied with the N taps as a first tap of the first equalized values tj 1 value;
  • the fifth determining unit 405 is configured to determine, after determining Z 1 to Z K , that the most occurrences of all the values of (i 1 , j 1 ) are (s, h);
  • the sixth determining unit 406 is configured to determine, when the equalization device equalizes the equalized value, multiply the value to be equalized by the tap coefficient of the sth tap of the M taps, and the equalized value of the thth value and the N taps When the tap coefficients of the first tap in the multiplication are multiplied, the output value of the first adder is an equalized value of the value to be equalized.
  • the equalization apparatus 400 further includes:
  • the setting unit 407 is configured to set the tap coefficients of the M taps to C s,h when calculating the equalization value of the values to be equalized, and set the tap coefficients of the N taps to D s,h .
  • the equalization device in this embodiment and the method for setting the equalization device in Embodiment 2 are based on two aspects under the same inventive concept.
  • the implementation process of the method has been described in detail above, so that those skilled in the art can
  • the foregoing description clearly understands the structure and implementation process of the equalization apparatus in this embodiment. For the sake of brevity of the description, details are not described herein again.
  • the embodiment of the present application further provides an equalization apparatus 500.
  • the equalization apparatus 500 includes an equalizer and a decider.
  • the equalizer includes M-1 delay units connected in series, and M taps.
  • an adder wherein the input of the equalizer is respectively connected to the input of the first delay unit of the M-1 delay units and the input of the first tap of the M taps, M-1 delays
  • the output of each delay unit in the unit is connected in one-to-one correspondence with the M-1 taps of the M taps except the first tap, and each of the M taps multiplies the input value by the tap coefficient
  • the latter product is input to the input of the adder, which adds the sum of the M products to the input of the decider.
  • the equalization apparatus 500 further includes a bus 503 and a processor 501 and a storage unit 502 connected to the bus.
  • the storage unit 502 is configured to store instructions
  • the processor 501 is configured to execute instructions in the storage unit 502.
  • the storing unit 502 includes: when the equalizer receives the training sequence including the K values, multiplying the t-th value of the K values by the tap coefficient of the ith tap of the M taps
  • the output value of the time adder is used as the equalization value of the t-th value, and the tap coefficients C i of the M taps are determined according to the equalization algorithm; wherein t is any positive integer less than or equal to K, and i is less than or equal to M Any positive integer; determining the output coefficient Y t,i of the adder when the tap coefficient is C i , the t-th value is multiplied by the tap coefficient of the i-th tap; determining Y t,i as the t-th value equalization evaluation parameter Z t, i when the equilibrium value; determined Z t, 1 to Z t, the best equalization evaluation parameters M equalizing effect Z t, and it is determined that the t-th value obtained when the Z t
  • the storage unit further stores an instruction: when calculating the equalization value of the value to be equalized, setting the tap coefficients of the M taps to C s .
  • the processor 601 may be an integrated chip or may be composed of several independent chips, each of which is responsible for executing different instructions.
  • the equalization device in this embodiment and the method for setting the equalization device in Embodiment 1 are based on two aspects under the same inventive concept.
  • the implementation process of the method has been described in detail above, so that those skilled in the art can
  • the foregoing description clearly understands the structure and implementation process of the equalization apparatus in this embodiment. For the sake of brevity of the description, details are not described herein again.
  • the embodiment of the present application further provides an equalization device 600.
  • the equalization device 600 includes a feedforward equalizer, a feedback equalizer, a first adder, and a decider.
  • the feedforward equalizer includes an M-1. a series of delay units, M taps and a second adder, the input of the feedforward equalizer and the input of the first delay unit of the M-1 delay units and the first of the M taps
  • the input terminals are connected, and the output end of each of the M-1 delay units is connected in one-to-one correspondence with the M-1 taps of the M taps except the first tap, and each of the M taps
  • the taps multiply the product of the input value and the tap coefficient into the input of the second adder, and the second adder inputs the sum of the M products to the input of the first adder
  • the feedback equalizer includes N-1 a series delay unit, N taps, and a third adder, the input of the feedback equalizer and the input of the first one of the N-1 delay units and the input
  • the third adder inputs the sum value of the N products to the input end of the first adder, and the first adder inputs the sum of the output value of the second adder and the output value of the third adder
  • the input of the arbiter is connected to the input of the feedback equalizer.
  • the equalization apparatus 600 further includes a bus 603 and a processor 601 and a storage unit 602 connected to the bus 603.
  • the storage unit 602 is configured to store instructions
  • the processor 601 is configured to execute instructions in the storage unit 602.
  • the instruction stored in the storage unit 602 includes: when the equalizer receives the training sequence including K values, the t-th value of the K values and the tap coefficient of the ith tap of the M taps Multiplying the equalized value of the tjth value of the K values by the tap coefficient of the first tap of the N taps, the output value of the first adder is used as the equalized value of the tth value, and is determined according to the equalization algorithm the M taps of the tap coefficients C i, j and N taps of the tap coefficients D i, j; determining the tap coefficients M taps for C i, j, N taps tap coefficients D i, j, the first The t value is multiplied by the tap coefficient of the i-th tap, and the equalized value of the tjth value is multiplied by the tap coefficient of the first tap of the N taps.
  • the output value of the first adder Y t,i,j Determine the equilibrium evaluation parameter Z t,i,j when Y t,i,j is used as the equilibrium value of the t-th value; determine the best balance effect in Z t,1,1 to Z t,M,L the evaluation parameters of equalization Z t, and determines the M taps with the t-th multiplied data taps and tap number i 1 and N taps of the first pumping acquired when the Z t Multiplying data for the first numerical value tj 1 is equalized; after determining that Z 1 to Z K, it is determined that (i 1, j 1) all the values appearing in the value of the highest number (s, h) When equalizing the equalized value with the equalization device, determining that the value to be equalized is multiplied by the tap coefficient of the sth tap of the M taps, the equalized value of the thth value, and the first tap of the N taps When the tap coefficients are multiplied, the output of the first add
  • the storage unit further stores an instruction: when calculating the equalization value of the value to be equalized, setting the tap coefficients of the M taps to C s,h , and setting the tap coefficients of the N taps to D s,h .
  • the processor 601 may be an integrated chip or may be composed of several independent chips, each of which is responsible for executing different instructions.
  • the equalization device in this embodiment and the method for setting the equalization device in Embodiment 2 are based on two aspects under the same inventive concept.
  • the implementation process of the method has been described in detail above, so that those skilled in the art can
  • the foregoing description clearly understands the structure and implementation process of the equalization apparatus in this embodiment. For the sake of brevity of the description, details are not described herein again.
  • the equalizer when the equalizer receives the training sequence including K values for the equalizer training, the equalizer performs equalization under the M equalization interval, that is, the value and the M values respectively.
  • the output value of the adder (or the decider) is multiplied by each tap in the tap as the equalization value of the value, and after obtaining the M equalization values of the value, the respective equalization evaluation parameters when the M equalization values are obtained are compared, ie The better equalization interval for the value can be determined.
  • K preferred equalization intervals can be obtained, and the highest frequency among the K preferred equalization intervals is counted.
  • the equalization interval can be used as a formal equalization interval when the equalization device equalizes the input signal. Since the training sequence will be transmitted every time the signal transmission channel changes, the equalization interval of the equalization device can be re-determined for the changed channel. Adjusting the channel estimation interval adaptively can effectively reduce the bit error rate.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

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Abstract

本发明提供一种设置均衡装置的方法及均衡装置，该方法包括：以K个数值中的第t个数值与M个抽头中的第i个抽头的抽头系数相乘时加法器的输出值作为第t个数值的均衡值，根据均衡算法确定出M个抽头的抽头系数Ci；确定出抽头系数为Ci、第t个数值与第i个抽头的抽头系数相乘时加法器的输出值Yt,i；确定出以Yt,i作为第t个数值的均衡值时的均衡评估参数Zt,i；确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与第t个数值相乘的抽头的抽头编号St；确定出S1至SK之中重复次数最多的抽头编号为S；在利用均衡装置对待均衡数值进行均衡时，确定待均衡数值与M个抽头中的第S个抽头的抽头系数相乘时加法器的输出值为待均衡数值的均衡值。

Description

一种设置均衡装置的方法及均衡装置 技术领域
本发明涉及通信领域，尤其涉及一种设置均衡装置的方法及均衡装置。
背景技术
在光纤通信系统中，随着传输速率的提高，色散已经成为限制传输距离、影响传输质量的一个主要因素。抑制色散通常有两种方式：一种是光域色散补偿；另一种是电色散补偿(Electronic Dispersion Compensation，EDC)。
光域色散补偿采用色散补偿光纤或者色散补偿光栅对光信号在传输过程中的色散进行补偿。采用色散补偿光纤进行色散补偿时，由于色散斜率会导致色散补偿不完全，使得不同信道上具有不同的残余色散，而且还会带来较大的插入损耗，需要额外增加大量的光纤放大器，但随之会引入自发辐射噪声，降低传输信号的信噪比。采用色散补偿光栅虽然损耗很小，但是光谱通带很小，一个补偿光栅只能补偿一个通道，成本很高。另外，光域色散补偿的补偿范围由补偿器件决定，不能动态变化，缺乏自适应补偿能力。
电色散补偿技术通过对接收光信号在电域内进行抽样，软件优化和信号复原，能够根据链路损伤情况自适应地调节接收信号的波形，恢复由于群速度色散、偏振膜色散以及非线性引起的光信号展宽和失真，进而实现信号均衡。而且，电色散补偿模块(或芯片)能够直接集成在光接收机内，设计灵活、成本较低。上述特性使得电色散补偿技术成为目前一种关键的色散补偿技术。
电色散补偿技术的方案之一是采用前馈均衡器(Feed Forward Equalizer，FFE)进行均衡，参见图1，为FFE的结构示意图，FFE包括N个串联的延迟单元、N+1个抽头和一个加法器。N+1个抽头的间隔Tb可以为码元的周期T(码元间隔均衡器)，Tb也可以为部分码元周期(分数间隔均衡器)。FFE把所收到的信号的当前值和过去值按抽头系数Cn(即权重)作线性迭加，并把 生成的和作为输出，发送至判决器。
FFE的响应表达式为：
Figure PCTCN2014093411-appb-000001
式中hk为对FFE接收到的第K个数值的均衡值，xk-n为FFE收到的第K-n个数值。
FFE结构简单，容易实现，但是，由于FFE的均衡区间固定不变，信道估计区间不能改变，导致在信号传输信道改变时不能有效降低系统误码率。
发明内容
本申请实施例提供一种设置均衡装置的方法及均衡装置，用于解决现有技术中均衡装置的均衡区间不能自动改变的技术问题。
第一方面，本申请实施例提供了一种设置均衡装置的方法，所述均衡装置包括均衡器、判决器和处理器，所述均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器，其中，所述均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述加法器的输入端，所述加法器将M个乘积的和值输入所述判决器的输入端，所述方法包括：
在所述均衡器的输入端接收到包含K个数值的训练序列时，所述处理器以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘时所述加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；
所述处理器确定出所述抽头系数为Ci、所述第t个数值与所述第i个抽头的抽头系数相乘时所述加法器的输出值Yt,i；
所述处理器确定出以Yt,i作为所述第t个数值的均衡值时的均衡评估参数Zt,i；
所述处理器确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与所述第t个数值相乘的抽头的抽头编号St；
所述处理器在确定出S1至SK之后，确定出所述S1至SK之中重复次数最多的抽头编号为S；
在利用所述均衡装置对待均衡数值进行均衡时，所述处理器确定所述待均衡数值与所述M个抽头中的第S个抽头的抽头系数相乘时所述加法器的输出值为所述待均衡数值的均衡值。
结合第一方面，在第一方面的第一种可能的实现方式中，所述方法还包括：
在计算所述待均衡数值的均衡值时，所述处理器将所述M个抽头的抽头系数设置为Cs。
第二方面，本申请实施例提供一种设置均衡装置的方法，所述均衡装置包括前馈均衡器、反馈均衡器、第一加法器、判决器以及处理器，其中，所述前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，所述前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第二加法器的输入端，所述第二加法器将M个乘积的和值输入所述第一加法器的输入端；所述反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，所述反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及所述N个抽头中的第一个抽头的输入端相连，所述N-1个延迟单元中的每个延迟单元的输出端与所述N个抽头中除第一个抽头之外的N-1个抽头一一对应地连接，所述N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第三加法器的输入端，所述第三加法器将N个乘积的和值输入所述第一加法器的输入端，所述第一加法器将所述第二加法器的输出值和所述第三加法器的输出值的和值输入所述判决器的输入端，所述 判决器的输出端与所述反馈均衡器的输入端相连，所述方法包括：
在所述均衡器的输入端接收到包含K个数值的训练序列时，所述处理器以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘且所述K个数值中的第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci,j和所述N个抽头的抽头系数Di,j；其中，i为小于等于M的任一正整数，j为小于等于设定值L的任一正整数；
所述处理器确定出所述M个抽头的抽头系数为Ci,j、所述N个抽头的抽头系数为Di,j、所述第t个数值与所述第i个抽头的抽头系数相乘、所述第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值Yt,i,j；
所述处理器确定出以Yt,i,j作为所述第t个数值的均衡值时的均衡评估参数Zt,i,j；
所述处理器确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时所述M个抽头中与所述第t个数据相乘的抽头的抽头编号i1以及与所述N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值；
所述处理器在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)；
在利用所述均衡装置对待均衡数值进行均衡时，所述处理器确定所述待均衡数值与所述M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值为所述待均衡数值的均衡值。
结合第二方面，在第二方面的第一种可能的实现方式中，所述方法还包括：
在计算所述待均衡数值的均衡值时，所述处理器将所述M个抽头的抽头系数设置为Cs,h，将所述N个抽头的抽头系数设置为Ds,h。
第三方面，本申请实施例提供一种均衡装置，所述均衡装置分别与均衡器、判决器相连，所述均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器，其中，所述均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述加法器的输入端，所述加法器将M个乘积的和值输入所述判决器的输入端，所述均衡装置包括：
第一确定单元，用于在所述均衡器接收到包含K个数值的训练序列时，以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘时所述加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；
第二确定单元，用于确定出所述抽头系数为Ci、所述第t个数值与所述第i个抽头的抽头系数相乘时所述加法器的输出值Yt,i；
第三确定单元，用于确定出以Yt,i作为所述第t个数值的均衡值时的均衡评估参数Zt,i；
第四确定单元，用于确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与所述第t个数值相乘的抽头的抽头编号St；
第五确定单元，用于在确定出S1至SK之后，确定出所述S1至SK之中重复次数最多的抽头编号为S；
第六确定单元，用于在利用所述均衡装置对待均衡数值进行均衡时，确定所述待均衡数值与所述M个抽头中的第S个抽头的抽头系数相乘时所述加法器的输出值为所述待均衡数值的均衡值。
结合第三方面，在第三方面的第一种可能的实现方式中，所述均衡装置还包括：
设置单元，用于在计算所述待均衡数值的均衡值时将所述M个抽头的抽 头系数设置为Cs。
第四方面，本申请实施例提供一种均衡装置，所述均衡装置分别与前馈均衡器、反馈均衡器、第一加法器以及判决器相连，其中，所述前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，所述前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第二加法器的输入端，所述第二加法器将M个乘积的和值输入所述第一加法器的输入端；所述反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，所述反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及所述N个抽头中的第一个抽头的输入端相连，所述N-1个延迟单元中的每个延迟单元的输出端与所述N个抽头中除第一个抽头之外的N-1个抽头一一对应地连接，所述N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第三加法器的输入端，所述第三加法器将N个乘积的和值输入所述第一加法器的输入端，所述第一加法器将所述第二加法器的输出值和所述第三加法器的输出值的和值输入所述判决器的输入端，所述判决器的输出端与所述反馈均衡器的输入端相连，所述均衡装置包括：
第一确定单元，用于在所述均衡器接收到包含K个数值的训练序列时，以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘且所述K个数值中的第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci,j和所述N个抽头的抽头系数Di,j；其中，i为小于等于M的任一正整数，j为小于等于设定值L的任一正整数；
第二确定单元，用于确定出所述M个抽头的抽头系数为Ci,j、所述N个抽头的抽头系数为Di,j、所述第t个数值与所述第i个抽头的抽头系数相乘、 所述第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值Yt,i,j；
第三确定单元，用于确定出以Yt,i,j作为所述第t个数值的均衡值时的均衡评估参数Zt,i,j；
第四确定单元，用于确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时所述M个抽头中与所述第t个数据相乘的抽头的抽头编号i1以及与所述N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值；
第五确定单元，用于在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)；
第六确定单元，用于在利用所述均衡装置对待均衡数值进行均衡时，确定所述待均衡数值与所述M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值为所述待均衡数值的均衡值。
结合第四方面，在第四方面的第一种可能的实现方式中，所述均衡装置还包括：
设置单元，用于在计算所述待均衡数值的均衡值时将所述M个抽头的抽头系数设置为Cs,h，将所述N个抽头的抽头系数设置为Ds,h。
第五方面，本申请实施例提供一种均衡装置，所述均衡装置包括均衡器和判决器，所述均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器，其中，所述均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述加法器的输入端，所述加法器将M个乘积的和值输入所述判决器的输入端，所述均衡装置还包括：
存储单元，用于存储指令，所述指令包括：在所述均衡器接收到包含K 个数值的训练序列时，以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘时所述加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；确定出所述抽头系数为Ci、所述第t个数值与所述第i个抽头的抽头系数相乘时所述加法器的输出值Yt,i；确定出以Yt,i作为所述第t个数值的均衡值时的均衡评估参数Zt,i；确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与所述第t个数值相乘的抽头的抽头编号St；在确定出S1至SK之后，确定出所述S1至SK之中重复次数最多的抽头编号为S；在利用所述均衡装置对待均衡数值进行均衡时，确定所述待均衡数值与所述M个抽头中的第S个抽头的抽头系数相乘时所述加法器的输出值为所述待均衡数值的均衡值；
处理器，用于执行所述指令。
结合第五方面，在第五方面的第一种可能的实现方式中，所述存储单元还存储有指令：在计算所述待均衡数值的均衡值时，将所述M个抽头的抽头系数设置为Cs。
第六方面，本申请实施例提供一种均衡装置，所述均衡装置包括前馈均衡器、反馈均衡器、第一加法器以及判决器，其中，所述前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，所述前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第二加法器的输入端，所述第二加法器将M个乘积的和值输入所述第一加法器的输入端；所述反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，所述反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及所述N个抽头中的第一个抽头的输入端相连，所述N-1个延迟单元中的每个延迟单元的输出端与所述N个抽头中除第一个抽头之外的N-1个抽头一一 对应地连接，所述N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第三加法器的输入端，所述第三加法器将N个乘积的和值输入所述第一加法器的输入端，所述第一加法器将所述第二加法器的输出值和所述第三加法器的输出值的和值输入所述判决器的输入端，所述判决器的输出端与所述反馈均衡器的输入端相连，所述均衡装置还包括：
存储单元，用于存储指令，所述指令包括：在所述均衡器接收到包含K个数值的训练序列时，以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘且所述K个数值中的第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci,j和所述N个抽头的抽头系数Di,j，其中，i为小于等于M的任一正整数，j为小于等于设定值L的任一正整数；确定出所述M个抽头的抽头系数为Ci,j、所述N个抽头的抽头系数为Di,j、所述第t个数值与所述第i个抽头的抽头系数相乘、所述第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值Yt,i,j；确定出以Yt,i,j作为所述第t个数值的均衡值时的均衡评估参数Zt,i,j；确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时所述M个抽头中与所述第t个数据相乘的抽头的抽头编号i1以及与所述N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值；在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)；在利用所述均衡装置对待均衡数值进行均衡时，确定所述待均衡数值与所述M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值为所述待均衡数值的均衡值；
处理器，用于执行所述指令。
结合第六方面，在第六方面的第一种可能的实现方式中，所述存储单元还存储有指令：在计算所述待均衡数值的均衡值时，将所述M个抽头的抽头系数设置为Cs,h，将所述N个抽头的抽头系数设置为Ds,h。
本申请实施例中提供的一个或多个技术方案，至少具有如下技术效果或优点：
本申请实施例提供的技术方案中，均衡器在接收到包含K个数值的训练序列进行均衡器训练时，使每一个数值在M种均衡区间下进行均衡，即，分别将该数值与M个抽头中的每一个抽头相乘时加法器(或者判决器)的输出值作为该数值的均衡值，获得该数值的M个均衡值之后，比较获得M个均衡值时各自的均衡评估参数，即可确定出针对该数值较佳的均衡区间，在针对训练序列中的每一个数值均进行上述操作之后，即可获得K个较佳均衡区间，统计出K个较佳均衡区间中出现频次最高的均衡区间，即可作为均衡装置对输入信号进行均衡时的正式均衡区间。由于每次信号传输信道改变时都将发送训练序列，因此能够针对改变后的信道重新确定均衡装置的均衡区间，适应性地调整信道估值区间，能够有效地降低误码率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为FFE的结构示意图；
图2为本申请实施例1中设置均衡装置的方法的流程示意图；
图3为本申请实施例1中均衡器的均衡区间移动的示意图；
图4为本申请实施例2中的均衡装置的结构示意图；
图5为本申请实施例2中反馈均衡器的结构示意图；
图6为本申请实施例2中设置均衡装置的方法的流程示意图；
图7为本申请实施例2中前馈均衡器和反馈均衡器的均衡区间移动的示意图；
图8为本申请实施例3中均衡装置的结构示意框图；
图9为本申请实施例4中均衡装置的结构示意框图；
图10为本申请实施例5中均衡装置的结构示意框图；
图11为本申请实施例6中均衡装置的结构示意框图。
具体实施方式
针对均衡装置的均衡区间不能自动改变的技术问题，本申请实施例提供了一种设置均衡装置的方法，所述均衡装置包括均衡器、判决器和处理器，所述均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器，其中，所述均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述加法器的输入端，所述加法器将M个乘积的和值输入所述判决器的输入端，所述方法包括：在所述均衡器接收到包含K个数值的训练序列时，所述处理器以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘时所述加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；所述处理器确定出所述抽头系数为Ci、所述第t个数值与所述第i个抽头的抽头系数相乘时所述加法器的输出值Yt,i；所述处理器确定出以Yt,i作为所述第t个数值的均衡值时的均衡评估参数Zt,i；所述处理器确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与所述第t个数值相乘的抽头的抽头编号St；所述处理器在确定出S1至SK之后，确定出所述S1至SK之中重复次数最多的抽头编号为S；在利用所述均衡装置对待均衡数值进行均衡时，所述处理器确定所述待均衡数值与所述M个抽头中的第S个抽头的抽头系数相乘时所述加法器的输出值为所述待均衡数值的均衡值。
本申请实施例提供的技术方案中，均衡器在接收到包含K个数值的训练 序列进行均衡器训练时，使每一个数值在M种均衡区间下进行均衡，即，分别将该数值与M个抽头中的每一个抽头相乘时加法器(或者判决器)的输出值作为该数值的均衡值，获得该数值的M个均衡值之后，比较获得M个均衡值时各自的均衡评估参数，即可确定出针对该数值较佳的均衡区间，在针对训练序列中的每一个数值均进行上述操作之后，即可获得K个较佳均衡区间，统计出K个较佳均衡区间中出现频次最高的均衡区间，即可作为均衡装置对输入信号进行均衡时的正式均衡区间。由于每次信号传输信道改变时都将发送训练序列，因此能够针对改变后的信道重新确定均衡装置的均衡区间，适应性地调整信道估值区间，能够有效地降低误码率。
下面通过附图以及具体实施例对本申请技术方案做详细的说明，应当理解本申请实施例以及实施例中的具体特征是对本申请技术方案的详细的说明，而不是对本申请技术方案的限定，在不冲突的情况下，本申请实施例以及实施例中的技术特征可以相互组合。
实施例1
本申请实施例提供的设置均衡装置的方法可以应用于图1所示的均衡装置，该均衡装置包括均衡器和判决器，均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器以及处理器。
其中，M-1个延迟单元中相邻延迟单元的时间间隔为Tb，Tb可以与训练序列中相邻数值的时间间隔T相同，也可以小于T，本申请实施例以下内容以Tb等于T为例对本申请实施例提供的方法进行介绍。均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及M个抽头中的第一个抽头的输入端相连，M-1个延迟单元中的每个延迟单元的输出端与M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入加法器的输入端，加法器将M个乘积的和值输入判决器的输入端。判决器的作用是将待均衡数值的均衡值与参考值比较，以此来对数值的衡量均衡效果。在均衡器训练阶段，均衡装置将接收到训练序列，而判决器是能够获取到训练序列中每个数值的真实值，因此可 以将均衡值与真实值进行相减(或其他运算)，依次来衡量均衡值与真实值的接近程度。
不妨设在时刻T1＝0时，训练序列中的第t个数值Xt输入均衡器，此时M-1个延迟单元中依次存储了Xt-1、Xt-2、Xt-3…Xt-(M-1)，此时加法器的输出值
Figure PCTCN2014093411-appb-000002
式中，ch为M个抽头中第h个抽头的抽头系数，可以以Y1为Xt的均衡值，Xt对应的均衡区间为[Xt,Xt-1,Xt-2,Xt-3…Xt-(M-1)],，均衡区间指的是Xt的均衡值根据均衡区间内的数值来确定。
而在时刻T2＝T时，Xt位于第一个延迟单元的缓存器中，此时加法器的输出值
Figure PCTCN2014093411-appb-000003
也可以将Y2为Xt的均衡值，Xt对应的均衡区间为[Xt+1,Xt,Xt-1,Xt-2,Xt-3…Xt-(M-2)]。
依次类推，从时刻T3＝2T至时刻TN＝(N-1)T的过程中，Xt依次位于第2个延迟单元的缓存器到第M-1个延迟单元的缓存器，在每一个时刻可以求出一个Xt的均衡值。因此，在Xt一共可以有N个均衡区间，现有技术中Xt的均衡区间被固定为上述N个均衡区间中的一种。
参见图2，为实施例1提供的设置均衡器的方法的流程示意图，该流程包括如下步骤：
步骤101：在均衡器的输入端接收到包含K个数值的训练序列时，处理器以K个数值中的第t个数值与M个抽头中的第i个抽头的抽头系数相乘时加法器的输出值作为第t个数值的均衡值，根据均衡算法确定出M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数。
具体的，步骤101中，第t个数值为训练序号中的任意一个数值，第t数值可以有M种均衡区间，在M种均衡区间的第i个均衡区间下(即，以第t个数值与第i个抽头的抽头系数相乘时加法器的输出值作为第t个数值的均衡值时)，将根据均衡自适应算法来计算出该均衡区间下M个抽头中每个抽头的抽头系数，记为Ci＝(c1,i,c1,i,c2,i,c3,i…cM,i)，Ci为在取第i个均衡区间下能够使得第t个数值的均衡值与第t个数据的真实值最为接近的抽头系数，根据均 衡算法确定Ci的方式可以参考现有技术中的相关技术方案。
步骤102：处理器确定出抽头系数为Ci、第t个数值与第i个抽头的抽头系数相乘时加法器的输出值Yt,i。
具体的，步骤102中，在第t个数值的第i种均衡区间下，在确定出抽头系数Ci时，加法器的输出值
Figure PCTCN2014093411-appb-000004
即为第t数值在第i个均衡区间下的最佳均衡值。
步骤103：处理器确定出以Yt,i作为第t个数值的均衡值时的均衡评估参数Zt,i。
具体的，在确定出Yt,i时，可以根据Yt,i与第t个数值的真实值确定出均衡评估参数Zt,i，以Yt,i作为第t个数值的均衡值的均衡效果。本申请实施例中，均衡评估参数具体可以是由判决电路生成的数据均衡值与数据真实值之间的误差值，也可以是数据均衡后的误码率，也可以是数据均衡值与数据真实值的统计最小均方误差值，其中，均方误差值指的是训练序列中的所有数据的均衡误差值的平方和的平均值的平方根，而最小均方误差值指的是该均衡区间下均方误差值的最小值。
步骤104：处理器确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与第t个数值相乘的抽头的抽头编号St。
具体的，针对第t个数值的每一个均衡区间均进行步骤101～103的操作，然后可以获得第t个数值的M个均衡值，相应的有M个均衡评估参数，分别为Zt,1至Zt,M，从中确定出均衡效果最好的均衡评估参数，即为Zt，而Zt对应的均衡区间则为第t个数值的所有可能的均衡区间中均衡效果最好的均衡区间，记录下该均衡区间下第t个数值的位置，即获取到Zt时与第t个数值相乘的抽头的抽头编号St。
步骤105：处理器在确定出S1至SK之后，确定出S1至SK之中重复次数最多的抽头编号为S。
具体的，针对训练序号的k个数值中的每一个数值均进行步骤101～104的操作，确定出每一个数值的较佳均衡区间，统计出所有的M个均衡区间中 出现频次最高的均衡区间，即：确定出S1至SK之中重复次数最多的抽头编号，记为S，出现频次最高的均衡区间即为[Xt+1-s,Xt-s,Xt-1-s,…Xt-(M-s)]，其中，Xt为待均衡数据。其中，抽头编号指的是该抽头是M个抽头中的第几个抽头，例如，第一个抽头的编号为“1”，第M个抽头的编号为“M”。
步骤106：在利用均衡装置对待均衡数值进行均衡时，处理器确定待均衡数值与M个抽头中的第S个抽头的抽头系数相乘时加法器的输出值为待均衡数值的均衡值。
具体的，在均衡装置对传输信号进行正式的色散均衡时，确定采用步骤105中确定出来的出现频次最高的均衡区间[Xt+1-s,Xt-s,Xt-1-s,…Xt-(M-s)]作为待均衡数据Xt的均衡区间，即确定待均衡数值与M个抽头中的第S个抽头的抽头系数相乘时加法器的输出值为待均衡数值的均衡值。
本申请实施例上述技术方案中，均衡器在接收到包含K个数值的训练序列进行均衡器训练时，使每一个数值在M种均衡区间下进行均衡，即，分别将该数值与M个抽头中的每一个抽头相乘时加法器(或者判决器)的输出值作为该数值的均衡值，获得该数值的M个均衡值之后，比较获得M个均衡值时各自的均衡评估参数，即可确定出针对该数值较佳的均衡区间，在针对训练序列中的每一个数值均进行上述操作之后，即可获得K个较佳均衡区间，统计出K个较佳均衡区间中出现频次最高的均衡区间，即可作为均衡装置对输入信号进行均衡时的正式均衡区间。由于每次信号传输信道改变时都将发送训练序列，因此能够针对改变后的信道重新确定均衡装置的均衡区间，适应性地调整信道估值区间，能够有效地降低误码率。
本申请实施例上述技术方案可以采用逐比特的方式进行，即针对K个数值中的每一数值的每一种均衡区间执行步骤101～103，然后执行步骤104确定出该数值的最佳均衡评估参数，然后在对所有K个数值执行完步骤104之后，执行步骤105～106。
另外，本申请实施例上述技术方案可以采用数据流的方式进行，在待均衡数据的每一种取值区间，计算出K个数据中每一个数据的最佳均衡值和均 衡评估参数，然后切换至下一种取值区间，计算出该取值区间下每一个数据的均衡值和均衡评估参数，直至针对M种均衡区间都执行上述操作，再统计每一个数据的较佳取值区间，并统计出出现频次最高的最佳取值区间。
可选的，继续参见图2，设置均衡装置的方法还包括步骤107：在计算待均衡数值的均衡值时，处理器将M个抽头的抽头系数设置为Cs。Cs为步骤101中i的取值为S时求出的抽头系数。
步骤107执行时具体可以包括以下两种实现方式：
方式1，将M个抽头的抽头系数的初始值设置为Cs，然后在对传输信号进行均衡的过程中，根据体现均衡效果的反馈值动态地调整抽头系数，其具体实现方式可以参考现有技术中动态地调整抽头系数的技术方案。
方式2，将第一组抽头的抽头系数设置为Cs，在对传输信号进行均衡的过程中，使抽头系数保持不变，直至均衡器进行下一次训练时，再重新确定新的抽头系数。
由于调整抽头系数时，将产生计算延时，采用上述方式2，能够有效地避免调整抽头系数产生的延时对后续数据的影响。
本申请实施例中，步骤106与步骤107二者可以同时执行，也可以是步骤106先执行，或者是步骤107先执行。
可选的，本申请实施例1的技术方案还可以应用于具有前馈均衡器和反馈均衡器的判决反馈均衡结构，在设置均衡装置的过程中，前馈均衡器的均衡区间的设置采用上述步骤101～107所述的方式，而反馈均衡器的均衡区间固定为某一个均衡区间。
可选的，处理器可以是一块集成芯片，也可以由几个独立的芯片组成，其中的每一块芯片负责执行不同的指令。
为了更清楚的理解本发明，下面针对图1所示的均衡装置，以前馈均衡器包括5个抽头为例，通过具体应用实例对本申请实施例1提供的上述设置均衡器的方法进行详细描述。
在传输系统初始化时或者信号传输信道改变时，发射机会发射包含训练 序列的信号，前馈均衡器接收到训练序列并进行训练，调整均衡区间以及抽头系数。参见图3，在前馈均衡器以训练序列中的数据xt为待均衡数据进行训练时，首先使待均衡数据xt位于前馈均衡器的第1个抽头位置处，在这种均衡区间下根据均衡算法重复迭代，确定出抽头系数C1，并计算均衡评估参数Zt,1。
然后，调整均衡区间，使待均衡数据xt位于前馈均衡器的第2个抽头位置处，然后确定出这种均衡区间下的抽头系数C2和均衡评估参数Zt,2。
依此类推，直至使待均衡数据xt位于前馈均衡器的第5个抽头位置处，确定出抽头系数C5和均衡评估参数Zt,5。
然后，比较Zt,1至Zt,5这5个数值，确定出均衡效果最好的均衡评估参数为Zt,2，因此，确定出第t个数值的较佳均衡区间为xt与第2个抽头相乘时加法器的输出值作为xt的均衡值这种情况下的取值区间。
然后针对训练序列的K个数据中的每个数据进行上述操作，获得K个较佳均衡区间，统计出出现频次最高的较佳均衡区间作为对待均衡数值进行正式均衡时的均衡区间。
实施例2
基于相同的发明构思，本申请实施例提供了一种设置均衡器的方法，该方法应用于图4所示的均衡装置，该均衡装置包括前馈均衡器、反馈均衡器、第一加法器、判决器以及处理器，其中，前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及M个抽头中的第一个抽头的输入端相连，M-1个延迟单元中的每个延迟单元的输出端与M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入第二加法器的输入端，第二加法器将M个乘积的和值输入第一加法器的输入端；参见图5，反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及N个抽头中的第一个抽头的输入端相连，N-1个延 迟单元中的每个延迟单元的输出端与N个抽头中除第一个抽头之外的N-1个抽头一一对应地连接，N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入第三加法器的输入端，第三加法器将N个乘积的和值输入第一加法器的输入端，第一加法器将第二加法器的输出值和第三加法器的输出值的和值输入判决器的输入端，判决器的输出端与反馈均衡器的输入端相连。
在图4所示的均衡装置中，前馈均衡器的作用与图1中的前馈均衡器作用一致，而反馈均衡器的作用为将之前已经获得的输入数据的均衡值作为输入，与反馈均衡器的抽头的抽头系数相乘迭加，然后将迭加结果与前馈均衡器生成的均衡值相加，作为针对当前待均衡数据的均衡值。因此，在图4所示的均衡结构中，待均衡数据最终的均衡值除了与待均衡数据前后的输入数据相关(由前馈均衡器处理)，还与待均衡数据之前的数据的均衡值有关(由反馈均衡器处理)。
另外，本申请实施例中，第一加法器、第二加法器、第三加法器可以合并为一个加法器，把第一加法器和第二加法器的输入均作为合并的加法器的输入，合并加法器的输出作为判决器的输入，本申请实施例意图保护这一变形技术方案。
参见图6，为本申请实施例2提供的设置均衡装置的方法的流程示意图，该流程包括如下步骤：
步骤201：在均衡器的输入端接收到包含K个数值的训练序列时，处理器以K个数值中的第t个数值与M个抽头中的第i个抽头的抽头系数相乘且K个数值中的第t-j个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值作为第t个数值的均衡值，根据均衡算法确定出M个抽头的抽头系数Ci,j和N个抽头的抽头系数Di,j；其中，i为小于等于M的任一正整数，j为小于等于设定值L的任一正整数。
具体的，图4所示的均衡装置在对训练序列的k个数值中的第t个数值Xt进行均衡时，具体根据训练序列中包括Xt在内的连续的M个数值(由前馈均衡器处理)以及根据Xt之前的N个连续的数值的均衡值(由反馈均衡器处 理)确定Xt的均衡值。由于前馈均衡器中与M个抽头相乘的连续的M个数值可以有M种取值(每一种取值时Xt与不同的抽头相乘)。
而反馈均衡器中与N个抽头相乘的连续的N个数值可以有t-1种取值，实际情况中，我们将反馈均衡器中与N个抽头相乘的连续的N个数值的取值个数限制为设定值L，即，反馈均衡器有L种均衡区间，其中第1种均衡区间为[Yt-1,Ytt-2,Yt-3..Yt-N]这N个值与反馈均衡器的N个抽头的抽头系数一一相乘并将N个乘积相加作为第一加法器的输入的情形，在第2种均衡区间中，与N个抽头相乘的数据变为[Ytt-2,Yt-3..Yt-N-1]，而在第L种均衡区间中，与N个抽头相乘的数据变为[Ytt-L,Yt-L-1..Yt-L-N+1]。综上，针对数据Xt，前馈均衡器有M种均衡区间，反馈均衡器由N种均衡区间，整个均衡装置共有M*L种均衡结构。
步骤201中，针对Xt的M*L种均衡结构中的任一一种均衡结构，根据均衡自适应算法求出该均衡结构下的前馈均衡器的抽头系数和反馈均衡器的系数。即：以K个数值中的第t个数值与M个抽头中的第i个抽头的抽头系数相乘且K个数值中的第t-j个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值作为第t个数值的均衡值，根据均衡算法确定出M个抽头的抽头系数Ci,j和N个抽头的抽头系数Di,j，其中，Ci,j表示在当前均衡结构下的达到自适应稳定后前馈均衡器的M个抽头中每一个抽头的抽头系数取值的集合，Di,j表示在当前均衡结构下的达到自适应稳定后反馈均衡器的N个抽头中每一个抽头的抽头系数取值的集合。
步骤202：处理器确定出M个抽头的抽头系数为Ci,j、N个抽头的抽头系数为Di,j、第t个数值与第i个抽头的抽头系数相乘、第t-j个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值Yt,i,j。
具体的，在确定出Ci,j、Di,j时，第一加法器的输出值
Figure PCTCN2014093411-appb-000005
即为该均衡结构下Xt的最佳均衡值。
步骤203：处理器确定出以Yt,i,j作为第t个数值的均衡值时的均衡评估参数Zt,i,j。
具体的，确定出以Yt,i,j作为第t个数值的均衡值时的均衡评估参数Zt,i,j，以衡量该均衡结构的均衡效果，实施例2中均衡评估参数的定义可以参考实施例1中的均衡评估参数的定义。
步骤204：处理器确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时M个抽头中与第t个数据相乘的抽头的抽头编号i1以及与N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值。
具体来讲，从Zt,1,1至Zt,M,L这M*L个均衡评估参数之中确定出均衡效果最好的均衡评估参数，记为Zt，Zt对应的均衡结构为Xt的均衡效果最好的均衡结构，即：M个抽头中第i1个抽头与第t个数据相乘、N个抽头中的第一个抽头与第t-j1个数值的均衡值相乘时的均衡结构。
步骤205：处理器在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)。
具体的，通过特征数组(i1，j1)来表示一个数值的较佳均衡结构，在对K个数据中的每个数据均执行步骤201～204的操作后，可以获得K个较佳均衡结构，统计出出现频次最高的较佳均衡结构，即：确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)，特征数组(s，h)表征的均衡结构即为出现频次最高的均衡结构。
步骤206：在利用均衡装置对待均衡数值进行均衡时，处理器确定待均衡数值与M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值为待均衡数值的均衡值。
具体的，在均衡装置对传输信号进行正式的色散均衡时，确定采用步骤205中确定出来的出现频次最高的均衡结构作为对待均衡数据Xt进行均衡的均衡结构，即确定待均衡数值与M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值为待均衡数值的均衡值。
本申请实施例上述技术方案中，均衡器在接收到包含K个数值的训练序 列进行均衡器训练时，使每一个数值在M*L种均衡结构下进行均衡，即，分别将该数值与M个抽头中的每一个抽头相乘且K个数值中的第t-j个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值作为第t个数值的均衡值，获得该数值的M*L个均衡值之后，比较获得M*L个均衡值时各自的均衡评估参数，即可确定出针对该数值较佳的均衡结构，在针对训练序列中的每一个数值均进行上述操作之后，即可获得K个较佳均衡结构，统计出K个较佳均衡结构中出现频次最高的均衡结构，即可作为均衡装置对输入信号进行均衡时的正式均衡结构。由于每次信号传输信道改变时都将发送训练序列，因此能够针对改变后的信道重新确定均衡装置的均衡结构，适应性地调整信道估值区间，能够有效地降低误码率。
与实施例1类似，实施例2中的技术方案也可以采用逐比特的方式进行，也可以在一种均衡结构下处理完训练序列中的所有信号，即通过数据流的方式进行，在此不再一一举例说明。
可选的，继续参见图6，在步骤206之后，还包括如下步骤：
步骤207：在计算待均衡数值的均衡值时，处理器将M个抽头的抽头系数设置为Cs,h，将N个抽头的抽头系数设置为Ds,h。Cs,h为步骤201中i的取值为S、j的取值为h时求出的前馈均衡器的抽头系数，Ds,h为步骤201中i的取值为S、j的取值为h时求出的反馈均衡器的抽头系数。
步骤207执行时具体可以包括以下两种实现方式：
方式1，将所述M个抽头的抽头系数的初始值设置为Cs,h、将所述N个抽头的抽头系数的初始值设置为Ds,h，然后在对传输信号进行均衡的过程中，根据体现均衡效果的反馈值动态地调整前馈均衡器和反馈均衡器的抽头的抽头系数，其具体实现方式可以参考现有技术中动态地调整抽头系数的技术方案。
方式2，将所述M个抽头的抽头系数的初始值设置为Cs,h、将所述N个抽头的抽头系数的初始值设置为Ds,h，在对传输信号进行均衡的过程中，使抽头系数保持不变，直至均衡器进行下一次训练时，再重新确定新的抽头系数。
由于调整抽头系数时，将产生计算延时，采用上述方式2，能够有效地避免调整抽头系数产生的延时对后续数据的影响。
本申请实施例中，步骤206与步骤207二者可以同时执行，也可以是步骤206先执行，或者是步骤207先执行。
可选的，处理器可以是一块集成芯片，也可以由几个独立的芯片组成，其中的每一块芯片负责执行不同的指令。
为了便于理解，下面结合图7，对确定K个数值中的第t个数值的均衡评估参数Zt的过程予以说明。不妨设前馈均衡器具有5个抽头、反馈均衡器具有3个抽头、设定值L等于6为例，对以遍历的方式改变均衡器的均衡结构的方式进行详细描述。
首先将前馈均衡器的均衡区间设置为第A1均衡区间(即，使Xt与M个抽头中的第一个抽头相乘)，在第A1均衡区间下，将反馈均衡器的均衡区间设置为第B1均衡区间(即，使Yt-1与N个抽头中的第一个抽头相乘)，确定出此时的前馈均衡器的抽头的抽头系数为C1,1、反馈均衡器的抽头的抽头系数为D1,1、均衡评估参数为Z1,1,。然后，保持第A1取值范围不变，将第二取值范围设置为第B2取值范围(使Yt-2与N个抽头中的第一个抽头相乘)，确定出此时的第一抽头系数为C1,2、第二抽头系数为D1,2、均衡评估参数为Z1,2。依此类推，直至将第二取值范围设置为第BL取值范围(使Yt-6与N个抽头中的第一个抽头相乘)，确定出此时的第一抽头系数为C1,6、第二抽头系数为D1,6、均衡评估参数为Z1,6。
然后将第一取值范围设置为第A2取值范围(使Xt与M个抽头中的第二个抽头相乘)，将第二取值范围设置为第B1取值范围，确定出此时的第一抽头系数为C2,1、第二抽头系数为D2,1、均衡评估参数为Z2,1,。依此类推，直至将第一取值范围设置为第A5取值范围(使Xt与M个抽头中的第五个抽头相乘)，将第二取值范围设置为第B6取值范围，确定出此时的第一抽头系数为C5,6、第二抽头系数为D5,6、均衡评估参数为Z5,6。
然后，在确定出30(5*6)个均衡评估参数之后，从中选出均衡效果最好 的均衡评估参数，即为Zt。
实施例3
基于相同的技术构思，本申请实施例还提供了一种均衡装置300，均衡装置300用于实施图2及其实施例所述的方法。均衡装置300与均衡器和判决器相连。均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器，其中，均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及M个抽头中的第一个抽头的输入端相连，M-1个延迟单元中的每个延迟单元的输出端与M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入加法器的输入端，加法器将M个乘积的和值输入判决器的输入端。
参见图8，均衡装置300包括：
第一确定单元301，用于在均衡器接收到包含K个数值的训练序列时，以K个数值中的第t个数值与M个抽头中的第i个抽头的抽头系数相乘时加法器的输出值作为第t个数值的均衡值，根据均衡算法确定出M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；
第二确定单元302，用于确定出抽头系数为Ci、第t个数值与第i个抽头的抽头系数相乘时加法器的输出值Yt,i；
第三确定单元303，用于确定出以Yt,i作为第t个数值的均衡值时的均衡评估参数Zt,i；
第四确定单元304，用于确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与第t个数值相乘的抽头的抽头编号St；
第五确定单元305，用于在确定出S1至SK之后，确定出S1至SK之中重复次数最多的抽头编号为S；
第六确定单元306，用于在利用均衡装置对待均衡数值进行均衡时，确定待均衡数值与M个抽头中的第S个抽头的抽头系数相乘时加法器的输出值为待均衡数值的均衡值。
可选的，均衡装置300还包括：
设置单元307，用于在计算待均衡数值的均衡值时将M个抽头的抽头系数设置为Cs。
本实施例中的均衡装置与实施例1中的设置均衡装置的方法是基于同一发明构思下的两个方面，在前面已经对方法的实施过程作了详细的描述，所以本领域技术人员可根据前述描述清楚地了解本实施例中的均衡装置的结构及实施过程，为了说明书的简洁，在此就不再赘述了。
实施例4
基于相同的技术构思，本申请实施例还提供了一种均衡装置400，均衡装置400用于实施图6及其实施例所述的方法。均衡装置400分别与前馈均衡器、反馈均衡器、第一加法器以及判决器相连。其中，前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及M个抽头中的第一个抽头的输入端相连，M-1个延迟单元中的每个延迟单元的输出端与M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入第二加法器的输入端，第二加法器将M个乘积的和值输入第一加法器的输入端；反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及N个抽头中的第一个抽头的输入端相连，N-1个延迟单元中的每个延迟单元的输出端与N个抽头中除第一个抽头之外的N-1个抽头一一对应地连接，N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入第三加法器的输入端，第三加法器将N个乘积的和值输入第一加法器的输入端，第一加法器将第二加法器的输出值和第三加法器的输出值的和值输入判决器的输入端，判决器的输出端与反馈均衡器的输入端相连。
参见图9，均衡装置400包括：
第一确定单元401，用于在均衡器接收到包含K个数值的训练序列时，以K个数值中的第t个数值与M个抽头中的第i个抽头的抽头系数相乘且K 个数值中的第t-j个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值作为第t个数值的均衡值，根据均衡算法确定出M个抽头的抽头系数Ci,j和N个抽头的抽头系数Di,j；
第二确定单元402，用于确定出M个抽头的抽头系数为Ci,j、N个抽头的抽头系数为Di,j、第t个数值与第i个抽头的抽头系数相乘、第t-j个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值Yt,i,j；
第三确定单元403，用于确定出以Yt,i,j作为第t个数值的均衡值时的均衡评估参数Zt,i,j；
第四确定单元404，用于确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时M个抽头中与第t个数据相乘的抽头的抽头编号i1以及与N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值；
第五确定单元405，用于在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)；
第六确定单元406，用于在利用均衡装置对待均衡数值进行均衡时，确定待均衡数值与M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值为待均衡数值的均衡值。
可选的，继续参见图9，均衡装置400还包括：
设置单元407，用于在计算待均衡数值的均衡值时将M个抽头的抽头系数设置为Cs,h，将N个抽头的抽头系数设置为Ds,h。
本实施例中的均衡装置与实施例2中的设置均衡装置的方法是基于同一发明构思下的两个方面，在前面已经对方法的实施过程作了详细的描述，所以本领域技术人员可根据前述描述清楚地了解本实施例中的均衡装置的结构及实施过程，为了说明书的简洁，在此就不再赘述了。
实施例5
基于相同的技术构思，本申请实施例还提供了一种均衡装置500，均衡装置500包括均衡器和判决器，均衡器包括M-1个串联的延迟单元、M个抽头 和一个加法器，其中，均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及M个抽头中的第一个抽头的输入端相连，M-1个延迟单元中的每个延迟单元的输出端与M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入加法器的输入端，加法器将M个乘积的和值输入判决器的输入端。
参见图10，均衡装置500还包括总线503以及连接到总线的处理器501和存储单元502。其中存储单元502用于存储指令，处理器501用于执行存储单元502中的指令。
具体的，存储单元502存储的指令包括：在均衡器接收到包含K个数值的训练序列时，以K个数值中的第t个数值与M个抽头中的第i个抽头的抽头系数相乘时加法器的输出值作为第t个数值的均衡值，根据均衡算法确定出M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；确定出抽头系数为Ci、第t个数值与第i个抽头的抽头系数相乘时加法器的输出值Yt,i；确定出以Yt,i作为第t个数值的均衡值时的均衡评估参数Zt,i；确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与第t个数值相乘的抽头的抽头编号St；在确定出S1至SK之后，确定出S1至SK之中重复次数最多的抽头编号为S；在利用均衡装置对待均衡数值进行均衡时，确定待均衡数值与M个抽头中的第S个抽头的抽头系数相乘时加法器的输出值为待均衡数值的均衡值。
可选的，存储单元还存储有指令：在计算待均衡数值的均衡值时，将M个抽头的抽头系数设置为Cs。
可选的，处理器601可以是一块集成芯片，也可以由几个独立的芯片组成，其中的每一块芯片负责执行不同的指令。
本实施例中的均衡装置与实施例1中的设置均衡装置的方法是基于同一发明构思下的两个方面，在前面已经对方法的实施过程作了详细的描述，所以本领域技术人员可根据前述描述清楚地了解本实施例中的均衡装置的结构及实施过程，为了说明书的简洁，在此就不再赘述了。
实施例6
基于相同的技术构思，本申请实施例还提供了一种均衡装置600，均衡装置600包括前馈均衡器、反馈均衡器、第一加法器以及判决器，其中，前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及M个抽头中的第一个抽头的输入端相连，M-1个延迟单元中的每个延迟单元的输出端与M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入第二加法器的输入端，第二加法器将M个乘积的和值输入第一加法器的输入端；反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及N个抽头中的第一个抽头的输入端相连，N-1个延迟单元中的每个延迟单元的输出端与N个抽头中除第一个抽头之外的N-1个抽头一一对应地连接，N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入第三加法器的输入端，第三加法器将N个乘积的和值输入第一加法器的输入端，第一加法器将第二加法器的输出值和第三加法器的输出值的和值输入判决器的输入端，判决器的输出端与反馈均衡器的输入端相连.
参见图11，均衡装置600还包括：总线603以及连接到总线603的处理器601和存储单元602。其中存储单元602用于存储指令，处理器601用于执行存储单元602中的指令。
具体的，存储单元602中存储的指令包括：在均衡器接收到包含K个数值的训练序列时，以K个数值中的第t个数值与M个抽头中的第i个抽头的抽头系数相乘且K个数值中的第t-j个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值作为第t个数值的均衡值，根据均衡算法确定出M个抽头的抽头系数Ci,j和N个抽头的抽头系数Di,j；确定出M个抽头的抽头系数为Ci,j、N个抽头的抽头系数为Di,j、第t个数值与第i个抽头的抽头系数相乘、第t-j个数值的均衡值与N个抽头中的第1个抽头的抽头 系数相乘时第一加法器的输出值Yt,i,j；确定出以Yt,i,j作为第t个数值的均衡值时的均衡评估参数Zt,i,j；确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时M个抽头中与第t个数据相乘的抽头的抽头编号i1以及与N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值；在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)；在利用均衡装置对待均衡数值进行均衡时，确定待均衡数值与M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与N个抽头中的第1个抽头的抽头系数相乘时第一加法器的输出值为待均衡数值的均衡值。
可选的，存储单元还存储有指令：在计算待均衡数值的均衡值时，将M个抽头的抽头系数设置为Cs,h，将N个抽头的抽头系数设置为Ds,h。
可选的，处理器601可以是一块集成芯片，也可以由几个独立的芯片组成，其中的每一块芯片负责执行不同的指令。
本实施例中的均衡装置与实施例2中的设置均衡装置的方法是基于同一发明构思下的两个方面，在前面已经对方法的实施过程作了详细的描述，所以本领域技术人员可根据前述描述清楚地了解本实施例中的均衡装置的结构及实施过程，为了说明书的简洁，在此就不再赘述了。
本申请实施例中提供的一个或多个技术方案，至少具有如下技术效果或优点：
本申请实施例提供的技术方案中，均衡器在接收到包含K个数值的训练序列进行均衡器训练时，使每一个数值在M种均衡区间下进行均衡，即，分别将该数值与M个抽头中的每一个抽头相乘时加法器(或者判决器)的输出值作为该数值的均衡值，获得该数值的M个均衡值之后，比较获得M个均衡值时各自的均衡评估参数，即可确定出针对该数值较佳的均衡区间，在针对训练序列中的每一个数值均进行上述操作之后，即可获得K个较佳均衡区间，统计出K个较佳均衡区间中出现频次最高的均衡区间，即可作为均衡装置对输入信号进行均衡时的正式均衡区间。由于每次信号传输信道改变时都将发送训练序列，因此能够针对改变后的信道重新确定均衡装置的均衡区间，适 应性地调整信道估值区间，能够有效地降低误码率。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种设置均衡装置的方法，其特征在于，所述均衡装置包括均衡器、判决器和处理器，所述均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器，其中，所述均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述加法器的输入端，所述加法器将M个乘积的和值输入所述判决器的输入端，所述方法包括：
    在所述均衡器的输入端接收到包含K个数值的训练序列时，所述处理器以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘时所述加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；
    所述处理器确定出所述抽头系数为Ci、所述第t个数值与所述第i个抽头的抽头系数相乘时所述加法器的输出值Yt,i；
    所述处理器确定出以Yt,i作为所述第t个数值的均衡值时的均衡评估参数Zt,i；
    所述处理器确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与所述第t个数值相乘的抽头的抽头编号St；
    所述处理器在确定出S1至SK之后，确定出所述S1至SK之中重复次数最多的抽头编号为S；
    在利用所述均衡装置对待均衡数值进行均衡时，所述处理器确定所述待均衡数值与所述M个抽头中的第S个抽头的抽头系数相乘时所述加法器的输出值为所述待均衡数值的均衡值。
  2. 如权利要求1所述的方法，其特征在于，还包括：
    在计算所述待均衡数值的均衡值时，所述处理器将所述M个抽头的抽头系数设置为Cs。
  3. 一种设置均衡装置的方法，其特征在于，所述均衡装置包括前馈均衡器、反馈均衡器、第一加法器、判决器以及处理器，其中，所述前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，所述前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第二加法器的输入端，所述第二加法器将M个乘积的和值输入所述第一加法器的输入端；所述反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，所述反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及所述N个抽头中的第一个抽头的输入端相连，所述N-1个延迟单元中的每个延迟单元的输出端与所述N个抽头中除第一个抽头之外的N-1个抽头一一对应地连接，所述N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第三加法器的输入端，所述第三加法器将N个乘积的和值输入所述第一加法器的输入端，所述第一加法器将所述第二加法器的输出值和所述第三加法器的输出值的和值输入所述判决器的输入端，所述判决器的输出端与所述反馈均衡器的输入端相连，所述方法包括：
    在所述均衡器的输入端接收到包含K个数值的训练序列时，所述处理器以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘且所述K个数值中的第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci,j和所述N个抽头的抽头系数Di,j；其中，i为小于等于M的任一正整数，j为小于等于设定值L的任一正整数；
    所述处理器确定出所述M个抽头的抽头系数为Ci,j、所述N个抽头的抽 头系数为Di,j、所述第t个数值与所述第i个抽头的抽头系数相乘、所述第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值Yt,i,j；
    所述处理器确定出以Yt,i,j作为所述第t个数值的均衡值时的均衡评估参数Zt,i,j；
    所述处理器确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时所述M个抽头中与所述第t个数据相乘的抽头的抽头编号i1以及与所述N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值；
    所述处理器在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)；
    在利用所述均衡装置对待均衡数值进行均衡时，所述处理器确定所述待均衡数值与所述M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值为所述待均衡数值的均衡值。
  4. 如权利要求3所述的方法，其特征在于，还包括：
    在计算所述待均衡数值的均衡值时，所述处理器将所述M个抽头的抽头系数设置为Cs,h，将所述N个抽头的抽头系数设置为Ds,h。
  5. 一种均衡装置，其特征在于，所述均衡装置分别与均衡器、判决器相连，所述均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器，其中，所述均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述加法器的输入端，所述加法器将M个乘积的和值输入所述判决器的输入端，所述均衡装置包括：
    第一确定单元，用于在所述均衡器接收到包含K个数值的训练序列时，以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数 相乘时所述加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；
    第二确定单元，用于确定出所述抽头系数为Ci、所述第t个数值与所述第i个抽头的抽头系数相乘时所述加法器的输出值Yt,i；
    第三确定单元，用于确定出以Yt,i作为所述第t个数值的均衡值时的均衡评估参数Zt,i；
    第四确定单元，用于确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与所述第t个数值相乘的抽头的抽头编号St；
    第五确定单元，用于在确定出S1至SK之后，确定出所述S1至SK之中重复次数最多的抽头编号为S；
    第六确定单元，用于在利用所述均衡装置对待均衡数值进行均衡时，确定所述待均衡数值与所述M个抽头中的第S个抽头的抽头系数相乘时所述加法器的输出值为所述待均衡数值的均衡值。
  6. 如权利要求5所述的均衡装置，其特征在于，还包括：
    设置单元，用于在计算所述待均衡数值的均衡值时将所述M个抽头的抽头系数设置为Cs。
  7. 一种均衡装置，其特征在于，所述均衡装置分别与前馈均衡器、反馈均衡器、第一加法器以及判决器相连，其中，所述前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，所述前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第二加法器的输入端，所述第二加法器将M个乘积的和值输入所述第一加法器的输入端；所述反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，所述反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及所述N 个抽头中的第一个抽头的输入端相连，所述N-1个延迟单元中的每个延迟单元的输出端与所述N个抽头中除第一个抽头之外的N-1个抽头一一对应地连接，所述N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第三加法器的输入端，所述第三加法器将N个乘积的和值输入所述第一加法器的输入端，所述第一加法器将所述第二加法器的输出值和所述第三加法器的输出值的和值输入所述判决器的输入端，所述判决器的输出端与所述反馈均衡器的输入端相连，所述均衡装置包括：
    第一确定单元，用于在所述均衡器接收到包含K个数值的训练序列时，以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘且所述K个数值中的第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci,j和所述N个抽头的抽头系数Di,j；其中，i为小于等于M的任一正整数，j为小于等于设定值L的任一正整数；
    第二确定单元，用于确定出所述M个抽头的抽头系数为Ci,j、所述N个抽头的抽头系数为Di,j、所述第t个数值与所述第i个抽头的抽头系数相乘、所述第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值Yt,i,j；
    第三确定单元，用于确定出以Yt,i,j作为所述第t个数值的均衡值时的均衡评估参数Zt,i,j；
    第四确定单元，用于确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时所述M个抽头中与所述第t个数据相乘的抽头的抽头编号i1以及与所述N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值；
    第五确定单元，用于在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)；
    第六确定单元，用于在利用所述均衡装置对待均衡数值进行均衡时，确 定所述待均衡数值与所述M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值为所述待均衡数值的均衡值。
  8. 如权利要求7所述的均衡装置，其特征在于，还包括：
    设置单元，用于在计算所述待均衡数值的均衡值时将所述M个抽头的抽头系数设置为Cs,h，将所述N个抽头的抽头系数设置为Ds,h。
  9. 一种均衡装置，其特征在于，所述均衡装置包括均衡器和判决器，所述均衡器包括M-1个串联的延迟单元、M个抽头和一个加法器，其中，所述均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述加法器的输入端，所述加法器将M个乘积的和值输入所述判决器的输入端，所述均衡装置还包括：
    存储单元，用于存储指令，所述指令包括：在所述均衡器接收到包含K个数值的训练序列时，以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘时所述加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci；其中，t为小于或者等于K的任一正整数，i为小于或者等于M的任一正整数；确定出所述抽头系数为Ci、所述第t个数值与所述第i个抽头的抽头系数相乘时所述加法器的输出值Yt,i；确定出以Yt,i作为所述第t个数值的均衡值时的均衡评估参数Zt,i；确定出Zt,1至Zt,M中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时与所述第t个数值相乘的抽头的抽头编号St；在确定出S1至SK之后，确定出所述S1至SK之中重复次数最多的抽头编号为S；在利用所述均衡装置对待均衡数值进行均衡时，确定所述待均衡数值与所述M个抽头中的第S个抽头的抽头系数相乘时所述加法器的输出值为所述待均衡数值的均衡值；
    处理器，用于执行所述指令。
  10. 如权利要求9所述的均衡装置，其特征在于，所述存储单元还存储有指令：在计算所述待均衡数值的均衡值时，将所述M个抽头的抽头系数设置为Cs。
  11. 一种均衡装置，其特征在于，所述均衡装置包括前馈均衡器、反馈均衡器、第一加法器以及判决器，其中，所述前馈均衡器包括M-1个串联的延迟单元、M个抽头和第二加法器，所述前馈均衡器的输入端分别与M-1个延迟单元中的第一个延迟单元的输入端以及所述M个抽头中的第一个抽头的输入端相连，所述M-1个延迟单元中的每个延迟单元的输出端与所述M个抽头中除第一个抽头之外的M-1个抽头一一对应地连接，所述M个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第二加法器的输入端，所述第二加法器将M个乘积的和值输入所述第一加法器的输入端；所述反馈均衡器包括N-1个串联的延迟单元、N个抽头和第三加法器，所述反馈均衡器的输入端分别与N-1个延迟单元中的第一个延迟单元的输入端以及所述N个抽头中的第一个抽头的输入端相连，所述N-1个延迟单元中的每个延迟单元的输出端与所述N个抽头中除第一个抽头之外的N-1个抽头一一对应地连接，所述N个抽头中的每个抽头将输入值与抽头系数相乘后的乘积输入所述第三加法器的输入端，所述第三加法器将N个乘积的和值输入所述第一加法器的输入端，所述第一加法器将所述第二加法器的输出值和所述第三加法器的输出值的和值输入所述判决器的输入端，所述判决器的输出端与所述反馈均衡器的输入端相连，所述均衡装置还包括：
    存储单元，用于存储指令，所述指令包括：在所述均衡器接收到包含K个数值的训练序列时，以所述K个数值中的第t个数值与所述M个抽头中的第i个抽头的抽头系数相乘且所述K个数值中的第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值作为所述第t个数值的均衡值，根据均衡算法确定出所述M个抽头的抽头系数Ci,j和所述N个抽头的抽头系数Di,j，其中，i为小于等于M的任一正整数，j为小于等于设定值L的任一正整数；确定出所述M个抽头的抽头系数为Ci,j、 所述N个抽头的抽头系数为Di,j、所述第t个数值与所述第i个抽头的抽头系数相乘、所述第t-j个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值Yt,i,j；确定出以Yt,i,j作为所述第t个数值的均衡值时的均衡评估参数Zt,i,j；确定出Zt,1,1至Zt,M,L中均衡效果最好的均衡评估参数为Zt，并确定出获取到Zt时所述M个抽头中与所述第t个数据相乘的抽头的抽头编号i1以及与所述N个抽头中的第一个抽头相乘的数据为第t-j1个数值的均衡值；在确定出Z1至ZK之后，确定出(i1，j1)的所有取值中出现次数最多的取值为(s，h)；在利用所述均衡装置对待均衡数值进行均衡时，确定所述待均衡数值与所述M个抽头中的第s个抽头的抽头系数相乘、第t-h个数值的均衡值与所述N个抽头中的第1个抽头的抽头系数相乘时所述第一加法器的输出值为所述待均衡数值的均衡值；
    处理器，用于执行所述指令。
  12. 如权利要求11所述的均衡装置，其特征在于，所述存储单元还存储有指令：在计算所述待均衡数值的均衡值时，将所述M个抽头的抽头系数设置为Cs,h，将所述N个抽头的抽头系数设置为Ds,h。
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