WO2016082146A1 - 一种pcb中阶梯铜柱的制作方法 - Google Patents

一种pcb中阶梯铜柱的制作方法 Download PDF

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Publication number
WO2016082146A1
WO2016082146A1 PCT/CN2014/092351 CN2014092351W WO2016082146A1 WO 2016082146 A1 WO2016082146 A1 WO 2016082146A1 CN 2014092351 W CN2014092351 W CN 2014092351W WO 2016082146 A1 WO2016082146 A1 WO 2016082146A1
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WIPO (PCT)
Prior art keywords
layer
copper
dry film
stepped
plating
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PCT/CN2014/092351
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English (en)
French (fr)
Inventor
韦昊
邓峻
敖四超
刘松伦
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江门崇达电路技术有限公司
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Application filed by 江门崇达电路技术有限公司 filed Critical 江门崇达电路技术有限公司
Priority to CN201480002422.0A priority Critical patent/CN105830542B/zh
Priority to PCT/CN2014/092351 priority patent/WO2016082146A1/zh
Publication of WO2016082146A1 publication Critical patent/WO2016082146A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Definitions

  • the present invention relates to the field of PCB fabrication technology, and in particular, to a method for fabricating a stepped copper pillar in a PCB.
  • PCB It is the support of electronic components, and the carrier of electrical connection is one of the important components of the electronics industry. It is used in almost every electronic device, from electronic watches and calculators to computers, communication electronic devices, military weapon systems. Wait. With the continuous development of electronic devices, the multi-functionality of electronic devices also requires more diversified PCB design.
  • Existing PCBs are usually designed with inner layers, outer layers, metallized through holes or blind holes connecting the inner and outer lines, and stepped grooves.
  • PCBs with stepped copper pillars on the surface due to the complicated manufacturing process, have little or no application of such PCBs in electronic products, which greatly affects the development of PCBs with stepped copper pillars, and limits the design and diversification of PCBs.
  • this invention Aiming at the problem that the manufacturing process of the stepped copper column in the existing PCB manufacturing is complicated and difficult to realize, a method for manufacturing a stepped copper column on the PCB by multiple dry film and multiple electroplating is provided, and the method is simple and easy.
  • the present invention adopts the following technical solution, a method for fabricating a stepped copper pillar in a PCB, comprising the following steps:
  • the plating resist ink layer has a thickness of 20-26 ⁇ m.
  • the laminate is subjected to a roughening treatment after the baking of the laminate.
  • the first copper plating layer is electroplated at a current density of 22 ASF until the first copper plating layer is flush with the first dry film layer.
  • concentration of copper ions in the plating tank is 55-65 g/L, and the concentration of sulfuric acid is 125-135 mL/L.
  • the second copper plating layer is plated at a current density of 20 ASF until the second copper plating layer is flush with the second dry film layer.
  • concentration of copper ions in the plating tank is 55-65 g/L, and the concentration of sulfuric acid is 125-135 mL/L.
  • Step S3 is repeated to produce a stepped copper pillar having more steps.
  • other dry film layers are formed on the laminate by the method of step S3, and then other copper plating layers are plated at the window opening, and the first copper plating layer, the second copper plating layer and other copper plating layers constitute a step copper. column.
  • the first dry film layer, the second dry film layer and the other dry film layers on the laminate are then completely removed by the method of step S4, followed by electroplating the tin layer on the stepped copper pillars. And proceed to step S5.
  • the The laminate is a core board, or a multi-layer board in which a core board provided with an inner layer wiring and an outer layer copper foil are pressed together by a prepreg.
  • a stepped copper pillar is gradually formed by first forming an anti-plating ink layer on a laminate, and then sequentially forming a dry film layer and an electroplated copper plating layer.
  • the anti-plating ink layer is baked at a certain temperature and time, and then a dry film layer is formed thereon, so that the dry film layer can be selectively removed in the later process, and the anti-electroplating ink layer remains intact, and continues in the multi-layer board.
  • the unnecessary copper foil layer can be removed by etching to obtain a PCB having a stepped copper pillar.
  • the roughening treatment is performed on the anti-electroplating ink layer before the dry film layer is formed, so that the dry film layer can be better adhered to the anti-electroplating ink layer, and the adhesion between the anti-electroplating ink layer and the dry film layer can be avoided. Wrinkling or foaming; combined with high current density for electroplating, shortening plating time, so that the anti-electroplating ink layer and the dry film layer can maintain good adhesion under long-term plating conditions, no bubbles or detachment occurs between layers. To avoid the occurrence of plating.
  • the same exposure alignment site is used, and the exposure alignment precision is set within 20 ⁇ m, which can ensure that the steps of the fabricated stepped copper pillar are coaxial, and the stepped copper pillar The sides are vertically smooth.
  • FIG. 1 is a schematic structural view of an electroplating ink layer and a first dry film layer formed on a PCB in an embodiment
  • FIG. 2 is a schematic structural view of the first copper plating layer on the PCB after being electroplated in the embodiment
  • FIG. 3 is a schematic structural view of a second dry film layer formed on a PCB in an embodiment
  • FIG. 4 is a schematic structural view of an embodiment after plating a second copper plating layer on a PCB;
  • FIG. 5 is a schematic structural view of the embodiment after removing the first dry film layer and the second dry film layer on the PCB;
  • FIG. 6 is a schematic structural view of a tin plating layer on a PCB in an embodiment
  • FIG. 7 is a schematic structural view of the embodiment after removing the anti-electroplating ink layer on the PCB;
  • FIG. 8 is a schematic structural view of the PCB in the embodiment after removing the copper foil layer other than the stepped copper pillar;
  • FIG. 9 is a schematic structural view of a PCB after a stepped copper pillar is fabricated and a tin layer is removed.
  • this embodiment provides a method for fabricating a stepped copper pillar in a PCB.
  • the parameters of the PCB fabricated by using the method are as follows:
  • Peripheral Hole and Exposure Pair The peripheral hole is drilled on the process side of the core 10 using the drilling data. And an exposure pair site is formed on the process side of the core board 10, and the exposure pair position is used for the subsequent use of the plating resist layer 20, the first dry film layer 30 and the second dry film layer 50.
  • Exposure and development 6-7 grid exposure energy (21 grid exposure scale) and exposure to the site for the alignment exposure, and the exposure alignment accuracy is set within 20 ⁇ m, and then developed to make the core 10
  • the area outside the position where the stepped copper pillar 40 is to be formed is completely covered by the plating resist ink layer 20, and the position where the stepped copper pillar 40 is to be formed is completely exposed, that is, a window is opened at a position where the stepped copper pillar 40 is to be formed.
  • the anti-electroplating ink layer 20 is baked to ensure that the dry film layer can be selectively removed and the anti-plating ink layer 20 remains intact when the film layer is subsequently dried.
  • the first dry film layer 30 is formed on the core board 10 and opened at a position where the stepped copper pillar 40 is required to be formed, and then copper is plated at the window opening to form the first copper plating layer 41. As shown in Figure 1-2. details as follows:
  • First dry film is attached a dry film having a thickness of 50 ⁇ m is attached to the core plate 10, the film temperature is 112-118 ° C, the pressure is 5.0-5.5 Kgf/cm 2 , and the speed is 1.4-1.5 m/min. Plate temperature: 50-60 ° C, plate temperature: 70-85 ° C.
  • the area outside the position where the stepped copper pillar 40 is to be formed is completely covered by the first dry film layer 30, and the position where the stepped copper pillar 40 is to be formed is completely exposed, that is, the opening window is provided at the position where the stepped copper pillar 40 is to be formed.
  • the shape and size of the window opening are completely consistent with the window opening on the plating resist ink layer 20.
  • Microetching The surface of the core plate 10 is subjected to micro-etching treatment, and the amount of micro-etching is controlled to be 1.0-2.0 ⁇ m to ensure the cleanliness and roughness of the surface of the copper foil layer 11 at the window opening of the core plate 10, so that the subsequent plating is performed.
  • a copper plating layer 41 adheres well to the copper foil layer 11.
  • (d) electroplating the first copper plating layer 41 the core plate 10 is placed in an electroplating copper cylinder for electroplating, the concentration of copper ions in the electroplating copper cylinder is 55-65 g/L, and the concentration of sulfuric acid is 125-135 mL/L.
  • the current density of 22 ASF was electroplated, and the plating time was about 165 min to obtain a first copper plating layer 41, and the surface of the first copper plating layer 41 was flush with the surface of the first dry film layer 30.
  • Electroplating copper at a high current density can shorten the plating time and reduce the risk of detachment of the first dry film layer 30 or the plating resist ink layer 20.
  • the surface of the first copper plating layer 41 is flush with the surface of the first dry film layer 30, so that the surface of the core plate 10 can be flattened, and the subsequently attached dry film can adhere well to the first dry film layer 30.
  • Pasting the second upper dry film 52 continuing to apply a dry film having a thickness of 50 ⁇ m on the core plate 10, the film temperature is 112-118 ° C, the pressure is 5.0-5.5 Kgf/cm 2 , and the speed is 1.6-1.7 m/min. Plate temperature: 50-60 ° C, plate temperature: 65-80 ° C.
  • the dry film 52 forms the second dry film layer 50 such that the area on the core board 10 beyond which the stepped copper pillars 40 are to be formed is completely covered by the second dry film layer 50, and the position where the stepped copper pillars 40 are to be formed is completely exposed.
  • the opening window is smaller than The fenestration of the first dry film layer 30, that is, the size of the fenestration is smaller than the upper surface area of the first copper plating layer 41, and the sides of the fenestration are inwardly contracted by 0.25 from the upper surface of the first copper plating layer 41. Mm.
  • (d) electroplating the second copper plating layer 42 the core plate 10 is placed in an electroplating copper cylinder for electroplating, the concentration of copper ions in the electroplating copper cylinder is 55-65 g/L, and the concentration of sulfuric acid is 125-135 mL/L, The current density of 20 ASF is electroplated, and the plating time is about 235 min to obtain a second copper plating layer 42, and the surface of the second copper plating layer 42 is flush with the surface of the second dry film layer 50. Electroplating copper at a high current density can shorten the plating time and reduce the risk of detachment of the first dry film layer 30, the second dry film layer 50, or the plating resist ink layer 20. The surface of the second copper plating layer 42 is flush with the surface of the second dry film layer 50, so that the surface of the core plate 10 can be flattened.
  • a stepped copper pillar 40 having two steps is formed by the first copper plating layer 41 and the second copper plating layer 42.
  • the tin layer 60 is plated on the stepped copper pillar 40 to form a resist layer, and the tin layer 60 has a thickness of 5-8 ⁇ m.
  • the copper foil layer 11 not covered by the tin layer 60 is removed by alkaline etching.
  • the tin layer 60 is then removed.
  • an outer layer may also be formed on the surface of the core sheet such that the resulting PCB has an outer layer in addition to the stepped copper.
  • the core plate of the above embodiment may be replaced with a multilayer board provided with an inner layer circuit, the multilayer board being The core sheet provided with the inner layer is formed by pressing together the outer layer copper foil through the prepreg.
  • a stepped copper pillar having a larger number of step layers can be produced by repeating the step (3) before the step (4) of the above embodiment. That is, a third dry film layer is formed on the core board by the method of the step (3), and then a third copper plating layer is plated at the window opening, the first copper plating layer, the second copper plating layer and the third copper plating layer. The layers form a stepped copper column. Then, the first dry film layer, the second dry film layer and the third dry film layer on the laminate are all removed in the same manner as in the step S4, and then the tin layer is plated on the stepped copper column. And continue the process of steps (5) and (6). Thus, a stepped copper pillar having three steps is obtained.
  • step (3) If it is necessary to fabricate a stepped copper column having four steps, repeat step (3) one time before step (4) as described above. If you need to make more layers of stepped copper columns, and so on.
  • This comparative example provides a method for fabricating a stepped copper pillar in a PCB, which is basically the same as the method of the above embodiment, except that in step (1) The core sheet is not subjected to baking treatment (the e operation in the step 1 is omitted), that is, after the plating resist layer is formed on the core sheet, the plating ink layer is directly subjected to roughening treatment.
  • step (4) when the first dry film layer and the second dry film layer are removed by the film removing liquid, the plating resist ink layers are removed together, so that the tin plating and the operation of the step (5) cannot be continued.
  • This comparison provides A method for fabricating a stepped copper pillar in a PCB, the method is substantially the same as the method of the above embodiment, except that in the step (1), after the anti-plating ink layer is formed on the core board, the core board is placed at 106 -114 Bake the plate at °C for 18-22min.
  • step (4) when the first dry film layer and the second dry film layer are removed by the film removing liquid, part of the plating resist ink layer is removed together, so that the plating resist ink layer cannot be kept intact.
  • the copper layer on which the plating resist layer has been removed is also plated with a tin layer, and finally the copper foil layer (the copper foil layer other than the stepped copper pillar) to be removed is not etched, which affects the product. quality.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种PCB中阶梯铜柱（40）的制作方法，在包括铜箔层（11）的层压板上先制作抗电镀油墨层（20），抗电镀油墨层经一定的温度及时间烘烤后再在其上制作第一干膜层（30）和第一镀铜层（41），再在其上制作第二干膜层（50）和第二镀铜层（42），使后工序中可选择性的除去第一干膜层和第二干膜层，而抗电镀油墨层保持完好，继续在层压板上电镀锡层（60）后，通过蚀刻将不需要的铜箔层除去，制得具有阶梯铜柱的PCB。

Description

一种PCB中阶梯铜柱的制作方法
技术领域
本 发明涉及PCB制作技术领域 ，尤其涉及一种PCB中阶梯铜柱的制作方法 。
背景技术
PCB 是电子元器件的支撑体，电气连接的载体，是电子工业的重要部件之一，应用于几乎每种电子设备中，小到电子手表、计算器，大到计算机、通讯电子设备、军用武器系统等。随着电子设备的不断发展，电子设备的多功能化也要求PCB的设计更加多样化。现有的PCB通常设计有内层线路、外层线路、连接内外层线路的金属化通孔或盲孔，以及阶梯凹槽等。而表面具有阶梯铜柱的PCB，由于制作工艺复杂，电子产品中极少甚至没有应用该类PCB，极大的影响了具有阶梯铜柱的PCB的发展，限制了PCB的设计及其多样化。
发明内容
本发明 针对现有PCB制作中阶梯铜柱的制作工艺复杂难实现的问题，提供一种通过多次贴干膜和多次电镀在PCB上制作阶梯铜柱的方法，该方法简单易行。
为实现上述目的，本发明采用以下技术方案， 一种PCB中阶梯铜柱的制作方法 ，包括以下步骤：
S1 、在层压板上制作抗电镀油墨层并在需要制作阶梯铜柱的位置开窗，然后将层压板置于116-124℃下烤板23-27min；所述层压板包括基材层及与基材层压合在一起的铜箔层。
优选的，所述抗电镀油墨层的厚度为20-26μm。
优选的，对层压板进行烤板后，对抗电镀油墨层进行粗化处理。
S2 、在层压板上制作第一干膜层并在需要制作阶梯铜柱的位置开窗，所述第一干膜层的开窗与抗电镀油墨层的开窗形状大小一致；然后在开窗处电镀铜，形成第一镀铜层。
优选的，以22ASF的电流密度电镀第一镀铜层，至第一镀铜层与第一干膜层齐平。电镀缸中铜离子的浓度为55-65g/L，硫酸的浓度为125-135mL/L。
S3 、在层压板上制作第二干膜层并在需要制作阶梯铜柱的位置开窗，所述第二干膜层的开窗小于第一干膜层的开窗；然后在开窗处电镀铜，形成第二镀铜层；所述第一镀铜层和第二镀铜层构成阶梯铜柱。
优选的，以20ASF的电流密度电镀第二镀铜层，至第二镀铜层与第二干膜层齐平。电镀缸中铜离子的浓度为55-65g/L，硫酸的浓度为125-135mL/L。
S4 、除去第一干膜层和第二干膜层，然后在阶梯铜柱上电镀锡层。
S5 、除去抗电镀油墨层，然后蚀刻除去阶梯铜柱之外的铜箔层，接着除去锡层。
以上所述的 PCB 中阶梯铜柱的制作方法中，可以在步骤S4前通过 重复步骤S3来制作具有更多阶梯层数的阶梯铜柱。具体的，以步骤S3的方法在层压板上制作其它干膜层，然后在开窗处电镀其它镀铜层，所述第一镀铜层、第二镀铜层和其它镀铜层构成阶梯铜柱。然后以步骤S4的方法，将层压板上的第一干膜层、第二干膜层和其它干膜层全部除去，接着在阶梯铜柱上电镀锡层。并继续进行步骤S5。
以上所述的 PCB 中阶梯铜柱的制作方法中，所述的 层压板为一芯板，或者是设有内层线路的芯板与外层铜箔通过半固化片压合在一起的多层板。
与现有技术相比，本发明的有益效果是： 本发明通过在层压板上先制作抗电镀油墨层，然后再逐次制作干膜层和电镀镀铜层，从而逐渐形成阶梯铜柱。制作中，抗电镀油墨层经一定温度及时间烘烤后再在其上制作干膜层，使后工序中可选择性的除去干膜层，而抗电镀油墨层保持完好，继续在多层板上电镀锡层后即可通过蚀刻将不需要的铜箔层除去，制得具有阶梯铜柱的PCB。在抗电镀油墨层上制作干膜层前先进行粗化处理，可使干膜层更好的附着在抗电镀油墨层上，可避免抗电镀油墨层与干膜层之间因附着力不足而起皱或起泡；配合采用高电流密度进行电镀，缩短电镀时间，使抗电镀油墨层与干膜层在长时间的电镀条件下仍能保持良好的附着，层间不出现气泡或脱离等现象，可避免渗镀的发生。在制作抗电镀油墨层及各干膜层时，均采用同一曝光对位点，并将曝光对位精度设在20μm以内，可保证所制作的阶梯铜柱的各阶梯同轴，且阶梯铜柱的侧面垂直平滑。
附图说明
图1为实施例中在PCB上制作抗电镀油墨层和第一干膜层后的结构示意图；
图2为实施例中在PCB上电镀第一镀铜层后的结构示意图；
图3为实施例中在PCB上制作第二干膜层后的结构示意图；
图4为实施例中在PCB上电镀第二镀铜层后的结构示意图；
图5为实施例中除掉PCB上的第一干膜层和第二干膜层后的结构示意图；
图6为实施例中在PCB上电镀锡层后的结构示意图；
图7为实施例中除掉PCB上的抗电镀油墨层后的结构示意图；
图8为实施例中的PCB除掉阶梯铜柱以外的铜箔层后的结构示意图；
图9为实施例中制作好阶梯铜柱并退锡层后的PCB的结构示意图。
具体实施方式
为了更充分理解本发明的技术内容，下面结合具体实施例对本发明的技术方案作进一步介绍和说明。
实施例
参照图1-9，本实施例提供 一种PCB中阶梯铜柱的制作方法，使用该方法所制作的PCB的参数如下：
芯板：0.71mm H/H 层数：2L
板料Tg：170° 基铜：1 OZ
阶梯铜柱层数：2L
具体制作步骤如下：
（1）在芯板10的工艺边上钻外围孔及制作曝光对位点，然后在芯板10上制作 抗电镀油墨层20并在需要制作阶梯铜柱的位置开窗，接着烤板和粗化处理。具体如下：
（a） 开料：按拼板尺寸开出芯板10，芯板10厚度为 0.71mm H/H 。
（b） 外围孔及曝光对位点：利用钻孔资料在芯板10的工艺边上钻外围孔。并且在芯板10的工艺边上制作一曝光对位点，所制作的曝光对位点用于后续制作抗电镀油墨层20、第一干膜层30和第二干膜层50时共同使用。
（c）丝印抗电镀油墨：在芯板10上丝网印刷或涂布抗电镀油墨，制得抗电镀油墨层20，并将抗电镀油墨层20的厚度控制在20-26µm。
（d）曝光和显影：以6-7格曝光能量（21格曝光尺）及曝光对位点进行对位曝光，并将曝光对位精度设在20µm内，然后进行显影，使芯板10上需制作阶梯铜柱40的位置之外的区域完全被抗电镀油墨层20覆盖，而需制作阶梯铜柱40的位置则完全裸露出来，即在需制作阶梯铜柱40的位置处设开窗。
（e）烘烤：将芯板10置于 116-124 ℃下烤板23-27min。抗电镀油墨层20经过烘烤，可保证在后续退干膜层时，可选择性的退去干膜层而保留抗电镀油墨层20完好。
（f）粗化：利用喷砂对抗电镀油墨层20表面进行粗化处理，以增加后续干膜层在抗电镀油墨层20上的附着力。
（2）在芯板10上制作第一干膜层30并在需要制作阶梯铜柱40的位置开窗，然后在开窗处电镀铜，形成第一镀铜层41。如图1-2所示。具体如下：
（a）贴第一干膜：在芯板10上贴厚度为50µm的干膜，压膜温度：112-118℃，压力：5.0-5.5Kgf/cm2，速度：1.4-1.5m/min，入板板温：50-60℃，出板板温：70-85℃。
（b）曝光和显影： 以7-8格曝光能量（21格曝光尺）及曝光对位点进行对位曝光，并将曝光对位精度设在20µm内，然后进行显影形成第一干膜层30，使芯板10上需制作阶梯铜柱40的位置之外的区域完全被第一干膜层30覆盖，而需制作阶梯铜柱40的位置则完全裸露出来，即在需制作阶梯铜柱40的位置处设开窗，该开窗的形状及大小与抗电镀油墨层20上的开窗完全一致。
（c）微蚀 ：对芯板10进行表面微蚀处理，并将微蚀量控制在1.0-2.0µm，保证芯板10上开窗处的铜箔层11表面的洁净度与粗糙度，使后续电镀上去的第一镀铜层41可很好的附着在铜箔层11上。
（d）电镀第一镀铜层41：将芯板10置于电镀铜缸中进行电镀，电镀铜缸中铜离子的浓度为55-65g/L，硫酸的浓度为125-135mL/L，以22ASF的电流密度进行电镀，电镀时间约为165min，得第一镀铜层41，第一镀铜层41的表面与第一干膜层30的表面齐平。采用高电流密度进行电镀铜，可缩短电镀时间，降低第一干膜层30或抗电镀油墨层20出现脱离的风险。第一镀铜层41的表面与第一干膜层30的表面齐平，可使芯板10的板面平整，后续贴上的干膜可很好的附着在第一干膜层30上。
（e）清洗和干燥：对芯板10进行全面的表面清洗，并在负压环境下进行低温烘干（真空度：-400 mmHg至-500 mmHg，温度：55-65℃，时间：45min），以清除第一干膜层30与第一镀铜层41间残留的水气，防止后续所贴干膜层因水气的影响而起皱或起泡。
（3）在芯板10上制作第二干膜层50并在需要制作阶梯铜柱40的位置开窗，然后在开窗处电镀铜，形成第二镀铜层42；所述第一镀铜层41和第二镀铜层42构成阶梯铜柱40。如图3-4所示。具体如下：
（a）贴第二下干膜51：在芯板10上贴厚度为50µm的干膜，压膜温度：112-118℃，压力：5.0-5.5Kgf/cm2，速度：1.6-1.7m/min，入板板温：50-60℃，出板板温：65-80℃。
贴第二上干膜52：继续在芯板10上贴厚度为50µm的干膜，压膜温度：112-118℃，压力：5.0-5.5Kgf/cm2，速度：1.6-1.7m/min，入板板温：50-60℃，出板板温：65-80℃。
（b）曝光和显影： 以8-9格曝光能量（21格曝光尺）及曝光对位点进行对位曝光，并将曝光对位精度设在20µm内，然后进行显影，由第二下干膜51和第二 上 干膜52形成第二干膜层50，使芯板10上需制作阶梯铜柱40的位置之外的区域完全被第二干膜层50覆盖，而需制作阶梯铜柱40的位置则完全裸露出来，即在需制作阶梯铜柱40的位置处设开窗，该开窗小于 第一干膜层30的开窗，即 该开窗的尺寸比第一镀铜层41的上表面积小，该开窗的各边相比第一镀铜层41的上表面各边内缩0.25mm。
（c）微蚀 ：对芯板10进行表面微蚀处理，并将微蚀量控制在1.0-2.0µm，保证第一镀铜层41上表面的洁净度与粗糙度，使后续电镀上去的第二镀铜层42可很好的附着在第一镀铜层41上。
（d）电镀第二镀铜层42：将芯板10置于电镀铜缸中进行电镀，电镀铜缸中铜离子的浓度为55-65g/L，硫酸的浓度为125-135mL/L，以20ASF的电流密度进行电镀，电镀时间约为235min，得第二镀铜层42，第二镀铜层42的表面与第二干膜层50的表面齐平。采用高电流密度进行电镀铜，可缩短电镀时间，降低第一干膜层30、第二干膜层50或抗电镀油墨层20出现脱离的风险。第二镀铜层42的表面与第二干膜层50的表面齐平，可使芯板10的板面平整。
由第一镀铜层41和第二镀铜层42构成具有两层阶梯的阶梯铜柱40。
（4）退去第一干膜层30和第二干膜层50，然后在阶梯铜柱40上电镀锡层60。如图5-6所示。
（a）退干膜：用退膜液对芯板10进行退膜处理，使芯板10上的所有干膜完全除去，而抗电镀油墨层20则完好保留。温度：45-51℃，喷淋压力：1.2-1.8kgf/cm2，时间：2.5-3.0min。
（b）镀锡：在阶梯铜柱40上电镀锡层60，形成抗蚀层，锡层60的厚度为5-8μm。
（5）除去抗电镀油墨层20，然后蚀刻除去阶梯铜柱40之外的铜箔层11，接着除去锡层60。如图7-9所示。
将抗电镀油墨层20退去后，通过碱性蚀刻将未被锡层60覆盖的铜箔层11除去。接着将锡层60退去。
（6）对上述制作了阶梯铜柱40的芯板10进行表面处理后，再依次进行锣外形、电测试和终检，合格的产品即可出货。
在其它实施方案中，还可在芯板的表面制作外层线路，使所制得的PCB除具有阶梯铜外，还具有外层线路。
在其它实施方案中，还可将上述实施例中的芯板换成 设有内层线路的 多层板，该多层板由 设有内层线路的芯板与外层铜箔通过半固化片压合在一起形成。
此外，还可在上述实施例的步骤（4）前通过重复步骤（3）来制作具有更多阶梯层数的阶梯铜柱。即：以步骤（3）的方法在芯板上制作第三干膜层，然后在开窗处电镀第三镀铜层，所述第一镀铜层、第二镀铜层和第三镀铜层构成阶梯铜柱。然后以步骤S4的方法，将层压板上的第一干膜层、第二干膜层和第三干膜层全部除去，接着在阶梯铜柱上电镀锡层。并继续进行步骤（5）和（6）的流程。从而制得具有三层阶梯的阶梯铜柱。
若需制作具有四层阶梯的阶梯铜柱，则按照上述的方法在步骤（4）前再重复步骤（3）一次。若需制作更多层的阶梯铜柱，则以此类推。
对比例1
本对比例提供 一种PCB中阶梯铜柱的制作方法，该方法与上述实施例的方法基本相同，不同之处在于：步骤（1）中 不对芯板进行烘烤处理（省略步骤1中的e操作），即 在芯板上制作 抗电镀油墨层后，直接对抗电镀油墨层进行粗化处理。
在步骤（4）中，用退膜液退去第一干膜层和第二干膜层时，抗电镀油墨层会被一起除去，使得无法继续进行镀锡及步骤（5）的操作。
对比例2
本对比例提供 一种PCB中阶梯铜柱的制作方法，该方法与上述实施例的方法基本相同，不同之处在于：步骤（1）中，在芯板上制作 抗电镀油墨层后， 将芯板置于 106-114 ℃下烤板18-22min。
在步骤（4）中，用退膜液退去第一干膜层和第二干膜层时，部分抗电镀油墨层会被一起除去，使得抗电镀油墨层不能保持完整。继续进行镀锡时，已被除去抗电镀油墨层的铜面上也会镀上锡层，最终使得需除去的铜箔层（阶梯铜柱之外的铜箔层）未蚀刻干净，影响产品的品质。
以上所述仅以实施例来进一步说明本发明的技术内容，以便于读者更容易理解，但不代表本发明的实施方式仅限于此，任何依本发明所做的技术延伸或再创造，均受本发明的保护。

Claims (9)

  1. 一种PCB中阶梯铜柱的制作方法，其特征在于，包括以下步骤：
    S1、在层压板上制作抗电镀油墨层并在需要制作阶梯铜柱的位置开窗，然后将层压板置于116-124℃下烤板23-27min；所述层压板包括基材层及与基材层压合在一起的铜箔层；
    S2、在层压板上制作第一干膜层并在需要制作阶梯铜柱的位置开窗，所述第一干膜层的开窗与抗电镀油墨层的开窗形状大小一致；然后在开窗处电镀铜，形成第一镀铜层；
    S3、在层压板上制作第二干膜层并在需要制作阶梯铜柱的位置开窗，所述第二干膜层的开窗小于第一干膜层的开窗；然后在开窗处电镀铜，形成第二镀铜层；所述第一镀铜层和第二镀铜层构成阶梯铜柱；
    S4、除去第一干膜层和第二干膜层，然后在阶梯铜柱上电镀锡层；
    S5、除去抗电镀油墨层，然后蚀刻除去阶梯铜柱之外的铜箔层，接着除去锡层。
  2. 根据权利要求1所述一种PCB中阶梯铜柱的制作方法，其特征在于,步骤S1中，对层压板进行烤板后，对抗电镀油墨层进行粗化处理。
  3. 根据权利要求2所述一种PCB中阶梯铜柱的制作方法，其特征在于,步骤S2中，以22ASF的电流密度电镀第一镀铜层，至第一镀铜层与第一干膜层齐平。
  4. 根据权利要求3所述一种PCB中阶梯铜柱的制作方法，其特征在于,步骤S3中，以20ASF的电流密度电镀第二镀铜层，至第二镀铜层与第二干膜层齐平。
  5. 根据权利要求4所述一种PCB中阶梯铜柱的制作方法，其特征在于,步骤S2和S3中，电镀第一镀铜层和第二镀铜层时，电镀缸中铜离子的浓度为55-65g/L，硫酸的浓度为125-135mL/L。
  6. 根据权利要求5所述一种PCB中阶梯铜柱的制作方法，其特征在于,在步骤S4前重复步骤S3，以步骤S3的方法在层压板上制作其它干膜层，然后在开窗处电镀其它镀铜层，所述第一镀铜层、第二镀铜层和其它镀铜层构成阶梯铜柱；然后以步骤S4的方法将层压板上的第一干膜层、第二干膜层和其它干膜层全部除去并在阶梯铜柱上电镀锡层。
  7. 根据权利要求6所述一种PCB中阶梯铜柱的制作方法，其特征在于,所述抗电镀油墨层的厚度为20-26μm。
  8. 根据权利要求1-7任一项所述一种PCB中阶梯铜柱的制作方法，其特征在于,所述层压板为一芯板。
  9. 根据权利要求1-7任一项所述一种PCB中阶梯铜柱的制作方法，其特征在于,所述层压板为设有内层线路的芯板与外层铜箔通过半固化片压合在一起的多层板。
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