WO2016070441A1 - 印刷电路板 - Google Patents

印刷电路板 Download PDF

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Publication number
WO2016070441A1
WO2016070441A1 PCT/CN2014/090754 CN2014090754W WO2016070441A1 WO 2016070441 A1 WO2016070441 A1 WO 2016070441A1 CN 2014090754 W CN2014090754 W CN 2014090754W WO 2016070441 A1 WO2016070441 A1 WO 2016070441A1
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Prior art keywords
resistors
common
circuit board
printed circuit
input line
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PCT/CN2014/090754
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English (en)
French (fr)
Inventor
宋丽佳
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/420,373 priority Critical patent/US9565765B2/en
Publication of WO2016070441A1 publication Critical patent/WO2016070441A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

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  • the present invention relates to the field of circuit board manufacturing, and more particularly to a printed circuit board.
  • a first pad S01 and a second pad S02 are respectively disposed on the first resistor R1 and the second resistor R2 on the printed circuit board, and one lead of the first resistor R1 is provided.
  • the pin is connected to the first pad S01, and one pin of the second resistor R2 is connected to the second pad S02, and the first pad S01 and the second pad S02 are electrically connected.
  • I0 is connected to the other pin of the first resistor R1, and then the electronic component is fixed to the first pad S01 by a mounting process. At the end of the printed circuit board, only one pad is connected to the input line I0, which causes the remaining pads to be vacant, which greatly occupies space of the printed circuit board and increases the manufacturing cost of the printed circuit board.
  • the present invention provides a printed circuit board having high space utilization, small size, and cost saving.
  • a printed circuit board having a plurality of resistors connected to the same input line terminal by pins, at least two of the plurality of resistors overlapping an access pin connected to the input line terminal, and The pin overlap is connected using a common pad on which the circuit components are mounted.
  • two of the plurality of resistors overlap with an access pin connected to the input line end, A common pad is provided at the overlap of the pins, and the two resistors are arranged perpendicular to each other.
  • three of the plurality of resistors overlap with an access pin connected to the input line terminal, a common pad is disposed at the pin overlap, and two of the three resistors Collinearly arranged and perpendicular to the other resistor.
  • four of the plurality of resistors overlap with an access pin connected to the input line terminal, a common pad is disposed at the pin overlap, and the four resistors are arranged vertically.
  • the number of resistors connected to the same input line end is greater than four, the plurality of common pads are adjacent, the plurality of the common pads are adjacent and electrically connected, and at least one of the common pads is connected to the input line end. .
  • the printed circuit board comprises two shared pads, and five resistors are connected to the same input line end, wherein three resistors overlap with the access pins connected to the input line ends and a common solder is provided at the overlap of the pins a disk, and two of the three resistors are symmetrically disposed on both sides of the two common pad lines and perpendicular to the other resistor; two other resistors of the five resistors and the input line
  • the access pins of the end connections overlap, and another common pad is disposed at the overlap of the pins, and the other two resistors are symmetrically arranged on both sides of the two common pad wires.
  • the printed circuit board includes two common pads, and five resistors are connected to the same input line terminal, wherein three resistors overlap the access pins connected to the input line terminals and a common solder is provided at the pin overlaps.
  • a disk and two of the three resistors are symmetrically disposed on both sides of the two common pad wires and perpendicular to the other resistor; the other two resistors of the five resistors are connected to the input
  • the access pins connected to the line ends overlap, and another shared pad is provided at the overlap of the pins, and the other two resistors are arranged perpendicular to each other.
  • the printed circuit board includes four shared pads, ten resistors are connected to the same input line end, the four common pads are arranged in a line, and the ten resistors have four access pin overlaps, Four common pads are respectively disposed at the four pin overlaps; each of the common pads on both ends of the four common pad wires is connected with three resistors, and two of the three resistors Symmetrically arranged on both sides of the four shared pad lines and perpendicular to the other resistor; each of the common pads located in the middle of the four shared pad lines is connected with two perpendicular to the 4 The resistance of the shared pad wiring.
  • the printed circuit board includes five common pads, ten resistors are connected to the same input line terminal, and each of the ten resistors shares one common pad and is symmetrically arranged on the five shared pad lines. On both sides.
  • the invention improves the space utilization of the printed circuit board by overlapping the access pins of the at least two resistors connected to the same input line end on the printed circuit board, and the printed circuit board is smaller in size and reduces the manufacturing cost.
  • FIG. 1 is a schematic diagram of a pad layout of a prior art printed circuit board.
  • FIG. 2 is a schematic diagram of a circuit structure for transmitting signals of the same input line to a plurality of output lines.
  • FIG. 3 is a schematic view showing the arrangement of resistors and pads on a printed circuit board according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic view showing the arrangement of resistors and pads on a printed circuit board according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic diagram showing the arrangement of resistors and pads on a printed circuit board according to Embodiment 3 of the present invention.
  • FIG. 6 is a schematic view showing the arrangement of resistors and pads on a printed circuit board according to Embodiment 4 of the present invention.
  • FIG. 7 is a schematic view showing the arrangement of resistors and pads on a printed circuit board according to Embodiment 5 of the present invention.
  • Figure 8 is a schematic view showing the arrangement of resistors and pads on a printed circuit board according to Embodiment 6 of the present invention.
  • Figure 9 is a schematic view showing the arrangement of resistors and pads on a printed circuit board according to Embodiment 7 of the present invention.
  • Figure 10 is a schematic view showing the arrangement of resistors and pads on a printed circuit board according to Embodiment 8 of the present invention.
  • Embodiments of the present invention provide a printed circuit board.
  • a plurality of resistors on a printed circuit board are connected to the same input line terminal I0 through an access pin, and at least two resistors of the plurality of resistors are connected to the input line terminal I0.
  • the input pins overlap and a common pad connection is used at the overlap, and the circuit components are mounted on the common pads.
  • the two resistors Ra, Rb and a first common pad S1 form a binary module M2a, wherein the access pins of the two resistors Ra, Rb overlap and are connected to the input line terminal I0 through the first common pad S1, the resistor Ra, the other pin of the resistor Rb is respectively connected to different output lines O1, O2, and a first common pad S1 is provided at the overlap of the pins.
  • the resistor Ra is collinear with the resistor Rb. Arrangement.
  • the pads of the two resistors have another arrangement.
  • the two resistors Ra, Rb and a second common pad S2 form an angular binary module M2b, and the access pins of the resistor Ra and the resistor Rb overlap and are connected to the input line terminal I0 through the second common pad S2, and the resistor Ra
  • the other pin of the resistor Rb is respectively connected to different output lines O1 and O2, and a second common pad S2 is disposed at the overlap of the pins.
  • the resistor Ra and the resistor Rb are perpendicular to each other. Arrangement.
  • three resistors Rc, Rd, Re and a third common pad S3 form a ternary module M3, three resistors Rc, Rd, Re is connected to the input pin connected to the input line terminal I0, and a third common pad S3 is disposed at the overlap of the pin, and the other pins of the three resistors Rc, Rd, and Re are respectively connected to different output lines O1. O2, O3.
  • the resistor Rc among the three resistors is arranged in line with the resistor Re, and the other resistor Rd is disposed perpendicularly to the resistors Rc, Re.
  • the arrangement of the pads of the four resistors on the printed circuit board, the four resistors Rf, Rg, Rh, Ri and a fourth common pad S4 form a quaternary module M4, four resistors Rf Rg, Rh, and Ri are connected to the input line terminal I0 and the access pins are overlapped, and a fourth common pad S4 is disposed at the pin overlap.
  • the other pins of the resistor Rf, the resistor Rg, the resistor Rh, and the resistor Ri are connected to different output lines O1, O2, O3, O4, respectively.
  • four resistors Rf, Rg, Rh, Ri are arranged vertically.
  • the manner of setting the common pad is described in detail by taking the case of five resistors.
  • Two common pads are selected: a fifth shared pad S10 and a sixth shared pad S20, and five resistors and two shared pads are divided into one ternary module and one binary module for arrangement.
  • three resistors R10, R20, and R30 and the fifth common pad S10 are used as one ternary module, and the other two resistors R40 and R50 and the sixth common pad S20 are used as one binary module, and the fifth common welding is performed.
  • the disk S10 and the sixth common pad S20 are electrically connected.
  • the resistors R10, R20, and R30 overlap with the access pins connected to the input line terminal I0, and a fifth common pad S10 is disposed at the overlap of the pins, wherein the resistor R20 and the resistor R30 are symmetrically arranged on the two common pads S10.
  • S20 is connected to both sides of the line and perpendicular to another resistor R10; the other two resistors R40 and R50 overlap with the access pins connected to the input line terminal I0, and a sixth common pad S20 is disposed at the overlap of the pins.
  • the resistors R40 and R50 are symmetrically arranged on both sides of the line connecting the two common pads S10 and S20.
  • the other pins of the five resistors R10, R20, R30, R40 and R50 are respectively connected to different output lines O10, O20, O30, O40, O50, and the input line terminal I0 is connected to the fifth common pad at one of the ends. S10.
  • This embodiment is another arrangement of the common pads of the five resistors.
  • the plurality of common pads are also arranged adjacent to each other and electrically connected, and at least one common pad is connected to the input line terminal I0, and then
  • the common pad and the resistor are divided into a plurality of modules, and the pads are freely arranged according to the combination of the binary module M2a, the angular binary module M2b, the ternary module M3, and the quaternary module M4 described in Embodiment 1-4. Seek to connect all resistors with fewer pads to avoid the presence of empty pads.
  • the common pad S20 is arranged by dividing five resistors and two common pads into one ternary module and one angular binary module. Specifically, three resistors R10, R20, and R30 and the fifth common pad S10 are used as one ternary module, and the other two resistors R40 and R50 and the sixth common pad S20 are used as one angular binary module, and the fifth sharing is performed.
  • the pad S10 and the sixth common pad S20 are electrically connected.
  • the resistor R20 and the resistor R30 are symmetrically arranged on both sides of the two common pads S10 and S20, and are perpendicular to the other resistor R10, and the resistors R40 and R50 are arranged on the side adjacent to the resistor R20, so that the resistor R40 It is parallel to the resistor R20, and the resistor R50 is perpendicular to the resistor R40.
  • the other pins of the five resistors R10, R20, R30, R40 and R50 are respectively connected to different output lines O10, O20, O30, O40, O50, and the input line terminal I0 is connected therein.
  • a fifth common pad S10 at one end.
  • the manner of setting the common pad is described in detail by taking the case of 10 resistors.
  • a plurality of common pads are also arranged adjacent to each other and electrically connected, and at least one common pad is connected to the input line end. I0, then divide the common pad and the resistor into a plurality of modules, and freely arrange according to the combination of the binary module M2a, the angular binary module M2b, the ternary module M3 and the quaternary module M4 described in Embodiment 1-4.
  • Pads in order to achieve the connection of all resistors with fewer pads, avoiding the presence of empty pads.
  • a seventh shared pad S7 an eighth shared pad S8, and a ninth shared solder.
  • the disk S9 and the tenth shared pad S10 are arranged by dividing 10 resistors and 4 common pads into two ternary modules and two binary modules. Specifically, three resistors R1, R2, R3 and seventh pad S7 are used as one ternary module, three resistors R8, R9, R10 and tenth common pad S10 are used as another ternary module, and four other resistors are used.
  • R4 and R5, R6 and R7 are respectively connected to the eighth shared pad S8 and the ninth shared pad S9, and as the two binary modules, the seventh shared pad S7, the eighth shared pad S8, and the ninth shared solder are connected.
  • the disk S9 and the tenth common pad S10 are sequentially electrically connected, and the input line terminal I0 is connected to the seventh common pad S7 at one of the ends. That is, 10 resistors are connected to the same input line terminal I0 and respectively connected to different output lines O1-O10.
  • Four common pads S7, S8, S9, S10 are arranged in line, and 10 resistors have four access pins. At the overlap, the four shared pads are placed at the overlap of the four pins.
  • each of the common pads located at the two ends of the four shared pad lines is connected with three resistors, that is, the seventh pad S7 is connected to the resistors R1, R2, and R3, and the tenth shared pad S10 is connected to the resistors R8 and R9. R10.
  • the resistor R2 and the resistor R3, the resistor R8 and the resistor R9 are symmetrically arranged on both sides of the four common pad lines, and the resistor R1 and the resistor R10 share the seventh common pad S7 and the tenth shared pad S10 at both ends, respectively.
  • the eighth common pad S8 and the ninth common pad S9 located in the middle of the four shared pad lines are respectively connected with resistors R4 and R5 and resistors R6 and R7, and resistors R4, R5 and resistors R6, R7 are perpendicular to the wiring of the four shared pads.
  • This embodiment is another arrangement manner of the shared pads of 10 resistors.
  • the plurality of common pads are also arranged adjacent to each other and electrically connected, and at least one common pad is connected to the input line terminal I0, and then
  • the common pad and the resistor are divided into a plurality of modules, and the pads are freely arranged according to the combination of the binary module M2a, the angular binary module M2b, the ternary module M3, and the quaternary module M4 described in Embodiment 1-4. Seek to connect all resistors with fewer pads to avoid the presence of empty pads.
  • a seventh shared pad S7 an eighth shared pad S8, and a ninth.
  • the common pad S9, the tenth shared pad S10, and the eleventh shared pad S11 are arranged by dividing 10 resistors and 5 common pads into five binary modules, and the seventh shared pads S7 and eighth are arranged.
  • the common pad S8, the ninth common pad S9, the tenth common pad S10, and the eleventh common pad S11 are sequentially electrically connected, and the input line terminal I0 is connected to the seventh common pad S7 at one of the ends.
  • 10 resistors are connected to the same input line terminal I0 and respectively connected to different output lines O1-O10.
  • Each of the 10 resistors shares a common pad and is symmetrically arranged on both sides of the 5 shared pad lines. More specifically, the resistors R1 and R2 share the seventh common pad S7, the resistors R3 and R4 share the eighth shared pad S8, the resistors R5 and R6 share the ninth shared pad S9, and the resistors R7 and R8 share the tenth common pad. In the disk S10, the resistors R9 and R10 share the eleventh common pad S11.
  • the printed circuit board of the present invention is not limited to the number of resistors listed in the above embodiments.
  • the number of resistors connected to the same input line terminal I0 on the printed circuit board is greater than four, one pad cannot realize all.
  • the connection of the resistors only needs to divide the common pads and the resistor into a plurality of modules, which are combined according to the binary module M2a, the angular binary module M2b, the ternary module M3 and the quaternary module M4 described in the embodiments 1-4.
  • the method freely arranges the pads so that the plurality of common pads are adjacent and electrically connected, and at least one of the common pads is connected to the input line terminal I0, so that all the resistors can be connected with a minimum of pads, avoiding the vacant pads The presence.
  • the resistor connected to the same input line terminal I0 on the printed circuit board of the embodiment of the present invention is combined with a plurality of shared pads by a reasonable arrangement, and the resistor and the shared pad are in accordance with a binary module, an angular binary module, and a ternary
  • the module and the quaternary module are arranged in combination, and then all the common pads are electrically connected through the wires, thereby avoiding the occurrence of vacant pads, saving the use of solder paste for electronic component patches, and improving the printed circuit board.
  • the space utilization makes the printed circuit board smaller in size and ultimately reduces manufacturing costs.

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  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本发明公开了一种印刷电路板，印刷电路板上的多个电阻通过引脚连接到同一输入线路端，所述多个电阻中至少有两个所述电阻与所述输入线路端连接的接入引脚重叠，并在重叠处使用共用焊盘连接，电路元件贴装在所述共用焊盘上。本发明通过将印刷电路板上连接到同一输入线路端的至少两个电阻的接入引脚重叠，提高了印刷电路板的空间利用率，印刷电路板的尺寸更小，降低了制造成本。

Description

印刷电路板 技术领域
本发明涉及电路板制造领域，尤其涉及一种印刷电路板。
背景技术
通常，印刷电路板上焊接有许多元器件，元器件的数量越多，所需要的印刷电路板的体积越大，制造印刷电路板需要花费的成本更高。
如图1所示，现有技术中，印刷电路板上的第一电阻R1和第二电阻R2上分别设有第一焊盘S01、第二焊盘S02，并使第一电阻R1的一个引脚与第一焊盘S01连接，第二电阻R2的一个引脚与第二焊盘S02连接，再将第一焊盘S01和第二焊盘S02电连接。结合图2，印刷电路板上有许多输出线路O1、O2、…、On(这里n为不小于2的自然数)，当需要将元件连接在某一输出线路如O1时，通常是先将输入线路I0连接第一电阻R1的另一个引脚，然后通过贴装工艺将电子元件固定到第一焊盘S01上。这种印刷电路板最后只有一个焊盘与输入线路I0连接，导致其余的焊盘空置，大大占用了印刷电路板的空间，增加了印刷电路板的制造成本。
发明内容
鉴于现有技术存在的不足，本发明提供了一种空间利用率高、尺寸小、节约成本的印刷电路板。
为了实现上述的目的，本发明采用了如下的技术方案：
一种印刷电路板，印刷电路板上的多个电阻通过引脚连接到同一输入线路端，所述多个电阻中至少两个电阻与所述输入线路端连接的接入引脚重叠，并在引脚重叠处使用共用焊盘连接，电路元件贴装在所述共用焊盘上。
其中，所述多个电阻中的两个电阻与所述输入线路端连接的接入引脚重叠，所述引脚重叠处设有一个共用焊盘，且所述两个电阻共线布置。
或者，所述多个电阻中的两个电阻与所述输入线路端连接的接入引脚重叠， 所述引脚重叠处设有一个共用焊盘，且所述两个电阻相互垂直布置。
或者，所述多个电阻中的三个电阻与所述输入线路端连接的接入引脚重叠，所述引脚重叠处设有一个共用焊盘，且所述三个电阻之中的两个共线布置，并与另一个电阻垂直。
或者，所述多个电阻中的四个电阻与所述输入线路端连接的接入引脚重叠，所述引脚重叠处设有一个共用焊盘，且所述四个电阻两两垂直布置。
其中，连接到同一输入线路端的电阻数量大于4个，所述共用焊盘有多个，多个所述共用焊盘相邻并电连接，且至少一个所述共用焊盘连接所述输入线路端。
其中，印刷电路板包括两个共用焊盘，5个电阻连接到同一输入线路端，其中3个电阻与所述输入线路端连接的接入引脚重叠并在引脚重叠处设有一个共用焊盘，且所述3个电阻之中的两个对称布置于所述两个共用焊盘连线两侧，并与另一个电阻垂直；所述5个电阻的另外2个电阻与所述输入线路端连接的接入引脚重叠，并在引脚重叠处设有另一个共用焊盘，所述另外2个电阻对称布置于所述两个共用焊盘连线两侧。
或者，印刷电路板包括两个共用焊盘，5个电阻连接到同一输入线路端，其中3个电阻与所述输入线路端连接的接入引脚重叠并在引脚重叠处设有一个共用焊盘，且所述3个电阻之中的两个对称布置于所述两个共用焊盘连线的两侧，并与另一个电阻垂直；所述5个电阻的另外2个电阻与所述输入线路端连接的接入引脚重叠，并在引脚重叠处设有另一个共用焊盘，所述另外2个电阻相互垂直布置。
其中，印刷电路板包括4个共用焊盘，10个电阻连接到同一输入线路端，所述4个共用焊盘共线布置，所述10个电阻具有四个接入引脚重叠处，所述4个共用焊盘分别设于所述四个引脚重叠处；位于所述4个共用焊盘连线两端的每个共用焊盘均连接3个电阻，且所述3个电阻之中的两个对称布置于所述4个共用焊盘连线两侧，并与另一个电阻垂直；位于所述4个共用焊盘连线中间的每个共用焊盘均连接有两个垂直于所述4个共用焊盘连线的电阻。
或者，印刷电路板包括5个共用焊盘，10个电阻连接到同一输入线路端，所述10个电阻的每两个共用一个共用焊盘并对称布置于所述5个共用焊盘连线的两侧。
本发明通过将印刷电路板上连接到同一输入线路端的至少两个电阻的接入引脚重叠，提高了印刷电路板的空间利用率，印刷电路板的尺寸更小，降低了制造成本。
附图说明
图1为现有技术印刷电路板的焊盘布局示意图。
图2为将同一输入线路的信号传递至多个输出线路的电路结构示意图。
图3为本发明实施例1的印刷电路板上的电阻与焊盘设置方式示意图。
图4为本发明实施例2的印刷电路板上的电阻与焊盘设置方式示意图。
图5为本发明实施例3的印刷电路板上的电阻与焊盘设置方式示意图。
图6为本发明实施例4的印刷电路板上的电阻与焊盘设置方式示意图。
图7为本发明实施例5的印刷电路板上的电阻与焊盘设置方式示意图。
图8为本发明实施例6的印刷电路板上的电阻与焊盘设置方式示意图。
图9为本发明实施例7的印刷电路板上的电阻与焊盘设置方式示意图。
图10为本发明实施例8的印刷电路板上的电阻与焊盘设置方式示意图。
具体实施方式
下面将对结合附图用实施例对本发明做进一步说明。
参阅图2，在印刷电路板制造中，通常有多种电路布线方式，有时需要将印刷电路板表面的多个电阻R1、R2、…、Rn的接入引脚连接到同一输入线路端I0，再通过它们的另一引脚连接至不同的输出线路O1、O2、…、On(这里n为不小于2的自然数)，以通过在印刷电路板上不同的电阻上打上元件使其中一个网络连通。本发明实施例将这些电阻中的至少两个的接入引脚重叠，从而共用焊盘，省去焊盘空置的成本，提高了空间利用率。
本发明实施例提供了一种印刷电路板，印刷电路板上的多个电阻通过接入引脚连接到同一输入线路端I0，多个电阻中至少有两个电阻与输入线路端I0连接的接入引脚重叠，并在重叠处使用共用焊盘连接，电路元件贴装在共用焊盘上。
实施例1
如图3所示，为印刷电路板上两个电阻的焊盘设置方式。两个电阻Ra、Rb和一个第一共用焊盘S1组成一个二元模块M2a，其中两个电阻Ra、Rb的接入引脚重叠并通过第一共用焊盘S1与输入线路端I0连接，电阻Ra、电阻Rb的另一引脚分别连接至不同的输出线路O1、O2，并在引脚重叠处设有一个第一共用焊盘S1，在二元模块M2a中，电阻Ra与电阻Rb共线布置。
实施例2
如图4所示，两个电阻的焊盘还有另一种设置方式。两个电阻Ra、Rb和一个第二共用焊盘S2组成一个角二元模块M2b，电阻Ra和电阻Rb的接入引脚重叠并通过第二共用焊盘S2与输入线路端I0连接，电阻Ra、电阻Rb的另一引脚分别连接至不同的输出线路O1、O2，并在引脚重叠处设有一个第二共用焊盘S2，在角二元模块M2b中，电阻Ra与电阻Rb相互垂直布置。
实施例3
如图5所示，为印刷电路板上三个电阻的焊盘设置方式，三个电阻Rc、Rd、Re与一个第三共用焊盘S3组成一个三元模块M3，三个电阻Rc、Rd、Re与输入线路端I0连接的接入引脚重叠，引脚重叠处设有一个第三共用焊盘S3，三个电阻Rc、Rd、Re的另一引脚分别连接至不同的输出线路O1、O2、O3。具体地，在三元模块M3中，三个电阻之中的电阻Rc与电阻Re共线布置，另一个电阻Rd与电阻Rc、Re垂直设置。
实施例4
如图6所示，为印刷电路板上四个电阻的焊盘的设置方式，四个电阻Rf、Rg、Rh、Ri与一个第四共用焊盘S4组成一个四元模块M4，四个电阻Rf、Rg、Rh、Ri与输入线路端I0连接且接入引脚重叠，引脚重叠处设有一个第四共用焊盘S4。电阻Rf、电阻Rg、电阻Rh、电阻Ri的另一引脚分别连接至不同的输出线路O1、O2、O3、O4。在四元模块M4中，四个电阻Rf、Rg、Rh、Ri两两垂直布置。
实施例5
当印刷电路板上连接到同一输入线路端I0的电阻数量大于4个时，一个焊盘无法实现所有电阻的连接，此时共用焊盘需要设置多个，同时将多个共用焊盘相邻布置并电连接，将至少一个共用焊盘连接至输入线路端I0，然后将共用焊盘和电阻划分成多个模块，按照实施例1-4中所描述的二元模块M2a、角二元 模块M2b、三元模块M3和四元模块M4组合的方式自由布置焊盘，以求利用较少的焊盘实现所有电阻的连接，避免空置焊盘的存在。
本实施例以5个电阻的情形为例对共用焊盘的设置方式进行详细描述，参阅图7，当有5个电阻R10、R20、R30、R40和R50连接到同一输入线路端I0时，可以选取两个共用焊盘：第五共用焊盘S10和第六共用焊盘S20，将5个电阻和2个共用焊盘划分为一个三元模块和一个二元模块进行布置。具体地，其中3个电阻R10、R20、R30与第五共用焊盘S10作为一个三元模块，另外2个电阻R40和R50与第六共用焊盘S20作为一个二元模块，将第五共用焊盘S10和第六共用焊盘S20电连接。即电阻R10、R20、R30与输入线路端I0连接的接入引脚重叠，并在该引脚重叠处设置第五共用焊盘S10，其中电阻R20、电阻R30对称布置于两个共用焊盘S10、S20连线两侧，并与另一个电阻R10垂直；另外2个电阻R40、R50与输入线路端I0连接的接入引脚重叠，并在该引脚重叠处设置第六共用焊盘S20，电阻R40、R50对称布置于两个共用焊盘S10、S20连线的两侧。5个电阻R10、R20、R30、R40和R50的另一引脚分别连接至不同的输出线路O10、O20、O30、O40、O50，输入线路端I0连接位于其中一个端部的第五共用焊盘S10。
实施例6
本实施例为5个电阻的共用焊盘的另一种设置方式，本实施例也是将多个共用焊盘相邻布置并电连接，将至少一个共用焊盘连接至输入线路端I0，然后将共用焊盘和电阻划分成多个模块，按照实施例1-4中所描述的二元模块M2a、角二元模块M2b、三元模块M3和四元模块M4组合的方式自由布置焊盘，以求利用较少的焊盘实现所有电阻的连接，避免空置焊盘的存在。
如图8所示，当有5个电阻R10、R20、R30、R40和R50连接到同一输入线路端I0时，印刷电路板上设置有两个共用焊盘：第五共用焊盘S10和第六共用焊盘S20，将5个电阻和2个共用焊盘划分为一个三元模块和一个角二元模块进行布置。具体地，其中3个电阻R10、R20、R30与第五共用焊盘S10作为一个三元模块，另外2个电阻R40和R50与第六共用焊盘S20作为一个角二元模块，将第五共用焊盘S10和第六共用焊盘S20电连接。即电阻R20、电阻R30对称布置于两个共用焊盘S10、S20连线两侧，并与另一个电阻R10垂直，同时将电阻R40、R50布置在相邻于电阻R20的一侧，使电阻R40与电阻R20平行，且电阻R50与电阻R40垂直。5个电阻R10、R20、R30、R40和R50的另一引脚分别连接至不同的输出线路O10、O20、O30、O40、O50，输入线路端I0连接位于其中 一个端部的第五共用焊盘S10。
实施例7
本实施例以10个电阻的情形为例对共用焊盘的设置方式进行详细描述，本实施例也是将多个共用焊盘相邻布置并电连接，将至少一个共用焊盘连接至输入线路端I0，然后将共用焊盘和电阻划分成多个模块，按照实施例1-4中所描述的二元模块M2a、角二元模块M2b、三元模块M3和四元模块M4组合的方式自由布置焊盘，以求利用较少的焊盘实现所有电阻的连接，避免空置焊盘的存在。
参阅图9，当有10个电阻R1-R10连接到同一输入线路端I0时，印刷电路板上设置4个共用焊盘：第七共用焊盘S7、第八共用焊盘S8、第九共用焊盘S9、第十共用焊盘S10，将10个电阻和4个共用焊盘划分为两个三元模块和两个二元模块进行布置。具体地，其中3个电阻R1、R2、R3与第七焊盘S7作为一个三元模块，3个电阻R8、R9、R10与第十共用焊盘S10作为另一个三元模块，另外4个电阻R4与R5、R6与R7分别与第八共用焊盘S8、第九共用焊盘S9连接，作为两个二元模块，将第七共用焊盘S7、第八共用焊盘S8、第九共用焊盘S9和第十共用焊盘S10依次电连接，输入线路端I0连接位于其中一个端部的第七共用焊盘S7。即10个电阻连接到同一输入线路端I0，并分别连接至不同的输出线路O1-O10。4个共用焊盘S7、S8、S9、S10共线布置，10个电阻具有四个接入引脚重叠处，4个共用焊盘分别设于四个引脚重叠处。具体地，位于4个共用焊盘连线两端的每个共用焊盘均连接3个电阻，即第七焊盘S7连接电阻R1、R2、R3，第十共用焊盘S10连接电阻R8、R9、R10。且电阻R2与电阻R3、电阻R8与电阻R9分别对称布置于该4个共用焊盘连线两侧，电阻R1与电阻R10分别共用两端的第七共用焊盘S7、第十共用焊盘S10并与该4个共用焊盘连线平行布置；位于这4个共用焊盘连线中间的第八共用焊盘S8、第九共用焊盘S9分别连接有电阻R4、R5与电阻R6、R7，电阻R4、R5与电阻R6、R7均垂直于4个共用焊盘的连线。
实施例8
本实施例为10个电阻的共用焊盘的另一种设置方式，本实施例也是将多个共用焊盘相邻布置并电连接，将至少一个共用焊盘连接至输入线路端I0，然后将共用焊盘和电阻划分成多个模块，按照实施例1-4中所描述的二元模块M2a、角二元模块M2b、三元模块M3和四元模块M4组合的方式自由布置焊盘，以求利用较少的焊盘实现所有电阻的连接，避免空置焊盘的存在。
如图10所示，当有10个电阻R1-R10连接到同一输入线路端I0时，印刷电路板上设置5个共用焊盘：第七共用焊盘S7、第八共用焊盘S8、第九共用焊盘S9、第十共用焊盘S10和第十一共用焊盘S11，将10个电阻和5个共用焊盘划分为5个二元模块进行布置，将第七共用焊盘S7、第八共用焊盘S8、第九共用焊盘S9、第十共用焊盘S10和第十一共用焊盘S11依次电连接，输入线路端I0连接位于其中一个端部的第七共用焊盘S7。即10个电阻连接到同一输入线路端I0，并分别连接至不同的输出线路O1-O10。10个电阻的每两个共用一个共用焊盘并对称布置于5个共用焊盘连线的两侧，更具体地，电阻R1、R2共用第七共用焊盘S7，电阻R3、R4共用第八共用焊盘S8，电阻R5、R6共用第九共用焊盘S9，电阻R7、R8共用第十共用焊盘S10，电阻R9、R10共用第十一共用焊盘S11。
可以理解的是，本发明的印刷电路板并不限于以上实施例中列出的电阻数量，当印刷电路板上连接到同一输入线路端I0的电阻数量大于4个时，一个焊盘无法实现所有电阻的连接，只需将共用焊盘和电阻划分成多个模块，按照实施例1-4中所描述的二元模块M2a、角二元模块M2b、三元模块M3和四元模块M4组合的方式自由布置焊盘，使多个共用焊盘相邻并电连接，将共用焊盘中的至少一个连接至输入线路端I0，即可利用最少的焊盘实现所有电阻的连接，避免空置焊盘的存在。
本发明的实施例的印刷电路板上连接到同一输入线路端I0的电阻被通过合理布置与若干个共用焊盘进行组合，将电阻与共用焊盘按照二元模块、角二元模块、三元模块、四元模块的方式进行组合布置，然后将所有的共用焊盘通过导线电连接，避免了焊盘空置的现象发生，节约了电子元件贴片时锡膏的使用量，提高了印刷电路板的空间利用率，使印刷电路板的尺寸更小，最终降低了制造成本。
以上所述仅是本发明的几种具体实施方式，应当指出的是，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

  1. 一种印刷电路板，其中，印刷电路板上的多个电阻通过引脚连接到同一输入线路端，所述多个电阻中至少有两个所述电阻与所述输入线路端连接的接入引脚重叠，并在引脚重叠处使用共用焊盘连接，电路元件贴装在所述共用焊盘上。
  2. 根据权利要求1所述的印刷电路板，其中，所述多个电阻中的两个电阻与所述输入线路端连接的接入引脚重叠，所述引脚重叠处设有一个共用焊盘，且所述两个电阻共线布置。
  3. 根据权利要求1所述的印刷电路板，其中，所述多个电阻中的两个电阻与所述输入线路端连接的接入引脚重叠，所述引脚重叠处设有一个共用焊盘，且所述两个电阻相互垂直布置。
  4. 根据权利要求1所述的印刷电路板，其中，所述多个电阻中的三个电阻与所述输入线路端连接的接入引脚重叠，所述引脚重叠处设有一个共用焊盘，且所述三个电阻之中的两个共线布置，并与另一个电阻垂直。
  5. 根据权利要求1所述的印刷电路板，其中，所述多个电阻中的四个电阻与所述输入线路端连接的接入引脚重叠，所述引脚重叠处设有一个共用焊盘，且所述四个电阻两两垂直布置。
  6. 根据权利要求1所述的印刷电路板，其中，连接到同一输入线路端的电阻数量大于4个，所述共用焊盘有多个，多个所述共用焊盘相邻并电连接，且至少一个所述共用焊盘连接所述输入线路端。
  7. 根据权利要求6所述的印刷电路板，其中，印刷电路板包括两个共用焊盘，5个电阻连接到同一输入线路端，其中3个电阻与所述输入线路端连接的接入引脚重叠并在引脚重叠处设有一个共用焊盘，且所述3个电阻之中的两个对称布置于所述两个共用焊盘连线两侧，并与另一个电阻垂直；所述5个电阻的另外2个电阻与所述输入线路端连接的接入引脚重叠，并在引脚重叠处设有另一个共用焊盘，所述另外2个电阻对称布置于所述两个共用焊盘连线两侧。
  8. 根据权利要求6所述的印刷电路板，其中，印刷电路板包括两个共用焊盘，5个电阻连接到同一输入线路端，其中3个电阻与所述输入线路端连接的接入引脚重叠并在引脚重叠处设有一个共用焊盘，且所述3个电阻之中的两个 对称布置于所述两个共用焊盘连线的两侧，并与另一个电阻垂直；所述5个电阻的另外2个电阻与所述输入线路端连接的接入引脚重叠，并在引脚重叠处设有另一个共用焊盘，所述另外2个电阻相互垂直布置。
  9. 根据权利要求6所述的印刷电路板，其中，印刷电路板包括4个共用焊盘，10个电阻连接到同一输入线路端，所述4个共用焊盘共线布置，所述10个电阻具有四个接入引脚重叠处，所述4个共用焊盘分别设于所述四个引脚重叠处；位于所述4个共用焊盘连线两端的每个共用焊盘均连接3个电阻，且所述3个电阻之中的两个对称布置于所述4个共用焊盘连线两侧，并与另一个电阻垂直；位于所述4个共用焊盘连线中间的每个共用焊盘均连接有两个垂直于所述4个共用焊盘连线的电阻。
  10. 根据权利要求6所述的印刷电路板，其中，印刷电路板包括5个共用焊盘，10个电阻连接到同一输入线路端，所述10个电阻的每两个共用一个共用焊盘并对称布置于所述5个共用焊盘连线的两侧。
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CN106455306A (zh) * 2016-11-30 2017-02-22 努比亚技术有限公司 焊盘共用结构、pcb板以及移动终端
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1601739A (zh) * 2003-09-22 2005-03-30 夏普株式会社 焊盘模式结构
CN101193494A (zh) * 2006-11-30 2008-06-04 株式会社东芝 印刷电路板
CN202931666U (zh) * 2012-10-26 2013-05-08 比亚迪股份有限公司 一种印刷电路板及应用其的移动终端

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810512B1 (ko) * 2001-10-31 2008-03-07 삼성전자주식회사 인쇄회로기판
US7667299B2 (en) * 2004-01-27 2010-02-23 Panasonic Corporation Circuit board and method for mounting chip component
KR101046138B1 (ko) * 2009-07-17 2011-07-01 삼성전기주식회사 다층 배선판 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1601739A (zh) * 2003-09-22 2005-03-30 夏普株式会社 焊盘模式结构
CN101193494A (zh) * 2006-11-30 2008-06-04 株式会社东芝 印刷电路板
CN202931666U (zh) * 2012-10-26 2013-05-08 比亚迪股份有限公司 一种印刷电路板及应用其的移动终端

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