WO2016045138A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2016045138A1
WO2016045138A1 PCT/CN2014/087792 CN2014087792W WO2016045138A1 WO 2016045138 A1 WO2016045138 A1 WO 2016045138A1 CN 2014087792 W CN2014087792 W CN 2014087792W WO 2016045138 A1 WO2016045138 A1 WO 2016045138A1
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Prior art keywords
storage capacitor
scan line
pixel electrode
predetermined distance
capacitance value
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PCT/CN2014/087792
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English (en)
French (fr)
Inventor
郑华
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/396,054 priority Critical patent/US9217902B1/en
Publication of WO2016045138A1 publication Critical patent/WO2016045138A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • the liquid crystal display panel has the advantages of excellent color performance, large viewing angle and high contrast, which makes it have broad market prospects.
  • the liquid crystal display panel 11 is typically driven to be displayed by a data driver 12 and a scan driver 13 located therearound.
  • the scan signals of one scan line are respectively input by the scan driver 13 connected to both ends of the scan line to control the opening of the thin film transistor (TFT) connected to the scan line, so that the data driver 12 can pass through the thin film transistor to the liquid crystal display panel 11.
  • the pixel electrode 14 inputs a voltage signal required for displaying a picture to realize display of the liquid crystal display panel 11.
  • the waveform of the scan signal input to the scan line is distorted, that is, the scan signal of the original waveform input from both ends of the scan line is transmitted in the middle of the scan line.
  • the scan signal is gradually reduced by the RC Delay of the scan line, and the scan signal is particularly reduced when transmitted to the scan line of the middle portion, thereby causing the charge rate of the pixel electrode 14 in the middle of the liquid crystal display panel 11 to decrease.
  • the voltage 15 of the pixel electrode 14 in the middle of the liquid crystal display panel 11 is lower than the voltage 16 of the pixel electrode 14 on both sides of the liquid crystal display panel 11, so that the brightness of the intermediate portion of the liquid crystal display panel 11 is lower than the brightness of the side regions of the two sides, that is, The phenomenon that the liquid crystal display panel is "white on both sides” appears, and the uniformity of brightness of the liquid crystal display panel 11 is lowered.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can improve the uniformity of brightness of a screen.
  • a technical solution adopted by the present invention is to provide an array substrate, a scan line, a data line, a thin film transistor, and a storage capacitor; the storage capacitor is formed by a pixel electrode and a common electrode; and the thin film transistor a gate electrode is connected to the scan line, a source of the thin film transistor is connected to the data line, a drain of the thin film transistor is connected to a pixel electrode of the storage capacitor; and the thin film transistor is a horseshoe-shaped structure;
  • the capacitance value of the storage capacitor is gradually increased from the middle of the scan line to the predetermined distance between the two ends of the scan line, and the capacitance values of the storage capacitors in the same predetermined distance are equal, so that the middle of the scan line is corresponding.
  • a capacitance value of the storage capacitor is smaller than a capacitance value corresponding to a storage capacitor at both ends of the scan line to cause a pixel electrode corresponding to a storage capacitor in the middle of the scan line when the voltage line is input to the data line and corresponding to the The voltage difference between the pixel electrodes of the storage capacitors at both ends of the scan line is less than a threshold.
  • the overlapping area between the pixel electrode and the common electrode of the storage capacitor is gradually increased by a predetermined distance from the middle of the scan line to the two ends of the scan line, and the pixel of the storage capacitor within the same predetermined distance
  • the area of overlap between the electrode and the common electrode is equal.
  • the capacitance value of the storage capacitor is sequentially increased by 2% from the middle of the scan line to the predetermined distance between the two ends of the scan line.
  • an array substrate including scan lines, data lines, thin film transistors, and storage capacitors; the storage capacitors are formed by pixel electrodes and common electrodes; a gate of the thin film transistor is connected to the scan line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor is connected to a pixel electrode of the storage capacitor; wherein, in a scan In the storage capacitor corresponding to the line, a capacitance value corresponding to a storage capacitor in the middle of the scan line is smaller than a capacitance value corresponding to a storage capacitor at both ends of the scan line, so as to correspond to the input when the voltage signal is input to the data line A voltage difference between a pixel electrode of a storage capacitor in the middle of the scan line and a pixel electrode corresponding to a storage capacitor at both ends of the scan line is smaller than a threshold.
  • a capacitance value of the storage capacitor is incremented by a predetermined distance from the middle of the scan line to a predetermined distance between the two ends of the scan line, and is stored within the same predetermined distance.
  • the capacitance values of the capacitors are equal.
  • the overlapping area between the pixel electrode and the common electrode of the storage capacitor is gradually increased by a predetermined distance from the middle of the scan line to the two ends of the scan line, and the pixel of the storage capacitor within the same predetermined distance
  • the area of overlap between the electrode and the common electrode is equal.
  • the capacitance value of the storage capacitor is sequentially increased by 2% from the middle of the scan line to the predetermined distance between the two ends of the scan line.
  • a capacitance value of the storage capacitor is sequentially increased from the middle of the scan line to both ends of the scan line.
  • a liquid crystal display panel including an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate;
  • the array substrate includes a scan line, a data line, a thin film transistor, and a storage battery
  • the storage capacitor is formed by a pixel electrode and a common electrode; a gate of the thin film transistor is connected to the scan line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor Connected to the pixel electrode of the storage capacitor; wherein, in a storage capacitor corresponding to one of the scan lines, a capacitance value corresponding to a storage capacitor in the middle of the scan line is smaller than a storage capacitor corresponding to both ends of the scan line And a capacitance value such that a voltage difference between a pixel electrode corresponding to a storage capacitor intermediate the scan line and a pixel electrode corresponding to a storage capacitor at both ends of the scan line when the voltage signal
  • a capacitance value of the storage capacitor is incremented by a predetermined distance from the middle of the scan line to a predetermined distance between the two ends of the scan line, and is stored within the same predetermined distance.
  • the capacitance values of the capacitors are equal.
  • the overlapping area between the pixel electrode and the common electrode of the storage capacitor is gradually increased by a predetermined distance from the middle of the scan line to the two ends of the scan line, and the pixel of the storage capacitor within the same predetermined distance
  • the area of overlap between the electrode and the common electrode is equal.
  • the capacitance value of the storage capacitor is sequentially increased by 2% from the middle of the scan line to the predetermined distance between the two ends of the scan line.
  • a capacitance value of the storage capacitor is sequentially increased from the middle of the scan line to both ends of the scan line.
  • the beneficial effects of the present invention are: different from the prior art, in the array substrate of the present invention, by setting different capacitance values of the storage capacitors corresponding to different positions of the scan lines, so that pixel electrodes corresponding to different positions of the scan lines are arranged
  • the voltage difference is smaller than the threshold value, so that the voltages of the pixel electrodes corresponding to different positions of the scanning lines can be made substantially equal, and the brightness of the display screen corresponding to different positions of the scanning lines is substantially the same, whereby the uniformity of the brightness of the screen can be improved.
  • FIG. 1 is a voltage waveform diagram of a pixel electrode of a liquid crystal display panel in the prior art
  • FIG. 2 is an equivalent circuit diagram of an embodiment of a pixel structure in an array substrate of the present invention
  • FIG. 3 is a schematic diagram showing a charging rate of a pixel electrode in an embodiment of an array substrate of the present invention, wherein a graph showing a charging rate of a pixel electrode of the prior art is shown in the drawing;
  • FIG. 4 is a voltage waveform diagram of a pixel electrode in an embodiment of an array substrate of the present invention, wherein a voltage waveform diagram of a pixel electrode of the prior art is shown in the figure;
  • FIG. 5 is a schematic diagram of dividing an array substrate by a predetermined distance length along a length direction of a scan line in an embodiment of the array substrate of the present invention
  • FIG. 6 is a schematic diagram showing a capacitance change curve of a storage capacitor in an embodiment of the array substrate of the present invention.
  • FIG. 7 is a schematic structural view of a pixel structure corresponding to a middle of a scan line in an embodiment of the array substrate of the present invention.
  • FIG. 8 is a schematic diagram of a pixel structure corresponding to two ends of a scan line in an embodiment of the array substrate of the present invention.
  • FIG. 9 is a schematic diagram showing a capacitance change curve of a storage capacitor in another embodiment of the array substrate of the present invention.
  • FIG. 10 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • FIG. 2 is an equivalent circuit diagram of an embodiment of a pixel structure in an array substrate of the present invention.
  • the array substrate includes a scan line 21, a data line 22, a storage capacitor C, and a thin film transistor Q1.
  • the scan line 21 and the data line 22 cross each other.
  • a memory capacitor C, a thin film transistor Q1, and a scan line 21 and a data line 22 intersecting each other define a pixel structure.
  • the array substrate includes a plurality of matrix-arranged pixel structures.
  • the storage capacitor C is formed by the pixel electrode 23 and the common electrode Com.
  • the gate of the thin film transistor Q1 is connected to the scanning line 21, the source is connected to the data line 22, and the drain is connected to the pixel electrode 23.
  • scan drivers (not shown) at both ends of the scan line 21 respectively input scan signals from the scan lines 21 into the scan lines 21 to control the thin film transistor Q1 to be turned on, and the data lines 22 pass through the thin film.
  • the transistor Q1 inputs a voltage signal required for display to the pixel electrode 23 to charge the storage capacitor C, thereby realizing display of the screen.
  • Each scan line 21 is used to drive a row of pixel electrodes 23, and a scan line 21 and a plurality of data lines 22 cooperate to realize charging of a row of storage capacitors C.
  • One scan line 21 corresponds to one row of storage capacitors C.
  • the capacitance value of the storage capacitor C_a corresponding to the middle of the scanning line 21 is smaller than the capacitance value corresponding to the storage capacitor C_b at both ends of the scanning line 21.
  • the storage capacitor C_a corresponding to the middle of the scan line 21 refers to the storage capacitor C_a connected to the thin film transistor Q1 connected to the scan line 21, and the storage capacitor C_b corresponding to the two ends of the scan line 21 refers to the scan line.
  • the storage capacitor C corresponding to the scan line 21 has the above characteristics.
  • the charging rate of the pixel electrode 23 refers to the ratio of the voltage of the pixel electrode 23 to the voltage of the data line 22. In the ideal case, after the data line 22 charges the pixel electrode 23, the voltage of the pixel electrode 23 should reach the voltage of the data line 22. .
  • the storage capacitor C_a corresponding to the middle of the scan line 21 is only a storage capacitor, but does not mean that the storage capacitor C_a corresponding to the middle of the scan line 21 described in this embodiment refers only to
  • the storage capacitor C_a connected to one of the thin film transistors Q1 connected to the midpoint of the scanning line 21 may be a plurality of storage capacitors C_a corresponding to the scanning line 21 of the intermediate portion where the scanning signal is severely distorted. The same applies to the storage capacitor C_b corresponding to both ends of the scan line.
  • the capacitance values of all the storage capacitors are generally the same, and the scan signal reaching the middle of the scan line is lower than the scan signal at the two ends of the scan line due to the RC Delay of the scan line, that is, the scan signal in the middle of the scan line. More severe distortion occurs, so that after the data line is charged to the pixel electrode, the voltage of the pixel electrode in the middle of the corresponding scan line is much lower than the voltage of the pixel electrode at both ends of the corresponding scan line, causing whitening on both sides.
  • the storage capacitor C_a corresponding to the middle of the scan line 21 has a small value
  • the storage capacitor C_b corresponding to both ends of the scan line 21 has a large value to utilize different capacitance values of the storage capacitors at different positions.
  • Different degrees of distortion of the scanning signals at different positions are dealt with, so that the difference between the charging rates of the pixel electrodes 23 corresponding to different positions of the scanning lines 21 can be made to be reduced, even approaching the same.
  • FIG. 3 is a waveform diagram of charging rates of the pixel electrode of the prior art and the pixel electrode of the present embodiment
  • FIG. 4 is a voltage of the pixel electrode of the prior art and the pixel electrode of the present embodiment.
  • the pixel electrode of the prior art is affected by the RC Delay of the scan signal, and the charging rate of the pixel electrode corresponding to the middle of the scan line is generally only 90%, and the pixel electrode corresponding to both ends of the scan line is especially closest to the scan signal input end.
  • the charging rate of the pixel electrode can reach 100%, as shown by curve a in FIG.
  • the voltage waveforms of the pixel electrodes on both sides and the voltage waveforms of the pixel electrodes in the middle are respectively waveforms e_1 and e_2 shown in FIG. 4, and as can be seen from the waveform diagram, the pixel electrodes on both sides are The voltage is higher than the voltage of the intermediate pixel electrode.
  • the capacitance value of the storage capacitor C_b corresponding to the left and right ends of the scan line 21 is greater than the capacitance corresponding to the storage capacitor C_a in the middle of the scan line 21.
  • the difference in charging rate between the electrode 23 and the pixel electrode 23 corresponding to the storage capacitor C_a in the middle of the scanning line 21, so that the pixel electrode 23 corresponding to the storage capacitor C_a in the middle of the scanning line 21 and the storage capacitor corresponding to both ends of the scanning line can be made
  • the voltage difference between the pixel electrodes 23 of C_b is smaller than the threshold value, that is, the voltage of the pixel electrode 23 corresponding to the storage capacitor C_a in the middle of the scanning line 21 and the voltage of the pixel electrode 23 corresponding to the storage capacitor C_b at both ends of the scanning line can be made approximately equal.
  • the brightness of the screen corresponding to the middle of the scanning line 21 and the brightness of the screen corresponding to both ends of the scanning line 21 can be made substantially the same, so that the uniformity of the brightness of the screen can be improved.
  • the voltage waveform of the pixel electrode 23 corresponding to both ends of the scanning line 21 and the voltage waveform of the pixel electrode 23 corresponding to the middle of the scanning line 21 are waveforms f_1 and f_2 shown in FIG. 4, respectively.
  • the voltage of the pixel electrode 23 on both sides is lower than the voltage of the pixel electrode on both sides of the prior art, which is substantially the same as the voltage of the pixel electrode 23 in the middle.
  • the capacitance value of the storage capacitor C corresponding to different positions of the scan line 21 can be set according to the degree of distortion of the scan signal, that is, the distortion of the corresponding scan signal is slight.
  • the capacitance value of the storage capacitor C_b at both ends of the scan line 21 can be set larger, and the storage capacitor C_a in the middle of the scan line 21 corresponding to the worse distortion of the scan signal can be set smaller, so that the intermediate pixel electrode 23 and both sides can be completely made.
  • the voltage difference between the pixel electrodes 23 on the side is as small as possible, so that the brightness of the intermediate picture and the brightness of the pictures on both sides are similar to each other, so as to improve the uniformity of the brightness of the picture.
  • the difference in the degree of distortion of the scanning signal of the scanning line 21 at different positions is not large, and therefore the difference in charging rate between the plurality of pixel electrodes 23 corresponding to the scanning line 21 is also
  • the predetermined distance d in the present embodiment is the length of the scanning line 21 of which the difference in the degree of distortion of the scanning signal is not large, and the distance length can be set according to the degree of distortion of the scanning signal.
  • the array substrate is divided into 11 regions having a distance length d along the length direction of the scan line 21, the intermediate region 1st is a region corresponding to the middle of the scan line 21, and the storage capacitor C located at the intermediate region 1st is The storage capacitor corresponding to the middle of the scan line 21; the two most side regions 6th, that is, the regions corresponding to the two ends of the scan line 21, the storage capacitors located at the two most side regions 6th are the storage capacitors corresponding to the two ends of the scan line 21.
  • the substrate structures on the left and right sides of the intermediate portion 1st are symmetrically arranged, and therefore only the right side will be described.
  • the capacitance value of the storage capacitor C is gradually increased from the intermediate region 1st to the rightmost region 6th, and the capacitance values of the storage capacitors C in the same region are equal. Therefore, in the present embodiment, the capacitance value of the storage capacitor C located in the intermediate portion 1st is the smallest, and the capacitance value of the storage capacitor C located in the rightmost region 6th is the largest.
  • FIG. 5 only one scanning line 21 corresponding to two storage capacitors C is schematically illustrated as a spacing distance d.
  • the degree of distortion of the scanning signal may correspond to more ( A scan line 21 of the storage capacitor C, such as ten, twenty, etc., is used as a separation distance d.
  • the capacitance value of the storage capacitor C is sequentially increased from the intermediate region 1st to the rightmost region 6th in an equal manner, that is, the storage capacitor C between any two adjacent regions.
  • the difference in capacitance values is equal.
  • the difference between the capacitance values of the storage capacitors C between any two adjacent regions may also be set to be unequal, and the capacitance value of the storage capacitor C in each region may be set according to the distortion of the scan signal. Therefore, the voltages of the pixel electrodes 23 corresponding to the scan lines 21 corresponding to different distortion conditions may be substantially equal, thereby improving the uniformity of the brightness of the screen.
  • the storage capacitor C is specifically formed by the overlapping portion of the pixel electrode 23 and the common electrode Com.
  • the thin film transistor Q1 has a horseshoe-shaped structure, and the common electrode Com is located under the pixel electrode 23.
  • the pixel electrode 23 is a fishbone electrode, and a stem portion of the pixel electrode 23 in the longitudinal direction of the scanning line 21 overlaps with the common electrode Com to form a storage capacitor C.
  • the capacitance value of the storage capacitor C is changed by changing the overlapping area between the pixel electrode 23 and the common electrode Com of the storage capacitor C.
  • the overlapping area between the pixel electrode 23 and the common electrode Com of the storage capacitor C is gradually changed from the middle of the scan line 21 to the predetermined distance d between the two ends of the scan line 21. Incremental, and the overlapping area between the pixel electrode 23 and the common electrode Com of the storage capacitor C within the same predetermined distance d is equal, that is, the overlapping area between the pixel electrode 23 and the common electrode Com of the storage capacitor C is from the intermediate region 1st
  • the two most lateral regions 6th are incremented step by step, and the overlapping area between the pixel electrode 23 and the common electrode Com of the storage capacitor C in the same region is equal.
  • FIG. 7 is a schematic structural diagram of a pixel structure corresponding to the middle of the scanning line 21, wherein the elliptical dotted line portion in the figure is the pixel electrode 23 and the common electrode Com of the storage capacitor C located in the intermediate portion 1st in the present embodiment.
  • FIG. 8 is a schematic structural view of a pixel structure corresponding to both ends of the scanning line 21, wherein the elliptical dotted line in the figure is the pixel electrode 23 and the common electrode of the storage capacitor C located in the most lateral region 6th in the present embodiment.
  • the overlapping area between the pixel electrode 23 and the common electrode Com in the most side region 6th is the largest, and the overlapping area between the pixel electrode 23 and the common electrode Com in the intermediate region 1st is the smallest.
  • the overlapping area of the pixel electrode 23 and the common electrode Com when the overlapping area of the pixel electrode 23 and the common electrode Com is increased, the area of the main portion of the pixel electrode 23 in the longitudinal direction of the scanning line 21 and the area of the common electrode Com are simultaneously increased, thereby increasing the The overlapping area.
  • the overlap area between the pixel electrode 23 and the common electrode Com of the storage capacitor C is increased, and the capacitance value of the storage capacitor C is increased.
  • the overlapping area between the pixel electrode 23 and the common electrode Com of the storage capacitor C is sequentially increased by 2% from the middle of the scanning line 21 to the predetermined distance d between the two ends of the scanning line 21, thereby causing the storage capacitor C
  • the capacitance value is incremented by 2% from the middle of the scan line 21 to the predetermined distance d between the two ends of the scan line 21, as shown in Table 1 below.
  • the capacitance value of the storage capacitor C located in the most side region 6th is increased by 10% as compared with the capacitance value of the storage capacitor C in the intermediate region 1st.
  • the overlapping area between the pixel electrode 23 and the common electrode Com of the storage capacitor C may be increased by 1.5% from the middle of the scanning line 21 to a predetermined distance d between the two ends of the scanning line 21, respectively. %, 5% or 5.5%, etc., specifically, may be selected according to the degree of distortion of the scanning signal at different positions of the scanning line 21, and is not specifically limited herein, as long as the pixel electrode 23 corresponding to the different positions of the scanning line 21 can be made.
  • the charging rate approaches to be equal to improve the uniformity of the brightness of the picture.
  • the pixel electrode may also have other shapes, such as an integral strip electrode. In this case, when changing the overlapping area between the pixel electrode and the common electrode, it is only necessary to change the area of the common electrode. The effective overlap area between the pixel electrode and the common electrode can be changed.
  • the capacitance value of the storage capacitor C can also be changed by changing the distance between the pixel electrode 23 and the common electrode Com, between the pixel electrode 23 and the common electrode Com.
  • the larger the distance the smaller the capacitance value of the storage capacitor C.
  • the smaller the distance between the pixel electrode 23 and the common electrode Com the larger the capacitance value of the storage capacitor C.
  • the capacitance value of the storage capacitor C is stepwisely increased from the middle of the scanning line 21 to the scanning line 21, and the capacitance values of the storage capacitors C in the same region are the same.
  • the capacitance value of the storage capacitor may also be sequentially increased from the middle of the scan line to the ends of the scan line, and may be equal tolerance. The manners are sequentially increased, and may be increased in other manners.
  • the capacitance values between two adjacent storage capacitors are different, and the difference between the capacitance values of any two adjacent storage capacitors may be The same may be different, and the specific setting may be set according to the distortion of the scanning signal as long as the difference in the charging rate between the pixel electrodes corresponding to different positions of the scanning line can be reduced.
  • the storage capacitor in the middle of the corresponding scan line refers to the storage capacitor connected to a thin film transistor connected to the midpoint of the scan line, and the thin film transistors at the opposite ends of the scan line are respectively connected to the two ends of the scan line.
  • the liquid crystal display panel includes an array substrate 31 , a color filter substrate 32 , and a liquid crystal layer 33 between the array substrate 31 and the color filter substrate 32 .
  • the array substrate 31 is the array substrate of any of the above embodiments.

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Abstract

一种阵列基板及液晶显示面板，所述阵列基板中，与一条扫描线（21）连接的薄膜晶体管（Q1）中，对应于所述扫描线（21）中间的存储电容的电容值小于对应于所述扫描线（21）两端的存储电容的电容值，以在数据线（22）输入电压信号时使得对应于所述扫描线（21）中间的存储电容的像素电极（23）和对应于所述扫描线（21）两端的存储电容的像素电极（23）之间的电压差小于阈值。通过上述方式，能够提高画面亮度的均匀性。

Description

阵列基板及液晶显示面板 【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
液晶显示面板具有色彩表现优异、可视角度大、对比度高等优点，使得其具有广阔的市场前景。
如图1所示，液晶显示面板11通常由位于其周围的数据驱动器12和扫描驱动器13驱动显示。一条扫描线的扫描信号分别由与扫描线两端连接的扫描驱动器13输入，以控制与该条扫描线连接的薄膜晶体管(TFT)打开，从而数据驱动器12可通过薄膜晶体管对液晶显示面板11的像素电极14输入显示画面所需的电压信号，以实现液晶显示面板11的显示。
然而，由于扫描线的信号的阻容延迟(RC Delay)，导致输入至扫描线的扫描信号波形发生失真，即从扫描线两端输入的原本波形正常的扫描信号在向扫描线的中间传输时，受扫描线的RC Delay影响，扫描信号会逐渐减小，在传输到中间部分的扫描线时扫描信号的减小程度尤为严重，从而导致液晶显示面板11中间的像素电极14的充电率降低，使得液晶显示面板11中间的像素电极14的电压15低于液晶显示面板11两侧边的像素电极14的电压16，造成液晶显示面板11的中间区域的亮度低于两侧边区域的亮度，即出现液晶显示面板“两侧发白”的现象，降低液晶显示面板11亮度的均匀性。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够提高画面亮度的均匀性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，扫描线、数据线、薄膜晶体管以及存储电容；所述存储电容由像素电极和公共电极所形成；所述薄膜晶体管的栅极与所述扫描线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述存储电容的像素电极连接；所述薄膜晶体管为马蹄形结构；其中，在一条所述扫描线所对应的存储电容中， 存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的电容值相等，以使得对应于所述扫描线中间的存储电容的电容值小于对应于所述扫描线两端的存储电容的电容值，以在所述数据线输入电压信号时使得对应于所述扫描线中间的存储电容的像素电极和对应于所述扫描线两端的存储电容的像素电极之间的电压差小于阈值。
其中，所述存储电容的像素电极和公共电极之间的重叠面积由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的像素电极和公共电极之间的重叠面积相等。
其中，所述存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离依次递增2％。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括扫描线、数据线、薄膜晶体管以及存储电容；所述存储电容由像素电极和公共电极所形成；所述薄膜晶体管的栅极与所述扫描线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述存储电容的像素电极连接；其中，在一条所述扫描线所对应的存储电容中，对应于所述扫描线中间的存储电容的电容值小于对应于所述扫描线两端的存储电容的电容值，以在所述数据线输入电压信号时使得对应于所述扫描线中间的存储电容的像素电极和对应于所述扫描线两端的存储电容的像素电极之间的电压差小于阈值。
其中，在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的电容值相等。
其中，所述存储电容的像素电极和公共电极之间的重叠面积由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的像素电极和公共电极之间的重叠面积相等。
其中，所述存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离依次递增2％。
其中，在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线中间至所述扫描线两端依次递增。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括阵列基板、彩色滤光基板及位于所述阵列基板和所述彩色滤光基板之间的液晶层；所述阵列基板包括扫描线、数据线、薄膜晶体管以及存储电 容；所述存储电容由像素电极和公共电极所形成；所述薄膜晶体管的栅极与所述扫描线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述存储电容的像素电极连接；其中，在一条所述扫描线所对应的存储电容中，对应于所述扫描线中间的存储电容的电容值小于对应于所述扫描线两端的存储电容的电容值，以在所述数据线输入电压信号时使得对应于所述扫描线中间的存储电容的像素电极和对应于所述扫描线两端的存储电容的像素电极之间的电压差小于阈值。
其中，在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的电容值相等。
其中，所述存储电容的像素电极和公共电极之间的重叠面积由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的像素电极和公共电极之间的重叠面积相等。
其中，所述存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离依次递增2％。
其中，在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线中间至所述扫描线两端依次递增。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板中，通过设置对应于扫描线不同位置的存储电容的不同电容值，使得对应于扫描线不同位置的像素电极之间的电压差小于阈值，从而可以使得对应于扫描线不同位置的像素电极的电压大致相等，进而使得对应于扫描线不同位置的显示画面的亮度大致相同，由此能够提高画面亮度的均匀性。
【附图说明】
图1是现有技术中一种液晶显示面板的像素电极的电压波形图；
图2是本发明阵列基板中像素结构一实施方式的等效电路图；
图3是本发明阵列基板一实施方式中，像素电极的充电率的曲线示意图，其中，图中示出了现有技术的像素电极的充电率的曲线图；
图4是本发明阵列基板一实施方式中，像素电极的电压波形图，其中，图中示出了现有技术的像素电极的电压波形图；
图5是本发明阵列基板一实施方式中，沿扫描线的长度方向以预定距离长度对阵列基板进行划分区域的示意图；
图6是本发明阵列基板一实施方式中，存储电容的电容值变化曲线示意图；
图7是本发明阵列基板一实施方式中，对应扫描线中间的像素结构的结构示意图；
图8是本发明阵列基板一实施方式中，对应扫描线两端的像素结构示意图；
图9是本发明阵列基板另一实施方式中，存储电容的电容值变化曲线示意图；
图10是本发明液晶显示面板一实施方式的结构示意图。
【具体实施方式】
下面将通过附图和实施方式对本发明进行详细说明。
参阅图2，图2是本发明阵列基板中像素结构一实施方式的等效电路图。阵列基板包括扫描线21、数据线22、存储电容C以及薄膜晶体管Q1。扫描线21和数据线22相互交叉，由一个存储电容C、一个薄膜晶体管Q1和相互交叉的一条扫描线21、一条数据线22共同定义一个像素结构，阵列基板包括多个矩阵排列的像素结构。其中，存储电容C由像素电极23和公共电极Com所形成。
薄膜晶体管Q1的栅极和扫描线21连接，源极和数据线22连接，漏极和像素电极23连接。在驱动像素电极23以实现画面显示时，扫描线21两端的扫描驱动器(图未示)分别自扫描线21两端输入扫描信号至扫描线21中以控制薄膜晶体管Q1打开，数据线22通过薄膜晶体管Q1对像素电极23输入显示所需的电压信号，以对存储电容C进行充电，由此实现画面的显示。
每条扫描线21用于驱动一行像素电极23，通过一条扫描线21和多条数据线22的共同作用，以实现对一行存储电容C的充电，一条扫描线21对应一行存储电容C。其中，在与一条扫描线21所对应的存储电容C中，对应于扫描线21中间的存储电容C_a的电容值小于对应于扫描线21两端的存储电容C_b的电容值。所述对应于扫描线21中间的存储电容C_a即是指与扫描线21中间连接的薄膜晶体管Q1所连接的存储电容C_a，所述对应于扫描线21两端的存储电容C_b即是指与扫描线21两端连接的薄膜晶体管Q1_b所连接的存储电容C_a。在此，仅是以一条扫描线21所对应的一行存储电容C为例进行说明，其 他扫描线21对应的存储电容C均具有上述特征。
存储电容C越大，像素电极23越难以充电达到饱和状态(即数据线22的电压)，使得像素电极23的充电率越低；反之，存储电容C越小，像素电极23越容易达到饱和状态，使得像素电极23的充电率也就越高。像素电极23的充电率是指像素电极23的电压和数据线22的电压的比值，在理想情况下，在数据线22对像素电极23充电后，像素电极23的电压应达到数据线22的电压。
需要说明的是，在图2中，对应于扫描线21中间的存储电容C_a仅是标示一个存储电容，但是并不代表本实施方式所述的对应于扫描线21中间的存储电容C_a仅是指代与扫描线21中点连接的一个薄膜晶体管Q1所连接的存储电容C_a，可以是指代与扫描信号失真较严重的中间部分的扫描线21所对应的多个存储电容C_a。而对应于扫描线两端的存储电容C_b同理亦然。
现有技术中，所有存储电容的电容值通常都是相同的，而由于扫描线的RC Delay，导致到达扫描线中间的扫描信号较低于扫描线两端的扫描信号，即扫描线中间的扫描信号发生较严重的失真，使得在数据线对像素电极完成充电后，对应扫描线中间的像素电极的电压远低于对应扫描线两端的像素电极的电压，造成两侧边发白的现象。扫描信号越小像素电极的充电率越低，而存储电容的电容值越小，像素电极的充电率越高。本实施方式中，使对应于扫描线21中间的存储电容C_a具有较小值，并使对应于扫描线21两端的存储电容C_b具有较大值，以利用不同位置的存储电容的不同电容值来应对不同位置的扫描信号的不同失真程度，从而可以使得对应于扫描线21不同位置的像素电极23的充电率之间的差异减小，甚至趋近于相同。
例如，参阅图3和图4，图3是现有技术的像素电极和本实施方式的像素电极的充电率的波形图，图4是现有技术的像素电极和本实施方式的像素电极的电压波形图，其中，图4中仅示出两侧边和中间区域的像素电极的电压波形。现有技术的像素电极，受扫描信号的RC Delay的影响，对应于扫描线中间的像素电极的充电率一般仅为90％，而对应于扫描线两端的像素电极尤其是最靠近扫描信号输入端的像素电极的充电率可以达到100％，如图3所示的曲线a。而现有技术中，两侧边的像素电极的电压波形和中间的像素电极的电压波形则分别为图4所示的波形e_1、e_2，由该波形图可看出，两侧边像素电极的电压较高于中间像素电极的电压。而本发明实施方式中，通过使对应于扫描线21左右两端的存储电容C_b的电容值大于对应于扫描线21中间的存储电容C_a的电容 值，从而可以降低与对应于扫描线21左右两端的存储电容C_b的像素电极23的充电率，如图3所示的曲线b，以减小对应于扫描线21左右两端的存储电容C_b的像素电极23和对应于扫描线21中间的存储电容C_a的像素电极23之间充电率的差异，从而可以使得对应于扫描线21中间的存储电容C_a的像素电极23和对应于扫描线两端的存储电容C_b的像素电极23之间的电压差小于阈值，即可以使得对应于扫描线21中间的存储电容C_a的像素电极23的电压和对应于扫描线两端的存储电容C_b的像素电极23的电压大约相等，由此在显示画面时，可以使得对应于扫描线21中间的画面亮度和对应于扫描线21两端的画面亮度大致相同，从而能够提高画面亮度的均匀性。而本发明实施方式中，对应于扫描线21两端的像素电极23的电压波形和对应于扫描线21中间的像素电极23的电压波形则分别为图4所示的波形f_1、f_2，由该电压波形可看出，两侧边的像素电极23的电压较低于现有技术的两侧边的像素电极的电压，其与中间的像素电极23的电压大致相同。
在实际应用中，受制造工艺等因素的影响，有可能难以使得对应于扫描线21中间的存储电容C_a的像素电极23的电压和对应于扫描线21两端的存储电容C_b的像素电极23的电压完全相等。本领域技术人员可以理解的是，根据本发明实施方式所提供的方案，可以根据扫描信号的失真程度来设置对应于扫描线21不同位置的存储电容C的电容值，即对应扫描信号失真轻微的扫描线21两端的存储电容C_b的电容值可以设置得较大，对应扫描信号失真较严重的扫描线21中间的存储电容C_a可以设置得较小，从而完全可以使得中间的像素电极23和两侧边的像素电极23之间的电压差尽可能地小，进而使得中间画面的亮度和两侧边画面的亮度趋近于相同，以提高画面亮度的均匀性。
越远离信号输入端扫描信号失真越严重。为了进一步提高画面亮度的均匀性，在本发明阵列基板的一实施方式中，如图5所示，在与一条扫描线21对应的所有存储电容C中，即一条扫描线21所驱动的所有像素电极23所形成的存储电容C，存储电容C的电容值由扫描线21中间至扫描线21两端每间隔预定距离d逐级递增，在同一预定距离d内的存储电容C的电容值相等。通常在扫描线21的一小段范围内，不同位置的扫描线21其扫描信号的失真程度差异并不大，因此与这一段扫描线21对应的多个像素电极23之间的充电率差异也并不大，本实施方式所述的预定距离d即为扫描信号失真程度差异不大的这一段扫描线21的长度，可以根据扫描信号的失真程度设置该距离长度。
例如，根据扫描信号的失真程度将阵列基板沿扫描线21的长度方向均分成距离长度为d的11个区域，中间区域1st即对应扫描线21中间的区域，位于中间区域1st的存储电容C即为对应于扫描线21中间的存储电容；两最侧边区域6th即对应扫描线21两端的区域，位于两最侧边区域6th的存储电容即为对应扫描线21两端的存储电容。其中，中间区域1st的左右两边的基板结构对称设置，因此仅以右边进行说明。因此，在一条扫描线21所对应的所有存储电容C中，存储电容C的电容值由中间区域1st至最右侧区域6th逐级递增，在同一个区域中的存储电容C的电容值相等。因此，本实施方式中，位于中间区域1st的存储电容C的电容值最小，位于最右侧区域6th的存储电容C的电容值最大。
其中，图5中仅是示意性地示出以对应两个存储电容C的一段扫描线21作为一个间隔距离d，在其他实施方式中，可以根据扫描信号的失真程度将对应于更多个(如十个、二十个等)存储电容C的一段扫描线21作为一个间隔距离d。
此外，本实施方式中，如图6所示，存储电容C的电容值由中间区域1st至最右侧区域6th以等差方式依次递增，即任意两个相邻区域之间的存储电容C的电容值的差值相等。当然，其他实施方式中，任意两个相邻区域之间的存储电容C的电容值的差值也可以设置为不相等，可以根据扫描信号的失真情况设置各个区域中的存储电容C的电容值，以使得对应不同失真情况的扫描线21所对应的像素电极23的电压大致相等即可，从而以提高画面亮度的均匀性。
存储电容C具体由像素电极23和公共电极Com的重叠部分所形成，像素电极23和公共电极Com之间的重叠面积越大，存储电容C的电容值越大，反之越小。参阅图7，在本发明阵列基板的实施方式中，薄膜晶体管Q1为马蹄形结构，公共电极Com位于像素电极23的下层。像素电极23为鱼骨状电极，像素电极23中在扫描线21的长度方向的主干部分与公共电极Com重叠以形成存储电容C。通过改变存储电容C的像素电极23和公共电极Com之间的重叠面积来改变存储电容C的电容值。
具体地，在一条扫描线21对应的所有存储电容C中，存储电容C的像素电极23和公共电极Com之间的重叠面积由扫描线21中间至扫描线21两端每间隔预定距离d逐级递增，而在同一预定距离d内的存储电容C的像素电极23和公共电极Com之间的重叠面积相等，也即存储电容C的像素电极23和公共电极Com之间的重叠面积由中间区域1st至两最侧边区域6th逐级递增，在同一区域内的存储电容C的像素电极23和公共电极Com之间的重叠面积相等。如图7 和图8所示，图7为对应扫描线21中间的像素结构的结构示意图，其中图中椭圆虚线部分为本实施方式中位于中间区域1st中的存储电容C的像素电极23和公共电极Com之间的重叠区域；图8为对应扫描线21两端的像素结构的结构示意图，其中图中椭圆虚线部分为本实施方式中位于最侧边区域6th中的存储电容C的像素电极23和公共电极Com之间的重叠区域。最侧边区域6th中的像素电极23和公共电极Com之间的重叠面积最大，中间区域1st中的像素电极23和公共电极Com之间的重叠面积最小。
其中，在增大像素电极23和公共电极Com的重叠面积时，同时增大像素电极23中在扫描线21的长度方向的主干部分的面积和公共电极Com的面积，从而增大两者之间的重叠面积。
存储电容C的像素电极23和公共电极Com之间的重叠面积增大了多少，存储电容C的电容值即增大了多少。在本发明实施方式中，存储电容C的像素电极23和公共电极Com之间的重叠面积由扫描线21中间至扫描线21两端每间隔预定距离d依次增大2％，从而使得存储电容C的电容值自扫描线由扫描线21中间至扫描线21两端每间隔预定距离d依次递增2％，如下表1所示，
Figure PCTCN2014087792-appb-000001
表1 阵列基板右侧各区域存储电容的电容值增大百分比
因此，位于最侧边区域6th中的存储电容C的电容值相较于中间区域1st内的存储电容C的电容值而言，增大了10％。
当然，在其他实施方式中，也可以使存储电容C的像素电极23和公共电极Com之间的重叠面积由扫描线21中间至扫描线21两端每间隔预定距离d依次增大1.5％、3％、5％或5.5％等，具体地可根据扫描信号在扫描线21的不同位置的失真程度进行选择，此处不进行具体限定，只要能够使得对应于扫描线21不同位置的像素电极23的充电率趋近于相等即可，以提高画面亮度的均匀性。此外，在其他实施方式中，像素电极也可以是其他的形状，例如为整体的条状电极，此时，在改变像素电极和公共电极之间的重叠面积时，只需改变公共电极的面积即可改变像素电极和公共电极之间的有效重叠面积。
上述实施方式中，通过改变像素电极23和公共电极Com之间的重叠面积 来改变存储电容C的电容值大小，在其他实施方式中，也可以通过改变像素电极23和公共电极Com之间的距离来改变存储电容C的电容值大小，像素电极23和公共电极Com之间的距离越大，存储电容C的电容值越小，反之，像素电极23和公共电极Com之间的距离越小，存储电容C的电容值越大。
另外，在上述各实施方式中，存储电容C的电容值由扫描线21中间至扫描线21两端呈阶梯状逐级递增，其在同一区域中的存储电容C的电容值是相同的。在本发明的其他实施方式中，如图9所示，在一条扫描线对应的存储电容中，存储电容的电容值也可以是由扫描线中间至扫描线两端依次递增，可以是以等公差方式依次递增，也可以是以其他方式增加，即本实施方式中，相邻两个存储电容之间的电容值不相同，而任意两个相邻的存储电容的电容值之间的差值可以相同也可以不相同，具体的可以根据扫描信号的失真情况进行设定，只要能够使得对应于扫描线不同位置的像素电极之间的充电率的差异减小即可。其中，本实施方式中，对应扫描线中间的存储电容是指与扫描线中点连接的一个薄膜晶体管所连接的存储电容，而对应扫描线两端的薄膜晶体管是指分别与扫描线两个端连接的最侧边的一个薄膜晶体管所连接的存储电容。
参阅图10，本发明液晶显示面板一实施方式中，液晶显示面板包括阵列基板31、彩色滤光基板32以及位于阵列基板31和彩色滤光基板32之间的液晶层33。其中，阵列基板31为上述任一实施方式的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板，其中，包括扫描线、数据线、薄膜晶体管以及存储电容；
    所述存储电容由像素电极和公共电极所形成；
    所述薄膜晶体管的栅极与所述扫描线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述存储电容的像素电极连接；所述薄膜晶体管为马蹄形结构；
    其中，在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的电容值相等，以使得对应于所述扫描线中间的存储电容的电容值小于对应于所述扫描线两端的存储电容的电容值，以在所述数据线输入电压信号时使得对应于所述扫描线中间的存储电容的像素电极和对应于所述扫描线两端的存储电容的像素电极之间的电压差小于阈值。
  2. 根据权利要求1所述的阵列基板，其中，
    所述存储电容的像素电极和公共电极之间的重叠面积由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的像素电极和公共电极之间的重叠面积相等。
  3. 根据权利要求2所述的阵列基板，其中，
    所述存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离依次递增2％。
  4. 一种阵列基板，其中，包括扫描线、数据线、薄膜晶体管以及存储电容；
    所述存储电容由像素电极和公共电极所形成；
    所述薄膜晶体管的栅极与所述扫描线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述存储电容的像素电极连接；
    其中，在一条所述扫描线所对应的存储电容中，对应于所述扫描线中间的存储电容的电容值小于对应于所述扫描线两端的存储电容的电容值，以在所述数据线输入电压信号时使得对应于所述扫描线中间的存储电容的像素电极和对应于所述扫描线两端的存储电容的像素电极之间的电压差小于阈值。
  5. 根据权利要求4所述的阵列基板，其中，
    在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线 中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的电容值相等。
  6. 根据权利要求5所述的阵列基板，其中，
    所述存储电容的像素电极和公共电极之间的重叠面积由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的像素电极和公共电极之间的重叠面积相等。
  7. 根据权利要求5所述的阵列基板，其中，
    所述存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离依次递增2％。
  8. 根据权利要求4所述的阵列基板，其中，
    在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线中间至所述扫描线两端依次递增。
  9. 一种液晶显示面板，其中，包括阵列基板、彩色滤光基板及位于所述阵列基板和所述彩色滤光基板之间的液晶层；
    所述阵列基板包括扫描线、数据线、薄膜晶体管以及存储电容；
    所述存储电容由像素电极和公共电极所形成；
    所述薄膜晶体管的栅极与所述扫描线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述存储电容的像素电极连接；
    其中，在一条所述扫描线所对应的存储电容中，对应于所述扫描线中间的存储电容的电容值小于对应于所述扫描线两端的存储电容的电容值，以在所述数据线输入电压信号时使得对应于所述扫描线中间的存储电容的像素电极和对应于所述扫描线两端的存储电容的像素电极之间的电压差小于阈值。
  10. 根据权利要求9所述的液晶显示面板，其中，
    在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的电容值相等。
  11. 根据权利要求10所述的液晶显示面板，其中，
    所述存储电容的像素电极和公共电极之间的重叠面积由所述扫描线中间至所述扫描线两端每间隔预定距离逐级递增，在同一所述预定距离内的存储电容的像素电极和公共电极之间的重叠面积相等。
  12. 根据权利要求10所述的液晶显示面板，其中，
    所述存储电容的电容值由所述扫描线中间至所述扫描线两端每间隔预定距离依次递增2％。
  13. 根据权利要求9所述的液晶显示面板，其中，
    在一条所述扫描线所对应的存储电容中，存储电容的电容值由所述扫描线中间至所述扫描线两端依次递增。
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