WO2016044878A1 - Agencement de gradateur à commande par découpage de phase comprenant une protection contre les surtensions et les transitoires électriques rapides - Google Patents

Agencement de gradateur à commande par découpage de phase comprenant une protection contre les surtensions et les transitoires électriques rapides Download PDF

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Publication number
WO2016044878A1
WO2016044878A1 PCT/AU2015/000582 AU2015000582W WO2016044878A1 WO 2016044878 A1 WO2016044878 A1 WO 2016044878A1 AU 2015000582 W AU2015000582 W AU 2015000582W WO 2016044878 A1 WO2016044878 A1 WO 2016044878A1
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WO
WIPO (PCT)
Prior art keywords
arrangement
voltage
capacitor
fets
igbts
Prior art date
Application number
PCT/AU2015/000582
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English (en)
Inventor
Paul Bourne
Original Assignee
Hendon Semiconductors Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2014903838A external-priority patent/AU2014903838A0/en
Application filed by Hendon Semiconductors Pty Ltd filed Critical Hendon Semiconductors Pty Ltd
Priority to AU2015321410A priority Critical patent/AU2015321410B2/en
Priority to NZ731291A priority patent/NZ731291A/en
Publication of WO2016044878A1 publication Critical patent/WO2016044878A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B39/00—Circuit arrangements or apparatus for operating incandescent light sources
    • H05B39/04—Controlling

Definitions

  • This invention relates to a phase cutting control dimmer arrangement that includes surge voltage and electrical fast transient protection.
  • this invention relates to a unique surge voltage and electrical fast transient protection system for a phase cutting control dimmer arrangement that includes components that can inherently utilise the developed voltages during a surge voltage and EFT events to instigate the protection without influencing the normal switching operation of the solid states switches.
  • Phase cutting control dimmer arrangements operate by switching AC mains supply to a lamp or light load for only a chosen time portion of each AC mains supply half cycle.
  • Two wire trailing edge dimmers also referred to as reversed phase control dimmers, remove power from the end or trailing edge of each AC mains supply half cycle.
  • the time period for the AC mains supply as applied to the load is determined conventionally by an analogue or digital timer, controlling the load switching device, that must be started and stopped at exact times during each AC mains supply half cycle.
  • the two terminals that being the active terminal and the load terminal, are wired in series with the load and the time at which the timer is started and stopped, once again for the most part is derived from the processing of the voltage that appears across each of the active and load dimmer voltage terminals.
  • Solid state switching devices such as field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs), in these kinds of dimmer arrangements provide the load current switching.
  • FETs field effect transistors
  • IGBTs insulated gate bipolar transistors
  • the dimmer arrangement requires to be configured so as to protect these solid state switching devices against these kinds of events without effecting the operational integrity of the solid state switching devices.
  • the solid state switching devices can be protected during voltage surges provided that the solid state switching devices are turned on during the voltage surge event so that the applied surge voltage and its associated energy will be shared minimally by the solid state switching devices and for the most part by the lamp under the control of the dimmer arrangement. It is to be expected that if the solid state switching devices can be promptly turned on when a voltage surge is recognised at either of the active or load terminals the energy of the surge voltage can be absorbed within the load and then the residual part of the surge voltage energy absorbed by the solid state switching devices being small enough so that the voltage surge event is non-destructive upon the operational ongoing integrity of the solid state switching devices.
  • MOVs metal oxide varistors
  • MOVs are adapted to protect the solid state switching devices even if the dimmer is switched to an 'off' or low power standby during the voltage surge event.
  • MOVs provide componentry that can be introduced into the dimmer arrangement to handle the effects of a voltage surge, MOVs are also inherently susceptible to malfunction and destruction when
  • MOVs present an unacceptable risk to the safety of the dimmer arrangement in that while the MOVs may in some circumstances provide appropriate protection against generated voltage surges within the dimmer arrangement, if the voltage surge is prolonged, uninterrupted and/or repetitive, which is often a requirement during regulatory testing to determine whether or not a dimmer arrangement can handle voltage surges and/or short duration electrical transients, the effects of the voltage surge to be handled by the MOVs could potentially exceed the safe operating conditions for the MOV overloading it causing it to catch fire which would be completely unacceptable.
  • EFTs electrical fast transients
  • EFTs characterised from a voltage surge event. While these EFTs events are unlikely to contain enough energy to directly destroy the solid state switching devices switching current to the load in the phase cutting control dimmer arrangement, EFTs can cause consequential destruction and malfunctioning of operation if it results in the operation of switching the AC mains supply to the lamp in an uncontrolled way inconsistent with the chosen time portion of each AC mains supply half cycle.
  • AC mains supply voltage rated capacitors could potentially allow current up to 15 mA to flow through the load even when the solid state switching devices are turned “off” thereby making such capacitors unsuitable for use as a protection means against EFTs if no illuminating visible light is to be observable from the lamp under the control of the dimmer when the solid state switching devices have switched the current "off" to the load.
  • EFT electrical fast transients
  • FTBs fast transient bursts
  • EFTs electrical fast transient bursts
  • phase cutting control dimmer arrangement with a surge voltage and electrical fast transient (EFT) protection said arrangement including:
  • a load control arrangement including back-to-back field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs) with connected gates;
  • FETs back-to-back field effect transistors
  • IGBTs insulated gate bipolar transistors
  • a primary EFT shunt capacitor located across an active terminal and a load terminal wherein a first plate of said primary EFT shunt capacitor is in electrically operable communication with a drain of a first FET or IGBT of said back-to-back FETs or IGBTs, and wherein a second plate of said primary EFT shunt capacitor is in electrically operable communication with a drain of a second FET or IGBT of said back-to-back FETs or IGBTs, said primary EFT shunt capacitor valued to provide a low reactive impedance at EFT frequencies such that EFT voltages are shuntable across a lamp under control of the phase cutting control dimmer arrangement without electrically interfering with either connected gates of the back-to-back FETs or IGBTs, and wherein said primary EFT shunt capacitor is valued to provide high impedance at AC mains supply frequency so as to provide a minimal current through the active terminal and the load terminal when the phase cutting control dimmer arrangement is "off
  • a surge voltage event at the active terminal or load terminal provides a surge current into the respective first capacitor or second capacitor establishing a threshold voltage across said current sensing resistor, wherein said threshold voltage across said current sensing resistor is adapted to charge a gate drive capacitor, wherein said gate drive capacitor is adapted to provide a voltage for duration of the surge voltage event to the connected gates of the back-to-back FETs or IGBTs, thereby turning the back-to-back FETs or IGBTs "on" during the surge voltage event.
  • the current sensing resistor is in parallel with a secondary EFT shunt capacitor, wherein the secondary EFT shunt capacitor is valued with a reactive impedance lower than the current sensing resistor such that the threshold voltage is not reached across the current sensing resistor during an EFT event.
  • the primary EFT shunt capacitor along with the EFT bypass capacitor across the sensing resistor that also serves as a secondary EFT shunt capacitor.
  • the primary EFT shunt capacitor as introduced above is connected directly across the Active and Load terminals to bypass most of the EFT.
  • the two voltage surge sensing first and second capacitors may have a reactance similar to the primary EFT shunt capacitor and therefore will conduct EFT currents possibly comparable in magnitude with those in the primary EFT shunt capacitor.
  • the current sensing resistor is valued such that an AC mains supply voltage on the active terminal or the load terminal provides an insufficient rise in voltage for current flowing into the first capacitor or second capacitor to establish a threshold voltage across said current sensing resistor.
  • the arrangement further includes a zener diode in electrically operable communication with both the gate drive capacitor and the connected gates of the back-to-back FETs or IGBTs wherein the zener diode is valued and configured within the dimmer arrangement to limit the amplitude of the voltage of the gate drive capacitor below the rated maximum tolerance level upon the connected gates of the FETs or IGBTs.
  • the arrangement provides for a fast acting means to turn on the FETs or IGBTs during high voltage surges the kinds of which are often specified in regulatory standards.
  • Such standards may require multiple application of test voltages being applied to the active terminal or load terminal that are in series with the lamp load under control of the dimmer arrangement, wherein these voltages for test purposes exceed the voltage rating of the FETs or IGBTs incorporated within the dimmer arrangement.
  • Applied voltages used in voltage surge testing may range up from 500V.
  • the protection provided for by the surge voltage gate arrangement of this invention provides its voltages for operation from the applied voltage surge itself thereby protection is afforded to the driver arrangement whether the dimmer arrangement is operational or in the "off' or standby mode. As is to be expected when the dimmer arrangement is in the "off' or standby mode its general power supply will not be available.
  • the dimmer control arrangement includes an overcurrent protection arrangement adapted to provide a means to turn 'off the FETs or IGBTs if the load under the control of the dimmer arrangement becomes short circuit and/or overcurrent within the dimmer arrangement severely exceeds safe operating conditions.
  • the over-current protection arrangement is active and includes a transistor adapted to switch the connected gates of the back-to-back FETs or IGBTs to zero volts when an over-current event has been detected.
  • the primary EFT shunt capacitor has a value less than 4.7 nF.
  • the primary EFT shunt capacitor has a value of about 2.2 nF.
  • the surge voltage gate drive arrangement includes an active transistor connected to an operational gate drive path to the connected gates of the FETs or IGBTs to which the over-current protection arrangement in part controls said operational gate drive path to the connected gates of the FETs or IGBTs, such that during a voltage surge event the over-current protection arrangement is overridden so that the gate drive capacitor remains enabled to maintain voltage for the duration of the voltage surge event to the connected gates of the FETs or IGBTs thereby keeping the FETs or IGBTs on, although an over-current event has been detected by the over-current protection arrangement.
  • the dimmer arrangement over-current protection arrangement will be activated if the dimmer arrangement is in its normal operation mode when a voltage surge event, such as during testing takes place.
  • the active transistor in the over-current protection arrangement will try and remove the gate drive from the connected gates of the back-to-back FETs or IGBTs by shorting the connected gates to a zero volt reference rail thereby effectively shorting the connected gates of the FETs or IGBTs to their respective sources.
  • the surge voltage gate drive arrangement of this invention is able to over-ride the over-current protection arrangement trying to switch the connected gates of the FETs and IGBTs to zero volts thereby potentially turning the FETs or IGBTs Off' which would be completely counter-productive in a voltage surge event wherein the FETs or IGBTs must be kept "on” so that the voltage across them can be kept relatively low so that much of the surged voltage and energy can be dissipated across the lamp or load under the control of the dimmer arrangement rather than the FETs or IGBTs themselves.
  • the voltage applied in testing a dimmer arrangement's immunity to EFTs have extremely fast rise times, about 1 kV in 5 nanoseconds, of particularly short duration.
  • the EFTs are applied from a source with a relatively high 50 ohm impedance as compared to a 1 ohm for a voltage surge testing event.
  • EFTs signals will be shunted by the primary EFT shunt capacitor which is valued and adapted to provide low reactance impedance at EFT frequencies such that the EFT voltage and associated pulses are shunted across the lamp or load under the control of the dimmer arrangement without then operatively electrically interfering with either of the connected gates of the back-to-back FETs or IGBTs.
  • the primary EFT shunt capacitor is also valued and adapted so as to provide high impedance at AC mains supply frequency so as to provide a minimal current through the active and load terminals when the dimmer arrangement is in the 'off' or standby mode such that no visible light is observable from the lamp under the control of the dimmer arrangement.
  • the secondary EFT shunt capacitor allows the dimmer arrangement to recognise the differences between a surge voltage event and an EFT event wherein the switching state of the back-to-back FETs or IGBTs will have opposite
  • the drive to the interconnected gates of the back-to- back FETs or IGBTs must be such to turn the FETs or IGBTs On' so that the voltage across these solid state devices can be relatively low with most of the voltage surge energy appearing across the load under the control of the dimmer arrangement.
  • the secondary EFT shunt capacitor will prevent any recognizable build-up of the threshold voltage required upon the current sensing resistor which would adversely or at least unnecessarily for an EFT event start charging the surge voltage gate drive capacitor that provides the voltage to the connected gates of the FETs or IGBTs to turn them On'.
  • the current sensing resistor is also valued such that the AC mains supply voltage on the active terminal and load terminal, when switched mid-cycle by the FETs during normal operation of the dimmer and generally having edge rates about 7V per microsecond, will provide an insufficient rate of rise in voltage for current flowing into the respective first and second capacitance to establish a threshold voltage across the current sensing resistor.
  • the dimmer arrangement therefore is able to discriminate between general operation of switching AC mains supply to the lamp or light for that chosen time portion of each AC mains supply half cycle. Therefore surge voltage and EFT protection can be incorporated into the dimmer arrangement without interrupting the normal AC switching operation of the AC mains supply. Energy required to power the protection for the surge voltage event is derivable inherently from the surge voltage event itself, thereby as there is no active detection means required to instigate protection to protect the dimmer arrangement during the surge voltage, the FETs or IGBTs can still be turned On' during a surge voltage event even if no power is available when the dimmer arrangement is 'off' or in standby mode.
  • the load control arrangement includes back-to-back field effect transistors (FETs) with connected gates
  • Figure 1 illustrates an electric circuit of phase cutting control two wire trailing edge dimmer arrangement in a preferred embodiment of this invention.
  • Figure 1 provides a circuit arrangement for a two-wire trailing edge dimmer arrangement shown generally as (10) adapted to remove power from the end or trailing edge of each AC mains supply cycle.
  • the dimmer terminals include ACTIVE (12) and LOAD (14).
  • Parasitic diodes (16) and (18) are contained in the corresponding Field Effect Transistors (FETs) (20) and (22) that comprise the load current switch. As illustrated, FETs (20) and (22) are arranged back-to-back and operate in the N-Channel enhancement mode having source terminals (21 ) and (23) connected together via resistor (24) with the gates (25) and (27) of each of the FETs (20) and (22) also connected with the drain terminals (29) and (31 ) acting as two power terminals.
  • FETs (20) and (22) are arranged back-to-back and operate in the N-Channel enhancement mode having source terminals (21 ) and (23) connected together via resistor (24) with the gates (25) and (27) of each of the FETs (20) and (22) also connected with the drain terminals (29) and (31 ) acting as two power terminals.
  • the primary EFT shunt capacitor (34) located across the active terminal (12) and the load terminal (14) has a first plate (35a) of the primary EFT shunt capacitor (34) in electrically operable communication with the drain (29) of the first FET (20) of the back-to-back FETs (20) and (22), and wherein the second plate (35b) of the primary EFT shunt capacitor (34) is in electrically operable communication with the drain (31 ) of the second FET (22) of the back-to-back FETs, the primary EFT shunt capacitor (34) is valued and adapted to provide low reactive impedance at EFT frequencies such that EFT voltages are shunted across the lamp (not shown) under the control of the dimmer arrangement without electrically interfering with either connected gates (25) and (27) of the back-to-back FETs (20) and (22), and wherein the primary EFT shunt capacitor (34) is valued and adapted to provide high impedance at AC mains supply frequency so as to provide a minimal current
  • the arrangement When providing protection against mains voltage surges the arrangement derives any voltages required to instigate that protection from the applied voltage surge as the arrangement will need to provide the voltage surge protection no matter whether the dimmer arrangement (10) is operational or in the OFF/Standby mode. When the dimmer arrangement is in OFF/Standby mode the general power supply, shown as a functional block (36) with +10 V (37) in Figure 1 , will not be available.
  • the voltage surge pulse can be either a positive or a negative pulse as seen at the Active terminal (12) with respect to the Load terminal (14).
  • a pulse that is negative at the Active terminal (12) with respect to the Load terminal (14) will flow in the path marked by the dashed arrowed line (B), noting that this negative pulse also develops a voltage at node (43) that is positive with respect to the source terminal of (23) of the first FET (20).
  • the amplitude of the voltage that will be developed at node (43) across the current sensing resistor (40) in parallel with the secondary EFT shunt capacitor (42) can be calculated from the current flowing in first capacitor (44) or second capacitor (46) caused by the voltage surge pulse.
  • the voltage surge pulse test generator when set to 1 kV, develops an open circuit voltage, with a source impedance less than one ohm, having a peak value of 1 kV that is reached in 1 .2 microseconds and decays to 500 V over the next 50 microseconds.
  • a value 1 nF is selected for the first capacitor (44) and the second capacitor (46) so the maximum current that flows in the first capacitor (44) or the second capacitor (46) for a 1 kV test voltage surge pulse (800 V/us) is 800 mA.
  • a preferred value of around 150 ohms for the current sensing resistor (40) so the maximum voltage that will be developed across the current sensing resistor (40) in the absence of the secondary EFT shunt capacitor (42) or any other loading would be about 120 V.
  • the value of the current sensing resistor (40) therefore provides the ability to discriminate between mains voltage surge pulses, that will develop large voltages across the current sensing resistor (40), and normal dimmer arrangement operation of removing power from the end or trailing edge of each AC mains supply half cycle will not.
  • the voltage developed by the current pulses, derived from the voltage surge pulses, in the first capacitor (44) or the second capacitor (46) develop a voltage that will be applied to the FETs (20), (22) connected gates (25), (27) to ensure the FETs (20), (22) are turned ON whenever a voltage surge event takes place.
  • the current flowing in the first capacitor (44) or the second capacitor (46) will divide and some will flow in current sensing resistor (40) and EFT by pass capacitor (42), and some in diode (48) and into the surge voltage gate drive arrangement charge capacitor (50) or parallel arranged diodes (52), (54) depending on the relative impedances in those electrical paths.
  • the arrangement is such to develop, as quickly as possible, a substantial voltage across the charge capacitor (50) during the fast, but brief, rising edge of the voltage surge. That developed voltage across the charge capacitor (50) is applied to the FETs (20), (22) connected gates (25), (27), along an electrical path via diode (52), to turn the FETs (20), (22) ON, and keep the FETs (20), (22) ON, during the time of the surge voltage to avoid damage to the FETs (20), (22).
  • the rising edge of the surge voltage pulse may last just 1.2 microseconds. It is only while the surge voltage is rising that current flowing in the first capacitor (44) or the second capacitor (46) develops a threshold voltage across current sensing resistor (40) having the required positive polarity. As soon as the surge voltage pulse reaches a peak and starts to decrease the voltage developed across the current sensing resistor (40) will fall through zero and reverse in polarity as the applied surge voltage waveform's dV/dt has reversed polarity.
  • This threshold or peak voltage developed is used to turn on the FETs (20), (22) during the longer time, at least 20 - 50 us, while the applied surge voltage is falling from a peak value of 1 kV but is still exceeding the voltage rating of the FETs (20), (22) (about 500 V) and could still cause the FETs (20), (22) to be damaged.
  • the surge voltage arrangement of this invention is configured to provide protection active for about 10 times longer than the minimum time in the 1 kV example referred to herewith.
  • the dimmer's over-current protection shown generally as block (60) in figure 1 , will be activated if the dimmer arrangement is in its normal operational mode.
  • the NPN BJT transistor (62) connected to the gate drive path (64) will remove gate drive from the connected gates (25), (27) of the FETs (20), (22) by shorting the connected gates (25), (27) to the dimmer arrangement 0 V reference rail (66), so effectively shorting the connected gates (25), (27) of the FETs (20), (22) to their sources (23), (21 ).
  • the surge voltage protection must maintain the connected gates (25), (27) of the FETs (20), (22) ON even if that over-current protection (60) tries to oppose it.
  • the dimmer arrangement (10) further includes PNP BJT transistor (68) and resistor (70) into the gate drive (64) path between the current overload protection and the connected gates (25), (27) of the FETs (20), (22).
  • PNP BJT transistor (68) with resistor (70) provide a path for gate current to flow from the connected gates (25), (27) to the gate drive (64) or NPN BJT transistor (62) to turn the FETs (20), (22) OFF.
  • Resistor (70), connected collector-base on PNP BJT transistor (68), provides the base drive to turn PNP BJT transistor (68) ON.
  • the effective impedance of the arrangement resistor (70)/ PNP BJT transistor (68) is a diode in series with a resistance equal to resistor (70) divided by the gain of PNP BJT transistor (68).
  • resistor (70) is 47k and the minimum gain of PNP BJT transistor (68) is 200 the effective resistance is ⁇ 235 ohms and therefore may be neglected when compared with gate drive resistors (not identified) within the gate drive block (36), of at least 10k ohms.
  • the FETs (20), (22) may be turned ON at any time via diode (76).
  • the time-constant charge capacitor (50)/resistor (70) determines how long it takes for the charge capacitor (50) to be discharged to the point where the connected gates (25), (27) of the FETs (20), (22) voltage drops below about 3-4 V and the FETs (20), (22) will turn OFF.
  • capacitors (42) and (50) and the FETs (20), (22) gate-source capacitance can be charged quickly.
  • capacitors (42) and (50) are about 4.7 nF.
  • the FET gate-source capacitance can be around 2.5 nF each.
  • the drop on the diodes (48), (52) is small compared with the connected gates (25), (27) of the FETs (20), (22) voltage to be achieved that is in the order of at least 10 V. Accordingly
  • capacitors (42) and (50) and the gate capacitance are all charged together by the available charging current in the first (44) or second (46) capacitors of approximately 800 mA.
  • the total capacitance is about 14.4 nF so it can increase at a maximum rate of about 56 V/microsecond.
  • the applied pulse may rise 1 kV at 800 V/us
  • the voltage on the dimmer Active and load terminals (12), (14) when it starts can be equal to the peak AC mains supply voltage, around 350 V. Accordingly that the terminal voltage can only be allowed to rise to something less than the FETs (20), (22) breakdown voltage or less than the value [breakdown voltage minus 350 V], before the protective drive is generated.
  • the arrangement further includes the zener diode (78), having a breakdown voltage rating smaller than the connected gates (25), (27) of the FETs (20), (22) voltage rating, to ensure the connected gates (25), (27) of the FETs (20), (22) voltage rating is not exceeded.
  • a typical zener diode (78) will be in the range 20-30 V.
  • Resistors (72) and (74) in series with the connected gates (25), (27) of the FETs (20), (22) ensure high frequency stability of the FETs (20), (22) when the FETs (20), (22) have a drain load that is essentially pure capacitance, that is capacitor (34), at very high frequencies.
  • Resistors (72) and (74) will have values in the range 10 - 100 ohms and have essentially no effect on normal dimmer operation.
  • the thermal fuse (80) connected to the active terminal (12) while part of the preferred

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  • Circuit Arrangement For Electric Light Sources In General (AREA)
  • Electronic Switches (AREA)

Abstract

L'invention concerne un agencement de gradateur à commande par découpage de phase, comprenant une protection contre les surtensions et les transitoires électriques rapides (EFT), y compris un agencement de commande de charge comprenant des transistors à effet de champ (FET) ou transistors bipolaires à grille isolée (IGBT) montés tête-bêche, à grilles connectées. L'invention concerne également un condensateur en dérivation d'EFT, primaire, apprécié pour fournir une impédance élevée à une fréquence d'alimentation secteur en CA, de manière à fournir un courant minimum à travers la borne active et la borne de charge lorsque l'agencement de gradateur est sur "arrêt", et un agencement d'attaque de grille contre les surtensions, conçu pour "mettre en marche" les FET ou IGBT montés tête-bêche, à grilles connectées, en réponse à un événement de surtension.
PCT/AU2015/000582 2014-09-26 2015-09-24 Agencement de gradateur à commande par découpage de phase comprenant une protection contre les surtensions et les transitoires électriques rapides WO2016044878A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2015321410A AU2015321410B2 (en) 2014-09-26 2015-09-24 A phase cutting control dimmer arrangement with surge voltage and electrical fast transient protection
NZ731291A NZ731291A (en) 2014-09-26 2015-09-24 A phase cutting control dimmer arrangement with surge voltage and electrical fast transient protection

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AU2014903838 2014-09-26
AU2014903838A AU2014903838A0 (en) 2014-09-26 A phase cutting control dimmer arrangement with surge voltage and electrical fast transient protection

Publications (1)

Publication Number Publication Date
WO2016044878A1 true WO2016044878A1 (fr) 2016-03-31

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NZ (1) NZ731291A (fr)
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258647A1 (en) * 2004-05-19 2008-10-23 Goeken Group Corp. Dimming Circuit for Led Lighting Device With Means for Holding Triac in Conduction
US20120086361A1 (en) * 2010-10-12 2012-04-12 Microsemi Corp. - Analog Mixed Signal Group Ltd. Power saving arrangement for use with a user implementable phase cut dimmer
US8339062B2 (en) * 2008-05-15 2012-12-25 Marko Cencur Method for dimming non-linear loads using an AC phase control scheme and a universal dimmer using the method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258647A1 (en) * 2004-05-19 2008-10-23 Goeken Group Corp. Dimming Circuit for Led Lighting Device With Means for Holding Triac in Conduction
US8339062B2 (en) * 2008-05-15 2012-12-25 Marko Cencur Method for dimming non-linear loads using an AC phase control scheme and a universal dimmer using the method
US20120086361A1 (en) * 2010-10-12 2012-04-12 Microsemi Corp. - Analog Mixed Signal Group Ltd. Power saving arrangement for use with a user implementable phase cut dimmer

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NZ731291A (en) 2021-07-30
AU2015321410B2 (en) 2020-06-25
AU2015321410A1 (en) 2017-05-18

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