AU2015321410A1 - A phase cutting control dimmer arrangement with surge voltage and electrical fast transient protection - Google Patents

Abstract

A phase cutting control dimmer arrangement with a surge voltage and electrical fast transient (EFT) protection including a load control arrangement having back- to-back field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs) with connected gates. A primary EFT shunt capacitor valued to provide high impedance at AC mains supply frequency so as to provide a minimal current through the active terminal and the load terminal when the dimmer arrangement is "off" and a surge voltage gate drive arrangement adapted to turn "on" the back- to-back field FETs or IGBTs with connected gates in response to a surge voltage event.

Description

PCT/AU2015/000582 WO 2016/044878

A PHASE CUTTING CONTROL DIMMER ARRANGEMENT WITH SURGE VOLTAGE AND ELECTRICAL FAST TRANSIENT PROTECTION

FIELD OF THE INVENTION

[001] This invention relates to a phase cutting control dimmer arrangement that includes surge voltage and electrical fast transient protection.

[002] More particularly this invention relates to a unique surge voltage and electrical fast transient protection system for a phase cutting control dimmer arrangement that includes components that can inherently utilise the developed voltages during a surge voltage and EFT events to instigate the protection without influencing the normal switching operation of the solid states switches.

BACKGROUND ART DISCUSSION

[003] Phase cutting control dimmer arrangements operate by switching AC mains supply to a lamp or light load for only a chosen time portion of each AC mains supply half cycle. Two wire trailing edge dimmers, also referred to as reversed phase control dimmers, remove power from the end or trailing edge of each AC mains supply half cycle. The time period for the AC mains supply as applied to the load is determined conventionally by an analogue or digital timer, controlling the load switching device, that must be started and stopped at exact times during each AC mains supply half cycle.

[004] For two wire trailing edge dimmers the two terminals, that being the active terminal and the load terminal, are wired in series with the load and the time at which the timer is started and stopped, once again for the most part is derived from the processing of the voltage that appears across each of the active and load dimmer voltage terminals.

[005] Solid state switching devices, such as field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs), in these kinds of dimmer arrangements provide the load current switching. 1 PCT/AU2015/000582 WO 2016/044878 [006] As the solid state switching devices are connected in series to the active and load dimmer voltage terminals when there is an uninterrupted voltage increase such as a malfunction of power distribution causing a voltage surge or alternatively a voltage spike brought about by a short duration electrical transient, the dimmer arrangement requires to be configured so as to protect these solid state switching devices against these kinds of events without effecting the operational integrity of the solid state switching devices.

[007] For the most part conventional solid state switching devices acting as load current switches in dimmer arrangements generally would have rated peak values in the range of 500 - 700 V.

[008] It is recognised that the solid state switching devices can be protected during voltage surges provided that the solid state switching devices are turned on during the voltage surge event so that the applied surge voltage and its associated energy will be shared minimally by the solid state switching devices and for the most part by the lamp under the control of the dimmer arrangement. It is to be expected that if the solid state switching devices can be promptly turned on when a voltage surge is recognised at either of the active or load terminals the energy of the surge voltage can be absorbed within the load and then the residual part of the surge voltage energy absorbed by the solid state switching devices being small enough so that the voltage surge event is non-destructive upon the operational ongoing integrity of the solid state switching devices.

[009] Traditional arrangements to turn on FETs and IGBTs during voltage surge events includes the use of metal oxide varistors (MOVs). By introducing MOVs with a breakdown voltage above normal AC mains supply voltage peaks and below the FETs or IGBTs rated voltage, these MOVs can be configured to apply gate drive to the FETs and IGBTs when a voltage surge event is recognised at either of the active or load terminals.

[010] Advantageously the MOVs are adapted to protect the solid state switching devices even if the dimmer is switched to an ‘off’ or low power standby during the 2 PCT/AU2015/000582 WO 2016/044878 voltage surge event. However while MOVs provide componentry that can be introduced into the dimmer arrangement to handle the effects of a voltage surge, MOVs are also inherently susceptible to malfunction and destruction when overloaded. Accordingly MOVs present an unacceptable risk to the safety of the dimmer arrangement in that while the MOVs may in some circumstances provide appropriate protection against generated voltage surges within the dimmer arrangement, if the voltage surge is prolonged, uninterrupted and/or repetitive, which is often a requirement during regulatory testing to determine whether or not a dimmer arrangement can handle voltage surges and/or short duration electrical transients, the effects of the voltage surge to be handled by the MOVs could potentially exceed the safe operating conditions for the MOV overloading it causing it to catch fire which would be completely unacceptable.

[011] Therefore there needs to be alternative protection other than MOVs for ensuring that solid state switching devices turn on during a voltage surge event.

[012] As introduced above, dimmer arrangements are also exposed to electrical fast transients (EFTs) which provide a short duration electrical transient generally made up of voltage spikes or pulses of significantly shorter duration than those characterised from a voltage surge event. While these EFTs events are unlikely to contain enough energy to directly destroy the solid state switching devices switching current to the load in the phase cutting control dimmer arrangement, EFTs can cause consequential destruction and malfunctioning of operation if it results in the operation of switching the AC mains supply to the lamp in an uncontrolled way inconsistent with the chosen time portion of each AC mains supply half cycle.

[013] As EFTs events are of a shorter duration than one would expect from a voltage surge event, known protective measures conventionally used to handle such short duration electrical transients in voltage have included the use of relatively large value AC mains supply rated capacitors across the active and load terminals so that these over voltages of the EFTs events are essentially passed onto the load or the lamp under the control of the dimmer arrangement rather than being presented to the solid state switching devices within the dimmer arrangement. 3 PCT/AU2015/000582 WO 2016/044878 [014] Nonetheless AC mains supply rated capacitors in order to bypass the EFTs into the load are valued such that current would still flow from the AC mains supply rated capacitor when the solid state switching devices are meant to be turned ‘off’ and no visible light is meant to be illuminated from the lamp.

[015] In recent times the efficiency of lamps has increased significantly and the power required to be drawn through a lamp for illumination has substantially decreased. A modern electric lamp rated at 5 W on a 230 V mains voltage supply has a nominal operating current of less than 22 mA. If the dimmer controlled lamp is to be dimmed to 10% of the controlled lamps full brightness, then the lamp current being passed by the dimmer controlling the light would need to be reduced to 2.2 mA. Even a current much lower than 2.2 mA drawn through the dimmer active and load terminals when the dimmer is off will not ensure that the external lamp under the control of the dimmer will not be illuminated and it is likely that there will potentially still be visible light from the lamp. Accordingly AC mains supply voltage rated capacitors could potentially allow current up to 15 mA to flow through the load even when the solid state switching devices are turned “off” thereby making such capacitors unsuitable for use as a protection means against EFTs if no illuminating visible light is to be observable from the lamp under the control of the dimmer when the solid state switching devices have switched the current “off to the load.

[016] Accordingly it is an object of this invention to provide a phase cutting control dimmer arrangement for a lamp that includes surge voltage and EFTs protection wherein the components used to provide such protection will not involve the use of MOVs nor will the introduce components produce operational currents, when the solid state switching devices are “off’ or in “standby” mode, that would pass enough current through the lamp under the control of the dimmer arrangement to make it possible to visually observe illuminated light from the lamp despite the fact that the dimmer arrangement is “off’ or in “standby” mode.

[017] Further objects and advantages of the invention will become apparent from a complete reading of the following specification. 4 PCT/AU2015/000582 WO 2016/044878 [018] Throughout the specification reference is made to electrical fast transients (EFT) which in general serves to describe short duration electrical transients in voltage within the electrical circuit of the dimmer arrangement. These type of events are also in some instances generally referred to as fast transient bursts (FTBs) or electronic fast transients. This specification recognizes each of these forms of conventional language use to describe the short duration electrical transient and the use of the acronym (EFTs) is intended to provide a synonymous use and application for fast transient bursts or electronic fast transient accordingly.

SUMMARY OF THE INVENTION

[019] In one form of the invention there is provided a phase cutting control dimmer arrangement with a surge voltage and electrical fast transient (EFT) protection, said arrangement including: [020] a load control arrangement including back-to-back field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs) with connected gates; [021] a primary EFT shunt capacitor located across an active terminal and a load terminal wherein a first plate of said primary EFT shunt capacitor is in electrically operable communication with a drain of a first FET or IGBT of said back-to-back FETs or IGBTs, and wherein a second plate of said primary EFT shunt capacitor is in electrically operable communication with a drain of a second FET or IGBT of said back-to-back FETs or IGBTs, said primary EFT shunt capacitor valued to provide a low reactive impedance at EFT frequencies such that EFT voltages are shuntable across a lamp under control of the phase cutting control dimmer arrangement without electrically interfering with either connected gates of the back-to-back FETs or IGBTs, and wherein said primary EFT shunt capacitor is valued to provide high impedance at AC mains supply frequency so as to provide a minimal current through the active terminal and the load terminal when the phase cutting control dimmer arrangement is “off” or in a standby mode such so no visible light is observable from the lamp under the control of said phase cutting control dimmer arrangement; 5 PCT/AU2015/000582 WO 2016/044878 [022] a surge voltage gate drive arrangement adapted to turn “on” said back-to-back field FETs or IGBTs with connected gates in response to a surge voltage event at either the active terminal or load terminal, said surge voltage gate drive arrangement including a capacitor arrangement having a first capacitor with a first plate in electrically operable communication with the active terminal and a second plate of said first capacitor in electrically operable communication with a current sensing resistor, said capacitor arrangement further including a second capacitor with one plate in electrically operable communication with the load terminal and a second plate of said second capacitor in electrically operable communication with said current sensing resistor, [023] such that a surge voltage event at the active terminal or load terminal provides a surge current into the respective first capacitor or second capacitor establishing a threshold voltage across said current sensing resistor, wherein said threshold voltage across said current sensing resistor is adapted to charge a gate drive capacitor, wherein said gate drive capacitor is adapted to provide a voltage for duration of the surge voltage event to the connected gates of the back-to-back FETs or IGBTs, thereby turning the back-to-back FETs or IGBTs “on” during the surge voltage event.

[024] In preference the current sensing resistor is in parallel with a secondary EFT shunt capacitor, wherein the secondary EFT shunt capacitor is valued with a reactive impedance lower than the current sensing resistor such that the threshold voltage is not reached across the current sensing resistor during an EFT event.

[025] In the preferred arrangement there is at least the primary EFT shunt capacitor along with the EFT bypass capacitor across the sensing resistor that also serves as a secondary EFT shunt capacitor. The primary EFT shunt capacitor as introduced above is connected directly across the Active and Load terminals to bypass most of the EFT. However the two voltage surge sensing first and second capacitors may have a reactance similar to the primary EFT shunt capacitor and therefore will conduct EFT currents possibly comparable in magnitude with those in the primary EFT shunt capacitor. 6 PCT/AU2015/000582 WO 2016/044878 [026] Those EFT currents in the two voltage surge sensing first and second capacitors will then flow in the current sensing resistor unless there is provided the secondary EFT shunt capacitor to bypass this current so there is insufficient voltage build up across the current sensing resistor that would be interpreted as a voltage surge event.

[027] In preference the current sensing resistor is valued such that an AC mains supply voltage on the active terminal or the load terminal provides an insufficient rise in voltage for current flowing into the first capacitor or second capacitor to establish a threshold voltage across said current sensing resistor.

[028] In preference the arrangement further includes a zener diode in electrically operable communication with both the gate drive capacitor and the connected gates of the back-to-back FETs or IGBTs wherein the zener diode is valued and configured within the dimmer arrangement to limit the amplitude of the voltage of the gate drive capacitor below the rated maximum tolerance level upon the connected gates of the FETs or IGBTs.

[029] Advantageously the arrangement provides for a fast acting means to turn on the FETs or IGBTs during high voltage surges the kinds of which are often specified in regulatory standards. Such standards may require multiple application of test voltages being applied to the active terminal or load terminal that are in series with the lamp load under control of the dimmer arrangement, wherein these voltages for test purposes exceed the voltage rating of the FETs or IGBTs incorporated within the dimmer arrangement. Applied voltages used in voltage surge testing may range up from 500V.

[030] Normal electric power distribution systems for a 230V AC mains supply have peaks around 325V wherein the operational non-destructive rating of the FETs or IGBTs may lie within the range of 500V to 800V, if such FETs and IGBTs are to be of a practical size to be incorporated into the enclosure or housing arrangement to which the dimmer arrangement is provided. 7 PCT/AU2015/000582 WO 2016/044878 [031] Advantageously as the dimmer arrangement includes a surge voltage drive arrangement which is adapted to turn on the FETs or IGBTs in response to a voltage surge event it means that the voltage across the FETs or IGBTs would be relatively low and most of the surge voltage energy will appear across the load or lamp under the control of the dimmer arrangement. Still further, advantageously the protection provided for by the surge voltage gate arrangement of this invention provides its voltages for operation from the applied voltage surge itself thereby protection is afforded to the driver arrangement whether the dimmer arrangement is operational or in the “off” or standby mode. As is to be expected when the dimmer arrangement is in the “off” or standby mode its general power supply will not be available.

[032] In preference the dimmer control arrangement includes an overcurrent protection arrangement adapted to provide a means to turn ‘off’ the FETs or IGBTs if the load under the control of the dimmer arrangement becomes short circuit and/or overcurrent within the dimmer arrangement severely exceeds safe operating conditions.

[033] In preference the over-current protection arrangement is active and includes a transistor adapted to switch the connected gates of the back-to-back FETs or IGBTs to zero volts when an over-current event has been detected.

[034] In preference the primary EFT shunt capacitor has a value less than 4.7 nF.

[035] In preference the primary EFT shunt capacitor has a value of about 2.2 nF.

[036] In preference the surge voltage gate drive arrangement includes an active transistor connected to an operational gate drive path to the connected gates of the FETs or IGBTs to which the over-current protection arrangement in part controls said operational gate drive path to the connected gates of the FETs or IGBTs, such that during a voltage surge event the over-current protection arrangement is overridden so that the gate drive capacitor remains enabled to maintain voltage for the duration of the voltage surge event to the connected gates of the FETs or IGBTs thereby 8 PCT/AU2015/000582 WO 2016/044878 keeping the FETs or IGBTs on, although an over-current event has been detected by the over-current protection arrangement.

[037] As consequential load current levels can be very large, of the order of 100A for periods of the order of 20 microseconds, the dimmer arrangement over-current protection arrangement will be activated if the dimmer arrangement is in its normal operation mode when a voltage surge event, such as during testing takes place. The active transistor in the over-current protection arrangement will try and remove the gate drive from the connected gates of the back-to-back FETs or IGBTs by shorting the connected gates to a zero volt reference rail thereby effectively shorting the connected gates of the FETs or IGBTs to their respective sources.

[038] Advantageously the surge voltage gate drive arrangement of this invention is able to over-ride the over-current protection arrangement trying to switch the connected gates of the FETs and IGBTs to zero volts thereby potentially turning the FETs or IGBTs ‘off’ which would be completely counter-productive in a voltage surge event wherein the FETs or IGBTs must be kept “on” so that the voltage across them can be kept relatively low so that much of the surged voltage and energy can be dissipated across the lamp or load under the control of the dimmer arrangement rather than the FETs or IGBTs themselves.

[039] Unlike the testing carried out for voltage surges, the voltage applied in testing a dimmer arrangement’s immunity to EFTs have extremely fast rise times, about 1kV in 5 nanoseconds, of particularly short duration. Generally the EFTs are applied from a source with a relatively high 50 ohm impedance as compared to a 1 ohm for a voltage surge testing event. Advantageously in the arrangement provided for in this invention EFTs signals will be shunted by the primary EFT shunt capacitor which is valued and adapted to provide low reactance impedance at EFT frequencies such that the EFT voltage and associated pulses are shunted across the lamp or load under the control of the dimmer arrangement without then operatively electrically interfering with either of the connected gates of the back-to-back FETs or IGBTs. 9 PCT/AU2015/000582 WO 2016/044878 [040] Importantly the primary EFT shunt capacitor is also valued and adapted so as to provide high impedance at AC mains supply frequency so as to provide a minimal current through the active and load terminals when the dimmer arrangement is in the ‘off’ or standby mode such that no visible light is observable from the lamp under the control of the dimmer arrangement.

[041] Hence this in-built protection to counter the effects of EFT with extremely fast rising times utilises a simple passive capacitor.

[042] Still further, introduction of the current sensing resistor in parallel with the secondary EFT shunt capacitor wherein that secondary EFT shunt capacitor is valued with a reactive impedance lower than the current sensing resistor means that during an EFT event the threshold voltage that needs to be established across the current sensing resistor in order to charge the surge voltage gate drive capacitor is not achieved.

[043] Hence the secondary EFT shunt capacitor allows the dimmer arrangement to recognise the differences between a surge voltage event and an EFT event wherein the switching state of the back-to-back FETs or IGBTs will have opposite requirements in that during the surge voltage event wherein there are rate rises around 800 V per microsecond the drive to the interconnected gates of the back-to-back FETs or IGBTs must be such to turn the FETs or IGBTs ‘on’ so that the voltage across these solid state devices can be relatively low with most of the voltage surge energy appearing across the load under the control of the dimmer arrangement.

[044] Conversely the extremely fast rise times of an EFT event which as introduced above are of a significantly shorter duration means that if the dimmer control arrangement is in the ‘off’ or standby mode and an EFT event is recognised the back-to-back FETs or IGBTs do not need to be turned ‘on’ as the EFT signals will be mostly shunted by capacitance across the active and load terminals. As EFT events are characterised by a much high frequency that means the secondary EFT shunt capacitor will prevent any recognizable build-up of the threshold voltage required upon the current sensing resistor which would adversely or at least unnecessarily for 10 PCT/AU2015/000582 WO 2016/044878 an EFT event start charging the surge voltage gate drive capacitor that provides the voltage to the connected gates of the FETs or IGBTs to turn them ‘on’.

[045] The current sensing resistor is also valued such that the AC mains supply voltage on the active terminal and load terminal, when switched mid-cycle by the FETs during normal operation of the dimmer and generally having edge rates about 7V per microsecond, will provide an insufficient rate of rise in voltage for current flowing into the respective first and second capacitance to establish a threshold voltage across the current sensing resistor.

[046] Advantageously the dimmer arrangement therefore is able to discriminate between general operation of switching AC mains supply to the lamp or light for that chosen time portion of each AC mains supply half cycle. Therefore surge voltage and EFT protection can be incorporated into the dimmer arrangement without interrupting the normal AC switching operation of the AC mains supply. Energy required to power the protection for the surge voltage event is derivable inherently from the surge voltage event itself, thereby as there is no active detection means required to instigate protection to protect the dimmer arrangement during the surge voltage, the FETs or IGBTs can still be turned ‘on’ during a surge voltage event even if no power is available when the dimmer arrangement is ‘off or in standby mode.

[047] In preference the load control arrangement includes back-to-back field effect transistors (FETs) with connected gates

BRIEF DESCRIPTION OF THE DRAWINGS

[048] In order now to describe the invention in greater detail a preferred embodiment will be presented with the assistance of the following illustrated circuit arrangement and accompanying text.

[049] Figure 1 illustrates an electric circuit of phase cutting control two wire trailing edge dimmer arrangement in a preferred embodiment of this invention. 11 PCT/AU2015/000582 WO 2016/044878

DETAILED DESCRIPTION OF THE INVENTION

[050] Referring to the drawing now in greater detail wherein Figure 1 provides a circuit arrangement for a two-wire trailing edge dimmer arrangement shown generally as (10) adapted to remove power from the end or trailing edge of each AC mains supply cycle. The dimmer terminals include ACTIVE (12) and LOAD (14).

[051] Parasitic diodes (16) and (18) are contained in the corresponding Field Effect Transistors (FETs) (20) and (22) that comprise the load current switch. As illustrated, FETs (20) and (22) are arranged back-to-back and operate in the N-Channel enhancement mode having source terminals (21) and (23) connected together via resistor (24) with the gates (25) and (27) of each of the FETs (20) and (22) also connected with the drain terminals (29) and (31) acting as two power terminals.

[052] The FETs (20) and (22), each have corresponding intrinsic body diodes as introduced above (16) and (18) that allow conduction of current in one direction as configured back-to-back arrangements of the FETs (20) and (22) allows load current to be controlled in either direction.

[053] The primary EFT shunt capacitor (34) located across the active terminal (12) and the load terminal (14) has a first plate (35a) of the primary EFT shunt capacitor (34) in electrically operable communication with the drain (29) of the first FET (20) of the back-to-back FETs (20) and (22), and wherein the second plate (35b) of the primary EFT shunt capacitor (34) is in electrically operable communication with the drain (31) of the second FET (22) of the back-to-back FETs, the primary EFT shunt capacitor (34) is valued and adapted to provide low reactive impedance at EFT frequencies such that EFT voltages are shunted across the lamp (not shown) under the control of the dimmer arrangement without electrically interfering with either connected gates (25) and (27) of the back-to-back FETs (20) and (22), and wherein the primary EFT shunt capacitor (34) is valued and adapted to provide high impedance at AC mains supply frequency so as to provide a minimal current through the active terminal (12) and the load terminal (14) when the dimmer arrangement is “off’ or in a standby mode such that no visible light is observable from the lamp under 12 PCT/AU2015/000582 WO 2016/044878 the control of said dimmer arrangement when the dimmer arrangement is in the “off’ or standby mode; [054] When providing protection against mains voltage surges the arrangement derives any voltages required to instigate that protection from the applied voltage surge as the arrangement will need to provide the voltage surge protection no matter whether the dimmer arrangement (10) is operational or in the OFF/Standby mode. When the dimmer arrangement is in OFF/Standby mode the general power supply, shown as a functional block (36) with +10 V (37) in Figure 1, will not be available.

[055] When a voltage surge pulse is applied to the Active terminal (12) current will flow through the dimmer arrangement to the Load terminal (14) and return via the lamp load (not shown). The voltage surge pulse can be either a positive or a negative pulse as seen at the Active terminal (12) with respect to the Load terminal (14).

[056] When a positive pulse is applied then current will flow in the electrical path designated by the dashed arrowed line marked (A). In this scenario there will be a voltage developed across the current sensing resistor (40), which is configured and valued to develop a threshold voltage that will be discussed in greater detail below, and the secondary EFT shunt capacitor (42). The polarity at node (43) is positive with respect to the source terminal (23) of the first FET (20). The current path is completed via an additional current sensing resistor (24) and the parasitic diode (18) in the second FET (22) then back to the Load terminal (14).

[057] A pulse that is negative at the Active terminal (12) with respect to the Load terminal (14) will flow in the path marked by the dashed arrowed line (B), noting that this negative pulse also develops a voltage at node (43) that is positive with respect to the source terminal of (23) of the first FET (20).

[058] The amplitude of the voltage that will be developed at node (43) across the current sensing resistor (40) in parallel with the secondary EFT shunt capacitor (42) 13 PCT/AU2015/000582 WO 2016/044878 can be calculated from the current flowing in first capacitor (44) or second capacitor (46) caused by the voltage surge pulse.

[059] The voltage surge pulse test generator, when set to 1 kV, develops an open circuit voltage, with a source impedance less than one ohm, having a peak value of 1kV that is reached in 1.2 microseconds and decays to 500 V over the next 50 microseconds. The maximum current “i” that will flow in the current sensing resistor (40), if the secondary EFT shunt capacitor (42) is not connected and the lamp load (not shown) is low resistance, is given by the expression [C x dV/dt] = i where C is the first capacitor (44) or second capacitor (46), dV/dt = rate of change of the applied surge voltage = 1kV in 1.2 microseconds.

[060] In this preferred embodiment a value 1 nF is selected for the first capacitor (44) and the second capacitor (46) so the maximum current that flows in the first capacitor (44) or the second capacitor (46) for a 1 kV test voltage surge pulse (800 V/us) is 800 mA. With a preferred value of around 150 ohms for the current sensing resistor (40) so the maximum voltage that will be developed across the current sensing resistor (40) in the absence of the secondary EFT shunt capacitor (42) or any other loading would be about 120 V.

[061] When the dimmer arrangement (10) is operating normally the voltage across the Active terminal (12) and the load terminal (14) as FETs (20), (22) switches the load OFF will be maximum 350 V and it will rise to that value in a controlled way to meet electromagnetic interference requirements. A typical rise time will be about 50 microseconds so the voltage developed across the current sensing resistor (40) will then be less than 0.7 V.

[062] Accordingly the value of the current sensing resistor (40) therefore provides the ability to discriminate between mains voltage surge pulses, that will develop large voltages across the current sensing resistor (40), and normal dimmer arrangement operation of removing power from the end or trailing edge of each AC mains supply half cycle will not. 14 PCT/AU2015/000582 WO 2016/044878 [063] The voltage developed by the current pulses, derived from the voltage surge pulses, in the first capacitor (44) or the second capacitor (46) develop a voltage that will be applied to the FETs (20), (22) connected gates (25), (27) to ensure the FETs (20), (22) are turned ON whenever a voltage surge event takes place.

[064] The current flowing in the first capacitor (44) or the second capacitor (46) will divide and some will flow in current sensing resistor (40) and EFT by pass capacitor (42), and some in diode (48) and into the surge voltage gate drive arrangement charge capacitor (50) or parallel arranged diodes (52), (54) depending on the relative impedances in those electrical paths.

[065] In this invention the arrangement is such to develop, as quickly as possible, a substantial voltage across the charge capacitor (50) during the fast, but brief, rising edge of the voltage surge. That developed voltage across the charge capacitor (50) is applied to the FETs (20), (22) connected gates (25), (27), along an electrical path via diode (52), to turn the FETs (20), (22) ON, and keep the FETs (20), (22) ON, during the time of the surge voltage to avoid damage to the FETs (20), (22).

[066] The rising edge of the surge voltage pulse may last just 1.2 microseconds. It is only while the surge voltage is rising that current flowing in the first capacitor (44) or the second capacitor (46) develops a threshold voltage across current sensing resistor (40) having the required positive polarity. As soon as the surge voltage pulse reaches a peak and starts to decrease the voltage developed across the current sensing resistor (40) will fall through zero and reverse in polarity as the applied surge voltage waveform’s dV/dt has reversed polarity.

[067] The voltage across current sensing resistor (40) is peak rectified to charge the charge capacitor (50). Diode (48) prevents the charge capacitor (50) being discharged via the current sensing resistor (40) when current sensing resistor (40) voltage reverses.

[068] This threshold or peak voltage developed is used to turn on the FETs (20), (22) during the longer time, at least 20 - 50 us, while the applied surge voltage is 15 PCT/AU2015/000582 WO 2016/044878 falling from a peak value of 1 kV but is still exceeding the voltage rating of the FETs (20), (22) (about 500 V) and could still cause the FETs (20), (22) to be damaged.

[069] It is also to be appreciated that in the example being described in the preferred embodiment a 1kV surge voltage is being applied, nonetheless test levels up to 4kV are also sometimes used. Accordingly the surge voltage arrangement of this invention is configured to provide protection active for about 10 times longer than the minimum time in the 1 kV example referred to herewith.

[070] As the consequential load current levels may be very large, of the order of 100 Amps for periods of the order of 20 microseconds, the dimmer’s over-current protection, shown generally as block (60) in figure 1, will be activated if the dimmer arrangement is in its normal operational mode. The NPN BJT transistor (62) connected to the gate drive path (64) will remove gate drive from the connected gates (25), (27) of the FETs (20), (22) by shorting the connected gates (25), (27) to the dimmer arrangement 0 V reference rail (66), so effectively shorting the connected gates (25), (27) of the FETs (20), (22) to their sources (23), (21). The surge voltage protection must maintain the connected gates (25), (27) of the FETs (20), (22) ON even if that over-current protection (60) tries to oppose it.

[071] As the gate drive (64) to the connected gates (25), (27) of the FETs (20), (22) may be OFF, or the over-current protection circuit (60) is active wherein NPN BJT transistor (62) is switching the connected gates (25), (27) of the FETs (20), (22) to zero volts, the dimmer arrangement (10) further includes PNP BJT transistor (68) and resistor (70) into the gate drive (64) path between the current overload protection and the connected gates (25), (27) of the FETs (20), (22).

[072] When the surge voltage protection is not activated PNP BJT transistor (68) with resistor (70) provide a path for gate current to flow from the connected gates (25), (27) to the gate drive (64) or NPN BJT transistor (62) to turn the FETs (20), (22) OFF. Resistor (70), connected collector-base on PNP BJT transistor (68), provides the base drive to turn PNP BJT transistor (68) ON. 16 PCT/AU2015/000582 WO 2016/044878 [073] The effective impedance of the arrangement resistor (70)/ PNP BJT transistor (68) is a diode in series with a resistance equal to resistor (70) divided by the gain of PNP BJT transistor (68). For example if resistor (70) is 47k and the minimum gain of PNP BJT transistor (68) is 200 the effective resistance is < 235 ohms and therefore may be neglected when compared with gate drive resistors (not identified) within the gate drive block (36), of at least 10k ohms. The FETs (20), (22) may be turned ON at any time via diode (76).

[074] When a voltage is present on charge capacitor (50) that is larger than the gate drive voltage, which may be zero, the FETs (20), (22) gate voltage, ahead of resistors (72), (74) and the voltage on the base of PNP BJT transistor (68) will be equal. Both being one diode drop, either diode (52) or (54), below the voltage on the charge capacitor (50). Accordingly PNP BJT transistor (68) has zero base-emitter voltage and is therefore turned OFF. The only current that can flow from the connected gates (25), (27), from the charge capacitor (50) is the current in resistor (70). With resistor (70) about 47k ohms the current in resistor (70) is small. The time-constant charge capacitor (50)/resistor (70) determines how long it takes for the charge capacitor (50) to be discharged to the point where the connected gates (25), (27) of the FETs (20), (22) voltage drops below about 3-4 V and the FETs (20), (22) will turn OFF.

[075] To ensure that capacitors (42) and (50) and the FETs (20), (22) gate-source capacitance can be charged quickly, capacitors (42) and (50) are about 4.7 nF. The FET gate-source capacitance can be around 2.5 nF each. The drop on the diodes (48), (52) is small compared with the connected gates (25), (27) of the FETs (20), (22) voltage to be achieved that is in the order of at least 10 V. Accordingly capacitors (42) and (50) and the gate capacitance are all charged together by the available charging current in the first (44) or second (46) capacitors of approximately 800 mA. The rate at which their voltage increases will be given by dV/dt = i/C. The total capacitance is about 14.4 nF so it can increase at a maximum rate of about 56 V/microsecond.

[076] While the applied pulse may rise 1kV at 800 V/us, the voltage on the dimmer Active and load terminals (12), (14) when it starts can be equal to the peak AC mains 17 PCT/AU2015/000582 WO 2016/044878 supply voltage, around 350 V. Accordingly that the terminal voltage can only be allowed to rise to something less than the FETs (20), (22) breakdown voltage or less than the value [breakdown voltage minus 350 V], before the protective drive is generated. For a typical breakdown of 550 V that’s just 200 V terminal voltage rise or so just [200/1 kV x 1.2 us] = 0.24 us of time available. In that time the gate drive can therefore rise [56 x 0.24] = 13.4 V achieving operational requirement.

[077] When the AC mains supply voltage is lower at the time of the surge voltage event, or if the surge voltage event has a larger rate of rise because its voltage is larger and it still rises in the same 1.2 us, then excessive gate voltage could be developed. Accordingly the arrangement further includes the zener diode (78), having a breakdown voltage rating smaller than the connected gates (25), (27) of the FETs (20), (22) voltage rating, to ensure the connected gates (25), (27) of the FETs (20), (22) voltage rating is not exceeded. A typical zener diode (78) will be in the range 20-30 V.

[078] Resistors (72) and (74) in series with the connected gates (25), (27) of the FETs (20), (22) ensure high frequency stability of the FETs (20), (22) when the FETs (20), (22) have a drain load that is essentially pure capacitance, that is capacitor (34), at very high frequencies. Resistors (72) and (74) will have values in the range 10 -100 ohms and have essentially no effect on normal dimmer operation. The thermal fuse (80) connected to the active terminal (12) while part of the preferred embodiment shown is not relevant to the surge voltage or EFT protection afforded by the dimmer arrangement (10). 18

Claims (16)

1. THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

   1. A phase cutting control dimmer arrangement with a surge voltage and electrical fast transient (EFT) protection, said arrangement including: a load control arrangement including back-to-back field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs) with connected gates; a primary EFT shunt capacitor located across an active terminal and a load terminal wherein a first plate of said primary EFT shunt capacitor is in electrically operable communication with a drain of a first FET or IGBT of said back-to-back FETs or IGBTs, and wherein a second plate of said primary EFT shunt capacitor is in electrically operable communication with a drain of a second FET or IGBT of said back-to-back FETs or IGBTs, said primary EFT shunt capacitor valued to provide a low reactive impedance at EFT frequencies such that EFT voltages are shuntable across a lamp under control of the phase cutting control dimmer arrangement without electrically interfering with either connected gates of the back-to-back FETs or IGBTs, and wherein said primary EFT shunt capacitor is valued to provide high impedance at AC mains supply frequency so as to provide a minimal current through the active terminal and the load terminal when the phase cutting control dimmer arrangement is “off’ or in a standby mode such so no visible light is observable from the lamp under the control of said phase cutting control dimmer arrangement; a surge voltage gate drive arrangement adapted to turn “on” said back-to-back field FETs or IGBTs with connected gates in response to a surge voltage event at either the active terminal or load terminal, said surge voltage gate drive arrangement including a capacitor arrangement having a first capacitor with a first plate in electrically operable communication with the active terminal and a second plate of said first capacitor in electrically operable communication with a current sensing resistor, said capacitor arrangement further including a second capacitor with one plate in electrically operable communication with the load terminal and a second plate of said second capacitor in electrically operable communication with said current sensing resistor, such that a surge voltage event at the active terminal or load terminal provides a surge current into the respective first capacitor or second capacitor establishing a threshold voltage across said current sensing resistor, wherein said threshold voltage across said current sensing resistor is adapted to charge a gate drive capacitor, wherein said gate drive capacitor is adapted to provide a voltage for duration of the surge voltage event to the connected gates of the back-to-back FETs or IGBTs, thereby turning the back-to-back FETs or IGBTs “on” during the surge voltage event.
2. 2. The phase cutting control dimmer arrangement of claim 1 wherein the current sensing resistor is configured in parallel with a secondary EFT shunt capacitor, wherein the secondary EFT shunt capacitor is valued with a reactive impedance lower than the current sensing resistor thereby keeping voltage across the current sensing resistor below the threshold voltage across the current sensing resistor for EFT voltages.
3. 3. The phase cutting control dimmer arrangement of claim 1 wherein the arrangement further includes a zener diode in electrically operable communication with the gate drive capacitor and the connected gates of the back-to-back FETs or IGBTs.
4. 4. The phase cutting control dimmer arrangement of claim 3 wherein the zener diode is valued to limit an amplitude of a voltage of the gate drive capacitor below a rated maximum tolerance level upon the connected gates of the FETs or IGBTs.
5. 5. The phase cutting control dimmer arrangement of claim 1 further including an overcurrent protection arrangement adapted to turn ‘off’ the FETs or IGBTs when the load under the control of the phase cutting control dimmer arrangement short circuits and/or overcurrent within the phase cutting control dimmer arrangement exceeds safe operating conditions.
6. 6. The phase cutting control dimmer arrangement of claim 5 wherein the overcurrent protection arrangement is active and includes a transistor adapted to switch the connected gates of the back-to-back FETs or IGBTs to zero volts when an overcurrent event has been detected.
7. 7. The phase cutting control dimmer arrangement of claim 6 wherein the surge voltage gate drive arrangement includes an active transistor connected to an operational gate drive path to the connected gates of the FETs or IGBTs to which the over-current protection arrangement in part controls said operational gate drive path to the connected gates of the FETs or IGBTs, such that during a voltage surge event the over-current protection arrangement is overridden so that the gate drive capacitor remains enabled to maintain voltage for the duration of the voltage surge event to the connected gates of the FETs or IGBTs thereby keeping the FETs or IGBTs on, although an over-current event has been detected by the over-current protection arrangement.
8. 8. The phase cutting control dimmer arrangement of claim 7 wherein current from a positive or negative voltage surge pulse is adapted to flow in an electrical path to provide the threshold voltage via voltage developed at a node across the current sensing resistor.
9. 9. The phase cutting control dimmer arrangement of claim 8 wherein an amplitude of voltage developed at the node across the current sensing resistor is dependent upon the current flowing in first capacitor or second capacitor as a result of the positive or negative voltage surge pulse.
10. 10. The phase cutting control dimmer arrangement of claim 10 wherein the first capacitor and the second capacitor have a value of around 1 nF.
11. 11. The phase cutting control dimmer arrangement of claim 10 wherein the current sensing resistor has a value of around 150 ohms
12. 12. The phase cutting control dimmer arrangement of claim 11 wherein voltage across the current sensing resistor is voltage peak rectified.
13. 13. The phase cutting control dimmer arrangement of claim 1 further including resistors in series with the connected gates of the FETs or IGBTs.
14. 14. The phase cutting control dimmer arrangement of claim 13 wherein the resistors in series with the connected gates of the FETs have values in the range 10 -100 ohms.
15. 15. The phase cutting control dimmer arrangement of claim 1 wherein the primary EFT shunt capacitor has a value less than 4.7 nF.
16. 16. The phase cutting control dimmer arrangement of claim 15 wherein the primary EFT shunt capacitor has a value of about 2.2 nF.