WO2016041273A1 - 高行频cmos-tdi图像传感器 - Google Patents

高行频cmos-tdi图像传感器 Download PDF

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WO2016041273A1
WO2016041273A1 PCT/CN2014/093752 CN2014093752W WO2016041273A1 WO 2016041273 A1 WO2016041273 A1 WO 2016041273A1 CN 2014093752 W CN2014093752 W CN 2014093752W WO 2016041273 A1 WO2016041273 A1 WO 2016041273A1
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pixel
pixels
output
switch
vint
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聂凯明
姚素英
徐江涛
高志远
史再峰
高静
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Tianjin University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/768—Addressed sensors, e.g. MOS or CMOS sensors for time delay and integration [TDI]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the invention relates to the field of analog integrated circuit design, in particular to a design of a CMOS-TDI image sensor capable of realizing a higher horizontal frequency, that is, a high horizontal frequency CMOS-TDI image sensor.
  • the image sensor converts the optical signals obtained by the lens into electrical signals that are easy to store, transmit, and process.
  • Image sensors can be divided into area array and line array according to the working mode.
  • the working principle of the area array type image sensor is to take an object to capture two-dimensional image information by a pixel array arranged in a two-dimensional array, and the line array type image sensor works on a pixel array arranged in a one-dimensional line array.
  • the two-dimensional image information is obtained by scanning and photographing the object, and the working mode of the line image sensor can be referred to FIG. 1 .
  • Line array image sensors are widely used in aerial photography, space imaging, machine vision and medical imaging in their special way of working.
  • the exposure time of the pixel is severely limited by the moving speed of the line image sensor relative to the object, especially in high-speed moving low-light applications (such as spatial imaging).
  • the signal-to-noise ratio (SNR) of the line image sensor becomes very low.
  • Time Delay Integration (TDI) technology has been proposed, which can increase the SNR and sensitivity of the line image sensor. It performs multiple times on the same target by its special scanning method. Exposure, achieving high SNR and sensitivity, is especially suitable for high-speed motion and low illumination environments.
  • the basic principle of TDI is to use the array of pixels arranged in the array to work in line scan mode, so that pixels of different rows can be exposed multiple times to the same object in motion, and the results of each exposure are accumulated, which is equivalent.
  • the exposure integration time of the pixel to the object is extended, so the SNR and sensitivity can be greatly improved.
  • TDI technology was first implemented by a Charge Coupled Device (CCD) image sensor.
  • CCD Charge Coupled Device
  • the CCD image sensor is also an ideal device for implementing TDI technology, which can achieve noise-free signal accumulation.
  • TDI technology is widely used in CCD image sensors.
  • the commonly used CCD-TDI image sensor has a structure similar to a rectangular area array CCD image sensor, but it works in a line sweep mode, as shown in Figure 2, CCD-TDI image.
  • the working process of the sensor is as follows: the n-level CCD-TDI image sensor has a total of n rows of pixels, and the charge collected by the first row of pixels in a column in the first exposure period is not directly output, but is the second in the same column.
  • the amplitude of the output signal is the accumulation of n pixels of integrated charge, which is equivalent to the charge collected in n times of the exposure period of one pixel, the amplitude of the output signal is expanded by n times and the amplitude of the noise is only expanded. Up Times, so the signal to noise ratio can be increased Times.
  • CMOS Complementary Metal Oxide Semiconductor
  • the analog signal output by the pixel first enters the analog signal accumulator to complete the accumulation of the same exposure signal, and then sends the accumulated analog signal to the ADC for quantization output.
  • the prior art has also proposed to first quantize the pixel output in the CMOS image sensor through an ADC, and then perform the accumulation of the same exposure signal through the on-chip integrated digital domain accumulator.
  • the two technologies first accumulate and then quantize the output or quantize and then accumulate the output, it is necessary to read the exposure results of all the pixels in the CMOS image sensor in one exposure period, so the read speed is bound to limit the shortest exposure. The cycle limits the maximum line rate.
  • the prior art proposes a method for integrating a buffer unit in a pixel to realize signal transmission between adjacent pixels, and a CCD-type TDI image sensor can perform a pipeline operation of accumulating signals, and only the last line in each exposure period.
  • the output of the pixel needs to be quantized and read out, thus solving the limitation of the read speed to the horizontal frequency, thereby achieving a faster line frequency.
  • this technique introduces a large amount of kT/C noise and an offset voltage of the op amp during the pipelined accumulation of the pixel output signal, and the sensitivity of the sensor is limited because the buffer unit is integrated in the pixel to reduce the fill factor of the pixel.
  • the present invention aims to overcome the deficiencies of the prior art, and aims to provide a CMOS image sensor capable of better implementing the TDI function, improving the line frequency of the CMOS-TDI image sensor, and expanding the application range of the TDI technology.
  • the technical solution adopted by the present invention is a high-frequency-frequency CMOS-TDI image sensor, and the pixel is composed of a photodiode, an operational amplifier, the same value of the integral capacitors C1 and C2, the offset voltage eliminating capacitor C3, and the switches S1 to S10;
  • the anode is connected to the 0 volt ground, the cathode of the photodiode is connected to one end of the switch S9, the other end of the switch S9 is connected to the reference voltage Vref;
  • the left plate of the offset voltage eliminating capacitor C3 is connected to the cathode of the photodiode, right
  • the plate is connected to the negative input of the op amp;
  • the negative input and output of the op amp are connected in series with the switch S10, the positive input of the op amp is connected to the reference voltage Vref, and the output of the op amp is also used as the whole
  • the output of the pixel; the left plate of the integrating capacitor C1 is
  • Switches S1 and S2 are controlled by clock clk1', switches S3 and S4 are controlled by clock clk2, switches S5 and S6 are controlled by clock clk2', switches S7 and S8 are controlled by clock clk1, switches S9 and S10 are controlled by clock rst, clock is high
  • the level period indicates that the pixel output is valid; the pixel pipeline performs the following operations: sampling the input signal, accumulating the photocurrent integration signal generated by the pixel in one exposure period based on the sampled input signal, and outputting the accumulated result.
  • the output Vint is expressed as:
  • V0 is the signal collected by the pixel during the last exposure period
  • iph is the photo-generated current value of the photodiode.
  • the signal stored by the integrating capacitor C2 in the xth pixel is Vint(1, x), and the signal stored in the integrating capacitor C1 is Vint(1, x-1); then all the pixels enter the reset state.
  • the photocurrent of the photodiode is integrated.
  • the signal stored by the integrating capacitor C1 in the xth pixel is Vint(1, x-1)+Vint(2, x), and the integrating capacitor C2 is stored.
  • the signal is Vint(1,x-2)+Vint(2,x-1), and so on.
  • the output of the Nth pixel after N exposure periods can be expressed as:
  • Vint_tot Vint(1,1)+Vint(2,2)+Vint(3,3)+...+Vint(N,N) (2)
  • Vint(1,1) to Vint(N,N) are the results of respectively exposing pixels 1 to N to the same object in 1 to N transit times, so the output of the Nth pixel is N-level TDI. After the accumulation, the result is finally quantized and output by the subsequent column parallel ADC during the high period of the Read clock, thereby completing the entire readout process; the output of the Nth pixel is N times in each exposure period. Cumulative results.
  • the layout of the layout is as follows: the center distance is P square is the photosensitive area of the photodiode, and the square of the same size adjacent to the lateral direction is the position where the operational amplifier, the switch and the capacitor layout are located, which is called the circuit area; each two laterally adjacent square shapes A layout of a pixel, wherein the odd-column pixel and the even-column pixel are not adjacent in the lateral direction, and the even-column pixel is entirely below the odd-numbered column pixel, and the photosensitive regions in each of the even-numbered columns of pixels are aligned with the circuit region in the odd-numbered column of pixels.
  • the photosensitive regions in the odd-numbered columns of each column except the first column are aligned with the circuit regions in the even-numbered columns, so there is a fill factor almost every P distance in the direction perpendicular to the scanning direction, ie, the length direction of the sensor array. It is a 100% photosensitive zone.
  • the pixel structure used in the CMOS-TDI image sensor can complete the transmission of the pre-stage pixel output signal to the subsequent stage pixel while exposing, and the same column pixel realizes the pipelined accumulation of the same object exposure result, and only each exposure period
  • the output of the last row of pixels needs to be read out, which reduces the limit of the readout speed to the shortest exposure time and increases the maximum line frequency of the sensor;
  • the proposed offset isolation technique eliminates the offset voltage of the pixel, and the pixel is received before receiving Only one sampling operation is introduced in the process of shifting the pixel output signal, thereby reducing the introduced thermal noise;
  • the proposed layout layout suitable for the pixel structure greatly improves the pixel without lowering the equivalent center distance of the pixel.
  • the invention can better realize the TDI function, improve the line frequency of the CMOS-TDI image sensor, and expand the application range of the TDI technology.
  • FIG. 1 is a schematic diagram showing the operation mode of a line image sensor provided by the prior art.
  • FIG. 2 is a schematic diagram showing the working principle of a CCD-TDI image sensor provided by the prior art.
  • FIG. 3 is a circuit diagram of a pixel employed in the high horizontal frequency CMOS-TDI image sensor proposed by the present invention.
  • FIG. 4 is a timing diagram of pixel control provided by the present invention.
  • Figure 5 is a circuit diagram of a single column of pixels provided by the present invention.
  • FIG. 6 is a schematic layout diagram of a pixel array provided by the present invention.
  • FIG. 7 is a diagram showing an example of a single pixel layout layout provided by the present invention.
  • the pixel structure used in the CMOS-TDI image sensor proposed by the present invention is as shown in FIG. 3, which is mainly composed of a photodiode, an operational amplifier (referred to as an operational amplifier), and integrating capacitors C1 and C2 (the capacitance values of C1 and C2 are the same)
  • the offset voltage elimination capacitor C3 and the switches S1 to S10 are composed.
  • the connection relationship of each component in the pixel is as follows: the anode of the photodiode is connected to the ground line (0V potential), the cathode of the photodiode is connected to one end of the switch S9, and the other end of the switch S9 is connected to the reference voltage Vref; the offset voltage is eliminated.
  • the left plate of the capacitor C3 is connected to the cathode of the photodiode, and the right plate is connected to the negative input terminal of the operational amplifier; the switch S10 is connected in series between the negative input terminal and the output terminal of the operational amplifier, and the positive input terminal of the operational amplifier is connected to On the reference voltage Vref, the output of the operational amplifier also serves as the output of the entire pixel; the left plate of the integrating capacitor C1 is simultaneously connected to one end of the switches S1 and S3, and the other end of the switch S1 is connected to the reference voltage Vref, the switch S3 The other end is connected to the cathode of the photodiode, the right plate of the integrating capacitor C1 is simultaneously connected to one end of the switches S2 and S4, the other end of the switch S2 is connected to the input end of the pixel, and the other end of the switch S4 is connected to the pixel
  • the output of the integrating capacitor C2 is simultaneously connected to one end of the switches S5 and S7, the other end of the
  • the control timing of the switches S1 to S10 is as shown in FIG. 4, where TL is the transit time, Tint is the pixel exposure time, the high level indicates that the switch is closed, and the low level indicates that the switch is off, wherein the switches S1 and S2 are subjected to the clock clk1' Control, switches S3 and S4 are controlled by clock clk2, switches S5 and S6 are controlled by clock clk2', switches S7 and S8 are controlled by clock clk1, switches S9 and S10 are controlled by clock rst, and the period of clock Read high indicates that the pixel output is valid.
  • the pixel structure shown in FIG. 3 can be pipelined under the timing manipulation shown in FIG. 4 to: sample the input signal and accumulate the photocurrent integral generated by the pixel in one exposure period based on the sampled input signal.
  • a signal that outputs the accumulated result which can be expressed as:
  • V0 is the signal collected by the pixel during the last exposure period
  • iph is the photo-generated current value of the photodiode.
  • the offset voltage canceling capacitor C3 in the pixel can complete the function of isolating the integrating capacitors C1 and C2 from the op amp offset voltage, so the integration result of the pixel output does not include the offset voltage of the op amp, and the pixel completes the process of accumulating the signal. Only one input of the input signal is introduced, that is, only one sampling of the thermal noise is introduced, which reduces the level of thermal noise introduced during the accumulated readout.
  • the TDI signal accumulation function can be realized by cascading such pixels, and the single column pixels formed by cascading the N pixels are as shown in FIG. 5.
  • the input end of the pixel 1 is connected to the reference voltage Vref
  • the input end of the pixel 2 is connected to the output end of the pixel 1, and so on
  • the output end of the pixel N is connected to the column parallel ADC through the Read readout switch. on.
  • the acquisition of the output signal of the previous pixel is started, and at the same time, the integration capacitor C2 starts to integrate the photocurrent of the photodiode.
  • the signal stored by the integration capacitor C2 in the xth pixel is Vint ( 1, x)
  • the integrating capacitor C2 in the prime begins to acquire the output signal of the previous pixel, while the integrating capacitor C1 starts to integrate the photocurrent of the photodiode.
  • the integrating capacitor C1 in the xth pixel The stored signal is Vint(1,x-1)+Vint(2,x), and its integrated capacitor C2 stores the signal Vint(1,x-2)+Vint(2,x-1), and so on.
  • the output of the Nth pixel after N exposure periods can be expressed as:
  • Vint_tot Vint(1,1)+Vint(2,2)+Vint(3,3)+...+Vint(N,N) (Equation 2)
  • Vint(1,1) to Vint(N,N) are the results of respectively exposing pixels 1 to N to the same object in 1 to N transit times, so the output of the Nth pixel is N-level TDI. After the accumulation, the result is finally quantized and output by the subsequent column parallel ADC while the Read clock is high, thereby completing the entire readout process.
  • the output of the Nth pixel is the result of the accumulation of N times of integration, so the ADC only needs to complete the read once, thus reducing the read speed limit on the line frequency, on the order of microseconds.
  • the read time can reach the line frequency of hundreds of K.
  • the pixel structure of the present invention integrates an operational amplifier and a capacitor, and these circuits are bound to reduce the fill factor of the photosensitive region of the photodiode.
  • the present invention proposes a layout layout matching the pixel structure. As shown in Figure 6. The center of each square is P, and the square filled with diagonal lines is the photosensitive area of the photodiode.
  • the white square of the same size adjacent to the lateral direction is the position of the op amp and the capacitor layout (called the circuit area), so each The horizontally adjacent filled slash squares and white squares form a layout of pixels, wherein the odd column pixels and the even column pixels are not adjacent laterally, and the even column pixels are entirely below the odd column pixels, and each column of the even columns of pixels
  • the photosensitive regions are aligned with the circuit regions in the odd-numbered columns of pixels, and the photosensitive regions in each of the odd-numbered columns of pixels except the first column are aligned with the circuit regions in the even-numbered columns, and thus in a direction perpendicular to the scanning direction (ie, the sensor array)
  • the length direction There is a photosensitive area with a fill factor of almost 100% every P distance.
  • the sensor length is 1024 pixels
  • the TDI level is 50
  • the horizontal frequency is 100KHz
  • the center distance of the pixel photosensitive area is 15 ⁇ m.
  • the on-chip parallel ADC uses a Cyclic ADC with a resolution of 10 bits and a conversion rate of 100KHz.
  • the layout of a single pixel is shown in Figure 7, where the size of the photodiode is 15 ⁇ m ⁇ 15 ⁇ m, and the capacitors C1, C2, C3, switches and op amps in the pixel are all placed in the layout space of 15 ⁇ m ⁇ 15 ⁇ m, where C1 and C2
  • the size of the capacitor is 7.5 ⁇ m ⁇ 7.5 ⁇ m
  • the size of the capacitor C3 is 2.5 ⁇ m ⁇ 15 ⁇ m
  • the rest of the space is placed on the switch and the op amp.
  • the capacitance of C1 and C2 is approximately 112.5fF
  • the capacitance of capacitor C3 is approximately 75fF
  • MIM is fabricated using the upper metal, so below the capacitor
  • transistors and lower metal wiring so some switches and op amp layouts can be placed underneath the capacitor to make the most of the space.
  • the center distance of the equivalent photosensitive region is 15 ⁇ m.
  • the transit time TL of the sensor is 10 ⁇ s, wherein Tint is 9 ⁇ s, the pixel reset time is 1 ⁇ s, and the conversion rate of the on-chip column parallel ADC is 100KHz, which can meet the requirement of the read rate.

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Abstract

本发明涉及模拟集成电路设计领域，为提供一种为使COMS图像传感器能够较好的实现TDI功能，提高CMOS-TDI图像传感器的行频，扩大TDI技术的应用范围，为此，本发明采用的技术方案是，高行频CMOS-TDI图像传感器，像素由光电二极管、运算放大器、容值相同积分电容C1和C2、失调电压消除电容C3、开关S1～S10组成；光电二极管的阳极连接到0伏特地线上，光电二极管的阴极连接到开关S9的一端，开关S9的另一端连接到参考电压Vref上；前述像素级联，最后像素N的输出端通过Read读出开关连接到列并行ADC上。本发明主要应用于模拟集成电路设计。

Description

高行频CMOS-TDI图像传感器 技术领域
本发明涉及模拟集成电路设计领域，特别涉及一种能够实现较高行频的CMOS-TDI图像传感器的设计，即高行频CMOS-TDI图像传感器。
背景技术
图像传感器可将镜头获得的光信号转换成易于存储、传输和处理的电学信号。图像传感器按照工作方式可以分为面阵型和线阵型。面阵型图像传感器的工作原理是以呈二维面阵排布的像素阵列对物体进行拍摄以获取二维图像信息，而线阵型图像传感器的工作原理是以呈一维线阵排布的像素阵列通过对物体扫描拍摄的方式来获取二维图像信息，其中线阵型图像传感器的工作方式可参考图1。线阵型图像传感器以其特殊的工作方式被广泛应用在航拍、空间成像、机器视觉和医疗成像等众多领域。但是由于在线阵型图像传感器的像素曝光期间物体始终在移动，因此像素的曝光时间严重受限于线阵型图像传感器相对被拍摄物体的移动速度，尤其在高速运动低照度应用环境下(例如空间成像)线阵型图像传感器的信噪比(Signal to Noise Ratio，SNR)会变得非常低。为解决SNR低的问题，有人提出了时间延时积分(Time Delay Integration，TDI)技术，其能够增加线阵图像传感器的SNR和灵敏度，它以其特殊的扫描方式，通过对同一目标进行多次曝光，实现很高的SNR和灵敏度，因此特別适用于高速运动低照度的环境下。TDI的基本原理是使用面阵排布的像素阵列以线阵扫描的方式工作，进而可实现不同行的像素对移动中的同一物体进行多次曝光，并将每次曝光结果进行累加，等效延长了像素对物体的曝光积分时间，因此可以大幅提升SNR和灵敏度。
TDI技术最早是通过电荷耦合器件(Charge Coupled Device,CCD)图像传感器实现的，CCD图像传感器也是实现TDI技术的理想器件，它能够实现无噪声的信号累加。目前TDI技术多应用在CCD图像传感器中，普遍采用的CCD-TDI图像传感器的结构类似一个长方形的面阵CCD图像传感器，但是其以线扫的方式工作，如图2所示，CCD-TDI图像传感器的工作过程如下：n级CCD-TDI图像传感器一共有n行像素，某一列上的第一行像素在第一个曝光周期内收集到的电荷并不直接输出，而是与同列第二个像素在第二个曝光周期内收集到的电荷相加，以此类推CCD-TDI图像传感器最后一行(第n行)的像素收集到的电荷与前面n-1次收集到的电荷累加后再按照普通线阵CCD器件的输出方式进行读出。在CCD-TDI图像传感器中，输出信号的幅度是n个像素积分电荷的累加，即相当于一个像素n倍曝光周期内所收集到的电荷，输出信号幅度扩大了n倍而噪声的幅度只扩大了
Figure PCTCN2014093752-appb-000001
倍，因此信噪比可以提高
Figure PCTCN2014093752-appb-000002
倍。
但是由于CCD图像传感器存在功耗大集成度低等缺点，目前其在各个领域的应用都在逐渐被CMOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)图像传感器所替代。如果通过CMOS图像传感器能够实现TDI功能(即CMOS-TDI图像传感器)，那么TDI相机的成本将大幅下降并得到更广泛的应用。为使CMOS图像传感器实现TDI功能，现有技术提出通过在CMOS图像传感器内部集成模拟信号累加器的方法来实现CMOS-TDI图 像传感器，即像素输出的模拟信号先进入模拟信号累加器中完成对相同曝光信号的累加，然后将完成累加的模拟信号送入ADC进行量化输出。此外，现有技术还曾提出首先通过ADC将CMOS图像传感器中像素输出进行量化，然后再通过片内集成的数字域累加器完成对相同曝光信号的累加。但是，这两种技术无论是先累加再量化输出还是先量化再累加输出，都需要在一个曝光周期内将CMOS图像传感器中所有像素的曝光结果进行读出，因此读出速度势必会限制最短曝光周期即限制最大行频。为解决这一问题，现有技术提出了像素内集成缓冲单元以实现临近像素间的信号传递的方法，类似CCD型TDI图像传感器可流水线式完成信号的累加操作，每个曝光周期内只有最后一行像素的输出需要被量化读出，因此解决了读出速度对行频的限制，进而可以实现更快的行频。但是该技术在对像素输出信号进行流水式累加过程中会引入大量的kT/C噪声和运放的失调电压，且因为像素内集成了缓冲单元降低了像素的填充因子，限制了传感器的灵敏度。
发明内容
本发明旨在解决克服现有技术的不足，本发明旨在提供一种为使CMOS图像传感器能够较好的实现TDI功能，提高CMOS-TDI图像传感器的行频，扩大TDI技术的应用范围，为此，本发明采用的技术方案是，高行频CMOS-TDI图像传感器，像素由光电二极管、运算放大器、容值相同积分电容C1和C2、失调电压消除电容C3、开关S1～S10组成；光电二极管的阳极连接到0伏特地线上，光电二极管的阴极连接到开关S9的一端，开关S9的另一端连接到参考电压Vref上；失调电压消除电容C3的左极板连接到光电二极管的阴极，右极板连接到运放的负输入端；运放的负输入端和输出端之间串联接入开关S10，运放的正输入端连接到参考电压Vref上，运放的输出端也同时作为整个像素的输出端；积分电容C1的左极板同时连接到开关S1和S3的一端，开关S1的另一端连接到参考电压Vref上，开关S3的另一端连接到光电二极管的阴极上，积分电容C1的右极板同时连接到开关S2和S4的一端，开关S2的另一端连接到该像素的输入端，开关S4的另一端连接到该像素的输出端；积分电容C2的左极板同时连接到开关S5和S7的一端，开关S5的另一端连接到参考电压Vref上，开关S7的另一端连接到光电二极管的阴极上，积分电容C2的右极板同时连接到开关S6和S8的一端，开关S6的另一端连接到该像素的输入端，开关S8的另一端连接到该像素的输出端；前述像素级联方式：像素1的输入端连接到参考电压Vref上，像素2的输入端连接到像素1的输出端，以此类推进行级联，最后像素N的输出端通过Read读出开关连接到列并行ADC上。
开关S1和S2受时钟clk1’控制，开关S3和S4受时钟clk2控制，开关S5和S6受时钟clk2’控制，开关S7和S8受时钟clk1控制，开关S9和S10受时钟rst控制，时钟Read高电平期间表示像素输出有效；像素流水式完成如下操作：采样输入信号，以采样到的输入信号为基础累积上该像素在一个曝光周期内产生的光电流积分信号，将该累加结果进行输出，输出Vint表示为：
Figure PCTCN2014093752-appb-000003
其中V0为该像素在上个曝光周期采集到的信号，iph为光电二极管的光生电流值。
像素工作过程如下：首先在初始化状态，clk1＝clk2＝0，clk1’＝clk2’＝rst＝1；此时所有像素的输入输出电压均为Vref；然后所有像素进入第一个曝光周期clk1＝clk1’＝1，clk2＝clk2’＝rst＝0，此时所有像素中的积分电容C1开始采集其前一个像素的输出信号，而与此同时积分电容C2开始对光电二极管的光电流进行积分，当第一个曝光周期结束时，第x个像素中积分电容C2存储的信号为Vint(1,x)，其积分电容C1存储的信号为Vint(1,x-1)；然后所有像素进入复位状态clk1＝clk1’＝clk2＝clk2’＝0，rst＝1，此时所有像素中的积分电容C1、C2均处于浮空状态，它们存储的信号保持不变，而光电二极管完成复位操作；然后所有像素进入第二个曝光周期clk1＝clk1’＝rst＝0，clk2＝clk2’＝1，此时所有像素中的积分电容C2开始采集其前一个像素的输出信号，而与此同时积分电容C1开始对光电二极管的光电流进行积分，当第二个曝光周期结束时，第x个像素中积分电容C1存储的信号为Vint(1,x-1)+Vint(2,x),其积分电容C2存储的信号为Vint(1,x-2)+Vint(2,x-1)，以此类推，经过N个曝光周期后第N个像素的输出可以表示为：
Vint_tot＝Vint(1,1)+Vint(2,2)+Vint(3,3)+…+Vint(N,N)     (2)
其中Vint(1,1)到Vint(N,N)分别是像素1到N对同一个物体在1到N个渡越时间内分别曝光的结果，因此第N个像素的输出即为N级TDI累加后的结果，该结果最后在Read时钟为高电平期间由后续的列并行ADC进行量化输出，进而完成整个读出过程；每个曝光周期内，第N个像素的输出即为N次积分累积的结果。
版图布局方式为：中心距为P正方形为光电二极管的感光区，与其横向毗邻的相同大小的正方形为运算放大器、开关与电容版图所处位置，称为电路区；每两个横向毗邻的正方形形构成一个像素的版图，其中奇数列像素和偶数列像素横向并不相邻，偶数列像素整体位于奇数列像素的下方，每列偶数列像素中的感光区均与奇数列像素中电路区对齐，除第一列以外每列奇数列像素中的感光区均与偶数列像素中的电路区对齐，因此在与扫描方向相垂直的方向即传感器阵列的长度方向每隔P距离都会存在一个填充因子几乎为100％的感光区。
本发明的技术特点及效果：
所述的CMOS-TDI图像传感器中采用的像素结构可在曝光同时完成前级像素输出信号向后级像素的传递，同列像素实现了对相同物体曝光结果的流水线式累加，每个曝光周期内只需读出最后一行像素的输出，降低了读出速度对最短曝光时间的限制，提升了传感器的最大行频；所提出的像素中使用失调隔离技术消除了像素的失调电压，且像素在接收前移级像素输出信号的过程中仅引入一个采样操作，进而降低了所引入的热噪声；所提出的适合该像素结构的版图布局方式在不降低像素等效中心距的前提下，大幅提升了像素感光区的填充因子。本发明可较好的实现TDI功能，提高CMOS-TDI图像传感器的行频，扩大TDI技术的应用范围。
附图说明
图1是现有技术提供的线阵图像传感器的工作模式示意图。
图2是现有技术提供的CCD-TDI图像传感器的工作原理示意图。
图3是本发明提出的高行频CMOS-TDI图像传感器中所采用的像素的电路图。
图4是本发明提供的像素控制时序示意图。
图5是本发明提供的单列像素的电路图。
图6是本发明提供的像素阵列的版图布局示意图。
图7是本发明提供的单个像素版图布局的实例示意图。
具体实施方式
本发明所提出的CMOS-TDI图像传感器中所采用的像素结构如图3所示，其主要由光电二极管、运算放大器(简称运放)、积分电容C1和C2(C1与C2的电容值相同)、失调电压消除电容C3、开关S1～S10组成。该像素中各个组件的连接关系如下：光电二极管的阳极连接到地线上(0V电位)，光电二极管的阴极连接到开关S9的一端，开关S9的另一端连接到参考电压Vref上；失调电压消除电容C3的左极板连接到光电二极管的阴极，右极板连接到运放的负输入端；运放的负输入端和输出端之间串联接入开关S10，运放的正输入端连接到参考电压Vref上，运放的输出端也同时作为整个像素的输出端；积分电容C1的左极板同时连接到开关S1和S3的一端，开关S1的另一端连接到参考电压Vref上，开关S3的另一端连接到光电二极管的阴极上，积分电容C1的右极板同时连接到开关S2和S4的一端，开关S2的另一端连接到该像素的输入端，开关S4的另一端连接到该像素的输出端；积分电容C2的左极板同时连接到开关S5和S7的一端，开关S5的另一端连接到参考电压Vref上，开关S7的另一端连接到光电二极管的阴极上，积分电容C2的右极板同时连接到开关S6和S8的一端，开关S6的另一端连接到该像素的输入端，开关S8的另一端连接到该像素的输出端。开关S1～S10的控制时序如图4所示，其中TL为渡越时间，Tint为像素曝光时间，高电平表示开关闭合，低电平表示开关断开，其中开关S1和S2受时钟clk1’控制，开关S3和S4受时钟clk2控制，开关S5和S6受时钟clk2’控制，开关S7和S8受时钟clk1控制，开关S9和S10受时钟rst控制，时钟Read高电平期间表示像素输出有效。图3中所示的像素结构在图4所示的时序操控下可流水式完成如下操作：采样输入信号，以采样到的输入信号为基础累积上该像素在一个曝光周期内产生的光电流积分信号，将该累加结果进行输出，该输出Vint可表示为：
Figure PCTCN2014093752-appb-000004
       (公式1)
其中V0为该像素在上个曝光周期采集到的信号，iph为光电二极管的光生电流值。该像素中失调电压消除电容C3可完成将积分电容C1、C2与运放失调电压隔离的作用，因此像素输出的积分结果中不包含运放的失调电压，且该像素在完成对信号累积的过程中只引入一次对输入信号采样，即只引入一次采样热噪声，降低了在累加读出过程中引入的热噪声水平。
将这样的像素进行级联后即可实现TDI信号累加功能，N个像素级联后形成的单列像素如图5所示。其中，像素1的输入端连接到参考电压Vref上，像素2的输入端连接到像素1的输出端，以此类推进行级联，最后像素N的输出端通过Read读出开关连接到列并行ADC 上。其工作过程如下：首先在初始化状态(clk1＝clk2＝0，clk1’＝clk2’＝rst＝1)，此时所有像素的输入输出电压均为Vref,完成了对所有像素中积分电容C1、C2的复位操作，同时也完成了对光电二极管的复位；然后所有像素进入第一个曝光周期(clk1＝clk1’＝1，clk2＝clk2’＝rst＝0)，此时所有像素中的积分电容C1开始采集其前一个像素的输出信号，而与此同时积分电容C2开始对光电二极管的光电流进行积分，当第一个曝光周期结束时，第x个像素中积分电容C2存储的信号为Vint(1,x)，其积分电容C1存储的信号为Vint(1,x-1)；然后所有像素进入复位状态(clk1＝clk1’＝clk2＝clk2’＝0，rst＝1)，此时所有像素中的积分电容C1、C2均处于浮空状态，它们存储的信号保持不变，而光电二极管完成复位操作；然后所有像素进入第二个曝光周期(clk1＝clk1’＝rst＝0，clk2＝clk2’＝1),此时所有像素中的积分电容C2开始采集其前一个像素的输出信号，而与此同时积分电容C1开始对光电二极管的光电流进行积分，当第二个曝光周期结束时，第x个像素中积分电容C1存储的信号为Vint(1,x-1)+Vint(2,x),其积分电容C2存储的信号为Vint(1,x-2)+Vint(2,x-1)，以此类推，经过N个曝光周期后第N个像素的输出可以表示为：
Vint_tot＝Vint(1,1)+Vint(2,2)+Vint(3,3)+…+Vint(N,N)     (公式2)
其中Vint(1,1)到Vint(N,N)分别是像素1到N对同一个物体在1到N个渡越时间内分别曝光的结果，因此第N个像素的输出即为N级TDI累加后的结果，该结果最后在Read时钟为高电平期间由后续的列并行ADC进行量化输出，进而完成整个读出过程。每个曝光周期内，第N个像素的输出即为N次积分累积的结果，因此ADC只需完成该一次读出即可，因此降低了读出速度对行频的限制，微秒量级的读出时间即可达到上百K的行频。
本发明所提出的像素结构内集成了运放和电容，这些电路势必会降低光电二极管感光区的填充因子，为解决这一问题，本发明提出一种与该像素结构所配套的版图布局方式，如图6所示。其中每个正方形的中心距均为P，填充斜线的正方形为光电二极管的感光区，与其横向毗邻的相同大小的白色正方形为运放与电容版图所处位置(称为电路区)，因此每个横向毗邻的填充斜线正方形与白色正方形构成了一个像素的版图，其中奇数列像素和偶数列像素横向并不相邻，偶数列像素整体位于奇数列像素的下方，每列偶数列像素中的感光区均与奇数列像素中电路区对齐，除第一列以外每列奇数列像素中的感光区均与偶数列像素中的电路区对齐，因此在与扫描方向相垂直的方向(即传感器阵列的长度方向)每隔P距离都会存在一个填充因子几乎为100％的感光区。通过这样的版图布局，在不降低等效像素中心距的前提下，降低了像素中电路部分对感光区填充因子的影响，可以形成几乎100％的填充因子，只是在奇偶列像素输出间引入一个固定时间差N×TL，该差别通过对输出的数字信号进行简单处理即可消除，并不会增加后端电路的负担。
为使本发明的目的、技术方案和优点更加清晰，下面将结合实例给出本发明实施方式的具体描述。该实例中传感器长度为1024像素，TDI级数为50级，行频为100KHz，像素感光区中心距为15μm，片内列并行ADC采用分辨率为10位、转换速率为100KHz的CyclicADC。单个像素的版图布局如图7所示，其中光电二极管的大小为15μm×15μm，像素中电容C1、C2、C3、开关和运放全部放置于15μm×15μm大小的版图空间中，其中C1和C2的大小均为7.5μm×7.5μm，电容C3的大小为2.5μm×15μm，其余的空间放置开关和运放。如果使用单位 面积电容为2fF/μm2的MIM电容实现电容中的电容，则C1和C2的电容值大约为112.5fF，电容C3的电容值约为75fF，且通常MIM使用上层金属制作，因此电容下面还可以放置晶体管和较低层的金属布线，所以部分开关和运放的版图可以放置在电容下方以充分利用空间。传感器像素阵列的长度为15μm×1024＝15360μm，高度为15μm×50×2＝1500μm，等效感光区中心距为15μm。针对100KHz的行频，传感器的渡越时间TL即为10μs，其中Tint为9μs，像素复位时间1μs，片内列并行ADC的转换速率是100KHz，其可满足该读出速率的要求。每个像素在采样前级像素输出时会引入的热噪声均方根值为
Figure PCTCN2014093752-appb-000005
因此经过50级TDI累加后引入的总热噪声均方根值为
Figure PCTCN2014093752-appb-000006
像素中参考电压Vref可使用1V，如果像素输出最大电压值为2.6V，则经过50级累加后像素输出的最大信号幅度为1.6V，如果只考虑读出过程中热噪声的影响，则输出信号最大信噪比为20log(1.6V/1.36mV)＝61.4dB，可满足10位分辨率ADC对信号源信噪比的要求。

Claims (4)

  1. 一种高行频CMOS-TDI图像传感器，其特征是，像素由光电二极管、运算放大器、容值相同积分电容C1和C2、失调电压消除电容C3、开关S1～S10组成；光电二极管的阳极连接到0伏特地线上，光电二极管的阴极连接到开关S9的一端，开关S9的另一端连接到参考电压Vref上；失调电压消除电容C3的左极板连接到光电二极管的阴极，右极板连接到运放的负输入端；运放的负输入端和输出端之间串联接入开关S10，运放的正输入端连接到参考电压Vref上，运放的输出端也同时作为整个像素的输出端；积分电容C1的左极板同时连接到开关S1和S3的一端，开关S1的另一端连接到参考电压Vref上，开关S3的另一端连接到光电二极管的阴极上，积分电容C1的右极板同时连接到开关S2和S4的一端，开关S2的另一端连接到该像素的输入端，开关S4的另一端连接到该像素的输出端；积分电容C2的左极板同时连接到开关S5和S7的一端，开关S5的另一端连接到参考电压Vref上，开关S7的另一端连接到光电二极管的阴极上，积分电容C2的右极板同时连接到开关S6和S8的一端，开关S6的另一端连接到该像素的输入端，开关S8的另一端连接到该像素的输出端；前述像素级联方式：像素1的输入端连接到参考电压Vref上，像素2的输入端连接到像素1的输出端，以此类推进行级联，最后像素N的输出端通过Read读出开关连接到列并行ADC上。
  2. 如权利要求1所述的高行频CMOS-TDI图像传感器，其特征是，开关S1和S2受时钟clk1’控制，开关S3和S4受时钟clk2控制，开关S5和S6受时钟clk2’控制，开关S7和S8受时钟clk1控制，开关S9和S10受时钟rst控制，时钟Read高电平期间表示像素输出有效；像素流水式完成如下操作：采样输入信号，以采样到的输入信号为基础累积上该像素在一个曝光周期内产生的光电流积分信号，将该累加结果进行输出，输出Vint表示为：
    Figure PCTCN2014093752-appb-100001
    其中V0为该像素在上个曝光周期采集到的信号，iph为光电二极管的光生电流值。
  3. 如权利要求1所述的高行频CMOS-TDI图像传感器，其特征是，像素工作过程如下：首先在初始化状态，clk1＝clk2＝0，clk1’＝clk2’＝rst＝1；此时所有像素的输入输出电压均为Vref；然后所有像素进入第一个曝光周期clk1＝clk1’＝1，clk2＝clk2’＝rst＝0，此时所有像素中的积分电容C1开始采集其前一个像素的输出信号，而与此同时积分电容C2开始对光电二极管的光电流进行积分，当第一个曝光周期结束时，第x个像素中积分电容C2存储的信号为Vint(1,x)，其积分电容C1存储的信号为Vint(1,x-1)；然后所有像素进入复位状态clk1＝clk1’＝clk2＝clk2’＝0，rst＝1，此时所有像素中的积分电容C1、C2均处于浮空状态，它们存储的信号保持不变，而光电二极管完成复位操作；然后所有像素进入第二个曝光周期clk1＝clk1’＝rst＝0，clk2＝clk2’＝1，此时所有像素中的积分电容C2开始采集其前一个像素的输出信号，而与此同时积分电容C1开始对光电二极管的光电流进行积分，当第二个曝光周期结束时，第x个像素中积分电容C1存储的信号为Vint(1,x-1)+Vint(2,x),其积分电 容C2存储的信号为Vint(1,x-2)+Vint(2,x-1)，以此类推，经过N个曝光周期后第N个像素的输出可以表示为：
    Vint_tot＝Vint(1,1)+Vint(2,2)+Vint(3,3)+…+Vint(N,N)  (2)
    其中Vint(1,1)到Vint(N,N)分别是像素1到N对同一个物体在1到N个渡越时间内分别曝光的结果，因此第N个像素的输出即为N级TDI累加后的结果，该结果最后在Read时钟为高电平期间由后续的列并行ADC进行量化输出，进而完成整个读出过程；每个曝光周期内，第N个像素的输出即为N次积分累积的结果。
  4. 如权利要求1所述的高行频CMOS-TDI图像传感器，其特征是，版图布局方式为：中心距为P正方形为光电二极管的感光区，与其横向毗邻的相同大小的正方形为运算放大器、开关与电容版图所处位置，称为电路区；每两个横向毗邻的正方形形构成一个像素的版图，其中奇数列像素和偶数列像素横向并不相邻，偶数列像素整体位于奇数列像素的下方，每列偶数列像素中的感光区均与奇数列像素中电路区对齐，除第一列以外每列奇数列像素中的感光区均与偶数列像素中的电路区对齐，因此在与扫描方向相垂直的方向即传感器阵列的长度方向每隔P距离都会存在一个填充因子几乎为100％的感光区。
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