WO2020252756A1 - 像素电路、图像传感器和电子设备 - Google Patents

像素电路、图像传感器和电子设备 Download PDF

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Publication number
WO2020252756A1
WO2020252756A1 PCT/CN2019/092154 CN2019092154W WO2020252756A1 WO 2020252756 A1 WO2020252756 A1 WO 2020252756A1 CN 2019092154 W CN2019092154 W CN 2019092154W WO 2020252756 A1 WO2020252756 A1 WO 2020252756A1
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Prior art keywords
switch
capacitor
pixel circuit
photodiode
voltage
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PCT/CN2019/092154
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English (en)
French (fr)
Inventor
李亮
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2019/092154 priority Critical patent/WO2020252756A1/zh
Priority to CN201980002460.9A priority patent/CN110771154B/zh
Publication of WO2020252756A1 publication Critical patent/WO2020252756A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements

Definitions

  • the embodiments of the present application relate to the technical field of pixel circuits, and more specifically, to a pixel circuit, an image sensor, and an electronic device.
  • the image sensor is a device that converts light signals into electrical signals.
  • An image sensor usually includes a pixel circuit, a readout circuit, an analog-to-digital conversion circuit, and a digital processing circuit.
  • the pixel circuit can convert the sensed light signal into an electrical signal and then input it into the readout circuit.
  • the readout circuit can convert the pixel
  • the electrical signal output by the circuit is amplified and read out
  • the analog-to-digital conversion circuit can convert the analog signal output by the read-out circuit into a digital signal
  • the digital processing circuit can perform arithmetic processing on the digital signal output by the analog-to-digital conversion circuit.
  • the pixel circuit includes a photodiode.
  • the device performance of the photodiode is closely related to the performance of the image sensor. The better the device performance of the photodiode, the better the upper limit of the performance of the image sensor. Therefore, after designing a photodiode, how to make it work in a state of excellent device performance is an urgent problem to be solved.
  • the embodiments of the present application provide a pixel circuit, an image sensor, and an electronic device, which can make the photodiode work in a state with excellent device performance.
  • a pixel circuit including: a photodiode, an integrating circuit, a first capacitor, and a first switch; wherein both ends of the first capacitor are connected to the negative terminal of the photodiode and the The input terminal of the integrating circuit; the first switch is arranged between the negative terminal of the photodiode and the voltage source; the positive terminal of the photodiode is grounded.
  • the voltage source charges the first capacitor; when the first switch is turned off, the first capacitor is used to maintain the The negative terminal voltage of the photodiode.
  • the capacitance of the first capacitor is greater than a preset capacitance, and the preset capacitance is used to ensure that the variation of the negative terminal voltage of the photodiode is within a target range.
  • the sum of the capacitances of the first capacitor and the parasitic capacitor of the photodiode is greater than a preset capacitance, and the preset capacitance is used to ensure that the negative terminal voltage of the photodiode varies within Within the target range.
  • the integration circuit includes: an operational amplifier, a first integration capacitor, and a second switch; wherein, two plates of the first integration capacitor are respectively connected to the input terminal and At the output end, both ends of the second switch are respectively connected to the two plates of the first integrating capacitor.
  • the output voltage of the pixel circuit satisfies:
  • V OUT is the output voltage of the pixel circuit
  • I PD and I D are the photocurrent and dark current of the photodiode, respectively
  • C p is the capacitance of the parasitic capacitor of the photodiode
  • C 1 is the first The capacitance of a capacitor
  • C F is the capacitance of the first integrating capacitor
  • V CM is the common mode voltage of the operational amplifier.
  • the switch states of the first switch and the second switch are the same.
  • the integration circuit includes: a first metal-oxide-semiconductor MOS tube, a second MOS tube, a second integration capacitor, a third switch, a fourth switch, and a fifth switch;
  • the drain of the first MOS tube is connected to the source of the second MOS tube, the source of the first MOS tube is grounded, and the gate of the first MOS tube is connected to the second integrating capacitor.
  • the left plate of the first capacitor is connected to the right plate of the first capacitor, the two ends of the fourth switch are respectively connected to the drain of the second MOS transistor and the right end of the third switch, and the third Both ends of the switch are respectively connected to the right plate of the second integrating capacitor and the output end of the pixel circuit, and both ends of the fifth switch are respectively connected to the left plate of the second integrating capacitor and the output end of the pixel circuit.
  • the right end of the third switch is connected to the source of the second MOS tube, the source of the first MOS tube is grounded, and the gate of the first MOS tube is connected to the second integrating capacitor.
  • the left plate of the first capacitor is connected to the right plate of the first capacitor
  • the two ends of the fourth switch are respectively connected to the drain of the second MOS transistor and the right end of the
  • the switch states of the first switch and the fifth switch are the same, and the switch states of the third switch and the fourth switch are the same.
  • an image sensor including the pixel circuit in the first aspect or any possible implementation of the first aspect.
  • an electronic device including the pixel circuit in the first aspect or any possible implementation of the first aspect.
  • the pixel circuit includes a first capacitor and a first switch, both ends of the first capacitor are respectively connected to the negative terminal of the photodiode and the input terminal of the integrating circuit, and the first switch is arranged at the negative terminal of the photodiode and the voltage source between.
  • the first switch when the first switch is turned on, the negative terminal voltage of the photodiode is the same as the voltage of the voltage source; and when the first switch is turned off, if the value of the first capacitor is larger, the negative terminal voltage of the photodiode can be Approximately equal to the voltage of the voltage source.
  • the negative terminal voltage of the photodiode is not limited by the integration circuit, so that the negative terminal voltage of the photodiode can be selected arbitrarily, and a suitable negative terminal voltage can make the photodiode work in a state with excellent device performance.
  • FIG. 1 is a schematic diagram of the structure of a conventional pixel circuit.
  • FIG. 2 is a schematic structural diagram of a pixel circuit of an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a super pixel circuit of an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of an application manner of the pixel circuit shown in FIG. 4 according to an embodiment of the present application.
  • FIG. 7 is a timing diagram of a control method corresponding to the pixel circuit shown in FIG. 4 and FIG. 5.
  • FIG. 8 is a schematic structural diagram of a readout circuit applicable to an embodiment of the present application.
  • Fig. 9 is a schematic block diagram of an electronic device according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of the structure of a conventional pixel circuit 100.
  • the pixel circuit 100 can be mainly composed of the following four parts: 1Photo-Diode (PD), where the photo-diode can convert an optical signal into a voltage signal; 2Integrating capacitor C F , integrating capacitor C F of capacitance C F; 3 op amp (operational amplifier, OPA), OPA gain of -A, a is ideally ⁇ , the input voltage of the OPA is V I, the output voltage V OUT; 4 reset switch SW, Its control signal is CLK R.
  • PD Photo-Diode
  • OPA operational amplifier
  • the names of the pixel circuit and the photodiode are not limited in the embodiments of the present application, that is, they can also be expressed as other names.
  • the pixel circuit can also be expressed as a pixel sensing unit circuit
  • the photodiode can also be expressed as a photosensitive diode, a photosensitive diode, and the like.
  • the embodiment of the present application defines that SW is turned on when CLK R is at a high level.
  • the photodiode is equivalent to the photocurrent I PD , the dark current I D and the parasitic capacitor C P , and the capacitance of the parasitic capacitor C P is C P.
  • C P includes the input parasitic capacitance of OPA, and the magnitude of the photocurrent I PD is positively correlated with the intensity of the optical signal, that is, the stronger the optical signal, the greater the photocurrent I PD .
  • dark current I D of the photodiode material size and operating temperature and other factors. It should be understood, in the absence of light, the dark current I D also exist.
  • the pixel circuit 100 has 2 phases:
  • the feedback may cause the OPA input voltage V I and the output voltage V OUT in the ideal case where the common-mode voltage were maintained. Assuming that the common mode voltage of the OPA is V CM , the charge stored on the parasitic capacitor C P is V CM *C P , and the charge stored on the integrating capacitor C F is zero.
  • the pixel circuit 100 can be in the reset phase first, and then switch from the reset phase to the integration phase to work.
  • the feedback may cause the OPA in the input voltage V I ideally maintaining the common mode voltage V at the CM charge, stored on a parasitic capacitor C P is V CM * C P, I PD photocurrent and the dark current I D can be Integration is performed on the integrating capacitor C F.
  • V OUT is the photoelectric signal output by the pixel circuit 100
  • t is the integration time
  • t ⁇ 0 It can be seen from formula (2) that adjusting C F can change the integration speed. Since the magnitude of the photocurrent I PD is positively correlated with the intensity of the optical signal, the V OUT of the integrated phase can reflect the magnitude of the optical signal.
  • the reverse bias voltage of the photodiode is the voltage difference between the negative terminal voltage and the positive terminal voltage of the photodiode. It can be seen that, in the pixel circuit 100, the negative terminal voltage of the photodiode is always V CM and the positive terminal voltage is always the ground voltage, so its reverse bias voltage is V CM .
  • the device performance of a photodiode is extremely related to its reverse bias voltage. For example, Full-Well Capacity (FWC) is the maximum number of electrons that a photodiode can hold during exposure. The greater the negative terminal voltage of the photodiode, the greater the full-well capacity.
  • FWC Full-Well Capacity
  • the OPA design may limit the value range of V CM , thereby limiting the value range of the reverse bias voltage of the photodiode, making the photodiode unable to work in a state with excellent device performance.
  • the reverse bias voltage of the photodiode may also be referred to as the negative terminal voltage of the photodiode or other names.
  • the embodiments of the present application propose a new pixel circuit, so that the reverse bias voltage of the photodiode can be selected arbitrarily, so that the photodiode can work in a state with excellent device performance.
  • FIG. 2 shows a schematic diagram of a pixel circuit 200 according to an embodiment of the present application.
  • the pixel circuit 200 may include a photodiode 210, an integration circuit 220, a first capacitor 230, and a first switch 240.
  • both ends of the first capacitor 230 are respectively connected to the negative terminal of the photodiode 210 and the input terminal of the integrating circuit 220, the first switch 240 is arranged between the negative terminal of the photodiode 210 and the voltage source, and the positive terminal of the photodiode 210 Ground.
  • the voltage source can charge the first capacitor 230; when the first switch 240 is turned off, the first capacitor 230 can be used to maintain the negative terminal voltage of the photodiode 210.
  • the pixel circuit includes a first capacitor and a first switch, both ends of the first capacitor are connected to the negative terminal of the photodiode and the input terminal of the integrating circuit, and the first switch is arranged at the negative terminal of the photodiode Between and voltage source.
  • the negative terminal voltage of the photodiode is the same as the voltage of the voltage source (ie, V REF ), and the voltage of the voltage source is not limited by the integrating circuit. Therefore, the reverse bias voltage of the photodiode 210 can be arbitrarily selected, and an appropriate reverse bias voltage can make the photodiode work in a state with excellent device performance.
  • the pixel circuit 200 of the embodiment of the present application may be a single pixel circuit, or may be a sub-pixel circuit in a super pixel circuit. Among them, one super pixel circuit may include multiple sub pixel circuits.
  • Figure 3 shows a schematic diagram of a superpixel circuit.
  • the super pixel circuit in FIG. 3 includes X sub-pixel circuits, and the output photoelectric signal of the sub-pixel circuit 1 is V PO1 ... the output photoelectric signal of the sub-pixel circuit X is V POX .
  • the pixel circuit 200 of the embodiment of the present application may be any one of the X sub-pixel circuits.
  • the pixel circuit 200 of the embodiment of the present application can be applied to the field of integrated circuits.
  • the pixel circuit 200 may be applied to an image sensor.
  • the image sensor may be an optical fingerprint sensor.
  • the image sensor can also be called an image sensor chip or other names, and the optical fingerprint sensor can also be called a fingerprint sensor, a light sensor, or a fingerprint sensor chip.
  • the capacitance of the first capacitor 230 may be greater than a preset capacitance.
  • the capacitance of the first capacitor 230 may be 10 pF.
  • the sum of the capacitance of the first capacitor 230 and the capacitance of the parasitic capacitor of the photodiode 210 may be greater than a preset capacitance.
  • the preset capacitance can ensure that the variation of the negative terminal voltage of the photodiode 210 is within the target range.
  • the preset capacitance can ensure that the negative terminal voltage of the photodiode 210 is V REF , or the preset capacitance can ensure that the negative terminal voltage of the photodiode 210 is slightly greater than or slightly less than V REF .
  • the reverse bias voltage of the photodiode 210 can be arbitrarily selected, and an appropriate reverse bias voltage can make the photodiode work in a state with excellent device performance.
  • the integration circuit 220 may include: an operational amplifier, a first integration capacitor, and a second switch.
  • the two plates of the first integrating capacitor can be respectively connected to the input terminal and the output terminal of the operational amplifier, and the two ends of the second switch can be respectively connected to the two plates of the first integrating capacitor.
  • the structure diagram of the pixel circuit 200 may be as shown in FIG. 4.
  • PD is a photodiode 210
  • C 1 is a first capacitor 230
  • SW 2 is a first switch
  • C F is a first integrating capacitor
  • SW 1 is a second switch.
  • the switch states of the second switch and the first switch may be the same, that is, when the first switch is turned on, the second switch is also turned on, and when the first switch is turned off, the second switch is also turned off.
  • control signals of the first switch and the second switch may be the same control signal. As shown in FIG. 4, the control signals of the first switch and the second switch are both CLK R.
  • control signals of the first switch and the second switch may be different.
  • the control signal of the first switch controls the conduction of the first switch
  • the control signal of the second switch also controls the conduction of the second switch
  • the control signal of the second switch also controls the second switch to turn off.
  • the gain of the operational amplifier OPA in Figure 4 is -A, ideally A is ⁇ , its input voltage is V I , and its output voltage is V OUT .
  • the control signals of the second switch SW 1 and the first switch SW 2 are both CLK R , the negative terminal voltage of the photodiode is V 0 , the capacitance of the first capacitor C 1 is C 1 , and the capacitance of the first integrating capacitor C F is C F , the voltage of the voltage source is V REF .
  • both the second switch SW 1 and the first switch SW 2 are defined as being turned on when the control signal is high.
  • the photodiode is equivalent to the photocurrent I PD , the dark current I D and the parasitic capacitor C P , and the capacitance of the parasitic capacitor C P is C P.
  • C P includes the input parasitic capacitance of OPA, and the magnitude of the photocurrent I PD is positively correlated with the intensity of the optical signal.
  • the pixel circuit 200 has 2 phases:
  • the pixel circuit 200 can be in the reset phase first, and then switch from the reset phase to the integration phase to work.
  • the negative terminal voltage of the photodiode in the integration phase is approximately equal to V REF , and the V REF voltage is not limited by the operational amplifier. Therefore, the negative terminal voltage of the photodiode can be arbitrarily selected, and a suitable negative terminal voltage can make the photodiode work in a state with excellent device performance.
  • V OUT is the photoelectric signal output by the pixel circuit 200
  • t is the integration time
  • t ⁇ 0 It can be seen from formula (6) that adjusting C F and C 1 can change the integration speed. Since the magnitude of the photocurrent I PD is positively correlated with the intensity of the optical signal, the V OUT of the integrated phase can reflect the magnitude of the optical signal. That is, the higher the intensity of the optical signal, the greater the V OUT .
  • the reset phase and the integration phase are only for distinguishing the different states of the pixel circuit 200, and do not impose any limitation on the scope of the embodiment of the present application.
  • the two different phases of the pixel circuit 200 The phase state can also be expressed by other names.
  • the reset phase and the integration phase may also be referred to as phase 1 and phase 2.
  • the pixel circuit of the embodiment of the present application has no special requirements on the structure of the operational amplifier, and the operational amplifier may be, for example, a double-ended input operational amplifier, a rail-to-rail operational amplifier, a fully differential operational amplifier, etc. Therefore, the pixel circuit of the embodiment of the present application can be widely used in the design of existing image sensors.
  • the integration circuit 220 may include: a first metal-oxide-semiconductor (MOS) tube, a second MOS tube, a second integrating capacitor, a third switch, and a fourth Switch and fifth switch.
  • MOS metal-oxide-semiconductor
  • the drain of the first MOS transistor is connected to the source of the second MOS transistor, the source of the first MOS transistor is grounded, and the gate of the first MOS transistor and the left plate of the second integrating capacitor are respectively connected to the first capacitor Right electrode plate connection, both ends of the fourth switch are respectively connected to the drain of the second MOS tube and the right end of the third switch, both ends of the third switch are respectively connected to the right electrode plate of the second integrating capacitor and the output of the pixel circuit The two ends of the fifth switch are respectively connected to the left plate of the second integrating capacitor and the right end of the fourth switch.
  • the switching states of the first switch and the fifth switch may be the same, and the switching states of the third switch and the fourth switch may be the same.
  • the control signals of the first switch and the fifth switch may be the same control signal
  • the control signals of the third switch and the fourth switch may be the same control signal.
  • the switch states of the first switch and the fifth switch may not be controlled by the same control signal.
  • the switch states of the third switch and the fourth switch may not be controlled by the same control signal. As long as the switching states of the first switch and the fifth switch are the same, and the switching states of the third switch and the fourth switch are the same.
  • a schematic diagram of a possible pixel circuit 200 may be as shown in FIG. 5.
  • MN 1 is the first MOS tube
  • MN 2 is the second MOS tube
  • the capacitance of the second integrating capacitor C F is C F
  • SW 3 is the third switch
  • SW 4 is the fourth switch
  • SW 1 is the first switch. Five switches. It can be seen that MN 1 and MN 2 form a cascode amplifier.
  • FIG. 6 is a schematic diagram of a possible application manner of the pixel circuit 200 shown in FIG. 5.
  • FIG. 6 includes: n pixel circuits, pixel circuit 1 to pixel circuit n, and a current source I BP .
  • n pixel circuits share a current source I BP
  • the current source I BP can form n operational amplifiers with n pixel circuits respectively, and these n operational amplifiers have the same output voltage V OUT .
  • the structure of each of the pixel circuits 1 to n is the same as the circuit structure of the pixel circuit 200 shown in FIG. 5.
  • the control signals of the first switch SW 21 and the fifth switch SW 21 in the pixel circuit 1 are both CLK R1
  • the control signals of the third switch SW 31 and the fourth switch SW 31 are both CLK RS1
  • the negative terminal voltage of the photodiode PD 1 is V 01
  • the voltage of the voltage source is V REF .
  • the operational amplifier 0 shown in FIG. 6 can be composed of two parts: one part is the current source I BP , and the other part is the first MOS tube MN 11 , the second MOS tube MN 21 , the third switch SW 3 and the second part of the pixel circuit 1 Four switches SW 4 .
  • the gain of operational amplifier 0 is ⁇
  • its input voltage is V I0
  • its output voltage is V OUT .
  • the device definitions of the pixel circuit 2 and the pixel circuit n are similar to those of the pixel circuit 1. For details, reference may be made to the description of the pixel circuit 1. For the sake of brevity, the details are not repeated here.
  • FIG. 7 shows a timing diagram of a control method corresponding to the pixel circuit shown in FIG. 6.
  • the working principle of the pixel circuit will be described in detail below in conjunction with FIG. 7.
  • all of the aforementioned switches are defined as being turned on when the control signal is high.
  • the photodiode PD 1 is equivalent to the photocurrent I PD1 , the dark current I D1 and the parasitic capacitor C P1 .
  • the capacitance of the parasitic capacitor C P1 is C P1
  • C P1 may include the input parasitic capacitance of the operational amplifier 0, and the magnitude of the photocurrent I PD1 is positively correlated with the intensity of the optical signal.
  • the photodiodes PD 2 , PD 3 ... PD n adopt a similar approximation to PD 1 .
  • the photodiode PD 2 can be equivalent to the photocurrent I PD2 , the dark current I D2 and the parasitic capacitor C P2 .
  • the negative terminal voltage V 01 of the photodiode PD 1 is the same as V REF , and the feedback can make the input voltage V I1 and the output voltage V OUT of the operational amplifier 0 maintain the common-mode voltage under ideal conditions.
  • the common-mode voltage of operational amplifier 0 is V CM
  • the charge stored on the parasitic capacitor C P1 can be V REF *C P1
  • the charge stored on the first capacitor C 11 can be (V REF -V CM )*C 11
  • the charge stored on the second integrating capacitor C F1 is zero.
  • V 01 in the formula (8) is the negative terminal voltage of the photodiode PD1 from t2 to t3.
  • V OUT in the formula (10) is the photoelectric signal output by the pixel circuit 1 during the period t2 to t3.
  • the negative terminal voltage V 01 of the photodiode PD1 from t3 to t7 can be obtained as:
  • the negative terminal voltage V 01 of the photodiode PD1 from t7 to t8 can be solved as:
  • the photoelectric signal V OUT output by the pixel circuit 1 from t7 to t8 can be obtained as:
  • the photoelectric signal V OUT output by the pixel circuit n during the period t10 to t11 can be obtained as:
  • the negative terminal voltages of the photodiodes PD 1 , PD 2 ... PD n in phase 2 are always V REF .
  • the capacitances of the parasitic capacitor C P and the first capacitor C 1 are larger, then according to formula (12), it can be seen that the negative terminal voltage of the photodiodes PD 1 , PD 2 ... PD n is approximately equal to V REF ;
  • the negative terminal voltage of the photodiodes PD 1 , PD 2 ... PD n in phase 1 is approximately equal to V REF , and the V REF voltage is not limited by the operational amplifier. Therefore, the negative terminal voltage of the photodiode can be arbitrarily selected, and a suitable negative terminal voltage can make the photodiode work in a state with excellent device performance.
  • the reset phase and the integration phase in the foregoing content are only for distinguishing different states of the pixel circuit, and do not impose any limitation on the scope of the embodiments of the present application.
  • the reset phase and the integration phase may also be referred to as phase 1 and phase 2.
  • the pixel circuit outputs the photoelectric signal, and the readout circuit can read the photoelectric signal output by the pixel circuit. It should be understood that the pixel circuit of the embodiment of the present application has no special requirements on the readout circuit, and any readout circuit can be applied to the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a possible readout circuit 400 according to an embodiment of the application.
  • the readout circuit 400 may be mainly composed of the following parts:
  • the input capacitor array may include capacitor bank 11 to capacitor bank 1S.
  • Capacitor bank 11 includes input capacitor C c1 and switch SW c1
  • capacitor bank 12 includes input capacitor C c2 and switch SW c2
  • Capacitor bank 1S includes input capacitor C cS And switch SW cS .
  • the input capacitor C c1 , the input capacitor C c2 ... the capacitances of the input capacitor C cS are C c1 , C c2 ... C cS, respectively .
  • the control signal of the capacitor bank switch SW 1 is CLK P1
  • the control signal of the capacitor bank switch SW 2 is CLK P2 ...
  • the control signal of the capacitor bank switch SW S is CLK PS .
  • the output circuit may be composed of a feedback capacitor C cF , an operational amplifier, a sampling switch SW S+1 , a first holding switch SW S+2 and a second holding switch SW S+3 .
  • the gain of the operational amplifier is -A, ideally A is ⁇ , the input voltage of the operational amplifier is V CI , and the output voltage is V O.
  • the control signal of the sampling switch SW S+1 is CLK S
  • the control signal of the first holding switch SW S+2 is CLK H1
  • the control signal of the second holding switch SW S+3 is CLK H2 .
  • the number of input capacitors in the input capacitor array may be less than or equal to the number of pixel circuits in one direction in the image sensor.
  • the pixel circuits in one direction may be pixel circuits in the same row or in the same column in the image sensor.
  • the input voltages V IN1 , V IN2 ... V INS in the readout circuit 400 are photoelectric signals output by S pixel circuits in one direction in the image sensor, that is, the output of the pixel circuit is the input of the readout circuit.
  • the readout circuit 400 can simultaneously store the photoelectric signals of the S pixel circuits independently, and at this time, all the switches in the input capacitor array are turned on. Then the photoelectric signals of the S pixel circuits are amplified and output one by one.
  • the switch corresponding to the capacitor 13 is turned on, and other switches in the input capacitor array are turned off.
  • the readout circuit simultaneously stores the output signals of the S pixel circuits independently, and then amplifies and outputs them one by one, so that the pixel circuits of S rows (or S columns) can share one readout circuit.
  • the image sensor may need m/S readout circuits, or n/S readout circuits, thereby reducing the area and power consumption of the image sensor.
  • the pixel circuit includes a first capacitor and a first switch.
  • the two ends of the first capacitor are respectively connected to the negative terminal of the photodiode and the input terminal of the integrating circuit.
  • the first switch is arranged at the negative terminal of the photodiode and the voltage Between sources. In this way, when the first switch is turned on, the negative terminal voltage of the photodiode is the same as the voltage of the voltage source; and when the first switch is turned off, if the value of the first capacitor is larger, the negative terminal voltage of the photodiode can be Approximately equal to the voltage of the voltage source.
  • the reverse bias voltage of the photodiode is not limited by the integration circuit, so that the reverse bias voltage of the photodiode can be selected arbitrarily, and the appropriate reverse bias voltage can make the photodiode work in a state with excellent device performance.
  • the embodiment of the present application also provides an image sensor for converting light signals into electrical signals.
  • the image sensor may include a pixel circuit.
  • the pixel circuit may be the pixel circuit 200 in the foregoing embodiment, and the corresponding operation of the pixel circuit 200 can be implemented. For the sake of brevity, it will not be repeated here.
  • the readout circuit of the embodiment of the present application can be applied to various electronic devices, such as portable or mobile computing devices such as smart phones, notebook computers, tablet computers, and game devices, as well as electronic databases, automobiles, and bank automated teller machines (Automated Teller). Machine, ATM) and other electronic devices, which are not limited in the embodiment of the present application.
  • portable or mobile computing devices such as smart phones, notebook computers, tablet computers, and game devices
  • electronic databases such as automobiles, and bank automated teller machines (Automated Teller). Machine, ATM) and other electronic devices, which are not limited in the embodiment of the present application.
  • an embodiment of the present application also provides an electronic device 500.
  • the electronic device 500 may include a pixel circuit 510.
  • the pixel circuit 510 may be the pixel circuit 200 in the foregoing embodiment, and the corresponding operation of the pixel circuit 200 can be implemented. For the sake of brevity, it will not be repeated here.
  • the electronic device may further include a display screen 520.
  • the display screen 520 may be a display screen with a self-luminous display unit, such as an Organic Light-Emitting Diode (OLED) display screen or a Micro-LED (Micro-LED) display screen.
  • OLED Organic Light-Emitting Diode
  • Micro-LED Micro-LED
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

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Abstract

本申请实施例提供了一种像素电路、图像传感器和电子设备，能够使光电二极管工作在器件性能优秀的状态。该像素电路包括：光电二极管、积分电路、第一电容器和第一开关；其中，第一电容器的两端分别连接至光电二极管的负端和积分电路的输入端；第一开关设置于光电二极管的负端与电压源之间；光电二极管的正端接地。

Description

像素电路、图像传感器和电子设备 技术领域
本申请实施例涉及像素电路技术领域，并且更具体地，涉及一种像素电路、图像传感器和电子设备。
背景技术
图像传感器是一种将光信号转换成电信号的装置。图像传感器通常包括像素电路、读出电路、模数转换电路和数字处理电路，其中，像素电路可以将感受到的光信号转换成电信号后，输入到读出电路中，读出电路可以将像素电路输出的电信号放大和读出，模数转换电路可以将读出电路输出的模拟信号转换为数字信号，数字处理电路可以对模数转换电路输出的数字信号进行算法处理。
像素电路中包括光电二极管，其中，光电二极管的器件性能与图像传感器的性能紧密相关，光电二极管的器件性能越好，则图像传感器的性能上限越好。因此，设计好一个光电二极管之后，如何使它工作在器件性能优秀的状态，是一项亟待解决的问题。
发明内容
本申请实施例提供一种像素电路、图像传感器和电子设备，能够使光电二极管工作在器件性能优秀的状态。
第一方面，提供了一种像素电路，包括：光电二极管、积分电路、第一电容器和第一开关；其中，所述第一电容器的两端分别连接至所述光电二极管的负端和所述积分电路的输入端；所述第一开关设置于所述光电二极管的负端与电压源之间；所述光电二极管的正端接地。
在一些可能的实施例中，在所述第一开关导通时，所述电压源对所述第一电容器进行充电；在所述第一开关断开时，所述第一电容器用于维持所述光电二极管的负端电压。
在一些可能的实施例中，所述第一电容器的电容大于预设电容，所述预设电容用于保证所述光电二极管的负端电压的变化量在目标范围内。
在一些可能的实施例中，所述第一电容器和所述光电二极管的寄生电容 器的电容之和大于预设电容，所述预设电容用于保证所述光电二极管的负端电压的变化量在目标范围内。
在一些可能的实施例中，所述积分电路包括：运算放大器、第一积分电容器和第二开关；其中，所述第一积分电容器的两个极板分别连接至所述运算放大器的输入端和输出端，所述第二开关的两端分别连接至所述第一积分电容器的两个极板。
在一些可能的实施例中，所述像素电路的输出电压满足：
Figure PCTCN2019092154-appb-000001
其中，V OUT为所述像素电路的输出电压，I PD和I D分别为所述光电二极管的光电流和暗电流，C p为所述光电二极管的寄生电容器的电容，C 1为所述第一电容器的电容，C F为所述第一积分电容器的电容，V CM为所述运算放大器的共模电压。
在一些可能的实施例中，所述第一开关和所述第二开关的开关状态相同。
在一些可能的实施例中，所述积分电路包括：第一金属-氧化物-半导体MOS管、第二MOS管、第二积分电容器、第三开关、第四开关和第五开关；
其中，所述第一MOS管的漏极与所述第二MOS管的源极连接，所述第一MOS管的源极接地，所述第一MOS管的栅极和所述第二积分电容器的左极板分别与所述第一电容器的右极板连接，所述第四开关的两端分别连接至所述第二MOS管的漏极和所述第三开关的右端，所述第三开关的两端分别连接至所述第二积分电容器的右极板和所述像素电路的输出端，所述第五开关的两端分别连接至所述第二积分电容器的左极板和所述第三开关的右端。
在一些可能的实施例中，所述第一开关和所述第五开关的开关状态相同，所述第三开关和所述第四开关的开关状态相同。
第二方面，提供了一种图像传感器，包括第一方面或第一方面的任意可能的实现方式中的像素电路。
第三方面，提供了一种电子设备，包括第一方面或第一方面的任意可能的实现方式中的像素电路。
上述技术方案，像素电路中包括第一电容器和第一开关，第一电容器的 两端分别连接至光电二极管的负端和积分电路的输入端，第一开关设置于光电二极管的负端与电压源之间。如此，在第一开关导通时，光电二极管的负端电压与电压源的电压相同；并且，在第一开关断开时，若第一电容器的取值较大，光电二极管的负端电压可以约等于电压源的电压。从而光电二极管的负端电压可以不受积分电路的限制，使得光电二极管的负端电压可以任意选取，合适的负端电压可以让光电二极管工作在器件性能优秀的状态。
附图说明
图1是现有的一种像素电路的结构示意图。
图2是本申请实施例的像素电路的结构示意图。
图3是本申请实施例的超像素电路的结构示意图。
图4是本申请实施例的一种像素电路的结构示意图。
图5是本申请实施例的另一种像素电路的结构示意图。
图6是本申请实施例的图4所示的像素电路的一种应用方式示意图。
图7是图4和图5所示的像素电路对应的控制方式时序图。
图8是本申请实施例适用的一种读出电路的结构示意图。
图9是本申请实施例的电子设备的示意性框图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
图1是一种现有的像素电路100的结构示意图。在图1中，像素电路100主要可以由以下4个部分构成：①光电二极管(Photo-Diode，PD)，其中，光电二极管可以将光信号转换成电压信号；②积分电容器C F，积分电容器C F的电容为C F；③运算放大器(Operational Amplifier，OPA)，OPA的增益为-A，理想情况下A为∞，OPA的输入电压为V I，输出电压为V OUT；④复位开关SW，它的控制信号为CLK R。
应理解，在本申请实施例对像素电路和光电二极管的名称并不限定，也就是说，他们也可以表述为其他名称。例如，像素电路也可以表述为像素传感单元电路，光电二极管也可以表述为感光二极管、光敏二极管等。
下面对像素电路100的工作原理进行描述。为了便于描述，本申请实施例定义CLK R为高电平时SW导通。为了便于分析，将光电二极管等效为光 电流I PD、暗电流I D以及寄生电容器C P，寄生电容器C P的电容为C P。其中，C P包括OPA的输入寄生电容，光电流I PD的大小与光信号的强度正相关，即光信号越强，光电流I PD越大。暗电流I D与光电二极管的材料、尺寸和工作温度等因素有关。应理解，在没有光照时，暗电流I D也是存在的。
像素电路100共有2个相位：
当CLK R为高电平时，SW导通，像素电路100处于复位相位。此时，反馈可以使得理想情况下的OPA输入电压V I和输出电压V OUT均维持在共模电压。设OPA的共模电压为V CM，则寄生电容器C P上存储的电荷为V CM*C P，积分电容器C F上存储的电荷为0。
一般情况下，像素电路100首先可以处于复位相位，再从复位相位切换到积分相位进行工作。
当CLK R由高电平变为低电平时，SW断开，像素电路100进入积分相位。此时，反馈可以使得理想情况下的OPA输入电压V I维持在共模电压V CM，则寄生电容器C P上存储的电荷为V CM*C P，光电流I PD和暗电流I D可以在积分电容器C F上进行积分。
从复位相位切换到积分相位的过程中，寄生电容器C P的上极板以及积分电容器C F的左极板除了光电流I PD和暗电流I D以外没有任何电荷通路。设CLK R由高电平变为低电平的时刻为t＝0，根据电荷守恒原理有：
Figure PCTCN2019092154-appb-000002
由公式(1)可以解得：
Figure PCTCN2019092154-appb-000003
其中，V OUT为像素电路100输出的光电信号，t为积分时间且t≥0。从公式(2)中可以看到，调整C F可以改变积分的速度。由于光电流I PD的大小和光信号的强度正相关，因此积分相位的V OUT可以反映出光信号的大小。
光电二极管的反偏电压为光电二极管的负端电压与正端电压之间的电压差。可以看到，在像素电路100中，光电二极管的负端电压一直为V CM，正端电压一直为地电压，因此它的反偏电压为V CM。而光电二极管的器件性能与它的反偏电压大小极其相关。例如，满阱容量(Full-Well Capacity，FWC)为光电二极管曝光时最多可以容纳的电子数，光电二极管的负端电压越大， 满阱容量越大。
然而，很多情况下OPA的设计可能会限制V CM的取值范围，从而限值光电二极管的反偏电压的取值范围，使得光电二极管无法工作在器件性能优秀的状态。应理解，在本申请实施例中，光电二极管的反偏电压也可以称为光电二极管的负端电压或者其他名称。
为了解决上述问题，本申请实施例提出了一种新的像素电路，使得光电二极管的反偏电压可以任意选取，从而可以使光电二极管工作在器件性能优秀的状态。
图2示出了本申请实施例的像素电路200的示意图。如图2所示，像素电路200可以包括光电二极管210、积分电路220、第一电容器230和第一开关240。其中，第一电容器230的两端分别连接至光电二极管210的负端和积分电路220的输入端，第一开关240设置于光电二极管210的负端与电压源之间，光电二极管210的正端接地。
其中，第一开关240导通时，电压源可以对第一电容器230进行充电；在第一开关240断开时，第一电容器230可以用于维持光电二极管210的负端电压。
在本申请实施例中，像素电路中包括第一电容器和第一开关，第一电容器的两端分别连接至光电二极管的负端和积分电路的输入端，第一开关设置于光电二极管的负端与电压源之间。如此，在第一开关导通时，光电二极管的负端电压与电压源的电压(即V REF)相同，而电压源的电压不受积分电路的限制。因此，光电二极管210的反偏电压可以任意选取，合适的反偏电压可以让光电二极管工作在器件性能优秀的状态。
可选地，本申请实施例的像素电路200可以为单独的一个像素电路，也可以为一个超像素电路中的子像素电路。其中，一个超像素电路可以包括多个子像素电路。图3示出了超像素电路的示意图。图3中的超像素电路包括X个子像素电路，子像素电路1的输出光电信号为V PO1……子像素电路X的输出光电信号为V POX。本申请实施例的像素电路200可以为X个子像素电路中的任意一个子像素电路。
应理解，本申请实施例的像素电路200可以应用于集成电路领域。可选地，像素电路200可以应用于图像传感器。例如，图像传感器可以为光学指纹传感器。其中，图像传感器也可以称为图像传感器芯片或其他名称，光学 指纹传感器也可以称为指纹传感器、光传感器、指纹传感器芯片。
可选地，在本申请实施例中，第一电容器230的电容可以大于预设电容。示例性地，第一电容器230的电容可以为10pF。
或者，第一电容器230的电容和光电二极管210的寄生电容器的电容之和可以大于预设电容。其中，预设电容可以保证光电二极管210的负端电压的变化量在目标范围内。示例性地，预设电容可以保证光电二极管210的负端电压为V REF，或者，预设电容可以保证光电二极管210的负端电压略大于或略小于V REF。
如此，在第一开关240断开时，光电二极管210的负端电压的减少量可以忽略不计，光电二极管210的负端电压仍然约等于电压源的电压(即V REF)，而电压源的电压不受积分电路的限制。因此，光电二极管210的反偏电压可以任意选取，合适的反偏电压可以让光电二极管工作在器件性能优秀的状态。
可选地，在一些实施例中，积分电路220可以包括：运算放大器、第一积分电容器和第二开关。其中，第一积分电容器的两个极板可以分别连接至运算放大器的输入端和输出端，第二开关的两端分别可以连接至第一积分电容器的两个极板。
此时，像素电路200的结构示意图可以如图4所示。在图4中，PD为光电二极管210，C 1为第一电容器230，SW 2为第一开关，C F为第一积分电容器，SW 1为第二开关。
应理解，在本申请实施例中，“第一”和“第二”仅仅为了区分不同的对象，但并不对本申请实施例的范围构成限制。
可选地，第二开关和第一开关的开关状态可以相同，即第一开关导通时第二开关也导通，第一开关关断时第二开关也关断。
作为一种示例，第一开关和第二开关的控制信号可以为同一个控制信号。如图4所示，第一开关和第二开关的控制信号都为CLK R。
作为另一种示例，第一开关和第二开关的控制信号可以不同，第一开关的控制信号控制第一开关导通时，第二开关的控制信号也控制第二开关导通；第一开关的控制信号控制第一开关断开时，第二开关的控制信号也控制第二开关断开。
下面将详细介绍图4所示的像素电路200的工作原理。图4中的运算放 大器OPA的增益为-A，理想情况下A为∞，它的输入电压为V I，输出电压为V OUT。第二开关SW 1和第一开关SW 2的控制信号均为CLK R，光电二极管的负端电压为V 0，第一电容器C 1的电容为C 1，第一积分电容器C F的电容为C F，电压源的电压为V REF。
为了便于描述，第二开关SW 1和第一开关SW 2均定义为：控制信号高电平时导通。为了便于分析，将光电二极管等效为光电流I PD、暗电流I D以及寄生电容器C P，寄生电容器C P的电容为C P。其中C P包括OPA的输入寄生电容，光电流I PD的大小与光信号的强度正相关。
像素电路200共有2个相位：
当CLK R为高电平时，SW1和SW2均导通，像素电路200处于复位相位。此时，光电二极管的负端电压V 0与V REF相同。反馈可以使得理想情况下的OPA输入电压V I和输出电压V OUT均维持在共模电压。设OPA的共模电压为V CM，则寄生电容器C P上存储的电荷可以为V REF*C P，第一电容器C 1上存储的电荷可以为(V REF-V CM)*C 1，第一积分电容器C F上存储的电荷为0。
一般情况下，像素电路200首先可以处于复位相位，再从复位相位切换到积分相位进行工作。
当CLK R由高电平变为低电平时，SW1和SW2均断开，像素电路200进入积分相位。此时，反馈可以使得理想情况下的OPA输入电压V I维持在共模电压V CM，光电流I PD和暗电流I D可以在第一电容器C 1和寄生电容器C P上进行积分。
从复位相位切换到积分相位的过程中，寄生电容器C P的上极板以及第一电容器C 1的左极板除了光电流I PD和暗电流I D以外没有任何电荷通路。设CLK R由高电平变为低电平的时刻为t＝0，根据电荷守恒原理可以得到：
Figure PCTCN2019092154-appb-000004
由公式(3)可以解得光电二极管的负端电压V 0为：
Figure PCTCN2019092154-appb-000005
参考公式(4)，若寄生电容器C P和第一电容器C 1的取值较大，则积分相位下光电二极管的负端电压约等于V REF，而V REF电压不受运算放大器的 限制。因此，光电二极管的负端电压可以任意选取，合适的负端电压可以让光电二极管工作在器件性能优秀的状态。
从复位相位切换到积分相位的过程中，第一电容器C 1的右极板以及第一积分电容器C F的左极板外没有任何电荷通路，并且OPA的输入电压V I始终维持在V CM，因此根据电荷守恒原理有：
( V0-V CM)*C 1+(V OUT-V CM)*C F＝(V REF-V CM)*C 1        (5)
根据公式(4)和公式(5)可以得到：
Figure PCTCN2019092154-appb-000006
其中，V OUT为像素电路200输出的光电信号，t为积分时间且t≥0。从公式(6)中可以看到，调整C F和C 1可以改变积分的速度。由于光电流I PD的大小和光信号的强度正相关，因此积分相位的V OUT可以反映出光信号的大小。即光信号的强度越高，V OUT越大。
需要说明的是，在对像素电路200的描述中，复位相位和积分相位仅是为了区分像素电路200的不同状态，并不对本申请实施例的范围造成任何限制，像素电路200的两个不同的相位状态还可以表述为其他名称。例如，复位相位和积分相位也可以称为相位1和相位2。
应理解，本申请实施例的像素电路对运算放大器的结构没有特殊要求，运算放大器例如可以是双端输入运算放大器、轨到轨运算放大器、全差分运算放大器等。因此本申请实施例的像素电路可以广泛应用于现有的图像传感器的设计中。
可选地，在另一些实施例中，积分电路220可以包括：第一金属-氧化物-半导体(Metal Oxide Semiconductor，MOS)管、第二MOS管、第二积分电容器、第三开关、第四开关和第五开关。其中，第一MOS管的漏极与第二MOS管的源极连接，第一MOS管的源极接地，第一MOS管的栅极和第二积分电容器的左极板分别与第一电容器的右极板连接，第四开关的两端分别连接至第二MOS管的漏极和第三开关的右端，第三开关的两端分别连接至第二积分电容器的右极板和像素电路的输出端，第五开关的两端分别连接至第二积分电容器的左极板和第四开关的右端。
可选地，第一开关和第五开关的开关状态可以相同，第三开关和第四开关的开关状态可以相同。作为一种示例，第一开关和第五开关的控制信号可 以为同一个控制信号，第三开关和第四开关的控制信号可以为同一个控制信号。作为另一种示例，第一开关和第五开关的开关状态也可以不采用同一个控制信号进行控制，同样，第三开关和第四开关的开关状态也可以不采用同一个控制信号进行控制，只要第一开关和第五开关的开关状态相同，以及第三开关和第四开关的开关状态相同即可。
在该实施例中，一种可能的像素电路200的示意图可以如图5所示。图5中的MN 1为第一MOS管，MN 2为第二MOS管，第二积分电容器C F的电容为C F，SW 3为第三开关，SW 4为第四开关，SW 1为第五开关。可以看到，MN 1和MN 2组成了共源共栅放大器。
图6是图5所示的像素电路200的一种可能的应用方式示意图。图6包括：n个像素电路，分别为像素电路1至像素电路n，以及一个电流源I BP。其中：n个像素电路共用一个电流源I BP，电流源I BP可以分别和n个像素电路组成n个运算放大器，这n个运算放大器具有同样的输出电压V OUT。从图6中可以看到，像素电路1至像素电路n中的每个像素电路的结构都与图5所示的像素电路200的电路结构相同。
对于像素电路1来说，像素电路1中的第一开关SW 21和第五开关SW 21的控制信号均为CLK R1，第三开关SW 31和第四开关SW 31和的控制信号均为CLK RS1。光电二极管PD 1的负端电压为V 01，电压源的电压为V REF。图6所示的运算放大器0可以由两部分组成：一部分为电流源I BP，另一部分为像素电路1中的第一MOS管MN 11、第二MOS管MN 21、第三开关SW 3和第四开关SW 4。理想情况下运算放大器0的增益为∞，它的输入电压为V I0，输出电压为V OUT。
像素电路2、像素电路n的器件定义与像素电路1类似，具体可以参考像素电路1的描述，为了内容的简洁，此处不再赘述。
图7示出了图6所示的像素电路对应的控制方式时序图。下面将结合图7详细介绍像素电路的工作原理。为了便于描述，前述所有开关均定义为：控制信号高电平时导通。为了便于分析，将光电二极管PD 1等效为光电流I PD1、暗电流I D1以及寄生电容器C P1。其中，寄生电容器C P1的电容为C P1，C P1可以包括运算放大器0的输入寄生电容，光电流I PD1的大小与光信号的强度正相关。
应理解，光电二极管PD 2、PD 3……PD n采用与PD 1类似的近似。如光电 二极管PD 2可以等效为光电流I PD2、暗电流I D2以及寄生电容器C P2。
在t＝0时刻，CLK RS1从低电平变为高电平时，CLK R1为低电平，并且从t＝0至t1时段SW 11、SW 21、SW 31和SW 41的开关状态没有发生变化。因此，在t＝0至t1时段，SW 31和SW 41均导通，SW 11和SW 21均断开，像素电路1处于相位1。
在t1时刻，CLK R1从低电平变为高电平时，CLK RS1为高电平，并且从t1至t2时段SW 11、SW 21、SW 31和SW 41的开关状态没有发生变化。因此在t1至t2时段SW 11、SW 21、SW 31和SW 41均导通，像素电路1处于相位2。
光电二极管PD 1的负端电压V 01与V REF相同，反馈可以使得理想情况下运算放大器0的输入电压V I1和输出电压V OUT均维持在共模电压。设运算放大器0的共模电压为V CM，则寄生电容器C P1上存储的电荷可以为V REF*C P1，第一电容器C 11上存储的电荷可以为(V REF-V CM)*C 11，第二积分电容器C F1上存储的电荷为0。
在t2时刻，CLK R1从高电平变为低电平时，CLK RS1为高电平，并且从t2至t3时段SW 11、SW 21、SW 31和SW 41的开关状态没有发生变化。因此在t2至t3时段。SW 31和SW 41均导通，SW 11和SW 21均断开，像素电路1重新处于相位1。反馈可以使得理想情况下运算放大器0的输入电压V I1维持在共模电压V CM，光电流I PD1和暗电流I D1将会在第一电容器C 11和寄生电容器C P1上进行积分。
t2至t3时段寄生电容器C P1的上极板以及第一电容器C 11的左极板除了光电流I PD1和暗电流I D1以外没有任何电荷通路，根据电荷守恒原理可以得到t2至t3时段有：
Figure PCTCN2019092154-appb-000007
根据公式(7)可以解得：
Figure PCTCN2019092154-appb-000008
其中，公式(8)中的V 01为光电二极管PD1在t2至t3时段的负端电压。
t2至t3时段第一电容器C 11的右极板以及第二积分电容器C F1的左极板以外没有任何电荷通路，并且运算放大器0的输入电压V I1始终维持在V CM。 根据电荷守恒原理在t2至t3时段有：
(V 01-V CM)*C 11+(V OUT-V CM)*C F1＝(V REF-V CM)*C 11       (9)
根据公式(8)和公式(9)可以得到：
Figure PCTCN2019092154-appb-000009
其中，公式(10)中的V OUT为像素电路1在t2至t3时段输出的光电信号。
在t3时刻，CLK RS1从高电平变为低电平时，CLK R1为低电平，并且从t3至t7时段SW 11、SW 21、SW 31和SW 41的开关状态没有发生变化。因此在t3至t7时段SW 11、SW 21、SW 31和SW 41均断开，像素电路1处于相位3。运算放大器0的输入点为高阻态，光电流I PD1和暗电流I D1可以在寄生电容器C P1上进行积分，根据电荷守恒原理可以得到在t3至t7时段有：
Figure PCTCN2019092154-appb-000010
根据公式(11)可以得到光电二极管PD1在t3至t7时段的负端电压V 01为：
Figure PCTCN2019092154-appb-000011
在t7时刻，CLK RS1从低电平变为高电平时，CLK R1为低电平，并且从t7至t8时段SW 11、SW 21、SW 31和SW 41的开关状态没有发生变化。因此在t7至t8时段SW 31和SW 41均导通，SW 11和SW 21均断开，像素电路1再次处于相位1。反馈可以使得理想情况下运算放大器0的输入电压V I1维持在共模电压V CM，光电流I PD1和暗电流I D1可以在第一电容器C 11和寄生电容器C P1上进行积分。
t2至t8时段，寄生电容器C P1的上极板以及第一电容器C 11的左极板除了光电流I PD1和暗电流I D1以外没有任何电荷通路，并且在t7至t8时段运算放大器0的输入电压V I1始终维持在V CM，根据电荷守恒原理可以在t7至t8时段得到公式(7)。
根据公式(7)可以解得光电二极管PD1在t7至t8时段的负端电压V 01为：
Figure PCTCN2019092154-appb-000012
t2至t8时段的过程中，第一电容器C 11的右极板以及第二积分电容器C F1的左极板外没有任何电荷通路，并且在t7至t8时段运算放大器0的输入电压V I1始终维持在V CM，因此根据电荷守恒原理在t7至t8时段可以得到公式(9)。
结合公式(9)和公式(13)可以得到像素电路1在t7至t8时段输出的光电信号V OUT为：
Figure PCTCN2019092154-appb-000013
从公式(14)中可以看到，调整第二积分电容器C F1的电容和第一电容器C 11的电容可以改变积分的速度。由于光电流I PD1的大小和光信号的强度正相关，因此t7至t8时段的V OUT可以反映出光信号的大小。
类似地，在t3至t9时段可以对像素电路2进行与像素电路1在t＝0至t8时段相同的操作，从而可以得到像素电路2在t8至t9时段输出的光电信号V OUT为：
Figure PCTCN2019092154-appb-000014
从公式(15)中可以看到，调整像素电路2中的第二积分电容器C F2的电容和第一电容器C 12的电容可以改变积分的速度。由于光电流I PD2的大小和光信号的强度正相关，因此像素电路2在t8至t9时段输出的光电信号V OUT可以反映出光信号的大小。
同样，在t5至t11时段对像素电路n进行与像素电路1在t＝0至t8时段相同的操作，可以得到像素电路n在t10至t11时段输出的光电信号V OUT为：
Figure PCTCN2019092154-appb-000015
从公式(16)中可以看到，调整像素电路n中的第二积分电容器C Fn的电容和第一电容器C 1n的电容可以改变积分的速度。由于光电流I PDn的大小和光信号的强度正相关，因此t10至t11时段的V OUT可以反映出光信号的大小。
在图6中的像素电路中，相位2下的光电二极管PD 1、PD 2……PD n的负端电压均一直为V REF。此外，若寄生电容器C P和第一电容器C 1的电容取值较大，则根据公式(12)可以看出，相位3下光电二极管PD 1、PD 2……PD n的负端电压约等于V REF；根据公式(13)可以看出相位1下光电二极管PD 1、PD 2……PD n的负端电压约等于V REF，而V REF电压不受运算放大器的限制。因此，光电二极管的负端电压可以任意选取，合适的负端电压可以让光电二极管工作在器件性能优秀的状态。
需要说明的是，上述内容中的复位相位和积分相位仅是为了区分像素电路的不同状态，并不对本申请实施例的范围造成任何限制。例如，复位相位和积分相位也可以称为相位1和相位2。
在像素电路输出光电信号，读出电路可以将像素电路输出的光电信号读出。应理解，本申请实施例的像素电路对读出电路没有特殊要求，任何读出电路都可以应用于本申请实施例。
图8为本申请实施例的一种可能的读出电路400结构示意图。在图8中，读出电路400可以主要可以由以下部分构成：
(a)输入电容阵列。其中，输入电容阵列可以包括电容组11至电容组1S，电容组11包括输入电容器C c1和开关SW c1，电容组12包括输入电容器C c2和开关SW c2……电容组1S包括输入电容器C cS和开关SW cS。输入电容器C c1、输入电容器C c2……输入电容器C cS的电容分别为C c1、C c2……C cS。电容组开关SW 1的控制信号为CLK P1，电容组开关SW 2的控制信号为CLK P2……电容组开关SW S的控制信号为CLK PS。
(b)输出电路。其中，输出电路可以由反馈电容器C cF、运算放大器、采样开关SW S+1、第一保持开关SW S+2和第二保持开关SW S+3组成。运算放大器的增益为-A，理想情况下A为∞，运算放大器的输入电压为V CI，输出电压为V O。采样开关SW S+1的控制信号为CLK S，第一保持开关SW S+2的控制信号为CLK H1，第二保持开关SW S+3的控制信号为CLK H2。
可选地，在一些实施例中，输入电容阵列中输入电容器的数量可以小于或等于图像传感器中一个方向上的像素电路的数量。其中，一个方向上的像素电路可以为图像传感器中同一行的像素电路，或者同一列的像素电路。
其中，读出电路400中的输入电压V IN1、V IN2……V INS为图像传感器中一个方向上的S个像素电路输出的光电信号，即像素电路的输出为读出电路 的输入。
可选地，在一些实施例中，读出电路400可以同时对S个像素电路的光电信号进行独立的存储，此时，输入电容阵列中的所有开关导通。然后逐个对S个像素电路的光电信号进行放大和输出。
例如，当输出电路用于放大和输出电容器13存储的信号时，电容器13对应的开关导通，输入电容阵列中其他开关断开。
上述技术方案，读出电路同时对S个像素电路的输出信号进行独立的存储，然后逐个进行放大和输出，使得S行(或者S列)的像素电路可以共用一个读出电路。例如，当图像传感器中包括m*n个像素电路时，该图像传感器可以需要m/S个读出电路，或者n/S个读出电路，从而可以降低图像传感器的面积和功耗开销。
本申请实施例，像素电路中包括第一电容器和第一开关，第一电容器的两端分别连接至光电二极管的负端和积分电路的输入端，第一开关设置于光电二极管的负端与电压源之间。如此，在第一开关导通时，光电二极管的负端电压与电压源的电压相同；并且，在第一开关断开时，若第一电容器的取值较大，光电二极管的负端电压可以约等于电压源的电压。从而光电二极管的反偏电压可以不受积分电路的限制，使得光电二极管的反偏电压可以任意选取，合适的反偏电压可以让光电二极管工作在器件性能优秀的状态。
本申请实施例还提供了一种图像传感器，用于将光信号转换成电信号。
可选地，该图像传感器可以包括像素电路。该像素电路可以为前述实施例中的像素电路200，可以实现像素电路200的相应操作，为了简洁，在此不再赘述。
应理解，本申请实施例的读出电路可以应用于各种电子设备，例如智能手机、笔记本电脑、平板电脑、游戏设备等便携式或移动计算设备，以及电子数据库、汽车、银行自动柜员机(Automated Teller Machine，ATM)等其他电子设备，本申请实施例对此并不限定。
本申请实施例还提供了一种电子设备500，如图9所示，所述电子设备500可以包括像素电路510。该像素电路510可以为前述实施例中的像素电路200，可以实现像素电路200的相应操作，为了简洁，在此不再赘述。
可选地，电子设备还可以包括显示屏520。该显示屏520可以为具有自发光显示单元的显示屏，比如有机发光二极管(Organic Light-Emitting Diode， OLED)显示屏或者微型发光二极管(Micro-LED)显示屏。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围。
应理解，在本申请实施例和所附权利要求书中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请实施例。例如，在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“上述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请 的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (11)

  1. 一种像素电路，其特征在于，包括：
    光电二极管、积分电路、第一电容器和第一开关；
    其中，所述第一电容器的两端分别连接至所述光电二极管的负端和所述积分电路的输入端；
    所述第一开关设置于所述光电二极管的负端与电压源之间；
    所述光电二极管的正端接地。
  2. 根据权利要求1所述的像素电路，其特征在于，在所述第一开关导通时，所述电压源对所述第一电容器进行充电；
    在所述第一开关断开时，所述第一电容器用于维持所述光电二极管的负端电压。
  3. 根据权利要求1或2所述的像素电路，其特征在于，所述第一电容器的电容大于预设电容，所述预设电容用于保证所述光电二极管的负端电压的变化量在目标范围内。
  4. 根据权利要求1至3中任一项所述的像素电路，其特征在于，所述第一电容器和所述光电二极管的寄生电容器的电容之和大于预设电容，所述预设电容用于保证所述光电二极管的负端电压的变化量在目标范围内。
  5. 根据权利要求1至4中任一项像素电路，其特征在于，所述积分电路包括：
    运算放大器、第一积分电容器和第二开关；
    其中，所述第一积分电容器的两个极板分别连接至所述运算放大器的输入端和输出端，所述第二开关的两端分别连接至所述第一积分电容器的两个极板。
  6. 根据权利要求5所述的像素电路，其特征在于，所述像素电路的输出电压满足：
    Figure PCTCN2019092154-appb-100001
    其中，V OUT为所述像素电路的输出电压，I PD和I D分别为所述光电二极管的光电流和暗电流，C p为所述光电二极管的寄生电容器的电容，C 1为所述第一电容器的电容，C F为所述第一积分电容器的电容，V CM为所述运算放大器的共模电压。
  7. 根据权利要求5或6所述的像素电路，其特征在于，所述第一开关和所述第二开关的开关状态相同。
  8. 根据权利要求1至4中任一项所述的像素电路，其特征在于，所述积分电路包括：
    第一金属-氧化物-半导体MOS管、第二MOS管、第二积分电容器、第三开关、第四开关和第五开关；
    其中，所述第一MOS管的漏极与所述第二MOS管的源极连接，所述第一MOS管的源极接地，所述第一MOS管的栅极和所述第二积分电容器的左极板分别与所述第一电容器的右极板连接，所述第四开关的两端分别连接至所述第二MOS管的漏极和所述第三开关的右端，所述第三开关的两端分别连接至所述第二积分电容器的右极板和所述像素电路的输出端，所述第五开关的两端分别连接至所述第二积分电容器的左极板和所述第三开关的右端。
  9. 根据权利要求8所述的像素电路，其特征在于，所述第一开关和所述第五开关的开关状态相同，所述第三开关和所述第四开关的开关状态相同。
  10. 一种图像传感器，其特征在于，包括：根据权利要求1至9中任一项所述的像素电路。
  11. 一种电子设备，其特征在于，包括：根据权利要求1至9中任一项所述的像素电路。
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