WO2021035605A1 - 暗电流相关双采样器、图像传感器和暗电流补偿方法 - Google Patents

暗电流相关双采样器、图像传感器和暗电流补偿方法 Download PDF

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WO2021035605A1
WO2021035605A1 PCT/CN2019/103247 CN2019103247W WO2021035605A1 WO 2021035605 A1 WO2021035605 A1 WO 2021035605A1 CN 2019103247 W CN2019103247 W CN 2019103247W WO 2021035605 A1 WO2021035605 A1 WO 2021035605A1
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Prior art keywords
capacitors
dark current
switch
pixels
dark
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PCT/CN2019/103247
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English (en)
French (fr)
Inventor
王程左
詹昶
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深圳市汇顶科技股份有限公司
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Priority to CN201980004076.2A priority Critical patent/CN111095915B/zh
Priority to PCT/CN2019/103247 priority patent/WO2021035605A1/zh
Publication of WO2021035605A1 publication Critical patent/WO2021035605A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

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  • the embodiments of the present application relate to the field of CMOS image sensors, and more specifically, to a dark current correlation double sampler, an image sensor, and a dark current compensation method.
  • CMOS Complementary Metal Oxide Semiconductor
  • CIS Complementary Metal Oxide Semiconductor
  • dark current refers to the reverse current generated by a photodiode in a dark environment under reverse bias conditions. Generally it is caused by carrier diffusion movement, device surface, internal defects and harmful impurities. Therefore, the size of dark current is closely related to temperature, and the distribution on the spatial plane may be inconsistent and random.
  • the dark current limits the sensitivity, dynamic range and signal-to-noise ratio (SIGNAL-NOISE RATIO, SNR) of the image sensor, etc., so dark current compensation is required.
  • SIGNAL-NOISE RATIO SIGNAL-NOISE RATIO
  • the dark current compensation in the prior art eliminates the dark current in the pixel array through complex hardware circuits. For example, some dark pixels are set in the active pixel area, the active pixels and dark pixels are sampled by the dark current correlated double sampling (CDS), and the active pixels and the dark pixels sampled by the CDS are stored through two memories. The output voltage of the dark pixel is amplified by a programmable-gain amplifier (PGA) and then the dark current in the active pixel is eliminated by the compensation circuit.
  • CDS dark current correlated double sampling
  • PGA programmable-gain amplifier
  • the embodiments of the application provide a dark current-related double sampler, an image sensor, and a dark current compensation method.
  • the output voltage of the active pixel and the output of the dark pixel can be realized by the dark current-related double sampler without a special memory and compensation circuit.
  • the voltage is subtracted to compensate for the dark current in the active pixel.
  • a dark current related double sampler in a first aspect, includes: a switch circuit, n first capacitors, m second capacitors, integrating capacitors, and operational amplifiers, wherein the The sum of the capacitance values of the n first capacitors is equal to the sum of the capacitance values of the m second capacitors, and both n and m are positive integers; the n first capacitors are connected to the n first capacitors through the switch circuit.
  • the output voltage of the source pixel is connected to the inverting input terminal of the operational amplifier, the m second capacitors are respectively connected to the output voltage of m dark pixels and the inverting input terminal through the switch circuit, and the integral A capacitor is connected between the inverting input terminal and the output terminal through the switch circuit.
  • the sum of the capacitance values of n first capacitors connected to the output voltage of the active pixel is set to be equal to the sum of capacitance values of the m second capacitors connected to the output voltage of the dark pixel, so that no special
  • the memory and the compensation circuit can realize the subtraction of the output voltage of the active pixel and the output voltage of the dark pixel through the output terminal of the dark current correlation double sampler, so as to compensate the dark current in the active pixel.
  • Using the dark current correlation double sampler in the embodiment of the present application is beneficial to reduce the hardware cost of the image sensor.
  • the switch circuit in the first stage, is used to control the n first capacitors and the m second capacitors to charge, and the switch circuit is also used to control the integral The capacitors are discharged; in the second stage, the switch circuit is used to control the n first capacitors and the m second capacitors to stop charging, and control the n first capacitors and the m second capacitors The capacitor discharges to the integrating capacitor.
  • the ratio of the sum of the capacitance values of the n first capacitors and the sum of the capacitance values of the m second capacitors to the capacitance value of the integrating capacitor is k/p, Among them, k is greater than or equal to p.
  • the signal can be amplified without a special PGA, which can further reduce the cost of the image sensor.
  • k may also be set to be smaller than p.
  • the dark current correlation double sampler in the embodiment of the present application can be implemented separately, without the need for a dedicated amplification or reduction circuit.
  • the n active pixels and the m dark pixels constitute a pixel unit in a pixel array.
  • n is a positive integer greater than 1.
  • n can also be equal to 1.
  • the dark current related double sampler in the embodiment of the present application when applied to an image sensor, can average multiple active pixels before performing dark current compensation, which can simplify the circuit structure of the image sensor, thereby reducing the cost of the image sensor .
  • the switch circuit includes a first switch group and a second switch group, and one end of the n first capacitors passes through the output of the first switch group and the n active pixels.
  • the voltage is connected to the common-mode voltage through the second switch group, and the other ends of the n first capacitors are connected to the common-mode voltage through the first switch group and to the inverter through the second switch group.
  • Phase input terminals are connected, one end of the m second capacitors is connected to the output voltage of the m dark pixels through the first switch group and to the inverting input terminal through the second switch group, the The other ends of the m second capacitors are connected to the common mode voltage, the integrating capacitor is connected in parallel with the switches in the first switch group, and the forward input end of the operational amplifier is connected to the common mode voltage.
  • the switch circuit includes a first switch group and a second switch group, and one end of the n first capacitors passes through the output of the first switch group and the n active pixels.
  • the voltage is connected to the inverting input terminal through the second switch group, the other ends of the n first capacitors are connected to a common mode voltage, and one end of the m second capacitors is connected to the first switch group through the first switch group.
  • the output voltages of the m dark pixels are connected to the common mode voltage through the second switch group, and the other ends of the m second capacitors are connected to the common mode voltage through the first switch group and through
  • the second switch group is connected to the inverting input terminal, the integrating capacitor is connected in parallel with the switches in the first switch group, and the forward input terminal of the operational amplifier is connected to the common mode voltage.
  • the first switch group is closed and the second switch group is opened; in the second stage, the first switch group is opened and the second switch group is closed.
  • any one of the n active pixels and the m dark pixels includes a photodiode, a transmission tube, a reset switch tube, a source follower input tube, and a strobe switch tube;
  • different intensities of light generate different amounts of charge in the photodiode, the generated charge is converted into a voltage under the transmission of the transmission tube, and the converted voltage is followed by the source to follow the input tube and the gate.
  • the switch tube outputs to the first capacitor or the second capacitor, and the reset switch tube is used to reset the photodiode.
  • any one of the pixels further includes a parasitic capacitor; wherein, the anode of the photodiode is grounded, the cathode of the photodiode is connected to the source of the transmission tube, and the gate of the transmission tube is The pole is controlled by a transmission signal, the drain of the transmission tube is connected to one end of the parasitic capacitor, the gate of the source follower input tube, and the source of the reset switch, and the other end of the parasitic capacitor is grounded ,
  • the drain of the reset switch is connected to the reset voltage, the gate of the reset switch is controlled by the reset signal, the source of the source follower input transistor is connected to the drain of the strobe switch, and the source
  • the drain of the following input tube is connected to the power supply voltage, the gate of the strobe switch is controlled by the strobe signal, and the source of the strobe switch outputs the output voltage of the corresponding pixel.
  • the reset switch tubes and transfer tubes of all pixels in the n active pixels and the m dark pixels are turned on, and the photodiodes of all pixels are turned on. Reset to the reset voltage; in the fourth stage, the reset switch tubes and transmission tubes of all pixels are turned off, and all pixels begin to expose.
  • an image sensor in a second aspect, includes a pixel array, a dark current-related double sampler and an analog-to-digital converter as in the first aspect or any of its implementations, and the pixel array includes the n active pixels and the m dark pixels, the analog-to-digital converter is used to convert the analog output of the dark current correlation double sampler into a digital output.
  • the n active pixels and the m dark pixels constitute a pixel unit in the pixel array
  • the image sensor further includes a row scan controller and a column scan controller, The row scan controller and the column scan controller are used to select the one pixel unit.
  • the pixel array may include a plurality of pixel units, where each pixel unit may include n active pixels and m dark pixels.
  • a dark current compensation method is provided.
  • the method is executed by a dark current-related double sampler.
  • the dark current-related double sampler includes a switch circuit, n first capacitors, m second capacitors, and integral A capacitor and an operational amplifier, the sum of the capacitance values of the n first capacitors is equal to the sum of the capacitance values of the m second capacitors, and both n and m are positive integers.
  • the method includes: in the first stage, Under the control of the switch circuit, the n first capacitors sample the output voltages of the n active pixels, and the m second capacitors sample the output voltages of the m dark pixels; In the second stage, under the control of the switch circuit, the sampled charges on the n first capacitors and the sampled charges on the m second capacitors are transferred to the integrating capacitor respectively, and the operational amplifier The output voltage of is used to represent the difference between the output voltage of the n active pixels and the output voltage of the m dark pixels.
  • the operational amplifier includes a non-inverting input terminal, an inverting input terminal, and an output terminal, and the n first capacitors are respectively connected to the output of the n active pixels through the switch circuit.
  • the voltage is connected to the inverting input terminal of the operational amplifier, the m second capacitors are respectively connected to the output voltage of the m dark pixels and the inverting input terminal through the switch circuit, and the integral A capacitor is connected between the inverting input terminal and the output terminal through the switch circuit.
  • the ratio of the sum of the capacitance values of the n first capacitors and the sum of the capacitance values of the m second capacitors to the capacitance value of the integrating capacitor is k/p, Among them, k is greater than or equal to p.
  • the n active pixels and the m dark pixels constitute a pixel unit in a pixel array.
  • the above-mentioned third aspect of the dark current compensation method of the embodiment of the present application can correspond to each unit/module in the dark current related double sampler of the embodiment of the present application of the first aspect, and the corresponding process in the method can be passed through the first aspect
  • Each unit/module in the dark current correlation double sampler is implemented. For the sake of brevity, it will not be repeated here.
  • Figure 1 shows a circuit block diagram of a typical image sensor.
  • Fig. 2 shows a schematic circuit block diagram of a dark current correlation double sampler according to an embodiment of the present application.
  • FIG. 3 shows a schematic circuit diagram of a pixel unit of an embodiment of the present application.
  • FIG. 4 shows a schematic circuit diagram of a dark current correlation double sampler according to an embodiment of the present application.
  • FIG. 5 shows another schematic circuit diagram of the dark current correlation double sampler according to an embodiment of the present application.
  • Fig. 6 shows a working sequence diagram of the dark current correlation double sampler according to an embodiment of the present application.
  • Fig. 7 shows a circuit block diagram of an image sensor according to an embodiment of the present application.
  • FIG. 8 shows a schematic block diagram of a dark current compensation method according to an embodiment of the present application.
  • the dark current compensation principle If the output signal is sampled separately at the start time t1 and the end time t2 of the integration of the photoelectric signal (in one signal output period, two sampling pulses are generated, and the two voltages of the output signal are sampled separately, that is, once The output voltage of the dark pixel is sampled, and the output voltage of the active pixel is sampled the other time), and the time interval between the two samplings is grasped. If the two sampled values are processed by the subsequent compensation circuit, it is basically eliminated The dark current is used to obtain the effective signal amount for the conversion of the light input amount of the active pixel within a certain exposure time.
  • FIG. 1 shows a schematic diagram of a typical image sensor 10.
  • the image sensor 10 includes a pixel array 11, a CDS 13, a first memory 14, a second memory 15, and a compensation circuit 16, wherein the pixel array 11 includes a plurality of dark pixels 11a and a plurality of active pixels 11b.
  • the CDS13 is used to sample the output voltage of the active pixel 11b and the dark pixel 11a
  • the first memory 14 is used to store the output voltage of the active pixel 11b
  • the second memory is used to store the output voltage of the dark pixel 11a
  • the compensation circuit 16 The output voltage of the dark pixel 11a in the second memory is subtracted from the output voltage of the active pixel 11b in the first memory to perform dark current compensation.
  • the image sensor 10 may also include a PGA (not shown in the figure), and the output voltage of the compensation circuit is amplified by the PGA.
  • the CDS in Fig. 1 is only used to sample the output voltages of the dark pixels and active pixels, and the processing of the sampled output voltages of the active pixels and the output voltages of the dark pixels is implemented on other hardware circuits. Therefore, the cost of the image sensor in FIG. 1 is relatively high.
  • the dark current-related double sampler may include: a switch circuit, n first capacitors, m second capacitors, an integrating capacitor, and an operational amplifier, wherein the capacitance value of the n first capacitors is one of And is equal to the sum of the capacitance values of the m second capacitors, n and m are both positive integers; the n first capacitors are connected to the output voltage of the n active pixels and the operation through the switch circuit, respectively The inverting input terminal of the amplifier is connected, the m second capacitors are respectively connected to the output voltage of the m dark pixels and the inverting input terminal through the switch circuit, and the integrating capacitor is connected to the inverting input terminal through the switch circuit. Between the inverting input terminal and the output terminal of the operational amplifier.
  • the n first capacitors and the m second capacitors can be charged, and the integrating capacitor can be discharged, so that the amount of charge across the integrating capacitor is zero . Then, under the control of the switch circuit, the n first capacitors and the m second capacitors after charging are discharged to the integrating capacitor, and output through the output terminal of the operational amplifier.
  • the n first capacitors sample the output voltages of the n active pixels
  • the m second capacitors sample the output voltages of the m dark pixels. The voltage is sampled. Then, under the control of the switch circuit, the sampled charges on the n first capacitors and the m second capacitors are transferred to the integrating capacitor respectively, and passed through the output of the operational amplifier.
  • the output voltage of the operational amplifier is used to represent the difference between the output voltage of the n active pixels and the output voltage of the m dark pixels.
  • the sum of capacitance values of n first capacitors connected to the output voltage of active pixels and the sum of capacitance values of m second capacitors connected to the output voltage of dark pixels are set equal, so that no special
  • the memory and the compensation circuit can realize the subtraction of the output voltage of the active pixel and the output voltage of the dark pixel through the output terminal of the dark current correlation double sampler, so as to compensate the dark current in the active pixel.
  • first capacitor, the second capacitor, and the operational amplifier in the working state should use the same voltage as the reference voltage, for example, a common mode voltage.
  • the ratio of the sum of the capacitance values of the n first capacitors and the sum of the capacitance values of the m second capacitors to the capacitance value of the integrating capacitor is k/p.
  • the sum of the capacitance values of the n first capacitors is equal to the sum of the capacitance values of the m second capacitors, whether it is the ratio of the sum of the capacitance values of the n first capacitors to the capacitance value of the integrating capacitor or the m th
  • the ratio of the sum of the capacitance values of the two capacitors to the capacitance value of the integrating capacitor is k/p.
  • the proportional coefficient k/p of the capacitance value of the charging and discharging capacitor (the first capacitor or the second capacitor) and the integrating capacitor for example, k is greater than or equal to p, and signal amplification can be achieved.
  • the dark current correlation double sampler is applied to the image sensor, the signal can be amplified without a special PGA, which can further reduce the cost of the image sensor.
  • k may also be set to be smaller than p.
  • the dark current correlation double sampler in the embodiment of the present application can be implemented separately, without the need for a dedicated amplification or reduction circuit.
  • the n active pixels and the m dark pixels may constitute a pixel unit in a pixel array.
  • one pixel unit can be divided into multiple sub-pixels, and the multiple sub-pixels can be set as active sub-pixels and dark sub-pixels, respectively.
  • each of the n active pixels and the m dark pixels may also be a pixel unit in a pixel array.
  • the pixel array in the embodiments of the present application may include multiple pixel units, and each pixel unit may be divided into multiple sub-pixels including active sub-pixels and dark sub-pixels, and each pixel unit uses a dark sub-pixel.
  • the current correlation double sampler realizes the elimination of dark current; it is also possible that each pixel unit in some pixel units is divided into multiple sub-pixels including active sub-pixels and dark sub-pixels, and this part of the pixel units uses a dark current respectively
  • the correlated double sampler realizes the elimination of dark current, and each pixel unit in the other part of the pixel unit can be an active pixel or a dark pixel, which together constitute n active pixels and m dark pixels, and adopts a dark current Correlated double sampler to achieve the elimination of dark current.
  • dark pixels are usually arranged on the periphery of the active pixel area, and the average value of the dark pixels is read to characterize the dark current in the pixel array, and the dark current signal is estimated and eliminated by the later software algorithm. Due to the uneven distribution of the dark current in the pixel array, uneven heating, etc., the dark current of each pixel unit may have a relatively large difference, so the prior art cannot achieve the expected effect. In the embodiment of the present application, a certain ratio of dark pixels may be inserted into each pixel unit, so that the compensation of the dark current of each pixel unit can be completed, so that the result of the dark current elimination is more accurate and the precision is higher.
  • n is a positive integer greater than 1, that is, the n first capacitors are multiple first capacitors.
  • the dark current related double sampler in the embodiment of the present application when applied to an image sensor, can average multiple active pixels before performing dark current compensation, which can simplify the circuit structure of the image sensor, thereby reducing the cost of the image sensor .
  • n can also be equal to 1, and similarly, the output voltage of the active pixel and the output voltage of the dark pixel can be subtracted at the output end of the dark current-related double sampler to compensate for the dark current in the active pixel.
  • Fig. 3 shows an embodiment of a pixel unit provided by the present application.
  • one pixel unit is composed of 4 identical sub-pixels 1 to 4, among which 3 sub-pixels are active pixels and 1 sub-pixel is dark pixel.
  • the ratio of active pixels to dark pixels is 3:1. It should be noted that the embodiment of the present application is not limited to the ratio of active pixels and dark pixels in FIG. 3, and any reasonable ratio value can be set during specific implementation. Or in specific implementation, it is sufficient to ensure that the ratio of the PD area of the active pixel and the dark pixel in FIG. 3 is equal to the ratio of the FD point parasitic capacitor C FD.
  • one pixel unit is composed of 4 sub-pixels, where sub-pixels 1 to 3 are active sub-pixels, and sub-pixel 4 is a dark sub-pixel.
  • a sub-pixel may include a photodiode (PD), a transmission tube M1, a reset switch tube M2, a source follower input tube M3, and a strobe switch tube M4; wherein, light of different intensities produces different amounts in the photodiode PD.
  • the charge is transferred to the FD point through the transmission tube M1, and the charge is converted into a voltage signal.
  • the node voltage is output to the first capacitor or the second capacitor through the source follower input tube M3 and the gate switch tube M4.
  • a capacitor, the reset switch tube M2 is used to reset the photodiode PD.
  • one sub-pixel further includes a parasitic capacitor C FD , wherein the anode of the photodiode PD is grounded, and the cathode of the photodiode PD is connected to the source of the transmission tube M1,
  • the gate of the transmission tube M1 is controlled by the transmission signal TX, and the drain of the transmission tube M1 is respectively connected to one end of the parasitic capacitor C FD , the gate of the source follower input tube M3, and the reset switch tube M2.
  • the source of the parasitic capacitor C FD is connected to the ground, the drain of the reset switch is connected to the reset voltage V rst , the gate of the reset switch is controlled by the reset signal RST, and the source follows the input transistor
  • the source of M3 is connected to the drain of the gate switch M4, the drain of the source follower input tube M3 is connected to the power supply voltage VCCP, and the gate of the gate switch M4 is controlled by the gate signal RSEL, so
  • the source of the strobe switch M4 outputs the output voltage of the corresponding sub-pixel. For example, sub-pixel 1 outputs V p1 , sub-pixel 2 outputs V p2 , sub-pixel 3 outputs V p3 , and sub-pixel 4 outputs V p4 .
  • circuit structure of the sub-pixel in the embodiment of the present application includes but is not limited to the circuit structure shown in FIG. 3.
  • the circuit structure of the sub-pixel may also be a capacitive feedback trans-impedance amplifier (Capacitive Trans-impedance Amplifier, CTIA) structure.
  • CTIA Capacitive Trans-impedance Amplifier
  • Fig. 4 is a schematic circuit diagram of a dark current correlation double sampler according to an embodiment of the present application.
  • V p1 , V p2 , V p3 , and V p4 respectively correspond to the output voltage of each sub-pixel in FIG. 3
  • V p1 , V p2 and V p3 are the output voltages of the active sub-pixels in a pixel unit
  • V p4 It is the output voltage of the dark sub-pixel in a pixel unit.
  • the dark current correlation double sampler includes: 1 capacitor 101 (ie, the second capacitor in Figure 2), three capacitors 102 (ie, the first capacitor in Figure 2), an operational amplifier 103 (ie, Figure 2). 2), the switch group 1041 and the switch group 1042 (that is, the switch circuit in FIG. 2 may include the first switch group and the second switch group), and the integrating capacitor 105 (that is, the integrating capacitor in FIG. 2).
  • one end of the capacitor 101 is connected to the output voltage Vp4 of the dark sub-pixel in a pixel unit in FIG. 3 through at least one switch in the switch group 1041, and through a switch in the switch group 1042 and the op amp 103.
  • the input terminal is connected, and the other terminal of the capacitor 101 is connected to the common mode voltage VCM, which may also be referred to as a reference voltage.
  • VCM common mode voltage
  • One end of each capacitor 102 is connected to the output voltage of one active sub-pixel in one pixel unit in FIG. 3 through a switch in the switch group 1041.
  • one end of the three capacitors 102 is connected to V p1 , V p2 and V p3 respectively, and one end of each capacitor 102 can also be connected to the common mode voltage through a switch in the switch group 1042, that is, one end of the three first capacitors 102 Both are connected to the common mode voltage.
  • the other ends of the three capacitors 102 can be connected to the inverting input terminal of the operational amplifier 103 through the same switch in the switch group 1042 and connected to the common mode voltage through the switch group 1041.
  • the integrating capacitor 105 is connected in parallel with one switch in the switch group 1041 and connected between the inverting input terminal and the output terminal of the operational amplifier 103.
  • the positive input terminal of the operational amplifier 103 may be connected to the common mode voltage.
  • one end of the capacitor 101 through a switch or switch group 1041 and a plurality of switches connected to V p4, e.g., the number of capacitors can be connected via the same switch 102 V p4, embodiments of the present application which is not Constitutive limit.
  • one end of the capacitor 101 can be connected to V p4 through three switches in the switch group 1041, so as to avoid the impact of the switch on the charge feedthrough (or charge injection) caused by the switch. Impact).
  • the working sequence of the dark current correlation double sampler in Fig. 4 mainly includes four stages, among which, the first stage (the following T4 time period), the second stage (the following T5 time period), and the third stage (T1 time period below) and the fourth stage (T2 time period below).
  • the RST and TX of the four sub-pixels in the selected pixel unit in a certain row and column are high, the reset switch tube M2 and the transmission tube M1 are turned on, and the FD and the photodiode PD are both reset to V rst voltage, the theoretical value of the output voltage at this time is V P1_0 , V P2_0 , V P3_0 and V P3_0 .
  • RST and TX are low, the reset switch tube M2 and the transmission tube M1 are turned off, and the pixel unit starts to expose.
  • the active sub-pixels convert the corresponding electrons according to the amount of light input, and correspondingly the electrons accumulated by the dark current; the dark sub-pixels are in a dark environment and are insensitive to light and therefore only accumulate the electrons generated by the dark current.
  • the switch group 1041 is controlled by the switch signal SW1
  • the switch group 1042 is controlled by the switch signal SW2
  • the capacitance value of the capacitor 102 is represented by C2
  • the capacitance value of the capacitor 101 is represented by C1
  • the capacitance value of the integrating capacitor 105 is represented by C int .
  • the switch group 1041 is turned off by pulling SW1 low, and the switch group 1042 is turned on by pulling SW2 high.
  • the upper plate of capacitor 101 is connected to the inverting input terminal of OP
  • the lower plate of capacitor 101 is connected to VCM
  • the lower plate of capacitor 102 is connected to the inverting input terminal of OP
  • the upper plate of capacitor 102 is connected to VCM
  • capacitor 101 capacitor
  • the charge of 102 is transferred to the integrating capacitor 105.
  • the dark current-related double sampler in the embodiment of the present application can simultaneously sample the output voltage of the active pixel and the output voltage of the dark pixel through n first capacitors and m second capacitors, and sample the output voltage of the dark pixel.
  • the charges on the n first capacitors and m second capacitors are transferred to the integrating capacitor at the same time, so that the purpose of eliminating the dark current in the active pixel can be achieved.
  • only the common mode voltage VCM and the light conversion voltage V P_LI are left in the output signal of the dark current-related double sampler, and a useful light conversion signal can be obtained, thereby achieving the effect of eliminating the effect of dark current.
  • the PGA can be eliminated by adjusting the coefficient n to achieve signal amplification.
  • Fig. 5 is a schematic circuit diagram of a dark current correlation double sampler according to another embodiment of the present application.
  • V p1 , V p2 , V p3 , and V p4 respectively correspond to the output voltage of each sub-pixel in FIG. 3
  • V p1 , V p2 and V p3 are the output voltages of the active sub-pixels in a pixel unit
  • V p4 It is the output voltage of the dark sub-pixel in a pixel unit.
  • the dark current correlation double sampler includes: 1 capacitor 201 (ie, the second capacitor in Figure 2), three capacitors 202 (ie, the first capacitor in Figure 2), operational amplifier 203 (ie, Figure 2). 2), the switch group 2041 and the switch group 2042 (that is, the switch circuit in FIG. 2 may include the first switch group and the second switch group), and the integration capacitor 205 (that is, the integration capacitor in FIG. 2).
  • one end of the capacitor 201 is connected to the output voltage Vp4 of the dark sub-pixel in one pixel unit in FIG. 3 through at least one switch in the switch group 2041, and is connected to the common mode voltage VCM through at least one switch in the switch group 2042.
  • the common-mode voltage can also be referred to as the reference voltage.
  • the other end of the capacitor 201 is connected to the inverting input terminal of the operational amplifier 203 through a switch in the switch group 2042 and is connected to the VCM through a switch in the switch group 2041.
  • One end of each capacitor 202 is connected to the output voltage of one active sub-pixel in one pixel unit in FIG. 3 through a switch in the switch group 2041.
  • one end of the three capacitors 202 is connected to V p1 , V p2 and V p3 respectively, and one end of each capacitor 202 can also be connected to the inverting input terminal of the operational amplifier 203 through a switch in the switch group 2042, that is, three One end of the capacitor 202 can be connected to the inverting input terminal of the operational amplifier 203 through the same switch in the switch group 2042.
  • the other end of each capacitor 202 is connected to the common mode voltage.
  • the integrating capacitor 205 is connected in parallel with one switch in the switch group 2041, and is connected between the inverting input terminal and the output terminal of the operational amplifier 203.
  • the positive input terminal of the operational amplifier 203 is connected to the common mode voltage.
  • one end of the capacitor 201 through a switch or switch group 2041 is connected to V p4 with more switches, e.g., the number of capacitors can be connected via the same switch 202 V p4, embodiments of the present application which is not Constitutive limit.
  • one end of the capacitor 201 can be connected to V p4 through the three switches in the switch group 2041, so as to avoid the impact of the switch on the charge feedthrough (or charge injection) caused by the circuit as much as possible. Impact).
  • the working sequence of the dark current correlation double sampler in Fig. 4 mainly includes four stages, among which the first stage (the following T4 time period), the second stage (the following T5 time period), The third stage (the following T1 time period) and the fourth stage (the following T2 time period).
  • the RST and TX of the four sub-pixels in the selected pixel unit in a certain row and column are high, the reset switch tube M2 and the transmission tube M1 are turned on, and the FD and the photodiode PD are both reset to V rst voltage, the theoretical value of the output voltage at this time is V P1_0 , V P2_0 , V P3_0 and V P3_0 .
  • RST and TX are low, the reset switch tube M2 and the transmission tube M1 are turned off, and the pixel unit starts to expose.
  • the active sub-pixels convert the corresponding electrons according to the amount of light input, and correspondingly the electrons accumulated by the dark current; the dark sub-pixels are in a dark environment and are insensitive to light and therefore only accumulate the electrons generated by the dark current.
  • V P_LI V sig_a1 ⁇ 3
  • V P_DK V sig_a1 ⁇ 3
  • V P_LI means that the exposure is constant
  • the switch group 2041 is controlled by the switch signal SW1
  • the switch group 2042 is controlled by the switch signal SW2
  • the capacitance value of the capacitor 202 is denoted by C1
  • the capacitance value of the capacitor 201 is denoted by C2
  • the capacitance value of the integrating capacitor 205 is denoted by C int .
  • SW1 pulls down to close the switch group 2041
  • SW2 pulls high to turn on the switch group 2042
  • the lower plate of the capacitor 201 is connected to the inverting input terminal of OP
  • the upper plate of the capacitor 201 is connected to VCM
  • the upper electrode of the capacitor 202 is connected.
  • the plate is connected to the inverting input terminal of OP
  • the lower plate of capacitor 202 is connected to VCM
  • the charges of capacitor 201 and capacitor 202 are transferred to integrating capacitor 205.
  • the dark current-related double sampler in the embodiment of the present application can simultaneously sample the output voltage of the active pixel and the output voltage of the dark pixel through n first capacitors and m second capacitors, and sample the output voltage of the dark pixel.
  • the charges on the n first capacitors and m second capacitors are transferred to the integrating capacitor at the same time, so that the purpose of eliminating the dark current in the active pixel can be achieved.
  • only the common mode voltage VCM and the light conversion voltage V P_LI are left in the output signal of the dark current-related double sampler, and a useful light conversion signal can be obtained, thereby achieving the effect of eliminating the effect of dark current.
  • the PGA can be eliminated by adjusting the coefficient n to achieve signal amplification.
  • the dark current correlation double sampler in the embodiment of the present application includes but is not limited to being applied to an image sensor.
  • FIG. 7 takes an image sensor as an example for description.
  • the image sensor includes a pixel array 301, the dark current correlation double sampler 302 in the various embodiments described above, and an analog-to-digital converter 303.
  • the pixel array 301 may include pixel units in X rows and Y columns, and the number of dark current correlated double samplers 302 may be at least one, and each dark current correlated double sampler 302 is used to collect n active pixels in the pixel array 300.
  • the analog-to-digital converter 303 is used to convert the dark
  • the analog output of the current-correlated double sampler 302 is converted into a digital output.
  • the image sensor further includes a row scan controller 304 and a column scan controller 305, and the n active pixels and m dark pixels constitute a pixel unit in the pixel array 301, that is, the pixel
  • the array may include a plurality of pixel units, and the row scan controller 304 and the column scan controller 305 are used to select one pixel unit in the pixel array 301.
  • the dark current is sampled twice by the dark current correlation double sampler and subtracted and eliminated, so that no special memory, compensation circuit, PGA and other hardware circuits are needed, and the hardware cost of the image sensor can be reduced.
  • FIG. 8 shows a schematic block diagram of a dark current compensation method 400 according to an embodiment of the present application.
  • the method 400 is executed by a dark current-related double sampler, which includes a switch circuit, n first capacitors, m second capacitors, an integrating capacitor, and an operational amplifier.
  • the sum of the capacitance values is equal to the sum of the capacitance values of the m second capacitors. Both n and m are positive integers.
  • the specific process of the dark current compensation method 400 is as follows.
  • the n first capacitors sample the output voltages of the n active pixels, and the m second capacitors sample the output voltages of the m dark pixels. The output voltage is sampled;
  • the sampled charges on the n first capacitors and the sampled charges on the m second capacitors are respectively transferred to the integrating capacitor,
  • the output voltage of the operational amplifier is used to represent the difference between the output voltage of the n active pixels and the output voltage of the m dark pixels.
  • the output voltage of the operational amplifier is used to represent the difference between the average value of the output voltages of the n active pixels and the average value of the output voltages of the m dark pixels.
  • the dark current compensation method according to the embodiment of the present application can correspond to each unit/module in the dark current correlation double sampler of the embodiment of the present application, and the corresponding processes in the method can be referred to in Figure 2, Figure 4, and Figure 5.
  • Each unit/module in the dark current correlation double sampler shown in the figure is implemented. For brevity, it will not be repeated here.
  • one embodiment or “an embodiment” mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment” or “in an embodiment” in various places throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not correspond to the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B based on A does not mean that B is determined only based on A, and B can also be determined based on A and/or other information.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

Abstract

一种暗电流相关双采样器、图像传感器和暗电流补偿方法，包括：开关电路（1041、1042）、n个第一电容器（102）、m个第二电容器（101）、积分电容器（105）和运算放大器（103），n个第一电容器（102）的电容值之和与m个第二电容器（101）的电容值之和相等；n个第一电容器（102）通过开关电路（1041、1042）分别与n个有源像素的输出电压（V p1、V p2、V p3）和运算放大器（103）的反相输入端相连，m个第二电容器（101）通过开关电路（1041、1042）分别与m个暗像素的输出电压（V p4）和运算放大器（103）的反相输入端相连，积分电容器（105）通过开关电路（1041）连接在运算放大器（103）反相输入端与运算放大器（103）的输出端之间。通过暗电流相关双采样器直接实现有源像素的输出电压（V p1、V p2、V p3）与暗像素的输出电压（V p4）相减，以补偿有源像素中的暗电流。

Description

暗电流相关双采样器、图像传感器和暗电流补偿方法 技术领域
本申请实施例涉及CMOS图像传感器领域，并且更具体地，涉及一种暗电流相关双采样器、图像传感器和暗电流补偿方法。
背景技术
互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)(CMOS Image Sensor，CIS)暗电流是指光电二极管在反偏条件下，在暗环境时产生的反向电流。一般是由于载流子扩散运动、器件表面、内部缺陷以及有害杂质引起。因此暗电流的大小与温度密切相关，而且空间平面上分布可能存在不一致性和随机性。暗电流限制了图像传感器的灵敏度、动态范围和信噪比(SIGNAL-NOISE RATIO，SNR)等等，因此需要进行暗电流补偿。
现有技术中的暗电流补偿通过复杂的硬件电路来消除像素阵列中的暗电流。例如，在有源像素区域内设置一些暗像素，通过暗电流相关双采样器(Correlated Double Sampling，CDS)分别采样有源像素和暗像素，并通过两个存储器分别存储CDS采样的有源像素和暗像素的输出电压，再经过可编程增益放大器(programmable-gain amplifier，PGA)放大后由补偿电路将有源像素中的暗电流消除。现有技术需要开销很多硬件成本。
发明内容
本申请实施例提供一种暗电流相关双采样器、图像传感器和暗电流补偿方法，无需专门的存储器和补偿电路就可以通过暗电流相关双采样器实现有源像素的输出电压与暗像素的输出电压相减，以补偿有源像素中的暗电流。
第一方面，提供了一种暗电流相关双采样器，所述暗电流相关双采样器包括：开关电路、n个第一电容器、m个第二电容器、积分电容器和运算放大器，其中，所述n个第一电容器的电容值之和与所述m个第二电容器的电容值之和相等，n和m均为正整数；所述n个第一电容器通过所述开关电路分别与n个有源像素的输出电压和所述运算放大器的反相输入端相连，所述m个第二电容器通过所述开关电路分别与m个暗像素的输出电压和所述反 相输入端相连，所述积分电容器通过所述开关电路连接在所述反相输入端与所述输出端之间。
本申请实施例通过将连接有源像素的输出电压的n个第一电容器的电容值之和设置为与连接暗像素的输出电压的m个第二电容器的电容值之和相等，使得无需专门的存储器和补偿电路就可以通过暗电流相关双采样器的输出端实现有源像素的输出电压与暗像素的输出电压相减，以补偿有源像素中的暗电流。
使用本申请实施例中的暗电流相关双采样器，有利于降低图像传感器的硬件成本。
在一种可能的实现方式中，在第一阶段，所述开关电路用于控制所述n个第一电容器和所述m个第二电容器进行充电，所述开关电路还用于控制所述积分电容器进行放电；在第二阶段，所述开关电路用于控制所述n个第一电容器和所述m个第二电容器停止充电，并且控制所述n个第一电容器和所述m个第二电容器向所述积分电容器放电。
在一种可能的实现方式中，所述n个第一电容器的电容值之和以及所述m个第二电容器的电容值之和分别与所述积分电容器的电容值之比为k/p，其中，k大于或等于p。
通过调整充放电电容器(第一电容器或第二电容器)与积分电容器的电容值的比例系数k/p，就可以实现信号放大。
当暗电流相关双采样器应用于图像传感器中，无需专门的PGA就可以实现信号的放大，从而可以进一步地降低图像传感器的成本。
可选地，当需要实现信号缩小时，也可以设置k小于p。总之，无论是信号放大或缩小，本申请实施例中的暗电流相关双采样器均可以单独实现，而无需专用的放大或缩小电路。
在一种可能的实现方式中，所述n个有源像素和所述m个暗像素构成像素阵列中的一个像素单元。
由于每个像素单元内的暗电流可能存在差异比较大，在每个像素单元中插入一定比率的暗像素，可以完成每个像素单元的暗电流消除，从而使得暗电流消除的结果更准确，精度更高。
在一种可能的实现方式中，n为大于1的正整数。
可选地，n也可以等于1。
本申请实施例中的暗电流相关双采样器，当应用于图像传感器时，可以将多个有源像素平均之后再进行暗电流补偿，能够简化图像传感器的电路结构，从而可以降低图像传感器的成本。
在一种可能的实现方式中，所述开关电路包括第一开关组和第二开关组，所述n个第一电容器的一端通过所述第一开关组与所述n个有源像素的输出电压以及通过所述第二开关组与共模电压相连，所述n个第一电容器的另一端通过所述第一开关组与所述共模电压相连以及通过所述第二开关组与所述反相输入端相连，所述m个第二电容器的一端通过所述第一开关组与所述m个暗像素的输出电压以及通过所述第二开关组与所述反相输入端相连，所述m个第二电容器的另一端与所述共模电压相连，所述积分电容器与所述第一开关组中的开关并联，所述运算放大器的正向输入端与所述共模电压相连。
在一种可能的实现方式中，所述开关电路包括第一开关组和第二开关组，所述n个第一电容器的一端通过所述第一开关组与所述n个有源像素的输出电压以及通过所述第二开关组与所述反相输入端相连，所述n个第一电容器的另一端与共模电压相连，所述m个第二电容器的一端通过所述第一开关组与所述m个暗像素的输出电压以及通过所述第二开关组与所述共模电压相连，所述m个第二电容器的另一端通过所述第一开关组与所述共模电压以及通过所述第二开关组与所述反相输入端相连，所述积分电容器与所述第一开关组中的开关并联，所述运算放大器的正向输入端与所述共模电压相连。
可选地，在第一阶段，所述第一开关组闭合，所述第二开关组断开；在第二阶段，所述第一开关组断开，所述第二开关组闭合。
在一种可能的实现方式中，所述n个有源像素和所述m个暗像素中的任一像素包括光电二极管、传输管、复位开关管、源跟随器输入管以及选通开关管；其中，不同强度的光照在所述光电二极管中产生不同量的电荷，在所述传输管的传输下将产生的电荷转换成电压，转换后的电压通过所述源跟随输入管和所述选通开关管输出到所述第一电容器或所述第二电容器，所述复位开关管用于对所述光电二极管进行复位。
在一种可能的实现方式中，所述任一像素还包括寄生电容器；其中，所述光电二极管的正极接地，所述光电二极管的负极接所述传输管的源极，所述传输管的栅极由传输信号控制，所述传输管的漏极分别与所述寄生电容器的一端、所述源跟随输入管的栅极以及所述复位开关管的源极相连，所述寄 生电容器的另一端接地，所述复位开关管的漏极接复位电压，所述复位开关管的栅极由复位信号控制，所述源跟随输入管的源极与所述选通开关管的漏极相连，所述源跟随输入管的漏极接电源电压，所述选通开关管的栅极由选通信号控制，所述选通开关管的源极输出相应像素的输出电压。
在一种可能的实现方式中，在第三阶段，所述n个有源像素和所述m个暗像素中的所有像素的复位开关管和传输管导通，所述所有像素的光电二极管被复位至所述复位电压；在第四阶段，所述所有像素的复位开关管和传输管关闭，所述所有像素开始曝光。
第二方面，提供了一种图像传感器，所述图像传感器包括像素阵列、如第一方面或其任一实现方式中的暗电流相关双采样器和模数转换器，所述像素阵列包括所述n个有源像素和所述m个暗像素，所述模数转换器用于将所述暗电流相关双采样器的模拟输出转换成数字输出。
在一种可能的实现方式中，所述n个有源像素和所述m个暗像素构成所述像素阵列中的一个像素单元，所述图像传感器还包括行扫描控制器和列扫描控制器，所述行扫描控制器和所述列扫描控制器用于选择所述一个像素单元。
可选地，所述像素阵列可以包括多个像素单元，其中，每个像素单元可以都包括n个有源像素和m个暗像素。
第三方面，提供了一种暗电流补偿方法，所述方法由暗电流相关双采样器执行，所述暗电流相关双采样器包括开关电路、n个第一电容器、m个第二电容器、积分电容器和运算放大器，所述n个第一电容器的电容值之和与所述m个第二电容器的电容值之和相等，n和m均为正整数，所述方法包括：在第一阶段，在所述开关电路的控制下，所述n个第一电容器分别对n个有源像素的输出电压进行采样，所述m个第二电容器分别对m个暗像素的输出电压进行采样；在第二阶段，在所述开关电路的控制下，采样后的所述n个第一电容器上的电荷和采样后的所述m个第二电容器的电荷分别向所述积分电容器转移，所述运算放大器的输出电压用于表示所述n个有源像素的输出电压与所述m个暗像素的输出电压的差值。
在一种可能的实现方式中，所述运算放大器包括正相输入端、反相输入端和输出端，所述n个第一电容器通过所述开关电路分别与所述n个有源像素的输出电压和所述运算放大器的所述反相输入端相连，所述m个第二电容 器通过所述开关电路分别与所述m个暗像素的输出电压和所述反相输入端相连，所述积分电容器通过所述开关电路连接在所述反相输入端与所述输出端之间。
在一种可能的实现方式中，所述n个第一电容器的电容值之和以及所述m个第二电容器的电容值之和分别与所述积分电容器的电容值之比为k/p，其中，k大于或等于p。
在一种可能的实现方式中，所述n个有源像素和所述m个暗像素构成像素阵列中的一个像素单元。
上述第三方面本申请实施例的暗电流补偿方法可对应于第一方面本申请实施例的暗电流相关双采样器中的各个单元/模块，并且，该方法中的相应流程可以通过第一方面暗电流相关双采样器中的各个单元/模块来实现，为了简洁，在此不再赘述。
附图说明
图1示出了一种典型的图像传感器的电路框图。
图2示出了本申请实施例的暗电流相关双采样器的示意性电路框图。
图3示出了本申请实施例的像素单元的示意性电路图。
图4示出了本申请实施例的暗电流相关双采样器的一种电路示意图。
图5示出了本申请实施例的暗电流相关双采样器的另一种电路示意图。
图6示出了本申请实施例的暗电流相关双采样器的工作时序图。
图7示出了本申请实施例的图像传感器的电路框图。
图8示出了本申请实施例的暗电流补偿方法的示意性框图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
暗电流补偿原理：若在光电信号的积分开始时刻t1和积分结束时刻t2，分别对输出信号采样(在一个信号输出周期内，产生两个采样脉冲，分别采样输出信号的两个电压，即一次是对暗像素的输出电压进行采样，另一次是对有源像素的输出电压进行采样)，并且把握好两次采样时间间隔，若将两次采样值通过后续的补偿电路的处理，就基本消除了暗电流，得到有源像素在一定曝光时间内进光量转换的有效信号量。
图1示出了一种典型的图像传感器10的示意图。如图1所示，图像传感器10包括像素阵列11、CDS13、第一存储器14、第二存储器15和补偿电路16，其中，像素阵列11包括多个暗像素11a和多个有源像素11b。CDS13分别用来采样有源像素11b和暗像素11a的输出电压，第一存储器14用于存储有源像素11b的输出电压，第二存储器用于存储暗像素11a的输出电压，补偿电路16通过从第一存储器中的有源像素11b的输出电压中减去第二存储器中的暗像素11a的输出电压来执行暗电流补偿。进一步地，该图像传感器10还可以包括PGA(图中未示出)，将补偿电路的输出电压通过PGA进行放大。图1中的CDS只是用来采样暗像素和有源像素的输出电压，而对采样到的有源像素的输出电压和暗像素的输出电压的处理则是在其他硬件电路上实现的。因此，图1中的图像传感器的成本相对比较高。
本申请实施例提供了一种新的暗电流相关双采样器，当该暗电流相关双采样器应用于图像传感器时，可以降低图像传感器的硬件成本。如图2所示，该暗电流相关双采样器可以包括：开关电路、n个第一电容器、m个第二电容器、积分电容器和运算放大器，其中，所述n个第一电容器的电容值之和与所述m个第二电容器的电容值之和相等，n和m均为正整数；所述n个第一电容器通过所述开关电路分别与n个有源像素的输出电压和所述运算放大器的反相输入端相连，所述m个第二电容器通过所述开关电路分别与m个暗像素的输出电压和所述反相输入端相连，所述积分电容器通过所述开关电路连接在所述反相输入端与所述运算放大器的输出端之间。
具体地，在所述开关电路的控制下，所述n个第一电容器和所述m个第二电容器可以进行充电，所述积分电容器可以进行放电，使得所述积分电容器两端的电荷量为零。接着，在所述开关电路的控制下，充电后的所述n个第一电容器和所述m个第二电容器向所述积分电容器放电，并通过运算放大器的输出端输出。
或者，也可以说，在所述开关电路的控制下，所述n个第一电容器分别对n个有源像素的输出电压进行采样，所述m个第二电容器分别对m个暗像素的输出电压进行采样。接着，在所述开关电路的控制下，将采样后的所述n个第一电容器上的电荷和所述m个第二电容器上的电荷分别向所述积分电容器转移，并通过运算放大器的输出端输出，所述运算放大器的输出电压用于表示所述n个有源像素的输出电压与所述m个暗像素的输出电压的差值。
本申请实施例通过将连接有源像素的输出电压的n个第一电容器的电容值之和与连接暗像素的输出电压的m个第二电容器的电容值之和设置为相等，使得无需专门的存储器和补偿电路就可以通过暗电流相关双采样器的输出端实现有源像素的输出电压与暗像素的输出电压相减，以补偿有源像素中的暗电流。
应理解，处于工作状态下的第一电容器、第二电容器和运算放大器应该以同一电压为参考电压，例如，共模电压。
可选地，在本申请的一个实施例中，所述n个第一电容器的电容值之和以及所述m个第二电容器的电容值之和分别与所述积分电容器的电容值之比为k/p。
由于n个第一电容器的电容值之和与m个第二电容器的电容值之和相等，因此，无论是n个第一电容器的电容值之和与积分电容器的电容值之比还是m个第二电容器的电容值之和与积分电容器的电容值之比均为k/p。
通过调整充放电电容器(第一电容器或第二电容器)与积分电容器的电容值的比例系数k/p，例如，k大于或等于p，就可以实现信号放大。当暗电流相关双采样器应用于图像传感器中，无需专门的PGA就可以实现信号的放大，从而可以进一步地降低图像传感器的成本。
可选地，当需要实现信号缩小时，也可以设置k小于p。总之，无论是信号放大或缩小，本申请实施例中的暗电流相关双采样器均可以单独实现，而无需专用的放大或缩小电路。
可选地，在本申请的一个实施例中，所述n个有源像素和所述m个暗像素可以构成像素阵列中的一个像素单元。也就是说，可以将一个像素单元划分成多个子像素，并将多个子像素分别设置为有源子像素和暗子像素。
可选地，在本申请的另一实施例中，所述n个有源像素和所述m个暗像素中的每个像素也可以是像素阵列中的一个像素单元。
应理解，本申请实施例中的像素阵列可以包括多个像素单元，可以是每个像素单元都划分成包括有源子像素和暗子像素的多个子像素，并且每个像素单元都采用一个暗电流相关双采样器来实现暗电流的消除；也可以是部分像素单元中的每个像素单元划分成包括有源子像素和暗子像素的多个子像素，并且该部分像素单元分别采用一个暗电流相关双采样器来实现暗电流的消除，而另外一部分像素单元中的每个像素单元可以是一个有源像素或暗像 素，共同构成n个有源像素和m个暗像素，并且采用一个暗电流相关双采样器来实现暗电流的消除。
在现有技术方案中，通常是在有源像素区域外围设置暗像素，读取暗像素平均值用于表征像素阵列中的暗电流，经过后期软件算法处理估计暗电流信号并消除。由于暗电流在像素阵列分布不均、发热不均等原因导致每个像素单元暗电流可能存在差异比较大，因此现有技术无法达到预期效果。而本申请实施例，可以是在每个像素单元中插入一定比率的暗像素，可以完成每个像素单元的暗电流的补偿，从而使得暗电流消除的结果更准确，精度更高。
可选地，n为大于1的正整数，也就是说，所述n个第一电容器为多个第一电容器。
本申请实施例中的暗电流相关双采样器，当应用于图像传感器时，可以将多个有源像素平均之后再进行暗电流补偿，能够简化图像传感器的电路结构，从而可以降低图像传感器的成本。
可选地，n也可以等于1，同样地能够在暗电流相关双采样器的输出端实现有源像素的输出电压与暗像素的输出电压相减，以补偿有源像素中的暗电流。
图3示出了本申请提供的一个像素单元实施例。在该示例中，一个像素单元由4个完全相同的子像素1～4组成，其中有3个子像素是有源像素，1个子像素是暗像素。有源像素和暗像素的比率为3:1。需要说明的是，本申请实施例并不限定于图3中有源像素和暗像素的比率，具体实施时可以设置任意合理的比率值。或者在具体实施中只要保证图3中的有源像素和暗像素的PD面积比值与FD点寄生电容器C FD比值相等即可。
具体地，如图3所示，一个像素单元由4个子像素构成，其中，子像素1～3为有源子像素，子像素4为暗子像素。一个子像素可以包括光电二极管(photodiode，PD)、传输管M1、复位开关管M2、源跟随输入管M3和选通开关管M4；其中，不同强度的光照在所述光电二极管PD中产生不同量的电荷，通过所述传输管M1传输到FD点上，将电荷转换为电压信号，该结点电压通过源跟随输入管M3以及选通开关管M4输出到所述第一电容器或所述第二电容器，该复位开关管M2用于对光电二极管PD进行复位。
可选地，如图3所示，其中，一个子像素还包括寄生电容器C FD，其中，所述光电二极管PD的正极接地，所述光电二极管PD的负极接所述传输管 M1的源极，所述传输管M1的栅极由传输信号TX控制，所述传输管M1的漏极分别与所述寄生电容器C FD的一端、所述源跟随输入管M3的栅极以及所述复位开关管M2的源极相连，所述寄生电容器C FD的另一端接地，所述复位开关管的漏极接复位电压V rst，所述复位开关管的栅极由复位信号RST控制，所述源跟随输入管M3的源极与所述选通开关管M4的漏极相连，所述源跟随输入管M3的漏极接电源电压VCCP，所述选通开关管M4的栅极由选通信号RSEL控制，所述选通开关管M4的源极输出相应子像素的输出电压。例如，子像素1输出V p1，子像素2输出V p2，子像素3输出V p3，子像素4输出V p4。
需要说明的是，本申请实施例中子像素的电路结构包括但不限于图3所示电路结构。例如，该子像素的电路结构还可以是电容反馈跨阻放大器(Capacitive Trans-impedance Amplifier，CTIA)结构。
下面将结合图3的实施例在下文中详细说明本申请实施例的暗电流相关双采样器。
图4是本申请一个实施例的暗电流相关双采样器的电路示意图。其中，V p1，V p2，V p3，V p4分别对应图3中的每个子像素的输出电压，V p1，V p2以及V p3为一个像素单元中的有源子像素的输出电压，V p4为一个像素单元中的暗子像素的输出电压。
如图4所示，暗电流相关双采样器包括：1个电容器101(即图2中的第二电容器)、3个电容器102(即图2中的第一电容器)、运算放大器103(即图2中的运算放大器)、开关组1041和开关组1042(即图2中的开关电路，可以包括第一开关组和第二开关组)以及积分电容器105(即图2中的积分电容器)。
其中，电容器101的一端与图3中的一个像素单元中的暗子像素的输出电压V p4通过开关组1041中的至少一个开关相连以及通过开关组1042中的一个开关与运算放大器103的反相输入端相连，电容器101的另一端与共模电压VCM相连，该共模电压也可以称为是参考电压。每个电容器102的一端通过开关组1041中的一个开关与图3中的一个像素单元中的一个有源子像素的输出电压相连。即3个电容器102的一端分别与V p1，V p2以及V p3相连，该每个电容器102的一端还可以通过开关组1042中的一个开关与共模电压相连，即3个第一电容器102的一端均连接到共模电压。该3个电容器 102的另一端可以通过开关组1042中的同一个开关与运算放大器103的反相输入端相连以及通过开关组1041与共模电压相连。积分电容器105与开关组1041中的一个开关并联，并且连接在运算放大器103的反相输入端与输出端之间。运算放大器103的正向输入端可以与共模电压相连。
可选地，电容器101的一端可以通过开关组1041中的一个开关或多个开关与V p4相连，例如，可以通过与电容器102的数量相同的开关与V p4相连，本申请实施例对此不构成限定。具体地，在本申请实施例中，电容器101的一端可以通过开关组1041中的3个开关与V p4相连，由此可以尽量避免开关对电路所带来的电荷馈通的影响(或电荷注入的影响)。
下面将结合图6中的时序图描述图4中所示的暗电流相关双采样器的工作时序。
对于图6，图4中的暗电流相关双采样器的工作时序主要包括四个阶段，其中，第一阶段(下述T4时间段)、第二阶段(下述T5时间段)、第三阶段(下述T1时间段)以及第四阶段(下述T2时间段)。
具体地，在T1时间段，所选中的某行、某列像素单元中的四个子像素的RST和TX为高，复位开关管M2和传输管M1导通，FD和光电二极管PD均被复位至V rst电压，此时输出电压理论值为V P1_0、V P2_0、V P3_0和V P3_0。因为它们是同时被复位，且认为每个子像素的读出电路误差相同，那么V P1_0＝V P2_0＝V P3_0＝V P4_0＝V P_RST，其中，V P_RST＝V rst-V gs，V gs为源跟随输入管的栅源电压。在T2时间段，RST和TX为低，复位开关管M2和传输管M1关闭，所述像素单元开始曝光。在此阶段里，有源子像素根据进光量不同转换出对应的电子，相应的还有暗电流积累的电子；暗子像素因为处于暗环境而对光不敏感因此仅积累暗电流产生的电子。可选地，在单个像素单元内，我们可以认为四个子像素的暗电流密度近似相等，而它们的PD面积之比和C FD之比相等，因此在曝光结束时刻，我们可以表示有源子像素的输出电压V p1～3＝V P_RST–V P_LI–V P_DK＝V sig_a1～3，即V p1＝V sig_a1,V p2＝V sig_a2,V p3＝V sig_a3,其中，V P_LI表示在一定曝光时间内进光量转换出的电压，V P_DK表示在一定曝光时间内暗电流产生电压，假设V sig_a1～3＝V sig_a；同理，在曝光结束时刻V P4＝V P_RST–V P_DK＝V sig_d。在T3时间段，暗电流相关双采样器的运算放大器使能信号OP_EN为高，运算放大器103提前开启准备工作。
假设，开关组1041由开关信号SW1控制，开关组1042由开关信号SW2 控制，电容器102的电容值用C2表示，电容器101的电容值用C1表示，积分电容器105的电容值用C int表示，运算放大器用OP表示，其中，C1与3个C2之和相等，即若C2＝C，则C1＝3C。
在T4时间段，SW1拉高导通开关组1041，SW2拉低闭合开关组1042。电容器101对V P4采样，电容器101上的电荷量：Q1＝3C*(V sig_d-VCM)；电容器102对V P1/V P2/V P3采样并求平均，3个电容器102并联构成的等效电容器上的电荷量：Q2＝3C*(V sig_a-VCM)；积分电容器105被复位，利用OP的虚短原理，VO＝VCM。
在T5时间段，SW1拉低关闭开关组1041，SW2拉高导通开关组1042。电容器101的上极板接OP的反相输入端，电容器101的下极板接VCM，电容器102的下极板接OP的反相输入端，电容器102的上极板接VCM，电容器101、电容器102的电荷转移至积分电容器105，假设OP增益足够大，利用OP的虚短原理，
Figure PCTCN2019103247-appb-000001
根据电容器101上的电荷与3个电容器102并联构成的等效电容器上的电荷之和等于积分电容器105上的电荷，可以推导出如下公式：
-C int(VO-VCM)+C1*(V sig_d-VCM)-C2’*(V sig_a-VCM)＝0
其中，C2’表示3个电容器102并联构成的等效电容器的电容值，假设C int＝n*C，C1＝C2’＝3*C，代入上述公式，则
VO＝VCM+(V sig_d-V sig_a)*3/n＝VCM-V P_LI*3/n
从上可知，本申请实施例中的暗电流相关双采样器可以通过n个第一电容器和m个第二电容器同时对有源像素的输出电压和暗像素的输出电压进行采样，并且将采样后的n个第一电容器和m个第二电容器上的电荷同时转移到积分电容器上，从而能够实现将有源像素中的暗电流消除的目的。在本申请实施例中，暗电流相关双采样器的输出信号仅剩共模电压VCM和光照转换电压V P_LI，即可得到有用的光照转换信号量，从而达到了消除暗电流影响的作用。同时可以通过调节系数n实现信号放大作用而省去PGA。
图5是本申请另一个实施例的暗电流相关双采样器的电路示意图。其中，V p1，V p2，V p3，V p4分别对应图3中的每个子像素的输出电压，V p1，V p2以及V p3为一个像素单元中的有源子像素的输出电压，V p4为一个像素单元中的暗子像素的输出电压。
如图5所示，暗电流相关双采样器包括：1个电容器201(即图2中的 第二电容器)、3个电容器202(即图2中的第一电容器)、运算放大器203(即图2中的运算放大器)、开关组2041和开关组2042(即图2中的开关电路，可以包括第一开关组和第二开关组)以及积分电容器205(即图2中的积分电容器)。
其中，电容器201的一端与图3中的一个像素单元中的暗子像素的输出电压V p4通过开关组2041中的至少一个开关相连，以及通过开关组2042中的至少一个开关与共模电压VCM相连，该共模电压也可以称为是参考电压。该电容器201的另一端通过开关组2042中的一个开关与运算放大器203的反相输入端相连以及通过开关组2041中的一个开关与VCM相连。每个电容器202的一端通过开关组2041中的一个开关与图3中的一个像素单元中的一个有源子像素的输出电压相连。即3个电容器202的一端分别与V p1，V p2以及V p3相连，该每个电容器202的一端还可以通过开关组2042中的一个开关与运算放大器203的反相输入端相连，即3个电容器202的一端可以通过开关组2042中的同一个开关与运算放大器203的反相输入端相连。每个电容器202的另一端与共模电压相连。积分电容器205与开关组2041中的一个开关并联，并且连接在运算放大器203的反相输入端与输出端之间。运算放大器203的正向输入端与共模电压相连。
可选地，电容器201的一端可以通过开关组2041中的一个开关或多个开关与V p4相连，例如，可以通过与电容器202的数量相同的开关与V p4相连，本申请实施例对此不构成限定。具体地，在本申请实施例中，电容器201的一端可以通过开关组2041中的3个开关与V p4相连，由此可以尽量避免开关对电路所带来的电荷馈通的影响(或电荷注入的影响)。
下面将结合图6中的时序图描述图5中所示的暗电流相关双采样器的工作时序。
类似地，对于图6，图4中的暗电流相关双采样器的工作时序主要包括四个阶段，其中，第一阶段(下述T4时间段)、第二阶段(下述T5时间段)、第三阶段(下述T1时间段)以及第四阶段(下述T2时间段)。
具体地，在T1时间段，所选中的某行、某列像素单元中的四个子像素的RST和TX为高，复位开关管M2和传输管M1导通，FD和光电二极管PD均被复位至V rst电压，此时输出电压理论值为V P1_0、V P2_0、V P3_0和V P3_0。因为它们是同时被复位，且认为每个子像素的读出电路误差相同，那么 V P1_0＝V P2_0＝V P3_0＝V P4_0＝V P_RST，其中，V P_RST＝V rst-V gs，V gs为源跟随输入管的栅源电压。在T2时间段，RST和TX为低，复位开关管M2和传输管M1关闭，所述像素单元开始曝光。在此阶段里，有源子像素根据进光量不同转换出对应的电子，相应的还有暗电流积累的电子；暗子像素因为处于暗环境而对光不敏感因此仅积累暗电流产生的电子。可选地，在单个像素单元内，我们可以认为四个子像素的暗电流密度近似相等，而它们的PD面积之比和C FD之比相等，因此在曝光结束T3时刻，我们可以表示有源子像素的输出电压V p1～3＝V P_RST–V P_LI–V P_DK＝V sig_a1～3，即V p1＝V sig_a1,V p2＝V sig_a2,V p3＝V sig_a3,其中，V P_LI表示在一定曝光时间内进光量转换出的电压，V P_DK表示在一定曝光时间内暗电流产生电压，假设V sig_a1～3＝V sig_a；同理，在曝光结束时刻V P4＝V P_RST–V P_DK＝V sig_d。在T3时间段，暗电流相关双采样器的运算放大器使能信号OP_EN为高，运算放大器103提前开启准备工作。
假设，开关组2041由开关信号用SW1控制，开关组2042由开关信号SW2控制，电容器202的电容值用C1表示，电容器201的电容值用C2表示，积分电容器205的电容值用C int表示，运算放大器用OP表示，其中，C2与3个C1之和相等，即若C1＝C，则C2＝3C。
在T4时间段，SW1拉高导通开关组2041，SW2拉低闭合开关组2042。电容器201对V P4采样，电容器201上的电荷量：Q1＝3C*(V sig_d-VCM)；电容器202对V P1/V P2/V P3采样并求平均，3个电容器202并联构成的等效电容器上的电荷量：Q2＝3C*(V sig_a-VCM)；积分电容器205被复位，利用OP的虚短原理，VO＝VCM。
在T5时间段，SW1拉低关闭开关组2041，SW2拉高导通开关组2042，电容器201的下极板接OP的反相输入端，电容器201的上极板接VCM，电容器202的上极板接OP的反相输入端，电容器202的下极板接VCM，电容器201、电容器202的电荷转移至积分电容器205，假设OP增益足够大，利用OP的虚短原理，
Figure PCTCN2019103247-appb-000002
根据电容器201上的电荷与3个电容202并联构成的等效电容器上的电荷之和等于积分电容器205上的电荷，可以推导出如下公式：
-C int(VO-VCM)-C1’*(V sig_d-VCM)+C2*(V sig_a-VCM)＝0
其中，C1’表示3个电容202并联构成的等效电容器的电容值，假设C int＝n*C，C1’＝C2＝3*C，代入上述公式，则
VO＝VCM+(V sig_a-V sig_d)*3/n＝VCM+V P_LI*3/n
从上可知，本申请实施例中的暗电流相关双采样器可以通过n个第一电容器和m个第二电容器同时对有源像素的输出电压和暗像素的输出电压进行采样，并且将采样后的n个第一电容器和m个第二电容器上的电荷同时转移到积分电容器上，从而能够实现将有源像素中的暗电流消除的目的。在本申请实施例中，暗电流相关双采样器的输出信号仅剩共模电压VCM和光照转换电压V P_LI，即可得到有用的光照转换信号量，从而达到了消除暗电流影响的作用。同时可以通过调节系数n实现信号放大作用而省去PGA。
需要说明的是，本申请实施例的暗电流相关双采样器包括但不限于应用于图像传感器中。
上述结合图2至图6详细说明本申请实施例的暗电流相关双采样器的电路示意图，下面结合图7说明上述暗电流相关双采样器的应用实例。这里，图7以图像传感器为例进行说明。
如图7所示，该图像传感器包括像素阵列301、上述各种实施例中的暗电流相关双采样器302以及模数转换器303。其中，像素阵列301可以包括X行Y列的像素单元，暗电流相关双采样器302的数量可以为至少一个，每一个暗电流相关双采样器302用于采集像素阵列300中的n个有源像素和m个暗像素，并通过从n个有源像素的输出电压中减去m个暗像素的输出电压，以补偿n个有源像素中的暗电流，模数转换器303用于将暗电流相关双采样器302的模拟输出转换成数字输出。
可选地，该图像传感器还包括行扫描控制器304和列扫描控制器305，并且该n个有源像素和m个暗像素构成了像素阵列301中的一个像素单元，也就是说，该像素阵列可以包括多个像素单元，该行扫描控制器304和列扫描控制器305用于选择像素阵列301中的一个像素单元。
通过暗电流相关双采样器对暗电流做两次采样并相减消除，从而不需要专门的存储器、补偿电路以及PGA等其他硬件电路，能够减少图像传感器的硬件成本。
图8示出了本申请实施例的暗电流补偿方法400的示意性框图。该方法400由暗电流相关双采样器执行，所述暗电流相关双采样器包括开关电路、n个第一电容器、m个第二电容器、积分电容器和运算放大器，所述n个第一电容器的电容值之和与所述m个第二电容器的电容值之和相等，n和m均 为正整数，暗电流补偿方法400的具体流程如下。
S401，在第一阶段，在所述开关电路的控制下，所述n个第一电容器分别对n个有源像素的输出电压进行采样，所述m个第二电容器分别对m个暗像素的输出电压进行采样；
S402，在第二阶段，在所述开关电路的控制下，采样后的所述n个第一电容器上的电荷和采样后的所述m个第二电容器的电荷分别向所述积分电容器转移，所述运算放大器的输出电压用于表示所述n个有源像素的输出电压与所述m个暗像素的输出电压的差值。
可选地，所述运算放大器的输出电压用于表示所述n个有源像素的输出电压的平均值与所述m个暗像素的输出电压的平均值之间的差值。
根据本申请实施例的暗电流补偿方法可对应于本申请实施例的暗电流相关双采样器中的各个单元/模块，并且，该方法中的相应流程都可以通过图2、图4和图5中所示暗电流相关双采样器中的各个单元/模块来实现，为了简洁，在此不再赘述。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
应理解，在本申请实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
另外，本文中术语“系统”和“网络”在本文中常可互换使用。应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各 示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限 于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (17)

  1. 一种暗电流相关双采样器，其特征在于，所述暗电流相关双采样器包括：开关电路、n个第一电容器、m个第二电容器、积分电容器和运算放大器，其中，所述n个第一电容器的电容值之和与所述m个第二电容器的电容值之和相等，n和m均为正整数；
    所述n个第一电容器通过所述开关电路分别与n个有源像素的输出电压和所述运算放大器的反相输入端相连，所述m个第二电容器通过所述开关电路分别与m个暗像素的输出电压和所述反相输入端相连，所述积分电容器通过所述开关电路连接在所述反相输入端与所述运算放大器的输出端之间。
  2. 根据权利要求1所述的暗电流相关双采样器，其特征在于，
    在第一阶段，所述开关电路用于控制所述n个第一电容器和所述m个第二电容器进行充电，所述开关电路还用于控制所述积分电容器进行放电；
    在第二阶段，所述开关电路用于控制所述n个第一电容器和所述m个第二电容器停止充电，并且控制所述n个第一电容器和所述m个第二电容器向所述积分电容器放电。
  3. 根据权利要求1或2所述的暗电流相关双采样器，其特征在于，所述n个第一电容器的电容值之和以及所述m个第二电容器的电容值之和分别与所述积分电容器的电容值之比为k/p，其中，k大于或等于p。
  4. 根据权利要求1至3中任一项所述的暗电流相关双采样器，其特征在于，所述n个有源像素和所述m个暗像素构成像素阵列中的一个像素单元。
  5. 根据权利要求1至4中任一项所述的暗电流相关双采样器，其特征在于，n为大于1的正整数。
  6. 根据权利要求1至5中任一项所述的暗电流相关双采样器，其特征在于，所述开关电路包括第一开关组和第二开关组，
    所述n个第一电容器的一端通过所述第一开关组与所述n个有源像素的输出电压以及通过所述第二开关组与共模电压相连，所述n个第一电容器的另一端通过所述第一开关组与所述共模电压相连以及通过所述第二开关组与所述反相输入端相连，所述m个第二电容器的一端通过所述第一开关组与所述m个暗像素的输出电压以及通过所述第二开关组与所述反相输入端相连，所述m个第二电容器的另一端与所述共模电压相连，所述积分电容器与所述第一开关组中的开关并联，所述运算放大器的正向输入端与所述共模电 压相连。
  7. 根据权利要求1至5中任一项所述的暗电流相关双采样器，其特征在于，所述开关电路包括第一开关组和第二开关组，
    所述n个第一电容器的一端通过所述第一开关组与所述n个有源像素的输出电压以及通过所述第二开关组与所述反相输入端相连，所述n个第一电容器的另一端与共模电压相连，所述m个第二电容器的一端通过所述第一开关组与所述m个暗像素的输出电压以及通过所述第二开关组与所述共模电压相连，所述m个第二电容器的另一端通过所述第一开关组与所述共模电压以及通过所述第二开关组与所述反相输入端相连，所述积分电容器与所述第一开关组中的开关并联，所述运算放大器的正向输入端与所述共模电压相连。
  8. 根据权利要求6或7所述的暗电流相关双采样器，其特征在于，
    在第一阶段，所述第一开关组闭合，所述第二开关组断开；
    在第二阶段，所述第一开关组断开，所述第二开关组闭合。
  9. 根据权利要求1至8中任一项所述的暗电流相关双采样器，其特征在于，所述n个有源像素和所述m个暗像素中的任一像素包括光电二极管、传输管、复位开关管、源跟随输入管以及选通开关管；
    其中，不同强度的光照在所述光电二极管中产生不同量的电荷，在所述传输管的传输下将产生的电荷转换成电压，转换后的电压通过所述源跟随输入管和所述选通开关管输出到所述第一电容器或所述第二电容器，所述复位开关管用于对所述光电二极管进行复位。
  10. 根据权利要求9所述的暗电流相关双采样器，其特征在于，所述任一像素还包括寄生电容器；
    其中，所述光电二极管的正极接地，所述光电二极管的负极接所述传输管的源极，所述传输管的栅极由传输信号控制，所述传输管的漏极分别与所述寄生电容器的一端、所述源跟随输入管的栅极以及所述复位开关管的源极相连，所述寄生电容器的另一端接地，所述复位开关管的漏极接复位电压，所述复位开关管的栅极由复位信号控制，所述源跟随输入管的源极与所述选通开关管的漏极相连，所述源跟随输入管的漏极接电源电压，所述选通开关管的栅极由选通信号控制，所述选通开关管的源极输出相应像素的输出电压。
  11. 根据权利要求9或10所述的暗电流相关双采样器，其特征在于，
    在第三阶段，所述n个有源像素和所述m个暗像素中的所有像素的复位 开关管和传输管导通，所述所有像素的光电二极管被复位至复位电压；
    在第四阶段，所述所有像素的复位开关管和传输管关闭，所述所有像素开始曝光。
  12. 一种图像传感器，其特征在于，包括像素阵列、如权利要求1至11中任一项所述的暗电流相关双采样器和模数转换器，所述像素阵列包括所述n个有源像素和所述m个暗像素，所述模数转换器用于将所述暗电流相关双采样器的模拟输出转换成数字输出。
  13. 根据权利要求12所述的图像传感器，其特征在于，所述n个有源像素和所述m个暗像素构成所述像素阵列中的一个像素单元，所述图像传感器还包括行扫描控制器和列扫描控制器，所述行扫描控制器和所述列扫描控制器用于选择所述一个像素单元。
  14. 一种暗电流补偿方法，其特征在于，所述方法由暗电流相关双采样器执行，所述暗电流相关双采样器包括开关电路、n个第一电容器、m个第二电容器、积分电容器和运算放大器，所述n个第一电容器的电容值之和与所述m个第二电容器的电容值之和相等，n和m均为正整数，所述方法包括：
    在第一阶段，在所述开关电路的控制下，所述n个第一电容器分别对n个有源像素的输出电压进行采样，所述m个第二电容器分别对m个暗像素的输出电压进行采样；
    在第二阶段，在所述开关电路的控制下，采样后的所述n个第一电容器上的电荷和采样后的所述m个第二电容器的电荷分别向所述积分电容器转移，所述运算放大器的输出电压用于表示所述n个有源像素的输出电压与所述m个暗像素的输出电压的差值。
  15. 根据权利要求14所述的暗电流补偿方法，其特征在于，所述n个第一电容器通过所述开关电路分别与所述n个有源像素的输出电压和所述运算放大器的反相输入端相连，所述m个第二电容器通过所述开关电路分别与所述m个暗像素的输出电压和所述反相输入端相连，所述积分电容器通过所述开关电路连接在所述反相输入端与所述运算放大器的输出端之间。
  16. 根据权利要求14或15所述的暗电流补偿方法，其特征在于，所述n个第一电容器的电容值之和以及所述m个第二电容器的电容值之和分别与所述积分电容器的电容值之比为k/p，其中，k大于或等于p。
  17. 根据权利要求14至16中任一项所述的暗电流补偿方法，其特征在于，所述n个有源像素和所述m个暗像素构成像素阵列中的一个像素单元。
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