WO2016026416A1 - 低压差线性稳压器电路、芯片和电子设备 - Google Patents

低压差线性稳压器电路、芯片和电子设备 Download PDF

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Publication number
WO2016026416A1
WO2016026416A1 PCT/CN2015/087312 CN2015087312W WO2016026416A1 WO 2016026416 A1 WO2016026416 A1 WO 2016026416A1 CN 2015087312 W CN2015087312 W CN 2015087312W WO 2016026416 A1 WO2016026416 A1 WO 2016026416A1
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Prior art keywords
transistor
voltage
terminal
module
regulator circuit
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PCT/CN2015/087312
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English (en)
French (fr)
Inventor
张楠
周晶
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无锡华润上华半导体有限公司
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Priority to US15/327,916 priority Critical patent/US9952609B2/en
Publication of WO2016026416A1 publication Critical patent/WO2016026416A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a low dropout linear regulator circuit, a chip, and an electronic device.
  • the output voltage-free low-dropout linear regulator circuit consists of the following components: a voltage reference source, an error amplifier, a power transfer device, and a feedback circuit.
  • the feedback voltage of the feedback circuit is compared with the reference voltage of the voltage reference source by the error amplifier, and the difference is amplified to control the conduction state of the power transmission device, thereby obtaining a stable output voltage.
  • the loop just started to work and the error amplifier can not effectively control the operation of the power transmission device. Therefore, there will be a conduction phase of the power transmission device, which will cause the input voltage to be directly output. To the output voltage terminal, a voltage overshoot occurs. Since the parasitic capacitance at the output voltage terminal is relatively small, the voltage overshoot has a large influence on the voltage at the output voltage terminal.
  • a low dropout linear regulator circuit comprising a voltage reference source module, an error amplifier, a reference voltage judging module, a power transfer device and a feedback module; the voltage reference source module providing a reference voltage for the error amplifier, the reference voltage
  • the determining module controls the enabling of the error amplifier according to whether the voltage reference source module is fully activated, and the error amplifier controls the reference according to a reference voltage provided by the voltage reference source module and a feedback voltage provided by the feedback module.
  • the power transmission device is switched on and off.
  • a chip comprising the low dropout linear regulator circuit described above.
  • An electronic device comprising the above described chip.
  • the low-dropout linear regulator circuit, chip and electronic device are applied to a no-output capacitor LDO circuit, including a reference voltage judging module, detecting whether the voltage reference source module is completed, and transmitting to the error amplifier if the voltage reference source module is completed.
  • a signal that starts to work that is, by delaying the start time of the error amplifier from the voltage reference source module, enables the error amplifier to effectively control the operation of the power transfer device, thereby avoiding an overshoot phenomenon in the startup process of the LDO without output capacitor.
  • FIG. 1 is a block diagram of an embodiment of a low dropout linear regulator circuit
  • FIG. 2 is a schematic diagram of a reference voltage judging module of an embodiment
  • FIG. 3 is a schematic diagram of a reference voltage judging module of another embodiment
  • FIG. 4 is a schematic diagram of a reference voltage judging module according to still another embodiment
  • FIG. 5 is a block diagram of another embodiment of a low dropout linear regulator circuit
  • FIG. 6 is a schematic diagram of another embodiment of a low dropout linear regulator circuit.
  • a reference signal port symbol indicates that the signal or a reference signal symbol indicates the signal port.
  • an embodiment of a low dropout linear regulator circuit includes a voltage reference source module 100, an error amplifier 200, a reference voltage determination module 300, a power transfer device 400, and a feedback module 500.
  • the voltage reference source module 100 provides a reference voltage for the error amplifier 200.
  • the reference voltage determination module 300 controls the enable of the error amplifier 200 according to whether the voltage reference source module 100 is fully activated.
  • the error amplifier 200 is based on the reference voltage supplied by the voltage reference source module 100.
  • the feedback voltage provided by the feedback module 500 controls the on and off of the power transfer device 400.
  • VIN is the input voltage terminal and represents the input voltage.
  • VOUT is the output voltage terminal and represents the output voltage.
  • the low-dropout linear regulator circuit is applied to the output-free capacitor LDO circuit, and includes a reference voltage judging module 300.
  • the sampling reference voltage Vref is used to detect whether the voltage reference source module 100 is completed, and if the voltage reference source module 100 completes the startup,
  • the error amplifier 200 sends a start signal ON, that is, by delaying the start time of the error amplifier 200 from the voltage reference source module 100, so that the error amplifier 200 can effectively control the operation of the power transfer device, thereby avoiding the output-free capacitor LDO circuit. Overshoot occurred during the startup process.
  • the voltage reference source module 100 includes a first output coupled to the inverting input (-) of the error amplifier 200 and a second output coupled to the decision signal input Vref of the reference voltage determination module 300.
  • the reference voltage determination module 300 includes a determination signal input terminal Vref and a determination signal output terminal ON connected to the enable terminal of the error amplifier 200.
  • the error amplifier 200 includes an inverting input (-), an enable terminal, an amplified signal output coupled to the control terminal of the power transfer device 400, and a non-inverting input (+) coupled to the feedback terminal of the feedback module 500.
  • the enable terminal can be the negative supply terminal of the error amplifier 200.
  • the power transfer device 400 includes a control terminal, a switch input terminal connected to the input voltage terminal VIN, and a switch output terminal connected to the current input terminal of the feedback module 500.
  • the feedback module 500 includes a feedback terminal and a current input terminal.
  • FIG. 2 is a schematic diagram of a reference voltage judging module of an embodiment.
  • the first extreme source of the transistor the second extreme drain of the transistor.
  • the reference voltage judging module 300 includes:
  • the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, the third transistor M3 and the fourth transistor M4 form a mirror current source, and the input voltage terminal VIN provides a reference current for the mirror current source.
  • the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are N-channel field effect transistors.
  • the gate of the first transistor M1 serves as a determination signal input terminal Vref for controlling the gate of the second transistor M2 to be turned on to the input voltage terminal VIN or the ground GND.
  • the first pole of the second transistor M2 is connected to the common gate terminal of the mirror current source, and the second pole of the second transistor M2 is grounded to control the mirror current source to provide the judgment signal ON for the error amplifier 200, that is, the enable end of the error amplifier 200.
  • a bias current is provided to operate the error amplifier 200.
  • the input voltage terminal VIN is connected to the first pole of the first transistor M1 and the gate of the fourth transistor M4 through the first load network 310, and is connected to the first pole of the second transistor M2 through the second load network 320; the first transistor M1 The second poles of the second transistor M2, the third transistor M3, and the fourth transistor M4 are grounded; the gate of the third transistor M3 and the gate of the fourth transistor M4 are connected as a common gate terminal of the mirror current source, and the second transistor M2 One pole is shorted to the gate, and the first pole of the third transistor M3 is turned ON as a determination signal.
  • the voltage reference source module 100 After the input voltage terminal VIN is powered on, the voltage reference source module 100 starts to start, the bias current in the voltage reference source module 100 starts to work normally, the reference voltage Vref starts to rise, and the determination signal input end of the reference voltage determination module 300 starts to benchmark. Voltage Vref is sampled.
  • the gate voltage of the first transistor M1 is insufficient to turn on the first transistor M1, and the gate voltage of the fourth transistor M4 is at a high level.
  • the four transistor M4 is turned on, and the gate of the third transistor M3 (connected to the common gate terminal of the mirror current source) is grounded, which lowers the voltage of the gate of the third transistor M3, so that the third transistor M3 cannot provide a bias to the error amplifier 200. Set the current.
  • the first transistor M1 When the reference voltage Vref rises to the turn-on voltage VR, the first transistor M1 is fully turned on, the gate of the fourth transistor M4 is grounded, the gate voltage of the fourth transistor M4 is pulled low, and the fourth transistor M4 is turned from off to off.
  • the mirror current source operates, and the third transistor M3 supplies a bias current to the error amplifier 200.
  • the foregoing embodiment may be further modified, in which the first load network 310 and the second load network 320 respectively take a current limit voltage limit of the first resistor R1 and the second resistor R2, or the first load network.
  • the third load network 310 and the second load network 320 are respectively taken as the fifth transistor M5 and the sixth transistor M6 to cooperate with the first transistor M1 and the second transistor M2.
  • the fifth transistor M5 and the sixth transistor M6 are P-channel field effect transistors.
  • the voltage reference source module 100 connects the gate of the fifth transistor M5 and the gate of the sixth transistor M6 to provide a bias voltage BIAS.
  • the input voltage terminal VIN is connected to the second pole of the fifth transistor M5 and the second pole of the sixth transistor M6, and the first pole of the fifth transistor M5 is connected to the first pole of the first transistor M1 and the gate of the fourth transistor, sixth The first pole of the transistor M6 is coupled to the first pole of the second transistor M2.
  • the input voltage terminal VIN is connected to the first electrode of the first transistor M1 through the first resistor R1
  • the input voltage terminal VIN is connected to the gate of the fourth transistor M4 through the first resistor R1
  • the input voltage terminal VIN is passed through the second
  • the resistor R2 is connected to the first pole of the second transistor M2. See Figure 4.
  • Figure 5 is a block diagram of another embodiment of a low dropout linear regulator circuit. Please refer to Figure 6.
  • a low dropout linear regulator circuit includes a voltage reference source module 100, an error amplifier 200, a reference voltage determination module 300, a power transfer device 400, a feedback module 500, and a startup circuit module 600.
  • the startup circuit module 600 is used to control the startup of the voltage reference source module 100.
  • the startup circuit 600 controls the connection voltage reference source module 100.
  • the first output terminal of the voltage reference source module 100 is connected to the inverting input terminal of the error amplifier 200, and the second output terminal of the voltage reference source module 100 is connected to the judgment of the reference voltage determination module 300.
  • the signal input terminal Vref, the determination signal output terminal of the reference voltage determination module 300 is connected to the enable terminal on of the error amplifier 200, and the amplification signal output terminal of the error amplifier 200 is connected to the control terminal of the power transmission device 400, and the non-inverting input terminal of the error amplifier 200.
  • the feedback terminal of the feedback module 500 is connected.
  • the switch input terminal of the power transfer device 400 is connected to the input voltage VIN, and the switch output terminal of the power transfer device 400 is connected to the current input terminal of the feedback module 500.
  • the enable end on the error amplifier 200 can be the negative supply terminal of the error amplifier 200.
  • the feedback module 500 includes a third resistor R3 and a fourth resistor R4.
  • the current input terminal is grounded through the third resistor R3 and the fourth resistor R4, and the junction of the third resistor R3 and the fourth resistor R4 serves as a feedback terminal.
  • the error amplifier 200 adjusts the output voltage VOUT by comparing the voltage of the fourth resistor R4 with the sampling of the reference voltage of the voltage reference source module 100.
  • the power transfer device 400 is a field effect transistor, which in this embodiment is a P-channel field effect transistor.
  • the control terminal of the power transfer device 400 is the gate of the P-channel field effect transistor, the switching input terminal, that is, the source of the P-channel field effect transistor, and the switching output terminal, that is, the drain of the P-channel field effect transistor.
  • the invention also discloses a chip and an electronic device.
  • a chip comprising the low dropout linear regulator circuit described above.
  • An electronic device comprising the low dropout linear regulator circuit described above.
  • the low-dropout linear regulator circuit, chip and electronic device comprise a reference voltage judging module, detecting whether the voltage reference source module is completed, and if the voltage reference source module is completed, sending a signal to the error amplifier to start working, that is, passing The delay time of the error amplifier is delayed compared with the voltage reference source module, so that the error amplifier can effectively control the operation of the power transmission device, thereby avoiding the overshoot phenomenon of the LDO circuit without the output capacitor during the startup process.

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Abstract

一种低压差线性稳压器电路，其特征在于，包括电压基准源模块（100）、误差放大器（200）、基准电压判断模块（300）、功率传输器件（400）和反馈模块（500）；所述电压基准源模块（100）为所述误差放大器（200）提供基准电压，所述基准电压判断模块（300）根据所述电压基准源模块（100）是否完全启动来控制所述误差放大器（200）的使能，所述误差放大器（200）根据所述电压基准源模块（100）提供的基准电压和所述反馈模块（500）提供的反馈电压来控制所述功率传输器件（400）的通断。一种具有上述低压差线性稳压器电路的芯片和具有上述芯片的电子设备。

Description

低压差线性稳压器电路、芯片和电子设备
【技术领域】
本发明涉及半导体器件技术领域，特别涉及一种低压差线性稳压器电路、芯片和电子设备。
【背景技术】
无输出电容低压差线性稳压器（LDO, Low Drop-Out regulator）电路由于具有结构简单、成本低廉、低噪声、低功耗及较小的封装尺寸等优点，已成为移动电子设备中电源管理的首选。由于其可以省去输出端的外挂电容和键合金线，可以有效降低产品的成本，逐渐被应用在SOC产品中。
无输出电容低压差线性稳压器电路主要由以下几个部分构成：电压基准源、误差放大器、功率传输器件和反馈电路。由误差放大器将反馈电路的反馈电压和电压基准源的参考电压进行比较，并放大其差值来控制功率传输器件的导通状态，从而得到稳定的输出电压。但是在刚上电的过程中，环路刚开始工作，误差放大器并不能有效的控制功率传输器件的工作，所以此时功率传输器件会存在一个导通的阶段，这样就会造成输入电压直接输出至输出电压端，产生电压过冲现象。由于输出电压端的寄生电容比较小，所以，电压过冲会对输出电压端的电压有较大影响。
【发明内容】
基于此，有必要提供一种低压差线性稳压器电路，该低压差线性稳压器电路可以有效避免电压过冲的现象。
一种低压差线性稳压器电路，包括电压基准源模块、误差放大器、基准电压判断模块、功率传输器件和反馈模块；所述电压基准源模块为所述误差放大器提供基准电压，所述基准电压判断模块根据所述电压基准源模块是否完全启动来控制所述误差放大器的使能，所述误差放大器根据所述电压基准源模块提供的基准电压和所述反馈模块提供的反馈电压来控制所述功率传输器件的通断。
一种芯片，包括上述的低压差线性稳压器电路。
一种电子设备，包括上述的芯片。
上述低压差线性稳压器电路、芯片和电子设备，应用于无输出电容LDO电路，包括了基准电压判断模块，检测电压基准源模块是否完成启动，如果电压基准源模块完成启动则给误差放大器发送一个开始工作的信号，即通过使误差放大器的启动时间较电压基准源模块延后，使得误差放大器能有效的控制功率传输器件的工作，从而避免无输出电容LDO电路在启动过程出现过冲现象。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例低压差线性稳压器电路的模块图；
图2是一实施例基准电压判断模块的原理图；
图3是另一实施例基准电压判断模块的原理图；
图4是再一实施例基准电压判断模块的原理图；
图5是另一实施例低压差线性稳压器电路的模块图；
图6是另一实施例低压差线性稳压器电路的原理图。
【具体实施方式】
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
下面结合附图，对本发明的具体实施方式进行详细描述。在下面说明书中，为了易于理解，引用信号端口符号表示该信号或者引用信号符号表示该信号端口。
请参阅图1，一实施例低压差线性稳压器电路包括电压基准源模块100、误差放大器200、基准电压判断模块300、功率传输器件400和反馈模块500。电压基准源模块100为误差放大器200提供基准电压，基准电压判断模块300根据电压基准源模块100是否完全启动来控制误差放大器200的使能，误差放大器200根据电压基准源模块100提供的基准电压和反馈模块500提供的反馈电压来控制功率传输器件400的通断。VIN为输入电压端同时表示输入电压，VOUT为输出电压端同时表示输出电压。
上述低压差线性稳压器电路，应用于无输出电容LDO电路，包括了基准电压判断模块300，通过采样基准电压Vref检测电压基准源模块100是否完成启动，如果电压基准源模块100完成启动则给误差放大器200发送一个开始工作的信号ON，即通过使误差放大器200的启动时间较电压基准源模块100延后，使得误差放大器200能有效的控制功率传输器件的工作，从而避免无输出电容LDO电路在启动过程出现过冲现象。
见图1，上述低压差线性稳压器电路的具体连接关系为：
电压基准源模块100包括与误差放大器200的反相输入端（-）连接的第一输出端、与基准电压判断模块300的判断信号输入端Vref连接的第二输出端。
基准电压判断模块300包括判断信号输入端Vref、与误差放大器200的使能端连接的判断信号输出端ON。
误差放大器200包括反相输入端（-）、使能端、与功率传输器件400的控制端连接的放大信号输出端、与反馈模块500的反馈端连接的同相输入端（+）。使能端可以是误差放大器200的负电源端。
功率传输器件400包括控制端、连接输入电压端VIN的开关输入端、与反馈模块500的电流输入端连接的开关输出端。
反馈模块500包括反馈端和电流输入端。
图2是一实施例基准电压判断模块的原理图。
在以下描述中，晶体管的第一极为源极，晶体管的第二极为漏极。
基准电压判断模块300包括：
第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4，第三晶体管M3和第四晶体管M4形成镜像电流源，输入电压端VIN为镜像电流源提供基准电流。第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4为N沟道场效应晶体管。
第一晶体管M1的栅极作为判断信号输入端Vref，用于控制第二晶体管M2的栅极接通输入电压端VIN或者接地GND。
第二晶体管M2的第一极连接镜像电流源的共栅极端，第二晶体管M2的第二极接地，以控制镜像电流源为误差放大器200提供判断信号ON，即为误差放大器200的使能端提供偏置电流以使误差放大器200工作。
输入电压端VIN通过第一负载网络310连接第一晶体管M1的第一极和第四晶体管M4的栅极、通过第二负载网络320连接第二晶体管M2的第一极；第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4的第二极接地；第三晶体管M3的栅极和第四晶体管M4的栅极连接作为镜像电流源的共栅极端，第二晶体管M2的第一极和栅极短接，第三晶体管M3的第一极作为判断信号输出端ON。
当输入电压端VIN上电后，电压基准源模块100开始启动，电压基准源模块100中的偏置电流开始正常工作，基准电压Vref开始上升，基准电压判断模块300的判断信号输入端开始对基准电压Vref采样。
当基准电压Vref在第一晶体管M1的开启电压VR以下时，第一晶体管M1的栅极电压不足以使第一晶体管M1导通，此时第四晶体管M4的栅极电压为高电平，第四晶体管M4导通，第三晶体管M3的栅极（接镜像电流源的共栅极端）接地，拉低了第三晶体管M3的栅极的电压，使第三晶体管M3无法为误差放大器200提供偏置电流。
当基准电压Vref上升到开启电压VR时，使第一晶体管M1充分导通，第四晶体管M4的栅极接地，拉低第四晶体管M4的栅极电压，使第四晶体管M4由开启变为关断，镜像电流源工作，此时第三晶体管M3为误差放大器200提供偏置电流。
通过合理控制基准电压Vref上升到开启电压VR的时间，可以有效避免电路在启动过程出现过冲现象。
在一些实施例中，还可以对上述的实施例进行改进，将第一负载网络310和第二负载网络320分别取第一电阻R1、第二电阻R2限流限压，或者将第一负载网络310和第二负载网络320分别取为第五晶体管M5、第六晶体管M6来配合第一晶体管M1和第二晶体管M2工作。第五晶体管M5和第六晶体管M6为P沟道场效应晶体管。
见图3，电压基准源模块100连接第五晶体管M5的栅极和第六晶体管M6的栅极以提供偏置电压BIAS。输入电压端VIN连接第五晶体管M5的第二极和第六晶体管M6的第二极，第五晶体管M5的第一极连接第一晶体管M1的第一极和第四晶体管的栅极，第六晶体管M6的第一极连接第二晶体管M2的第一极。
在其他实施例中，输入电压端VIN通过第一电阻R1连接第一晶体管M1的第一极，输入电压端VIN通过第一电阻R1连接第四晶体管M4的栅极，输入电压端VIN通过第二电阻R2连接第二晶体管M2的第一极。见图4。
图5是另一实施例低压差线性稳压器电路的模块图。请结合图6。
一种低压差线性稳压器电路，包括电压基准源模块100、误差放大器200、基准电压判断模块300、功率传输器件400、反馈模块500和启动电路模块600。启动电路模块600用于控制电压基准源模块100的启动。
启动电路600控制连接电压基准源模块100，电压基准源模块100的第一输出端连接误差放大器200的反相输入端-，电压基准源模块100的第二输出端连接基准电压判断模块300的判断信号输入端Vref，基准电压判断模块300的判断信号输出端ON连接误差放大器200的使能端on，误差放大器200的放大信号输出端连接功率传输器件400的控制端，误差放大器200的同相输入端+连接反馈模块500的反馈端，功率传输器件400的开关输入端连接输入电压VIN，功率传输器件400的开关输出端连接反馈模块500的电流输入端。误差放大器200的使能端on可以是误差放大器200的负电源端。
反馈模块500包括第三电阻R3和第四电阻R4，电流输入端通过第三电阻R3和第四电阻R4接地，第三电阻R3和第四电阻R4的连接处作为反馈端。误差放大器200通过对第四电阻R4的电压和电压基准源模块100的基准电压的采样比较来调节输出电压VOUT。
功率传输器件400为场效应晶体管，在本实施例中为P沟道场效应晶体管。功率传输器件400的控制端即P沟道场效应晶体管的栅极、开关输入端即P沟道场效应晶体管的源极、开关输出端即P沟道场效应晶体管的漏极。
本发明还公开了一种芯片和一种电子设备。
一种芯片，包括上述的低压差线性稳压器电路。
一种电子设备，包括上述的低压差线性稳压器电路。
上述低压差线性稳压器电路、芯片和电子设备，包括了基准电压判断模块，检测电压基准源模块是否完成启动，如果电压基准源模块完成启动则给误差放大器发送一个开始工作的信号，即通过使误差放大器的启动时间较电压基准源模块延后，使得误差放大器能有效的控制功率传输器件的工作，从而避免无输出电容LDO电路在启动过程出现过冲现象。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种低压差线性稳压器电路，其特征在于，包括电压基准源模块、误差放大器、基准电压判断模块、功率传输器件和反馈模块；所述电压基准源模块为所述误差放大器提供基准电压，所述基准电压判断模块根据所述电压基准源模块是否完全启动来控制所述误差放大器的使能，所述误差放大器根据所述电压基准源模块提供的基准电压和所述反馈模块提供的反馈电压来控制所述功率传输器件的通断。
  2. 根据权利要求1所述的低压差线性稳压器电路，其特征在于：
    还包括输入电压端；
    所述电压基准源模块包括与所述误差放大器的反相输入端连接的第一输出端、与所述基准电压判断模块的判断信号输入端连接的第二输出端；
    所述基准电压判断模块包括所述判断信号输入端、与所述误差放大器的使能端连接的判断信号输出端；
    所述误差放大器包括所述反相输入端、所述使能端、与所述功率传输器件的控制端连接的放大信号输出端、与所述反馈模块的反馈端连接的同相输入端；
    所述功率传输器件包括所述控制端、连接所述输入电压端的开关输入端、与所述反馈模块的电流输入端连接的开关输出端；
    所述反馈模块包括所述反馈端和所述电流输入端。
  3. 根据权利要求2 所述的低压差线性稳压器电路，其特征在于，所述基准电压判断模块还包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第三晶体管和所述第四晶体管形成镜像电流源，所述输入电压端为所述镜像电流源提供基准电流；
    所述第一晶体管的栅极作为所述判断信号输入端，用于控制所述第二晶体管的栅极接通所述输入电压端或者接地；
    所述第二晶体管的第一极连接所述镜像电流源的共栅极端，所述第二晶体管的第二极接地，以控制所述镜像电流源为所述误差放大器提供判断信号。
  4. 根据权利要求3所述的低压差线性稳压器电路，其特征在于:
    所述输入电压端连接所述第一晶体管的第一极、所述第二晶体管的第一极、所述第四晶体管的栅极；所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管的第二极接地；所述第二晶体管的栅极和所述第三晶体管的栅极连接作为所述镜像电流源的共栅极端，所述第二晶体管的第一极和栅极短接，所述第三晶体管的第一极作为所述判断信号输出端。
  5. 根据权利要求3所述的低压差线性稳压器电路，其特征在于，还包括第一负载网络和第二负载网络；所述输入电压端通过第一负载网络连接所述第一晶体管的第一极，所述输入电压端通过第一电阻或第五晶体管连接所述第四晶体管的栅极，所述输入电压端通过第二负载网络连接所述第二晶体管的第一极，所述电压基准源模块连接所述第五晶体管的栅极和所述第六晶体管的栅极以提供偏置电压。
  6. 根据权利要求5所述的低压差线性稳压器电路，其特征在于，所述第一负载网络为第一电阻，所述第二负载网络为第二电阻。
  7. 根据权利要求5所述的低压差线性稳压器电路，其特征在于，所述第一负载网络为第五晶体管，所述第二负载网络为第六晶体管。
  8. 根据权利要求2所述的低压差线性稳压器电路，其特征在于，所述反馈模块还包括第三电阻和第四电阻，所述电流输入端通过所述第三电阻和所述第四电阻接地，所述第三电阻和所述第四电阻的连接处作为所述反馈端。
  9. 根据权利要求1所述的低压差线性稳压器电路，其特征在于，所述功率传输器件为场效应晶体管。
  10. 根据权利要求1 所述的低压差线性稳压器电路，其特征在于，还包括启动电路模块，所述启动电路模块用于控制所述电压基准源模块的启动。
  11. 一种芯片，其特征在于，包括如权利要求1~10任一项所述的低压差线性稳压器电路。
  12. 一种电子设备，其特征在于，包括如权利要求11所述的芯片。
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CN117277783B (zh) * 2023-11-21 2024-04-26 辉芒微电子(深圳)股份有限公司 一种应用于ac-dc电源驱动芯片启动电路的ldo电路

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